1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 */
6 #ifndef __LINUX_CLK_PROVIDER_H
7 #define __LINUX_CLK_PROVIDER_H
8
9 #include <linux/of.h>
10 #include <linux/of_clk.h>
11
12 /*
13 * flags used across common struct clk. these flags should only affect the
14 * top-level framework. custom flags for dealing with hardware specifics
15 * belong in struct clk_foo
16 *
17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
18 */
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
23 /* unused */
24 /* unused */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
30 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31 /* parents need enable during gate/ungate, set rate and re-parent */
32 #define CLK_OPS_PARENT_ENABLE BIT(12)
33 /* duty cycle call may be forwarded to the parent clock */
34 #define CLK_DUTY_CYCLE_PARENT BIT(13)
35 #define CLK_DONT_HOLD_STATE BIT(14) /* Don't hold state */
36
37 struct clk;
38 struct clk_hw;
39 struct clk_core;
40 struct dentry;
41
42 /**
43 * struct clk_rate_request - Structure encoding the clk constraints that
44 * a clock user might require.
45 *
46 * @rate: Requested clock rate. This field will be adjusted by
47 * clock drivers according to hardware capabilities.
48 * @min_rate: Minimum rate imposed by clk users.
49 * @max_rate: Maximum rate imposed by clk users.
50 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
51 * requested constraints.
52 * @best_parent_hw: The most appropriate parent clock that fulfills the
53 * requested constraints.
54 *
55 */
56 struct clk_rate_request {
57 unsigned long rate;
58 unsigned long min_rate;
59 unsigned long max_rate;
60 unsigned long best_parent_rate;
61 struct clk_hw *best_parent_hw;
62 };
63
64 /**
65 * struct clk_duty - Structure encoding the duty cycle ratio of a clock
66 *
67 * @num: Numerator of the duty cycle ratio
68 * @den: Denominator of the duty cycle ratio
69 */
70 struct clk_duty {
71 unsigned int num;
72 unsigned int den;
73 };
74
75 /**
76 * struct clk_ops - Callback operations for hardware clocks; these are to
77 * be provided by the clock implementation, and will be called by drivers
78 * through the clk_* api.
79 *
80 * @prepare: Prepare the clock for enabling. This must not return until
81 * the clock is fully prepared, and it's safe to call clk_enable.
82 * This callback is intended to allow clock implementations to
83 * do any initialisation that may sleep. Called with
84 * prepare_lock held.
85 *
86 * @unprepare: Release the clock from its prepared state. This will typically
87 * undo any work done in the @prepare callback. Called with
88 * prepare_lock held.
89 *
90 * @is_prepared: Queries the hardware to determine if the clock is prepared.
91 * This function is allowed to sleep. Optional, if this op is not
92 * set then the prepare count will be used.
93 *
94 * @unprepare_unused: Unprepare the clock atomically. Only called from
95 * clk_disable_unused for prepare clocks with special needs.
96 * Called with prepare mutex held. This function may sleep.
97 *
98 * @enable: Enable the clock atomically. This must not return until the
99 * clock is generating a valid clock signal, usable by consumer
100 * devices. Called with enable_lock held. This function must not
101 * sleep.
102 *
103 * @disable: Disable the clock atomically. Called with enable_lock held.
104 * This function must not sleep.
105 *
106 * @is_enabled: Queries the hardware to determine if the clock is enabled.
107 * This function must not sleep. Optional, if this op is not
108 * set then the enable count will be used.
109 *
110 * @disable_unused: Disable the clock atomically. Only called from
111 * clk_disable_unused for gate clocks with special needs.
112 * Called with enable_lock held. This function must not
113 * sleep.
114 *
115 * @save_context: Save the context of the clock in prepration for poweroff.
116 *
117 * @restore_context: Restore the context of the clock after a restoration
118 * of power.
119 *
120 * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The
121 * parent rate is an input parameter. It is up to the caller to
122 * ensure that the prepare_mutex is held across this call.
123 * Returns the calculated rate. Optional, but recommended - if
124 * this op is not set then clock rate will be initialized to 0.
125 *
126 * @round_rate: Given a target rate as input, returns the closest rate actually
127 * supported by the clock. The parent rate is an input/output
128 * parameter.
129 *
130 * @determine_rate: Given a target rate as input, returns the closest rate
131 * actually supported by the clock, and optionally the parent clock
132 * that should be used to provide the clock rate.
133 *
134 * @set_parent: Change the input source of this clock; for clocks with multiple
135 * possible parents specify a new parent by passing in the index
136 * as a u8 corresponding to the parent in either the .parent_names
137 * or .parents arrays. This function in affect translates an
138 * array index into the value programmed into the hardware.
139 * Returns 0 on success, -EERROR otherwise.
140 *
141 * @get_parent: Queries the hardware to determine the parent of a clock. The
142 * return value is a u8 which specifies the index corresponding to
143 * the parent clock. This index can be applied to either the
144 * .parent_names or .parents arrays. In short, this function
145 * translates the parent value read from hardware into an array
146 * index. Currently only called when the clock is initialized by
147 * __clk_init. This callback is mandatory for clocks with
148 * multiple parents. It is optional (and unnecessary) for clocks
149 * with 0 or 1 parents.
150 *
151 * @set_rate: Change the rate of this clock. The requested rate is specified
152 * by the second argument, which should typically be the return
153 * of .round_rate call. The third argument gives the parent rate
154 * which is likely helpful for most .set_rate implementation.
155 * Returns 0 on success, -EERROR otherwise.
156 *
157 * @set_rate_and_parent: Change the rate and the parent of this clock. The
158 * requested rate is specified by the second argument, which
159 * should typically be the return of .round_rate call. The
160 * third argument gives the parent rate which is likely helpful
161 * for most .set_rate_and_parent implementation. The fourth
162 * argument gives the parent index. This callback is optional (and
163 * unnecessary) for clocks with 0 or 1 parents as well as
164 * for clocks that can tolerate switching the rate and the parent
165 * separately via calls to .set_parent and .set_rate.
166 * Returns 0 on success, -EERROR otherwise.
167 *
168 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
169 * is expressed in ppb (parts per billion). The parent accuracy is
170 * an input parameter.
171 * Returns the calculated accuracy. Optional - if this op is not
172 * set then clock accuracy will be initialized to parent accuracy
173 * or 0 (perfect clock) if clock has no parent.
174 *
175 * @get_phase: Queries the hardware to get the current phase of a clock.
176 * Returned values are 0-359 degrees on success, negative
177 * error codes on failure.
178 *
179 * @set_phase: Shift the phase this clock signal in degrees specified
180 * by the second argument. Valid values for degrees are
181 * 0-359. Return 0 on success, otherwise -EERROR.
182 *
183 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
184 * of a clock. Returned values denominator cannot be 0 and must be
185 * superior or equal to the numerator.
186 *
187 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
188 * the numerator (2nd argurment) and denominator (3rd argument).
189 * Argument must be a valid ratio (denominator > 0
190 * and >= numerator) Return 0 on success, otherwise -EERROR.
191 *
192 * @init: Perform platform-specific initialization magic.
193 * This is not used by any of the basic clock types.
194 * This callback exist for HW which needs to perform some
195 * initialisation magic for CCF to get an accurate view of the
196 * clock. It may also be used dynamic resource allocation is
197 * required. It shall not used to deal with clock parameters,
198 * such as rate or parents.
199 * Returns 0 on success, -EERROR otherwise.
200 *
201 * @terminate: Free any resource allocated by init.
202 *
203 * @debug_init: Set up type-specific debugfs entries for this clock. This
204 * is called once, after the debugfs directory entry for this
205 * clock has been created. The dentry pointer representing that
206 * directory is provided as an argument. Called with
207 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
208 *
209 * @pre_rate_change: Optional callback for a clock to fulfill its rate
210 * change requirements before any rate change has occurred in
211 * its clock tree. Returns 0 on success, -EERROR otherwise.
212 *
213 * @post_rate_change: Optional callback for a clock to clean up any
214 * requirements that were needed while the clock and its tree
215 * was changing states. Returns 0 on success, -EERROR otherwise.
216 *
217 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
218 * implementations to split any work between atomic (enable) and sleepable
219 * (prepare) contexts. If enabling a clock requires code that might sleep,
220 * this must be done in clk_prepare. Clock enable code that will never be
221 * called in a sleepable context may be implemented in clk_enable.
222 *
223 * Typically, drivers will call clk_prepare when a clock may be needed later
224 * (eg. when a device is opened), and clk_enable when the clock is actually
225 * required (eg. from an interrupt). Note that clk_prepare MUST have been
226 * called before clk_enable.
227 */
228 struct clk_ops {
229 int (*prepare)(struct clk_hw *hw);
230 void (*unprepare)(struct clk_hw *hw);
231 int (*is_prepared)(struct clk_hw *hw);
232 void (*unprepare_unused)(struct clk_hw *hw);
233 int (*enable)(struct clk_hw *hw);
234 void (*disable)(struct clk_hw *hw);
235 int (*is_enabled)(struct clk_hw *hw);
236 void (*disable_unused)(struct clk_hw *hw);
237 int (*save_context)(struct clk_hw *hw);
238 void (*restore_context)(struct clk_hw *hw);
239 unsigned long (*recalc_rate)(struct clk_hw *hw,
240 unsigned long parent_rate);
241 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
242 unsigned long *parent_rate);
243 int (*determine_rate)(struct clk_hw *hw,
244 struct clk_rate_request *req);
245 int (*set_parent)(struct clk_hw *hw, u8 index);
246 u8 (*get_parent)(struct clk_hw *hw);
247 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
248 unsigned long parent_rate);
249 int (*set_rate_and_parent)(struct clk_hw *hw,
250 unsigned long rate,
251 unsigned long parent_rate, u8 index);
252 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
253 unsigned long parent_accuracy);
254 int (*get_phase)(struct clk_hw *hw);
255 int (*set_phase)(struct clk_hw *hw, int degrees);
256 int (*get_duty_cycle)(struct clk_hw *hw,
257 struct clk_duty *duty);
258 int (*set_duty_cycle)(struct clk_hw *hw,
259 struct clk_duty *duty);
260 int (*init)(struct clk_hw *hw);
261 void (*terminate)(struct clk_hw *hw);
262 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
263 int (*pre_rate_change)(struct clk_hw *hw,
264 unsigned long rate,
265 unsigned long new_rate);
266 int (*post_rate_change)(struct clk_hw *hw,
267 unsigned long old_rate,
268 unsigned long rate);
269 };
270
271 /**
272 * struct clk_parent_data - clk parent information
273 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
274 * @fw_name: parent name local to provider registering clk
275 * @name: globally unique parent name (used as a fallback)
276 * @index: parent index local to provider registering clk (if @fw_name absent)
277 */
278 struct clk_parent_data {
279 const struct clk_hw *hw;
280 const char *fw_name;
281 const char *name;
282 int index;
283 };
284
285 /**
286 * struct clk_init_data - holds init data that's common to all clocks and is
287 * shared between the clock provider and the common clock framework.
288 *
289 * @name: clock name
290 * @ops: operations this clock supports
291 * @parent_names: array of string names for all possible parents
292 * @parent_data: array of parent data for all possible parents (when some
293 * parents are external to the clk controller)
294 * @parent_hws: array of pointers to all possible parents (when all parents
295 * are internal to the clk controller)
296 * @num_parents: number of possible parents
297 * @flags: framework-level hints and quirks
298 */
299 struct clk_init_data {
300 const char *name;
301 const struct clk_ops *ops;
302 /* Only one of the following three should be assigned */
303 const char * const *parent_names;
304 const struct clk_parent_data *parent_data;
305 const struct clk_hw **parent_hws;
306 u8 num_parents;
307 unsigned long flags;
308 };
309
310 /**
311 * struct clk_hw - handle for traversing from a struct clk to its corresponding
312 * hardware-specific structure. struct clk_hw should be declared within struct
313 * clk_foo and then referenced by the struct clk instance that uses struct
314 * clk_foo's clk_ops
315 *
316 * @core: pointer to the struct clk_core instance that points back to this
317 * struct clk_hw instance
318 *
319 * @clk: pointer to the per-user struct clk instance that can be used to call
320 * into the clk API
321 *
322 * @init: pointer to struct clk_init_data that contains the init data shared
323 * with the common clock framework. This pointer will be set to NULL once
324 * a clk_register() variant is called on this clk_hw pointer.
325 */
326 struct clk_hw {
327 struct clk_core *core;
328 struct clk *clk;
329 const struct clk_init_data *init;
330 };
331
332 /*
333 * DOC: Basic clock implementations common to many platforms
334 *
335 * Each basic clock hardware type is comprised of a structure describing the
336 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
337 * unique flags for that hardware type, a registration function and an
338 * alternative macro for static initialization
339 */
340
341 /**
342 * struct clk_fixed_rate - fixed-rate clock
343 * @hw: handle between common and hardware-specific interfaces
344 * @fixed_rate: constant frequency of clock
345 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
346 * @flags: hardware specific flags
347 *
348 * Flags:
349 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
350 * instead of what's set in @fixed_accuracy.
351 */
352 struct clk_fixed_rate {
353 struct clk_hw hw;
354 unsigned long fixed_rate;
355 unsigned long fixed_accuracy;
356 unsigned long flags;
357 };
358
359 #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
360
361 extern const struct clk_ops clk_fixed_rate_ops;
362 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
363 struct device_node *np, const char *name,
364 const char *parent_name, const struct clk_hw *parent_hw,
365 const struct clk_parent_data *parent_data, unsigned long flags,
366 unsigned long fixed_rate, unsigned long fixed_accuracy,
367 unsigned long clk_fixed_flags, bool devm);
368 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
369 const char *parent_name, unsigned long flags,
370 unsigned long fixed_rate);
371 /**
372 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
373 * framework
374 * @dev: device that is registering this clock
375 * @name: name of this clock
376 * @parent_name: name of clock's parent
377 * @flags: framework-specific flags
378 * @fixed_rate: non-adjustable clock rate
379 */
380 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
381 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
382 NULL, (flags), (fixed_rate), 0, 0, false)
383
384 /**
385 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
386 * framework
387 * @dev: device that is registering this clock
388 * @name: name of this clock
389 * @parent_name: name of clock's parent
390 * @flags: framework-specific flags
391 * @fixed_rate: non-adjustable clock rate
392 */
393 #define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
394 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
395 NULL, (flags), (fixed_rate), 0, 0, true)
396 /**
397 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
398 * the clock framework
399 * @dev: device that is registering this clock
400 * @name: name of this clock
401 * @parent_hw: pointer to parent clk
402 * @flags: framework-specific flags
403 * @fixed_rate: non-adjustable clock rate
404 */
405 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
406 fixed_rate) \
407 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
408 NULL, (flags), (fixed_rate), 0, 0, false)
409 /**
410 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
411 * the clock framework
412 * @dev: device that is registering this clock
413 * @name: name of this clock
414 * @parent_data: parent clk data
415 * @flags: framework-specific flags
416 * @fixed_rate: non-adjustable clock rate
417 */
418 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \
419 fixed_rate) \
420 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
421 (parent_data), (flags), (fixed_rate), 0, \
422 0, false)
423 /**
424 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
425 * the clock framework
426 * @dev: device that is registering this clock
427 * @name: name of this clock
428 * @parent_name: name of clock's parent
429 * @flags: framework-specific flags
430 * @fixed_rate: non-adjustable clock rate
431 * @fixed_accuracy: non-adjustable clock accuracy
432 */
433 #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
434 flags, fixed_rate, \
435 fixed_accuracy) \
436 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
437 NULL, NULL, (flags), (fixed_rate), \
438 (fixed_accuracy), 0, false)
439 /**
440 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
441 * clock with the clock framework
442 * @dev: device that is registering this clock
443 * @name: name of this clock
444 * @parent_hw: pointer to parent clk
445 * @flags: framework-specific flags
446 * @fixed_rate: non-adjustable clock rate
447 * @fixed_accuracy: non-adjustable clock accuracy
448 */
449 #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
450 parent_hw, flags, fixed_rate, fixed_accuracy) \
451 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
452 NULL, (flags), (fixed_rate), \
453 (fixed_accuracy), 0, false)
454 /**
455 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
456 * clock with the clock framework
457 * @dev: device that is registering this clock
458 * @name: name of this clock
459 * @parent_data: name of clock's parent
460 * @flags: framework-specific flags
461 * @fixed_rate: non-adjustable clock rate
462 * @fixed_accuracy: non-adjustable clock accuracy
463 */
464 #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
465 parent_data, flags, fixed_rate, fixed_accuracy) \
466 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
467 (parent_data), NULL, (flags), \
468 (fixed_rate), (fixed_accuracy), 0, false)
469 /**
470 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
471 * the clock framework
472 * @dev: device that is registering this clock
473 * @name: name of this clock
474 * @parent_data: name of clock's parent
475 * @flags: framework-specific flags
476 * @fixed_rate: non-adjustable clock rate
477 */
478 #define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \
479 flags, fixed_rate) \
480 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
481 (parent_data), (flags), (fixed_rate), 0, \
482 CLK_FIXED_RATE_PARENT_ACCURACY, false)
483
484 void clk_unregister_fixed_rate(struct clk *clk);
485 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
486
487 void of_fixed_clk_setup(struct device_node *np);
488
489 /**
490 * struct clk_gate - gating clock
491 *
492 * @hw: handle between common and hardware-specific interfaces
493 * @reg: register controlling gate
494 * @bit_idx: single bit controlling gate
495 * @flags: hardware-specific flags
496 * @lock: register lock
497 *
498 * Clock which can gate its output. Implements .enable & .disable
499 *
500 * Flags:
501 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
502 * enable the clock. Setting this flag does the opposite: setting the bit
503 * disable the clock and clearing it enables the clock
504 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
505 * of this register, and mask of gate bits are in higher 16-bit of this
506 * register. While setting the gate bits, higher 16-bit should also be
507 * updated to indicate changing gate bits.
508 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
509 * the gate register. Setting this flag makes the register accesses big
510 * endian.
511 */
512 struct clk_gate {
513 struct clk_hw hw;
514 void __iomem *reg;
515 u8 bit_idx;
516 u8 flags;
517 spinlock_t *lock;
518 };
519
520 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
521
522 #define CLK_GATE_SET_TO_DISABLE BIT(0)
523 #define CLK_GATE_HIWORD_MASK BIT(1)
524 #define CLK_GATE_BIG_ENDIAN BIT(2)
525
526 extern const struct clk_ops clk_gate_ops;
527 struct clk_hw *__clk_hw_register_gate(struct device *dev,
528 struct device_node *np, const char *name,
529 const char *parent_name, const struct clk_hw *parent_hw,
530 const struct clk_parent_data *parent_data,
531 unsigned long flags,
532 void __iomem *reg, u8 bit_idx,
533 u8 clk_gate_flags, spinlock_t *lock);
534 struct clk *clk_register_gate(struct device *dev, const char *name,
535 const char *parent_name, unsigned long flags,
536 void __iomem *reg, u8 bit_idx,
537 u8 clk_gate_flags, spinlock_t *lock);
538 /**
539 * clk_hw_register_gate - register a gate clock with the clock framework
540 * @dev: device that is registering this clock
541 * @name: name of this clock
542 * @parent_name: name of this clock's parent
543 * @flags: framework-specific flags for this clock
544 * @reg: register address to control gating of this clock
545 * @bit_idx: which bit in the register controls gating of this clock
546 * @clk_gate_flags: gate-specific flags for this clock
547 * @lock: shared register lock for this clock
548 */
549 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
550 clk_gate_flags, lock) \
551 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
552 NULL, (flags), (reg), (bit_idx), \
553 (clk_gate_flags), (lock))
554 /**
555 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
556 * framework
557 * @dev: device that is registering this clock
558 * @name: name of this clock
559 * @parent_hw: pointer to parent clk
560 * @flags: framework-specific flags for this clock
561 * @reg: register address to control gating of this clock
562 * @bit_idx: which bit in the register controls gating of this clock
563 * @clk_gate_flags: gate-specific flags for this clock
564 * @lock: shared register lock for this clock
565 */
566 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
567 bit_idx, clk_gate_flags, lock) \
568 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
569 NULL, (flags), (reg), (bit_idx), \
570 (clk_gate_flags), (lock))
571 /**
572 * clk_hw_register_gate_parent_data - register a gate clock with the clock
573 * framework
574 * @dev: device that is registering this clock
575 * @name: name of this clock
576 * @parent_data: parent clk data
577 * @flags: framework-specific flags for this clock
578 * @reg: register address to control gating of this clock
579 * @bit_idx: which bit in the register controls gating of this clock
580 * @clk_gate_flags: gate-specific flags for this clock
581 * @lock: shared register lock for this clock
582 */
583 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
584 bit_idx, clk_gate_flags, lock) \
585 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
586 (flags), (reg), (bit_idx), \
587 (clk_gate_flags), (lock))
588 void clk_unregister_gate(struct clk *clk);
589 void clk_hw_unregister_gate(struct clk_hw *hw);
590 int clk_gate_is_enabled(struct clk_hw *hw);
591
592 struct clk_div_table {
593 unsigned int val;
594 unsigned int div;
595 };
596
597 /**
598 * struct clk_divider - adjustable divider clock
599 *
600 * @hw: handle between common and hardware-specific interfaces
601 * @reg: register containing the divider
602 * @shift: shift to the divider bit field
603 * @width: width of the divider bit field
604 * @table: array of value/divider pairs, last entry should have div = 0
605 * @lock: register lock
606 *
607 * Clock with an adjustable divider affecting its output frequency. Implements
608 * .recalc_rate, .set_rate and .round_rate
609 *
610 * @flags:
611 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
612 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
613 * the raw value read from the register, with the value of zero considered
614 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
615 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
616 * the hardware register
617 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
618 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
619 * Some hardware implementations gracefully handle this case and allow a
620 * zero divisor by not modifying their input clock
621 * (divide by one / bypass).
622 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
623 * of this register, and mask of divider bits are in higher 16-bit of this
624 * register. While setting the divider bits, higher 16-bit should also be
625 * updated to indicate changing divider bits.
626 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
627 * to the closest integer instead of the up one.
628 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
629 * not be changed by the clock framework.
630 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
631 * except when the value read from the register is zero, the divisor is
632 * 2^width of the field.
633 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
634 * for the divider register. Setting this flag makes the register accesses
635 * big endian.
636 */
637 struct clk_divider {
638 struct clk_hw hw;
639 void __iomem *reg;
640 u8 shift;
641 u8 width;
642 u8 flags;
643 const struct clk_div_table *table;
644 spinlock_t *lock;
645 };
646
647 #define clk_div_mask(width) ((1 << (width)) - 1)
648 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
649
650 #define CLK_DIVIDER_ONE_BASED BIT(0)
651 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
652 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
653 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
654 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
655 #define CLK_DIVIDER_READ_ONLY BIT(5)
656 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
657 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
658
659 extern const struct clk_ops clk_divider_ops;
660 extern const struct clk_ops clk_divider_ro_ops;
661
662 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
663 unsigned int val, const struct clk_div_table *table,
664 unsigned long flags, unsigned long width);
665 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
666 unsigned long rate, unsigned long *prate,
667 const struct clk_div_table *table,
668 u8 width, unsigned long flags);
669 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
670 unsigned long rate, unsigned long *prate,
671 const struct clk_div_table *table, u8 width,
672 unsigned long flags, unsigned int val);
673 int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
674 const struct clk_div_table *table, u8 width,
675 unsigned long flags);
676 int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
677 const struct clk_div_table *table, u8 width,
678 unsigned long flags, unsigned int val);
679 int divider_get_val(unsigned long rate, unsigned long parent_rate,
680 const struct clk_div_table *table, u8 width,
681 unsigned long flags);
682
683 struct clk_hw *__clk_hw_register_divider(struct device *dev,
684 struct device_node *np, const char *name,
685 const char *parent_name, const struct clk_hw *parent_hw,
686 const struct clk_parent_data *parent_data, unsigned long flags,
687 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
688 const struct clk_div_table *table, spinlock_t *lock);
689 struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
690 struct device_node *np, const char *name,
691 const char *parent_name, const struct clk_hw *parent_hw,
692 const struct clk_parent_data *parent_data, unsigned long flags,
693 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
694 const struct clk_div_table *table, spinlock_t *lock);
695 struct clk *clk_register_divider_table(struct device *dev, const char *name,
696 const char *parent_name, unsigned long flags,
697 void __iomem *reg, u8 shift, u8 width,
698 u8 clk_divider_flags, const struct clk_div_table *table,
699 spinlock_t *lock);
700 /**
701 * clk_register_divider - register a divider clock with the clock framework
702 * @dev: device registering this clock
703 * @name: name of this clock
704 * @parent_name: name of clock's parent
705 * @flags: framework-specific flags
706 * @reg: register address to adjust divider
707 * @shift: number of bits to shift the bitfield
708 * @width: width of the bitfield
709 * @clk_divider_flags: divider-specific flags for this clock
710 * @lock: shared register lock for this clock
711 */
712 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
713 clk_divider_flags, lock) \
714 clk_register_divider_table((dev), (name), (parent_name), (flags), \
715 (reg), (shift), (width), \
716 (clk_divider_flags), NULL, (lock))
717 /**
718 * clk_hw_register_divider - register a divider clock with the clock framework
719 * @dev: device registering this clock
720 * @name: name of this clock
721 * @parent_name: name of clock's parent
722 * @flags: framework-specific flags
723 * @reg: register address to adjust divider
724 * @shift: number of bits to shift the bitfield
725 * @width: width of the bitfield
726 * @clk_divider_flags: divider-specific flags for this clock
727 * @lock: shared register lock for this clock
728 */
729 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
730 width, clk_divider_flags, lock) \
731 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
732 NULL, (flags), (reg), (shift), (width), \
733 (clk_divider_flags), NULL, (lock))
734 /**
735 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
736 * framework
737 * @dev: device registering this clock
738 * @name: name of this clock
739 * @parent_hw: pointer to parent clk
740 * @flags: framework-specific flags
741 * @reg: register address to adjust divider
742 * @shift: number of bits to shift the bitfield
743 * @width: width of the bitfield
744 * @clk_divider_flags: divider-specific flags for this clock
745 * @lock: shared register lock for this clock
746 */
747 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
748 shift, width, clk_divider_flags, \
749 lock) \
750 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
751 NULL, (flags), (reg), (shift), (width), \
752 (clk_divider_flags), NULL, (lock))
753 /**
754 * clk_hw_register_divider_parent_data - register a divider clock with the clock
755 * framework
756 * @dev: device registering this clock
757 * @name: name of this clock
758 * @parent_data: parent clk data
759 * @flags: framework-specific flags
760 * @reg: register address to adjust divider
761 * @shift: number of bits to shift the bitfield
762 * @width: width of the bitfield
763 * @clk_divider_flags: divider-specific flags for this clock
764 * @lock: shared register lock for this clock
765 */
766 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
767 reg, shift, width, \
768 clk_divider_flags, lock) \
769 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
770 (parent_data), (flags), (reg), (shift), \
771 (width), (clk_divider_flags), NULL, (lock))
772 /**
773 * clk_hw_register_divider_table - register a table based divider clock with
774 * the clock framework
775 * @dev: device registering this clock
776 * @name: name of this clock
777 * @parent_name: name of clock's parent
778 * @flags: framework-specific flags
779 * @reg: register address to adjust divider
780 * @shift: number of bits to shift the bitfield
781 * @width: width of the bitfield
782 * @clk_divider_flags: divider-specific flags for this clock
783 * @table: array of divider/value pairs ending with a div set to 0
784 * @lock: shared register lock for this clock
785 */
786 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
787 shift, width, clk_divider_flags, table, \
788 lock) \
789 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
790 NULL, (flags), (reg), (shift), (width), \
791 (clk_divider_flags), (table), (lock))
792 /**
793 * clk_hw_register_divider_table_parent_hw - register a table based divider
794 * clock with the clock framework
795 * @dev: device registering this clock
796 * @name: name of this clock
797 * @parent_hw: pointer to parent clk
798 * @flags: framework-specific flags
799 * @reg: register address to adjust divider
800 * @shift: number of bits to shift the bitfield
801 * @width: width of the bitfield
802 * @clk_divider_flags: divider-specific flags for this clock
803 * @table: array of divider/value pairs ending with a div set to 0
804 * @lock: shared register lock for this clock
805 */
806 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
807 reg, shift, width, \
808 clk_divider_flags, table, \
809 lock) \
810 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
811 NULL, (flags), (reg), (shift), (width), \
812 (clk_divider_flags), (table), (lock))
813 /**
814 * clk_hw_register_divider_table_parent_data - register a table based divider
815 * clock with the clock framework
816 * @dev: device registering this clock
817 * @name: name of this clock
818 * @parent_data: parent clk data
819 * @flags: framework-specific flags
820 * @reg: register address to adjust divider
821 * @shift: number of bits to shift the bitfield
822 * @width: width of the bitfield
823 * @clk_divider_flags: divider-specific flags for this clock
824 * @table: array of divider/value pairs ending with a div set to 0
825 * @lock: shared register lock for this clock
826 */
827 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
828 flags, reg, shift, width, \
829 clk_divider_flags, table, \
830 lock) \
831 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
832 (parent_data), (flags), (reg), (shift), \
833 (width), (clk_divider_flags), (table), \
834 (lock))
835 /**
836 * devm_clk_hw_register_divider - register a divider clock with the clock framework
837 * @dev: device registering this clock
838 * @name: name of this clock
839 * @parent_name: name of clock's parent
840 * @flags: framework-specific flags
841 * @reg: register address to adjust divider
842 * @shift: number of bits to shift the bitfield
843 * @width: width of the bitfield
844 * @clk_divider_flags: divider-specific flags for this clock
845 * @lock: shared register lock for this clock
846 */
847 #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
848 width, clk_divider_flags, lock) \
849 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
850 NULL, (flags), (reg), (shift), (width), \
851 (clk_divider_flags), NULL, (lock))
852 /**
853 * devm_clk_hw_register_divider_table - register a table based divider clock
854 * with the clock framework (devres variant)
855 * @dev: device registering this clock
856 * @name: name of this clock
857 * @parent_name: name of clock's parent
858 * @flags: framework-specific flags
859 * @reg: register address to adjust divider
860 * @shift: number of bits to shift the bitfield
861 * @width: width of the bitfield
862 * @clk_divider_flags: divider-specific flags for this clock
863 * @table: array of divider/value pairs ending with a div set to 0
864 * @lock: shared register lock for this clock
865 */
866 #define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \
867 reg, shift, width, \
868 clk_divider_flags, table, lock) \
869 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \
870 NULL, NULL, (flags), (reg), (shift), \
871 (width), (clk_divider_flags), (table), \
872 (lock))
873
874 void clk_unregister_divider(struct clk *clk);
875 void clk_hw_unregister_divider(struct clk_hw *hw);
876
877 /**
878 * struct clk_mux - multiplexer clock
879 *
880 * @hw: handle between common and hardware-specific interfaces
881 * @reg: register controlling multiplexer
882 * @table: array of register values corresponding to the parent index
883 * @shift: shift to multiplexer bit field
884 * @mask: mask of mutliplexer bit field
885 * @flags: hardware-specific flags
886 * @lock: register lock
887 *
888 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
889 * and .recalc_rate
890 *
891 * Flags:
892 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
893 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
894 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
895 * register, and mask of mux bits are in higher 16-bit of this register.
896 * While setting the mux bits, higher 16-bit should also be updated to
897 * indicate changing mux bits.
898 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
899 * .get_parent clk_op.
900 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
901 * frequency.
902 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
903 * the mux register. Setting this flag makes the register accesses big
904 * endian.
905 */
906 struct clk_mux {
907 struct clk_hw hw;
908 void __iomem *reg;
909 u32 *table;
910 u32 mask;
911 u8 shift;
912 u8 flags;
913 spinlock_t *lock;
914 };
915
916 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
917
918 #define CLK_MUX_INDEX_ONE BIT(0)
919 #define CLK_MUX_INDEX_BIT BIT(1)
920 #define CLK_MUX_HIWORD_MASK BIT(2)
921 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
922 #define CLK_MUX_ROUND_CLOSEST BIT(4)
923 #define CLK_MUX_BIG_ENDIAN BIT(5)
924
925 extern const struct clk_ops clk_mux_ops;
926 extern const struct clk_ops clk_mux_ro_ops;
927
928 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
929 const char *name, u8 num_parents,
930 const char * const *parent_names,
931 const struct clk_hw **parent_hws,
932 const struct clk_parent_data *parent_data,
933 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
934 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
935 struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
936 const char *name, u8 num_parents,
937 const char * const *parent_names,
938 const struct clk_hw **parent_hws,
939 const struct clk_parent_data *parent_data,
940 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
941 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
942 struct clk *clk_register_mux_table(struct device *dev, const char *name,
943 const char * const *parent_names, u8 num_parents,
944 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
945 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
946
947 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
948 shift, width, clk_mux_flags, lock) \
949 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
950 (flags), (reg), (shift), BIT((width)) - 1, \
951 (clk_mux_flags), NULL, (lock))
952 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
953 flags, reg, shift, mask, clk_mux_flags, \
954 table, lock) \
955 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
956 (parent_names), NULL, NULL, (flags), (reg), \
957 (shift), (mask), (clk_mux_flags), (table), \
958 (lock))
959 #define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \
960 num_parents, flags, reg, shift, mask, \
961 clk_mux_flags, table, lock) \
962 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
963 NULL, NULL, (parent_data), (flags), (reg), \
964 (shift), (mask), (clk_mux_flags), (table), \
965 (lock))
966 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
967 shift, width, clk_mux_flags, lock) \
968 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
969 (parent_names), NULL, NULL, (flags), (reg), \
970 (shift), BIT((width)) - 1, (clk_mux_flags), \
971 NULL, (lock))
972 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
973 reg, shift, width, clk_mux_flags, lock) \
974 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
975 (parent_hws), NULL, (flags), (reg), (shift), \
976 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
977 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
978 flags, reg, shift, width, \
979 clk_mux_flags, lock) \
980 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
981 (parent_data), (flags), (reg), (shift), \
982 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
983 #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
984 shift, width, clk_mux_flags, lock) \
985 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \
986 (parent_names), NULL, NULL, (flags), (reg), \
987 (shift), BIT((width)) - 1, (clk_mux_flags), \
988 NULL, (lock))
989
990 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
991 unsigned int val);
992 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
993
994 void clk_unregister_mux(struct clk *clk);
995 void clk_hw_unregister_mux(struct clk_hw *hw);
996
997 void of_fixed_factor_clk_setup(struct device_node *node);
998
999 /**
1000 * struct clk_fixed_factor - fixed multiplier and divider clock
1001 *
1002 * @hw: handle between common and hardware-specific interfaces
1003 * @mult: multiplier
1004 * @div: divider
1005 *
1006 * Clock with a fixed multiplier and divider. The output frequency is the
1007 * parent clock rate divided by div and multiplied by mult.
1008 * Implements .recalc_rate, .set_rate and .round_rate
1009 */
1010
1011 struct clk_fixed_factor {
1012 struct clk_hw hw;
1013 unsigned int mult;
1014 unsigned int div;
1015 };
1016
1017 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
1018
1019 extern const struct clk_ops clk_fixed_factor_ops;
1020 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
1021 const char *parent_name, unsigned long flags,
1022 unsigned int mult, unsigned int div);
1023 void clk_unregister_fixed_factor(struct clk *clk);
1024 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
1025 const char *name, const char *parent_name, unsigned long flags,
1026 unsigned int mult, unsigned int div);
1027 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
1028 struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
1029 const char *name, const char *parent_name, unsigned long flags,
1030 unsigned int mult, unsigned int div);
1031 /**
1032 * struct clk_fractional_divider - adjustable fractional divider clock
1033 *
1034 * @hw: handle between common and hardware-specific interfaces
1035 * @reg: register containing the divider
1036 * @mshift: shift to the numerator bit field
1037 * @mwidth: width of the numerator bit field
1038 * @nshift: shift to the denominator bit field
1039 * @nwidth: width of the denominator bit field
1040 * @approximation: clk driver's callback for calculating the divider clock
1041 * @lock: register lock
1042 *
1043 * Clock with adjustable fractional divider affecting its output frequency.
1044 *
1045 * @flags:
1046 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1047 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
1048 * is set then the numerator and denominator are both the value read
1049 * plus one.
1050 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1051 * used for the divider register. Setting this flag makes the register
1052 * accesses big endian.
1053 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1054 * be saturated and the caller will get quite far from the good enough
1055 * approximation. Instead the caller may require, by setting this flag,
1056 * to shift left by a few bits in case, when the asked one is quite small
1057 * to satisfy the desired range of denominator. It assumes that on the
1058 * caller's side the power-of-two capable prescaler exists.
1059 */
1060 struct clk_fractional_divider {
1061 struct clk_hw hw;
1062 void __iomem *reg;
1063 u8 mshift;
1064 u8 mwidth;
1065 u32 mmask;
1066 u8 nshift;
1067 u8 nwidth;
1068 u32 nmask;
1069 u8 flags;
1070 void (*approximation)(struct clk_hw *hw,
1071 unsigned long rate, unsigned long *parent_rate,
1072 unsigned long *m, unsigned long *n);
1073 spinlock_t *lock;
1074 };
1075
1076 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
1077
1078 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
1079 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
1080 #define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2)
1081
1082 struct clk *clk_register_fractional_divider(struct device *dev,
1083 const char *name, const char *parent_name, unsigned long flags,
1084 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1085 u8 clk_divider_flags, spinlock_t *lock);
1086 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
1087 const char *name, const char *parent_name, unsigned long flags,
1088 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1089 u8 clk_divider_flags, spinlock_t *lock);
1090 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
1091
1092 /**
1093 * struct clk_multiplier - adjustable multiplier clock
1094 *
1095 * @hw: handle between common and hardware-specific interfaces
1096 * @reg: register containing the multiplier
1097 * @shift: shift to the multiplier bit field
1098 * @width: width of the multiplier bit field
1099 * @lock: register lock
1100 *
1101 * Clock with an adjustable multiplier affecting its output frequency.
1102 * Implements .recalc_rate, .set_rate and .round_rate
1103 *
1104 * @flags:
1105 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1106 * from the register, with 0 being a valid value effectively
1107 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1108 * set, then a null multiplier will be considered as a bypass,
1109 * leaving the parent rate unmodified.
1110 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1111 * rounded to the closest integer instead of the down one.
1112 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1113 * used for the multiplier register. Setting this flag makes the register
1114 * accesses big endian.
1115 */
1116 struct clk_multiplier {
1117 struct clk_hw hw;
1118 void __iomem *reg;
1119 u8 shift;
1120 u8 width;
1121 u8 flags;
1122 spinlock_t *lock;
1123 };
1124
1125 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1126
1127 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1128 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
1129 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1130
1131 extern const struct clk_ops clk_multiplier_ops;
1132
1133 /***
1134 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1135 *
1136 * @hw: handle between common and hardware-specific interfaces
1137 * @mux_hw: handle between composite and hardware-specific mux clock
1138 * @rate_hw: handle between composite and hardware-specific rate clock
1139 * @gate_hw: handle between composite and hardware-specific gate clock
1140 * @mux_ops: clock ops for mux
1141 * @rate_ops: clock ops for rate
1142 * @gate_ops: clock ops for gate
1143 */
1144 struct clk_composite {
1145 struct clk_hw hw;
1146 struct clk_ops ops;
1147
1148 struct clk_hw *mux_hw;
1149 struct clk_hw *rate_hw;
1150 struct clk_hw *gate_hw;
1151
1152 const struct clk_ops *mux_ops;
1153 const struct clk_ops *rate_ops;
1154 const struct clk_ops *gate_ops;
1155 };
1156
1157 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1158
1159 struct clk *clk_register_composite(struct device *dev, const char *name,
1160 const char * const *parent_names, int num_parents,
1161 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1162 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1163 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1164 unsigned long flags);
1165 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1166 const struct clk_parent_data *parent_data, int num_parents,
1167 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1168 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1169 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1170 unsigned long flags);
1171 void clk_unregister_composite(struct clk *clk);
1172 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1173 const char * const *parent_names, int num_parents,
1174 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1175 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1176 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1177 unsigned long flags);
1178 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1179 const char *name,
1180 const struct clk_parent_data *parent_data, int num_parents,
1181 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1182 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1183 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1184 unsigned long flags);
1185 struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
1186 const char *name, const struct clk_parent_data *parent_data,
1187 int num_parents,
1188 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1189 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1190 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1191 unsigned long flags);
1192 void clk_hw_unregister_composite(struct clk_hw *hw);
1193
1194 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1195 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1196
1197 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1198 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1199 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1200
1201 void clk_unregister(struct clk *clk);
1202 void devm_clk_unregister(struct device *dev, struct clk *clk);
1203
1204 void clk_hw_unregister(struct clk_hw *hw);
1205 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
1206 void clk_sync_state(struct device *dev);
1207
1208 /* helper functions */
1209 const char *__clk_get_name(const struct clk *clk);
1210 const char *clk_hw_get_name(const struct clk_hw *hw);
1211 #ifdef CONFIG_COMMON_CLK
1212 struct clk_hw *__clk_get_hw(struct clk *clk);
1213 #else
__clk_get_hw(struct clk * clk)1214 static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1215 {
1216 return (struct clk_hw *)clk;
1217 }
1218 #endif
1219
1220 struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
1221 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1222 const char *con_id);
1223
1224 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1225 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1226 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1227 unsigned int index);
1228 int clk_hw_get_parent_index(struct clk_hw *hw);
1229 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1230 unsigned int __clk_get_enable_count(struct clk *clk);
1231 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1232 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1233 #define clk_hw_can_set_rate_parent(hw) \
1234 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1235
1236 bool clk_hw_is_prepared(const struct clk_hw *hw);
1237 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1238 bool clk_hw_is_enabled(const struct clk_hw *hw);
1239 bool __clk_is_enabled(struct clk *clk);
1240 struct clk *__clk_lookup(const char *name);
1241 int __clk_mux_determine_rate(struct clk_hw *hw,
1242 struct clk_rate_request *req);
1243 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1244 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1245 struct clk_rate_request *req);
1246 int clk_mux_determine_rate_flags(struct clk_hw *hw,
1247 struct clk_rate_request *req,
1248 unsigned long flags);
1249 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1250 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1251 unsigned long max_rate);
1252
__clk_hw_set_clk(struct clk_hw * dst,struct clk_hw * src)1253 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1254 {
1255 dst->clk = src->clk;
1256 dst->core = src->core;
1257 }
1258
divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags)1259 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
1260 unsigned long *prate,
1261 const struct clk_div_table *table,
1262 u8 width, unsigned long flags)
1263 {
1264 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
1265 rate, prate, table, width, flags);
1266 }
1267
divider_ro_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags,unsigned int val)1268 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
1269 unsigned long *prate,
1270 const struct clk_div_table *table,
1271 u8 width, unsigned long flags,
1272 unsigned int val)
1273 {
1274 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
1275 rate, prate, table, width, flags,
1276 val);
1277 }
1278
1279 /*
1280 * FIXME clock api without lock protection
1281 */
1282 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1283
1284 struct clk_onecell_data {
1285 struct clk **clks;
1286 unsigned int clk_num;
1287 };
1288
1289 struct clk_hw_onecell_data {
1290 unsigned int num;
1291 struct clk_hw *hws[];
1292 };
1293
1294 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
1295
1296 /*
1297 * Use this macro when you have a driver that requires two initialization
1298 * routines, one at of_clk_init(), and one at platform device probe
1299 */
1300 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1301 static void __init name##_of_clk_init_driver(struct device_node *np) \
1302 { \
1303 of_node_clear_flag(np, OF_POPULATED); \
1304 fn(np); \
1305 } \
1306 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1307
1308 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
1309 (&(struct clk_init_data) { \
1310 .flags = _flags, \
1311 .name = _name, \
1312 .parent_names = (const char *[]) { _parent }, \
1313 .num_parents = 1, \
1314 .ops = _ops, \
1315 })
1316
1317 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
1318 (&(struct clk_init_data) { \
1319 .flags = _flags, \
1320 .name = _name, \
1321 .parent_hws = (const struct clk_hw*[]) { _parent }, \
1322 .num_parents = 1, \
1323 .ops = _ops, \
1324 })
1325
1326 /*
1327 * This macro is intended for drivers to be able to share the otherwise
1328 * individual struct clk_hw[] compound literals created by the compiler
1329 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
1330 */
1331 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
1332 (&(struct clk_init_data) { \
1333 .flags = _flags, \
1334 .name = _name, \
1335 .parent_hws = _parent, \
1336 .num_parents = 1, \
1337 .ops = _ops, \
1338 })
1339
1340 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
1341 (&(struct clk_init_data) { \
1342 .flags = _flags, \
1343 .name = _name, \
1344 .parent_data = (const struct clk_parent_data[]) { \
1345 { .fw_name = _parent }, \
1346 }, \
1347 .num_parents = 1, \
1348 .ops = _ops, \
1349 })
1350
1351 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
1352 (&(struct clk_init_data) { \
1353 .flags = _flags, \
1354 .name = _name, \
1355 .parent_names = _parents, \
1356 .num_parents = ARRAY_SIZE(_parents), \
1357 .ops = _ops, \
1358 })
1359
1360 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
1361 (&(struct clk_init_data) { \
1362 .flags = _flags, \
1363 .name = _name, \
1364 .parent_hws = _parents, \
1365 .num_parents = ARRAY_SIZE(_parents), \
1366 .ops = _ops, \
1367 })
1368
1369 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1370 (&(struct clk_init_data) { \
1371 .flags = _flags, \
1372 .name = _name, \
1373 .parent_data = _parents, \
1374 .num_parents = ARRAY_SIZE(_parents), \
1375 .ops = _ops, \
1376 })
1377
1378 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
1379 (&(struct clk_init_data) { \
1380 .flags = _flags, \
1381 .name = _name, \
1382 .parent_names = NULL, \
1383 .num_parents = 0, \
1384 .ops = _ops, \
1385 })
1386
1387 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
1388 _div, _mult, _flags) \
1389 struct clk_fixed_factor _struct = { \
1390 .div = _div, \
1391 .mult = _mult, \
1392 .hw.init = CLK_HW_INIT(_name, \
1393 _parent, \
1394 &clk_fixed_factor_ops, \
1395 _flags), \
1396 }
1397
1398 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1399 _div, _mult, _flags) \
1400 struct clk_fixed_factor _struct = { \
1401 .div = _div, \
1402 .mult = _mult, \
1403 .hw.init = CLK_HW_INIT_HW(_name, \
1404 _parent, \
1405 &clk_fixed_factor_ops, \
1406 _flags), \
1407 }
1408
1409 /*
1410 * This macro allows the driver to reuse the _parent array for multiple
1411 * fixed factor clk declarations.
1412 */
1413 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1414 _div, _mult, _flags) \
1415 struct clk_fixed_factor _struct = { \
1416 .div = _div, \
1417 .mult = _mult, \
1418 .hw.init = CLK_HW_INIT_HWS(_name, \
1419 _parent, \
1420 &clk_fixed_factor_ops, \
1421 _flags), \
1422 }
1423
1424 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1425 _div, _mult, _flags) \
1426 struct clk_fixed_factor _struct = { \
1427 .div = _div, \
1428 .mult = _mult, \
1429 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1430 _parent, \
1431 &clk_fixed_factor_ops, \
1432 _flags), \
1433 }
1434
1435 #ifdef CONFIG_OF
1436 int of_clk_add_provider(struct device_node *np,
1437 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1438 void *data),
1439 void *data);
1440 int of_clk_add_hw_provider(struct device_node *np,
1441 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1442 void *data),
1443 void *data);
1444 int devm_of_clk_add_hw_provider(struct device *dev,
1445 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1446 void *data),
1447 void *data);
1448 void of_clk_del_provider(struct device_node *np);
1449 void devm_of_clk_del_provider(struct device *dev);
1450 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1451 void *data);
1452 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1453 void *data);
1454 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1455 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1456 void *data);
1457 int of_clk_parent_fill(struct device_node *np, const char **parents,
1458 unsigned int size);
1459 int of_clk_detect_critical(struct device_node *np, int index,
1460 unsigned long *flags);
1461
1462 #else /* !CONFIG_OF */
1463
of_clk_add_provider(struct device_node * np,struct clk * (* clk_src_get)(struct of_phandle_args * args,void * data),void * data)1464 static inline int of_clk_add_provider(struct device_node *np,
1465 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1466 void *data),
1467 void *data)
1468 {
1469 return 0;
1470 }
of_clk_add_hw_provider(struct device_node * np,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1471 static inline int of_clk_add_hw_provider(struct device_node *np,
1472 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1473 void *data),
1474 void *data)
1475 {
1476 return 0;
1477 }
devm_of_clk_add_hw_provider(struct device * dev,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1478 static inline int devm_of_clk_add_hw_provider(struct device *dev,
1479 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1480 void *data),
1481 void *data)
1482 {
1483 return 0;
1484 }
of_clk_del_provider(struct device_node * np)1485 static inline void of_clk_del_provider(struct device_node *np) {}
devm_of_clk_del_provider(struct device * dev)1486 static inline void devm_of_clk_del_provider(struct device *dev) {}
of_clk_src_simple_get(struct of_phandle_args * clkspec,void * data)1487 static inline struct clk *of_clk_src_simple_get(
1488 struct of_phandle_args *clkspec, void *data)
1489 {
1490 return ERR_PTR(-ENOENT);
1491 }
1492 static inline struct clk_hw *
of_clk_hw_simple_get(struct of_phandle_args * clkspec,void * data)1493 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1494 {
1495 return ERR_PTR(-ENOENT);
1496 }
of_clk_src_onecell_get(struct of_phandle_args * clkspec,void * data)1497 static inline struct clk *of_clk_src_onecell_get(
1498 struct of_phandle_args *clkspec, void *data)
1499 {
1500 return ERR_PTR(-ENOENT);
1501 }
1502 static inline struct clk_hw *
of_clk_hw_onecell_get(struct of_phandle_args * clkspec,void * data)1503 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1504 {
1505 return ERR_PTR(-ENOENT);
1506 }
of_clk_parent_fill(struct device_node * np,const char ** parents,unsigned int size)1507 static inline int of_clk_parent_fill(struct device_node *np,
1508 const char **parents, unsigned int size)
1509 {
1510 return 0;
1511 }
of_clk_detect_critical(struct device_node * np,int index,unsigned long * flags)1512 static inline int of_clk_detect_critical(struct device_node *np, int index,
1513 unsigned long *flags)
1514 {
1515 return 0;
1516 }
1517 #endif /* CONFIG_OF */
1518
1519 void clk_gate_restore_context(struct clk_hw *hw);
1520
1521 #endif /* CLK_PROVIDER_H */
1522