1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
22 */
23 #ifndef LINUX_PCI_H
24 #define LINUX_PCI_H
25
26
27 #include <linux/mod_devicetable.h>
28
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
39 #include <linux/io.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
42
43 #include <linux/pci_ids.h>
44 #include <linux/android_kabi.h>
45
46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
47 PCI_STATUS_SIG_SYSTEM_ERROR | \
48 PCI_STATUS_REC_MASTER_ABORT | \
49 PCI_STATUS_REC_TARGET_ABORT | \
50 PCI_STATUS_SIG_TARGET_ABORT | \
51 PCI_STATUS_PARITY)
52
53 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
54 #define PCI_NUM_RESET_METHODS 7
55
56 #define PCI_RESET_PROBE true
57 #define PCI_RESET_DO_RESET false
58
59 /*
60 * The PCI interface treats multi-function devices as independent
61 * devices. The slot/function address of each device is encoded
62 * in a single byte as follows:
63 *
64 * 7:3 = slot
65 * 2:0 = function
66 *
67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
68 * In the interest of not exposing interfaces to user-space unnecessarily,
69 * the following kernel-only defines are being added here.
70 */
71 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
72 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
73 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
74
75 /* pci_slot represents a physical slot */
76 struct pci_slot {
77 struct pci_bus *bus; /* Bus this slot is on */
78 struct list_head list; /* Node in list of slots */
79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
81 struct kobject kobj;
82 };
83
pci_slot_name(const struct pci_slot * slot)84 static inline const char *pci_slot_name(const struct pci_slot *slot)
85 {
86 return kobject_name(&slot->kobj);
87 }
88
89 /* File state for mmap()s on /proc/bus/pci/X/Y */
90 enum pci_mmap_state {
91 pci_mmap_io,
92 pci_mmap_mem
93 };
94
95 /* For PCI devices, the region numbers are assigned this way: */
96 enum {
97 /* #0-5: standard PCI resources */
98 PCI_STD_RESOURCES,
99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
100
101 /* #6: expansion ROM resource */
102 PCI_ROM_RESOURCE,
103
104 /* Device-specific resources */
105 #ifdef CONFIG_PCI_IOV
106 PCI_IOV_RESOURCES,
107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
108 #endif
109
110 /* PCI-to-PCI (P2P) bridge windows */
111 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
112 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
113 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
114
115 /* CardBus bridge windows */
116 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
117 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
118 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
119 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
120
121 /* Total number of bridge resources for P2P and CardBus */
122 #define PCI_BRIDGE_RESOURCE_NUM 4
123
124 /* Resources assigned to buses behind the bridge */
125 PCI_BRIDGE_RESOURCES,
126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
127 PCI_BRIDGE_RESOURCE_NUM - 1,
128
129 /* Total resources associated with a PCI device */
130 PCI_NUM_RESOURCES,
131
132 /* Preserve this for compatibility */
133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
134 };
135
136 /**
137 * enum pci_interrupt_pin - PCI INTx interrupt values
138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
139 * @PCI_INTERRUPT_INTA: PCI INTA pin
140 * @PCI_INTERRUPT_INTB: PCI INTB pin
141 * @PCI_INTERRUPT_INTC: PCI INTC pin
142 * @PCI_INTERRUPT_INTD: PCI INTD pin
143 *
144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
145 * PCI_INTERRUPT_PIN register.
146 */
147 enum pci_interrupt_pin {
148 PCI_INTERRUPT_UNKNOWN,
149 PCI_INTERRUPT_INTA,
150 PCI_INTERRUPT_INTB,
151 PCI_INTERRUPT_INTC,
152 PCI_INTERRUPT_INTD,
153 };
154
155 /* The number of legacy PCI INTx interrupts */
156 #define PCI_NUM_INTX 4
157
158 /*
159 * pci_power_t values must match the bits in the Capabilities PME_Support
160 * and Control/Status PowerState fields in the Power Management capability.
161 */
162 typedef int __bitwise pci_power_t;
163
164 #define PCI_D0 ((pci_power_t __force) 0)
165 #define PCI_D1 ((pci_power_t __force) 1)
166 #define PCI_D2 ((pci_power_t __force) 2)
167 #define PCI_D3hot ((pci_power_t __force) 3)
168 #define PCI_D3cold ((pci_power_t __force) 4)
169 #define PCI_UNKNOWN ((pci_power_t __force) 5)
170 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
171
172 /* Remember to update this when the list above changes! */
173 extern const char *pci_power_names[];
174
pci_power_name(pci_power_t state)175 static inline const char *pci_power_name(pci_power_t state)
176 {
177 return pci_power_names[1 + (__force int) state];
178 }
179
180 /**
181 * typedef pci_channel_state_t
182 *
183 * The pci_channel state describes connectivity between the CPU and
184 * the PCI device. If some PCI bus between here and the PCI device
185 * has crashed or locked up, this info is reflected here.
186 */
187 typedef unsigned int __bitwise pci_channel_state_t;
188
189 enum {
190 /* I/O channel is in normal state */
191 pci_channel_io_normal = (__force pci_channel_state_t) 1,
192
193 /* I/O to channel is blocked */
194 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
195
196 /* PCI card is dead */
197 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
198 };
199
200 typedef unsigned int __bitwise pcie_reset_state_t;
201
202 enum pcie_reset_state {
203 /* Reset is NOT asserted (Use to deassert reset) */
204 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
205
206 /* Use #PERST to reset PCIe device */
207 pcie_warm_reset = (__force pcie_reset_state_t) 2,
208
209 /* Use PCIe Hot Reset to reset device */
210 pcie_hot_reset = (__force pcie_reset_state_t) 3
211 };
212
213 typedef unsigned short __bitwise pci_dev_flags_t;
214 enum pci_dev_flags {
215 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
216 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
217 /* Device configuration is irrevocably lost if disabled into D3 */
218 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
219 /* Provide indication device is assigned by a Virtual Machine Manager */
220 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
221 /* Flag for quirk use to store if quirk-specific ACS is enabled */
222 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
223 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
224 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
225 /* Do not use bus resets for device */
226 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
227 /* Do not use PM reset even if device advertises NoSoftRst- */
228 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
229 /* Get VPD from function 0 VPD */
230 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
231 /* A non-root bridge where translation occurs, stop alias search here */
232 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
233 /* Do not use FLR even if device advertises PCI_AF_CAP */
234 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
235 /* Don't use Relaxed Ordering for TLPs directed at this device */
236 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
237 /* Device does honor MSI masking despite saying otherwise */
238 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
239 };
240
241 enum pci_irq_reroute_variant {
242 INTEL_IRQ_REROUTE_VARIANT = 1,
243 MAX_IRQ_REROUTE_VARIANTS = 3
244 };
245
246 typedef unsigned short __bitwise pci_bus_flags_t;
247 enum pci_bus_flags {
248 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
249 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
250 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
251 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
252 };
253
254 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
255 enum pcie_link_width {
256 PCIE_LNK_WIDTH_RESRV = 0x00,
257 PCIE_LNK_X1 = 0x01,
258 PCIE_LNK_X2 = 0x02,
259 PCIE_LNK_X4 = 0x04,
260 PCIE_LNK_X8 = 0x08,
261 PCIE_LNK_X12 = 0x0c,
262 PCIE_LNK_X16 = 0x10,
263 PCIE_LNK_X32 = 0x20,
264 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
265 };
266
267 /* See matching string table in pci_speed_string() */
268 enum pci_bus_speed {
269 PCI_SPEED_33MHz = 0x00,
270 PCI_SPEED_66MHz = 0x01,
271 PCI_SPEED_66MHz_PCIX = 0x02,
272 PCI_SPEED_100MHz_PCIX = 0x03,
273 PCI_SPEED_133MHz_PCIX = 0x04,
274 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
275 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
276 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
277 PCI_SPEED_66MHz_PCIX_266 = 0x09,
278 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
279 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
280 AGP_UNKNOWN = 0x0c,
281 AGP_1X = 0x0d,
282 AGP_2X = 0x0e,
283 AGP_4X = 0x0f,
284 AGP_8X = 0x10,
285 PCI_SPEED_66MHz_PCIX_533 = 0x11,
286 PCI_SPEED_100MHz_PCIX_533 = 0x12,
287 PCI_SPEED_133MHz_PCIX_533 = 0x13,
288 PCIE_SPEED_2_5GT = 0x14,
289 PCIE_SPEED_5_0GT = 0x15,
290 PCIE_SPEED_8_0GT = 0x16,
291 PCIE_SPEED_16_0GT = 0x17,
292 PCIE_SPEED_32_0GT = 0x18,
293 PCIE_SPEED_64_0GT = 0x19,
294 PCI_SPEED_UNKNOWN = 0xff,
295 };
296
297 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
298 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
299
300 struct pci_vpd {
301 struct mutex lock;
302 unsigned int len;
303 u8 cap;
304 };
305
306 struct irq_affinity;
307 struct pcie_link_state;
308 struct pci_sriov;
309 struct pci_p2pdma;
310 struct rcec_ea;
311
312 /* The pci_dev structure describes PCI devices */
313 struct pci_dev {
314 struct list_head bus_list; /* Node in per-bus list */
315 struct pci_bus *bus; /* Bus this device is on */
316 struct pci_bus *subordinate; /* Bus this device bridges to */
317
318 void *sysdata; /* Hook for sys-specific extension */
319 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
320 struct pci_slot *slot; /* Physical slot this device is in */
321
322 unsigned int devfn; /* Encoded device & function index */
323 unsigned short vendor;
324 unsigned short device;
325 unsigned short subsystem_vendor;
326 unsigned short subsystem_device;
327 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
328 u8 revision; /* PCI revision, low byte of class word */
329 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
330 #ifdef CONFIG_PCIEAER
331 u16 aer_cap; /* AER capability offset */
332 struct aer_stats *aer_stats; /* AER stats for this device */
333 #endif
334 #ifdef CONFIG_PCIEPORTBUS
335 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
336 struct pci_dev *rcec; /* Associated RCEC device */
337 #endif
338 u32 devcap; /* PCIe Device Capabilities */
339 u8 pcie_cap; /* PCIe capability offset */
340 u8 msi_cap; /* MSI capability offset */
341 u8 msix_cap; /* MSI-X capability offset */
342 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
343 u8 rom_base_reg; /* Config register controlling ROM */
344 u8 pin; /* Interrupt pin this device uses */
345 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
346 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
347
348 struct pci_driver *driver; /* Driver bound to this device */
349 u64 dma_mask; /* Mask of the bits of bus address this
350 device implements. Normally this is
351 0xffffffff. You only need to change
352 this if your device has broken DMA
353 or supports 64-bit transfers. */
354
355 struct device_dma_parameters dma_parms;
356
357 pci_power_t current_state; /* Current operating state. In ACPI,
358 this is D0-D3, D0 being fully
359 functional, and D3 being off. */
360 unsigned int imm_ready:1; /* Supports Immediate Readiness */
361 u8 pm_cap; /* PM capability offset */
362 unsigned int pme_support:5; /* Bitmask of states from which PME#
363 can be generated */
364 unsigned int pme_poll:1; /* Poll device's PME status bit */
365 unsigned int d1_support:1; /* Low power state D1 is supported */
366 unsigned int d2_support:1; /* Low power state D2 is supported */
367 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
368 unsigned int no_d3cold:1; /* D3cold is forbidden */
369 unsigned int bridge_d3:1; /* Allow D3 for bridge */
370 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
371 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
372 decoding during BAR sizing */
373 unsigned int wakeup_prepared:1;
374 unsigned int runtime_d3cold:1; /* Whether go through runtime
375 D3cold, not set for devices
376 powered on/off by the
377 corresponding bridge */
378 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
379 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
380 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
381 controlled exclusively by
382 user sysfs */
383 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
384 bit manually */
385 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
386 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
387
388 #ifdef CONFIG_PCIEASPM
389 struct pcie_link_state *link_state; /* ASPM link state */
390 unsigned int ltr_path:1; /* Latency Tolerance Reporting
391 supported from root to here */
392 u16 l1ss; /* L1SS Capability pointer */
393 #endif
394 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
395 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
396
397 pci_channel_state_t error_state; /* Current connectivity state */
398 struct device dev; /* Generic device interface */
399
400 int cfg_size; /* Size of config space */
401
402 /*
403 * Instead of touching interrupt line and base address registers
404 * directly, use the values stored here. They might be different!
405 */
406 unsigned int irq;
407 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
408
409 bool match_driver; /* Skip attaching driver */
410
411 unsigned int transparent:1; /* Subtractive decode bridge */
412 unsigned int io_window:1; /* Bridge has I/O window */
413 unsigned int pref_window:1; /* Bridge has pref mem window */
414 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
415 unsigned int multifunction:1; /* Multi-function device */
416
417 unsigned int is_busmaster:1; /* Is busmaster */
418 unsigned int no_msi:1; /* May not use MSI */
419 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
420 unsigned int block_cfg_access:1; /* Config space access blocked */
421 unsigned int broken_parity_status:1; /* Generates false positive parity */
422 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
423 unsigned int msi_enabled:1;
424 unsigned int msix_enabled:1;
425 unsigned int ari_enabled:1; /* ARI forwarding */
426 unsigned int ats_enabled:1; /* Address Translation Svc */
427 unsigned int pasid_enabled:1; /* Process Address Space ID */
428 unsigned int pri_enabled:1; /* Page Request Interface */
429 unsigned int is_managed:1;
430 unsigned int needs_freset:1; /* Requires fundamental reset */
431 unsigned int state_saved:1;
432 unsigned int is_physfn:1;
433 unsigned int is_virtfn:1;
434 unsigned int is_hotplug_bridge:1;
435 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
436 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
437 /*
438 * Devices marked being untrusted are the ones that can potentially
439 * execute DMA attacks and similar. They are typically connected
440 * through external ports such as Thunderbolt but not limited to
441 * that. When an IOMMU is enabled they should be getting full
442 * mappings to make sure they cannot access arbitrary memory.
443 */
444 unsigned int untrusted:1;
445 /*
446 * Info from the platform, e.g., ACPI or device tree, may mark a
447 * device as "external-facing". An external-facing device is
448 * itself internal but devices downstream from it are external.
449 */
450 unsigned int external_facing:1;
451 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
452 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
453 unsigned int irq_managed:1;
454 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
455 unsigned int is_probed:1; /* Device probing in progress */
456 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
457 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
458 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
459 pci_dev_flags_t dev_flags;
460 atomic_t enable_cnt; /* pci_enable_device has been called */
461
462 u32 saved_config_space[16]; /* Config space saved at suspend time */
463 struct hlist_head saved_cap_space;
464 int rom_attr_enabled; /* Display of ROM attribute enabled? */
465 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
466 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
467
468 #ifdef CONFIG_HOTPLUG_PCI_PCIE
469 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
470 #endif
471 #ifdef CONFIG_PCIE_PTM
472 unsigned int ptm_root:1;
473 unsigned int ptm_enabled:1;
474 u8 ptm_granularity;
475 #endif
476 #ifdef CONFIG_PCI_MSI
477 const struct attribute_group **msi_irq_groups;
478 #endif
479 struct pci_vpd vpd;
480 #ifdef CONFIG_PCIE_DPC
481 u16 dpc_cap;
482 unsigned int dpc_rp_extensions:1;
483 u8 dpc_rp_log_size;
484 #endif
485 #ifdef CONFIG_PCI_ATS
486 union {
487 struct pci_sriov *sriov; /* PF: SR-IOV info */
488 struct pci_dev *physfn; /* VF: related PF */
489 };
490 u16 ats_cap; /* ATS Capability offset */
491 u8 ats_stu; /* ATS Smallest Translation Unit */
492 #endif
493 #ifdef CONFIG_PCI_PRI
494 u16 pri_cap; /* PRI Capability offset */
495 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
496 unsigned int pasid_required:1; /* PRG Response PASID Required */
497 #endif
498 #ifdef CONFIG_PCI_PASID
499 u16 pasid_cap; /* PASID Capability offset */
500 u16 pasid_features;
501 #endif
502 #ifdef CONFIG_PCI_P2PDMA
503 struct pci_p2pdma __rcu *p2pdma;
504 #endif
505 u16 acs_cap; /* ACS Capability offset */
506 phys_addr_t rom; /* Physical address if not from BAR */
507 size_t romlen; /* Length if not from BAR */
508 char *driver_override; /* Driver name to force a match */
509
510 unsigned long priv_flags; /* Private flags for the PCI driver */
511
512 /* These methods index pci_reset_fn_methods[] */
513 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
514
515 ANDROID_KABI_RESERVE(1);
516 ANDROID_KABI_RESERVE(2);
517 ANDROID_KABI_RESERVE(3);
518 ANDROID_KABI_RESERVE(4);
519 };
520
pci_physfn(struct pci_dev * dev)521 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
522 {
523 #ifdef CONFIG_PCI_IOV
524 if (dev->is_virtfn)
525 dev = dev->physfn;
526 #endif
527 return dev;
528 }
529
530 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
531
532 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
533 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
534
pci_channel_offline(struct pci_dev * pdev)535 static inline int pci_channel_offline(struct pci_dev *pdev)
536 {
537 return (pdev->error_state != pci_channel_io_normal);
538 }
539
540 /*
541 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
542 * Group number is limited to a 16-bit value, therefore (int)-1 is
543 * not a valid PCI domain number, and can be used as a sentinel
544 * value indicating ->domain_nr is not set by the driver (and
545 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
546 * pci_bus_find_domain_nr()).
547 */
548 #define PCI_DOMAIN_NR_NOT_SET (-1)
549
550 struct pci_host_bridge {
551 struct device dev;
552 struct pci_bus *bus; /* Root bus */
553 struct pci_ops *ops;
554 struct pci_ops *child_ops;
555 void *sysdata;
556 int busnr;
557 int domain_nr;
558 struct list_head windows; /* resource_entry */
559 struct list_head dma_ranges; /* dma ranges resource list */
560 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
561 int (*map_irq)(const struct pci_dev *, u8, u8);
562 void (*release_fn)(struct pci_host_bridge *);
563 void *release_data;
564 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
565 unsigned int no_ext_tags:1; /* No Extended Tags */
566 unsigned int no_inc_mrrs:1; /* No Increase MRRS */
567 unsigned int native_aer:1; /* OS may use PCIe AER */
568 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
569 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
570 unsigned int native_pme:1; /* OS may use PCIe PME */
571 unsigned int native_ltr:1; /* OS may use PCIe LTR */
572 unsigned int native_dpc:1; /* OS may use PCIe DPC */
573 unsigned int preserve_config:1; /* Preserve FW resource setup */
574 unsigned int size_windows:1; /* Enable root bus sizing */
575 unsigned int msi_domain:1; /* Bridge wants MSI domain */
576
577 /* Resource alignment requirements */
578 resource_size_t (*align_resource)(struct pci_dev *dev,
579 const struct resource *res,
580 resource_size_t start,
581 resource_size_t size,
582 resource_size_t align);
583
584 ANDROID_KABI_RESERVE(1);
585 ANDROID_KABI_RESERVE(2);
586
587 unsigned long private[] ____cacheline_aligned;
588 };
589
590 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
591
pci_host_bridge_priv(struct pci_host_bridge * bridge)592 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
593 {
594 return (void *)bridge->private;
595 }
596
pci_host_bridge_from_priv(void * priv)597 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
598 {
599 return container_of(priv, struct pci_host_bridge, private);
600 }
601
602 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
603 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
604 size_t priv);
605 void pci_free_host_bridge(struct pci_host_bridge *bridge);
606 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
607
608 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
609 void (*release_fn)(struct pci_host_bridge *),
610 void *release_data);
611
612 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
613
614 /*
615 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
616 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
617 * buses below host bridges or subtractive decode bridges) go in the list.
618 * Use pci_bus_for_each_resource() to iterate through all the resources.
619 */
620
621 /*
622 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
623 * and there's no way to program the bridge with the details of the window.
624 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
625 * decode bit set, because they are explicit and can be programmed with _SRS.
626 */
627 #define PCI_SUBTRACTIVE_DECODE 0x1
628
629 struct pci_bus_resource {
630 struct list_head list;
631 struct resource *res;
632 unsigned int flags;
633 };
634
635 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
636
637 struct pci_bus {
638 struct list_head node; /* Node in list of buses */
639 struct pci_bus *parent; /* Parent bus this bridge is on */
640 struct list_head children; /* List of child buses */
641 struct list_head devices; /* List of devices on this bus */
642 struct pci_dev *self; /* Bridge device as seen by parent */
643 struct list_head slots; /* List of slots on this bus;
644 protected by pci_slot_mutex */
645 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
646 struct list_head resources; /* Address space routed to this bus */
647 struct resource busn_res; /* Bus numbers routed to this bus */
648
649 struct pci_ops *ops; /* Configuration access functions */
650 void *sysdata; /* Hook for sys-specific extension */
651 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
652
653 unsigned char number; /* Bus number */
654 unsigned char primary; /* Number of primary bridge */
655 unsigned char max_bus_speed; /* enum pci_bus_speed */
656 unsigned char cur_bus_speed; /* enum pci_bus_speed */
657 #ifdef CONFIG_PCI_DOMAINS_GENERIC
658 int domain_nr;
659 #endif
660
661 char name[48];
662
663 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
664 pci_bus_flags_t bus_flags; /* Inherited by child buses */
665 struct device *bridge;
666 struct device dev;
667 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
668 struct bin_attribute *legacy_mem; /* Legacy mem */
669 unsigned int is_added:1;
670 unsigned int unsafe_warn:1; /* warned about RW1C config write */
671
672 ANDROID_KABI_RESERVE(1);
673 ANDROID_KABI_RESERVE(2);
674 ANDROID_KABI_RESERVE(3);
675 ANDROID_KABI_RESERVE(4);
676 };
677
678 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
679
pci_dev_id(struct pci_dev * dev)680 static inline u16 pci_dev_id(struct pci_dev *dev)
681 {
682 return PCI_DEVID(dev->bus->number, dev->devfn);
683 }
684
685 /*
686 * Returns true if the PCI bus is root (behind host-PCI bridge),
687 * false otherwise
688 *
689 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
690 * This is incorrect because "virtual" buses added for SR-IOV (via
691 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
692 */
pci_is_root_bus(struct pci_bus * pbus)693 static inline bool pci_is_root_bus(struct pci_bus *pbus)
694 {
695 return !(pbus->parent);
696 }
697
698 /**
699 * pci_is_bridge - check if the PCI device is a bridge
700 * @dev: PCI device
701 *
702 * Return true if the PCI device is bridge whether it has subordinate
703 * or not.
704 */
pci_is_bridge(struct pci_dev * dev)705 static inline bool pci_is_bridge(struct pci_dev *dev)
706 {
707 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
708 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
709 }
710
711 #define for_each_pci_bridge(dev, bus) \
712 list_for_each_entry(dev, &bus->devices, bus_list) \
713 if (!pci_is_bridge(dev)) {} else
714
pci_upstream_bridge(struct pci_dev * dev)715 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
716 {
717 dev = pci_physfn(dev);
718 if (pci_is_root_bus(dev->bus))
719 return NULL;
720
721 return dev->bus->self;
722 }
723
724 #ifdef CONFIG_PCI_MSI
pci_dev_msi_enabled(struct pci_dev * pci_dev)725 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
726 {
727 return pci_dev->msi_enabled || pci_dev->msix_enabled;
728 }
729 #else
pci_dev_msi_enabled(struct pci_dev * pci_dev)730 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
731 #endif
732
733 /* Error values that may be returned by PCI functions */
734 #define PCIBIOS_SUCCESSFUL 0x00
735 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
736 #define PCIBIOS_BAD_VENDOR_ID 0x83
737 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
738 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
739 #define PCIBIOS_SET_FAILED 0x88
740 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
741
742 /* Translate above to generic errno for passing back through non-PCI code */
pcibios_err_to_errno(int err)743 static inline int pcibios_err_to_errno(int err)
744 {
745 if (err <= PCIBIOS_SUCCESSFUL)
746 return err; /* Assume already errno */
747
748 switch (err) {
749 case PCIBIOS_FUNC_NOT_SUPPORTED:
750 return -ENOENT;
751 case PCIBIOS_BAD_VENDOR_ID:
752 return -ENOTTY;
753 case PCIBIOS_DEVICE_NOT_FOUND:
754 return -ENODEV;
755 case PCIBIOS_BAD_REGISTER_NUMBER:
756 return -EFAULT;
757 case PCIBIOS_SET_FAILED:
758 return -EIO;
759 case PCIBIOS_BUFFER_TOO_SMALL:
760 return -ENOSPC;
761 }
762
763 return -ERANGE;
764 }
765
766 /* Low-level architecture-dependent routines */
767
768 struct pci_ops {
769 int (*add_bus)(struct pci_bus *bus);
770 void (*remove_bus)(struct pci_bus *bus);
771 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
772 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
773 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
774
775 ANDROID_KABI_RESERVE(1);
776 };
777
778 /*
779 * ACPI needs to be able to access PCI config space before we've done a
780 * PCI bus scan and created pci_bus structures.
781 */
782 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
783 int reg, int len, u32 *val);
784 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
785 int reg, int len, u32 val);
786
787 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
788 typedef u64 pci_bus_addr_t;
789 #else
790 typedef u32 pci_bus_addr_t;
791 #endif
792
793 struct pci_bus_region {
794 pci_bus_addr_t start;
795 pci_bus_addr_t end;
796 };
797
798 struct pci_dynids {
799 spinlock_t lock; /* Protects list, index */
800 struct list_head list; /* For IDs added at runtime */
801 };
802
803
804 /*
805 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
806 * a set of callbacks in struct pci_error_handlers, that device driver
807 * will be notified of PCI bus errors, and will be driven to recovery
808 * when an error occurs.
809 */
810
811 typedef unsigned int __bitwise pci_ers_result_t;
812
813 enum pci_ers_result {
814 /* No result/none/not supported in device driver */
815 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
816
817 /* Device driver can recover without slot reset */
818 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
819
820 /* Device driver wants slot to be reset */
821 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
822
823 /* Device has completely failed, is unrecoverable */
824 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
825
826 /* Device driver is fully recovered and operational */
827 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
828
829 /* No AER capabilities registered for the driver */
830 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
831 };
832
833 /* PCI bus error event callbacks */
834 struct pci_error_handlers {
835 /* PCI bus error detected on this device */
836 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
837 pci_channel_state_t error);
838
839 /* MMIO has been re-enabled, but not DMA */
840 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
841
842 /* PCI slot has been reset */
843 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
844
845 /* PCI function reset prepare or completed */
846 void (*reset_prepare)(struct pci_dev *dev);
847 void (*reset_done)(struct pci_dev *dev);
848
849 /* Device driver may resume normal operations */
850 void (*resume)(struct pci_dev *dev);
851
852 ANDROID_KABI_RESERVE(1);
853 };
854
855
856 struct module;
857
858 /**
859 * struct pci_driver - PCI driver structure
860 * @node: List of driver structures.
861 * @name: Driver name.
862 * @id_table: Pointer to table of device IDs the driver is
863 * interested in. Most drivers should export this
864 * table using MODULE_DEVICE_TABLE(pci,...).
865 * @probe: This probing function gets called (during execution
866 * of pci_register_driver() for already existing
867 * devices or later if a new device gets inserted) for
868 * all PCI devices which match the ID table and are not
869 * "owned" by the other drivers yet. This function gets
870 * passed a "struct pci_dev \*" for each device whose
871 * entry in the ID table matches the device. The probe
872 * function returns zero when the driver chooses to
873 * take "ownership" of the device or an error code
874 * (negative number) otherwise.
875 * The probe function always gets called from process
876 * context, so it can sleep.
877 * @remove: The remove() function gets called whenever a device
878 * being handled by this driver is removed (either during
879 * deregistration of the driver or when it's manually
880 * pulled out of a hot-pluggable slot).
881 * The remove function always gets called from process
882 * context, so it can sleep.
883 * @suspend: Put device into low power state.
884 * @resume: Wake device from low power state.
885 * (Please see Documentation/power/pci.rst for descriptions
886 * of PCI Power Management and the related functions.)
887 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
888 * Intended to stop any idling DMA operations.
889 * Useful for enabling wake-on-lan (NIC) or changing
890 * the power state of a device before reboot.
891 * e.g. drivers/net/e100.c.
892 * @sriov_configure: Optional driver callback to allow configuration of
893 * number of VFs to enable via sysfs "sriov_numvfs" file.
894 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
895 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
896 * This will change MSI-X Table Size in the VF Message Control
897 * registers.
898 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
899 * MSI-X vectors available for distribution to the VFs.
900 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
901 * @groups: Sysfs attribute groups.
902 * @dev_groups: Attributes attached to the device that will be
903 * created once it is bound to the driver.
904 * @driver: Driver model structure.
905 * @dynids: List of dynamically added device IDs.
906 */
907 struct pci_driver {
908 struct list_head node;
909 const char *name;
910 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
911 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
912 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
913 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
914 int (*resume)(struct pci_dev *dev); /* Device woken up */
915 void (*shutdown)(struct pci_dev *dev);
916 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
917 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
918 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
919 const struct pci_error_handlers *err_handler;
920 const struct attribute_group **groups;
921 const struct attribute_group **dev_groups;
922 struct device_driver driver;
923 struct pci_dynids dynids;
924
925 ANDROID_KABI_RESERVE(1);
926 ANDROID_KABI_RESERVE(2);
927 ANDROID_KABI_RESERVE(3);
928 ANDROID_KABI_RESERVE(4);
929 };
930
931 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
932
933 /**
934 * PCI_DEVICE - macro used to describe a specific PCI device
935 * @vend: the 16 bit PCI Vendor ID
936 * @dev: the 16 bit PCI Device ID
937 *
938 * This macro is used to create a struct pci_device_id that matches a
939 * specific device. The subvendor and subdevice fields will be set to
940 * PCI_ANY_ID.
941 */
942 #define PCI_DEVICE(vend,dev) \
943 .vendor = (vend), .device = (dev), \
944 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
945
946 /**
947 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
948 * override_only flags.
949 * @vend: the 16 bit PCI Vendor ID
950 * @dev: the 16 bit PCI Device ID
951 * @driver_override: the 32 bit PCI Device override_only
952 *
953 * This macro is used to create a struct pci_device_id that matches only a
954 * driver_override device. The subvendor and subdevice fields will be set to
955 * PCI_ANY_ID.
956 */
957 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
958 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
959 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
960
961 /**
962 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
963 * "driver_override" PCI device.
964 * @vend: the 16 bit PCI Vendor ID
965 * @dev: the 16 bit PCI Device ID
966 *
967 * This macro is used to create a struct pci_device_id that matches a
968 * specific device. The subvendor and subdevice fields will be set to
969 * PCI_ANY_ID and the driver_override will be set to
970 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
971 */
972 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
973 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
974
975 /**
976 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
977 * @vend: the 16 bit PCI Vendor ID
978 * @dev: the 16 bit PCI Device ID
979 * @subvend: the 16 bit PCI Subvendor ID
980 * @subdev: the 16 bit PCI Subdevice ID
981 *
982 * This macro is used to create a struct pci_device_id that matches a
983 * specific device with subsystem information.
984 */
985 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
986 .vendor = (vend), .device = (dev), \
987 .subvendor = (subvend), .subdevice = (subdev)
988
989 /**
990 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
991 * @dev_class: the class, subclass, prog-if triple for this device
992 * @dev_class_mask: the class mask for this device
993 *
994 * This macro is used to create a struct pci_device_id that matches a
995 * specific PCI class. The vendor, device, subvendor, and subdevice
996 * fields will be set to PCI_ANY_ID.
997 */
998 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
999 .class = (dev_class), .class_mask = (dev_class_mask), \
1000 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1001 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1002
1003 /**
1004 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
1005 * @vend: the vendor name
1006 * @dev: the 16 bit PCI Device ID
1007 *
1008 * This macro is used to create a struct pci_device_id that matches a
1009 * specific PCI device. The subvendor, and subdevice fields will be set
1010 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1011 * private data.
1012 */
1013 #define PCI_VDEVICE(vend, dev) \
1014 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1015 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1016
1017 /**
1018 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1019 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1020 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1021 * @data: the driver data to be filled
1022 *
1023 * This macro is used to create a struct pci_device_id that matches a
1024 * specific PCI device. The subvendor, and subdevice fields will be set
1025 * to PCI_ANY_ID.
1026 */
1027 #define PCI_DEVICE_DATA(vend, dev, data) \
1028 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1029 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1030 .driver_data = (kernel_ulong_t)(data)
1031
1032 enum {
1033 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1034 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1035 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1036 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1037 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1038 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1039 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1040 };
1041
1042 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1043 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1044 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1045 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1046
1047 /* These external functions are only available when PCI support is enabled */
1048 #ifdef CONFIG_PCI
1049
1050 extern unsigned int pci_flags;
1051
pci_set_flags(int flags)1052 static inline void pci_set_flags(int flags) { pci_flags = flags; }
pci_add_flags(int flags)1053 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
pci_clear_flags(int flags)1054 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
pci_has_flag(int flag)1055 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1056
1057 void pcie_bus_configure_settings(struct pci_bus *bus);
1058
1059 enum pcie_bus_config_types {
1060 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1061 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1062 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1063 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1064 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1065 };
1066
1067 extern enum pcie_bus_config_types pcie_bus_config;
1068
1069 extern struct bus_type pci_bus_type;
1070
1071 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1072 * code, or PCI core code. */
1073 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1074 /* Some device drivers need know if PCI is initiated */
1075 int no_pci_devices(void);
1076
1077 void pcibios_resource_survey_bus(struct pci_bus *bus);
1078 void pcibios_bus_add_device(struct pci_dev *pdev);
1079 void pcibios_add_bus(struct pci_bus *bus);
1080 void pcibios_remove_bus(struct pci_bus *bus);
1081 void pcibios_fixup_bus(struct pci_bus *);
1082 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1083 /* Architecture-specific versions may override this (weak) */
1084 char *pcibios_setup(char *str);
1085
1086 /* Used only when drivers/pci/setup.c is used */
1087 resource_size_t pcibios_align_resource(void *, const struct resource *,
1088 resource_size_t,
1089 resource_size_t);
1090
1091 /* Weak but can be overridden by arch */
1092 void pci_fixup_cardbus(struct pci_bus *);
1093
1094 /* Generic PCI functions used internally */
1095
1096 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1097 struct resource *res);
1098 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1099 struct pci_bus_region *region);
1100 void pcibios_scan_specific_bus(int busn);
1101 struct pci_bus *pci_find_bus(int domain, int busnr);
1102 void pci_bus_add_devices(const struct pci_bus *bus);
1103 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1104 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1105 struct pci_ops *ops, void *sysdata,
1106 struct list_head *resources);
1107 int pci_host_probe(struct pci_host_bridge *bridge);
1108 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1109 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1110 void pci_bus_release_busn_res(struct pci_bus *b);
1111 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1112 struct pci_ops *ops, void *sysdata,
1113 struct list_head *resources);
1114 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1115 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1116 int busnr);
1117 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1118 const char *name,
1119 struct hotplug_slot *hotplug);
1120 void pci_destroy_slot(struct pci_slot *slot);
1121 #ifdef CONFIG_SYSFS
1122 void pci_dev_assign_slot(struct pci_dev *dev);
1123 #else
pci_dev_assign_slot(struct pci_dev * dev)1124 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1125 #endif
1126 int pci_scan_slot(struct pci_bus *bus, int devfn);
1127 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1128 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1129 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1130 void pci_bus_add_device(struct pci_dev *dev);
1131 void pci_read_bridge_bases(struct pci_bus *child);
1132 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1133 struct resource *res);
1134 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1135 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1136 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1137 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1138 void pci_dev_put(struct pci_dev *dev);
1139 void pci_remove_bus(struct pci_bus *b);
1140 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1141 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1142 void pci_stop_root_bus(struct pci_bus *bus);
1143 void pci_remove_root_bus(struct pci_bus *bus);
1144 void pci_setup_cardbus(struct pci_bus *bus);
1145 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1146 void pci_sort_breadthfirst(void);
1147 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1148 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1149
1150 /* Generic PCI functions exported to card drivers */
1151
1152 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1153 u8 pci_find_capability(struct pci_dev *dev, int cap);
1154 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1155 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1156 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1157 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1158 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1159 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1160 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1161
1162 u64 pci_get_dsn(struct pci_dev *dev);
1163
1164 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1165 struct pci_dev *from);
1166 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1167 unsigned int ss_vendor, unsigned int ss_device,
1168 struct pci_dev *from);
1169 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1170 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1171 unsigned int devfn);
1172 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1173 int pci_dev_present(const struct pci_device_id *ids);
1174
1175 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1176 int where, u8 *val);
1177 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1178 int where, u16 *val);
1179 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1180 int where, u32 *val);
1181 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1182 int where, u8 val);
1183 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1184 int where, u16 val);
1185 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1186 int where, u32 val);
1187
1188 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1189 int where, int size, u32 *val);
1190 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1191 int where, int size, u32 val);
1192 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1193 int where, int size, u32 *val);
1194 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1195 int where, int size, u32 val);
1196
1197 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1198
1199 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1200 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1201 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1202 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1203 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1204 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1205
1206 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1207 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1208 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1209 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1210 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1211 u16 clear, u16 set);
1212 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1213 u32 clear, u32 set);
1214
pcie_capability_set_word(struct pci_dev * dev,int pos,u16 set)1215 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1216 u16 set)
1217 {
1218 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1219 }
1220
pcie_capability_set_dword(struct pci_dev * dev,int pos,u32 set)1221 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1222 u32 set)
1223 {
1224 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1225 }
1226
pcie_capability_clear_word(struct pci_dev * dev,int pos,u16 clear)1227 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1228 u16 clear)
1229 {
1230 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1231 }
1232
pcie_capability_clear_dword(struct pci_dev * dev,int pos,u32 clear)1233 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1234 u32 clear)
1235 {
1236 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1237 }
1238
1239 /* User-space driven config access */
1240 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1241 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1242 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1243 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1244 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1245 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1246
1247 int __must_check pci_enable_device(struct pci_dev *dev);
1248 int __must_check pci_enable_device_io(struct pci_dev *dev);
1249 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1250 int __must_check pci_reenable_device(struct pci_dev *);
1251 int __must_check pcim_enable_device(struct pci_dev *pdev);
1252 void pcim_pin_device(struct pci_dev *pdev);
1253
pci_intx_mask_supported(struct pci_dev * pdev)1254 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1255 {
1256 /*
1257 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1258 * writable and no quirk has marked the feature broken.
1259 */
1260 return !pdev->broken_intx_masking;
1261 }
1262
pci_is_enabled(struct pci_dev * pdev)1263 static inline int pci_is_enabled(struct pci_dev *pdev)
1264 {
1265 return (atomic_read(&pdev->enable_cnt) > 0);
1266 }
1267
pci_is_managed(struct pci_dev * pdev)1268 static inline int pci_is_managed(struct pci_dev *pdev)
1269 {
1270 return pdev->is_managed;
1271 }
1272
1273 void pci_disable_device(struct pci_dev *dev);
1274
1275 extern unsigned int pcibios_max_latency;
1276 void pci_set_master(struct pci_dev *dev);
1277 void pci_clear_master(struct pci_dev *dev);
1278
1279 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1280 int pci_set_cacheline_size(struct pci_dev *dev);
1281 int __must_check pci_set_mwi(struct pci_dev *dev);
1282 int __must_check pcim_set_mwi(struct pci_dev *dev);
1283 int pci_try_set_mwi(struct pci_dev *dev);
1284 void pci_clear_mwi(struct pci_dev *dev);
1285 void pci_disable_parity(struct pci_dev *dev);
1286 void pci_intx(struct pci_dev *dev, int enable);
1287 bool pci_check_and_mask_intx(struct pci_dev *dev);
1288 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1289 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1290 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1291 int pcix_get_max_mmrbc(struct pci_dev *dev);
1292 int pcix_get_mmrbc(struct pci_dev *dev);
1293 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1294 int pcie_get_readrq(struct pci_dev *dev);
1295 int pcie_set_readrq(struct pci_dev *dev, int rq);
1296 int pcie_get_mps(struct pci_dev *dev);
1297 int pcie_set_mps(struct pci_dev *dev, int mps);
1298 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1299 enum pci_bus_speed *speed,
1300 enum pcie_link_width *width);
1301 void pcie_print_link_status(struct pci_dev *dev);
1302 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1303 int pcie_flr(struct pci_dev *dev);
1304 int __pci_reset_function_locked(struct pci_dev *dev);
1305 int pci_reset_function(struct pci_dev *dev);
1306 int pci_reset_function_locked(struct pci_dev *dev);
1307 int pci_try_reset_function(struct pci_dev *dev);
1308 int pci_probe_reset_slot(struct pci_slot *slot);
1309 int pci_probe_reset_bus(struct pci_bus *bus);
1310 int pci_reset_bus(struct pci_dev *dev);
1311 void pci_reset_secondary_bus(struct pci_dev *dev);
1312 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1313 void pci_update_resource(struct pci_dev *dev, int resno);
1314 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1315 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1316 void pci_release_resource(struct pci_dev *dev, int resno);
pci_rebar_bytes_to_size(u64 bytes)1317 static inline int pci_rebar_bytes_to_size(u64 bytes)
1318 {
1319 bytes = roundup_pow_of_two(bytes);
1320
1321 /* Return BAR size as defined in the resizable BAR specification */
1322 return max(ilog2(bytes), 20) - 20;
1323 }
1324
1325 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1326 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1327 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1328 bool pci_device_is_present(struct pci_dev *pdev);
1329 void pci_ignore_hotplug(struct pci_dev *dev);
1330 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1331 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1332
1333 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1334 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1335 const char *fmt, ...);
1336 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1337
1338 /* ROM control related routines */
1339 int pci_enable_rom(struct pci_dev *pdev);
1340 void pci_disable_rom(struct pci_dev *pdev);
1341 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1342 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1343
1344 /* Power management related routines */
1345 int pci_save_state(struct pci_dev *dev);
1346 void pci_restore_state(struct pci_dev *dev);
1347 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1348 int pci_load_saved_state(struct pci_dev *dev,
1349 struct pci_saved_state *state);
1350 int pci_load_and_free_saved_state(struct pci_dev *dev,
1351 struct pci_saved_state **state);
1352 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1353 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1354 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1355 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1356 void pci_pme_active(struct pci_dev *dev, bool enable);
1357 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1358 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1359 int pci_prepare_to_sleep(struct pci_dev *dev);
1360 int pci_back_from_sleep(struct pci_dev *dev);
1361 bool pci_dev_run_wake(struct pci_dev *dev);
1362 void pci_d3cold_enable(struct pci_dev *dev);
1363 void pci_d3cold_disable(struct pci_dev *dev);
1364 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1365 void pci_resume_bus(struct pci_bus *bus);
1366 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1367
1368 /* For use by arch with custom probe code */
1369 void set_pcie_port_type(struct pci_dev *pdev);
1370 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1371
1372 /* Functions for PCI Hotplug drivers to use */
1373 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1374 unsigned int pci_rescan_bus(struct pci_bus *bus);
1375 void pci_lock_rescan_remove(void);
1376 void pci_unlock_rescan_remove(void);
1377
1378 /* Vital Product Data routines */
1379 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1380 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1381
1382 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1383 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1384 void pci_bus_assign_resources(const struct pci_bus *bus);
1385 void pci_bus_claim_resources(struct pci_bus *bus);
1386 void pci_bus_size_bridges(struct pci_bus *bus);
1387 int pci_claim_resource(struct pci_dev *, int);
1388 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1389 void pci_assign_unassigned_resources(void);
1390 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1391 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1392 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1393 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1394 void pdev_enable_device(struct pci_dev *);
1395 int pci_enable_resources(struct pci_dev *, int mask);
1396 void pci_assign_irq(struct pci_dev *dev);
1397 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1398 #define HAVE_PCI_REQ_REGIONS 2
1399 int __must_check pci_request_regions(struct pci_dev *, const char *);
1400 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1401 void pci_release_regions(struct pci_dev *);
1402 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1403 void pci_release_region(struct pci_dev *, int);
1404 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1405 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1406 void pci_release_selected_regions(struct pci_dev *, int);
1407
1408 /* drivers/pci/bus.c */
1409 void pci_add_resource(struct list_head *resources, struct resource *res);
1410 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1411 resource_size_t offset);
1412 void pci_free_resource_list(struct list_head *resources);
1413 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1414 unsigned int flags);
1415 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1416 void pci_bus_remove_resources(struct pci_bus *bus);
1417 void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res);
1418 int devm_request_pci_bus_resources(struct device *dev,
1419 struct list_head *resources);
1420
1421 /* Temporary until new and working PCI SBR API in place */
1422 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1423
1424 #define pci_bus_for_each_resource(bus, res, i) \
1425 for (i = 0; \
1426 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1427 i++)
1428
1429 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1430 struct resource *res, resource_size_t size,
1431 resource_size_t align, resource_size_t min,
1432 unsigned long type_mask,
1433 resource_size_t (*alignf)(void *,
1434 const struct resource *,
1435 resource_size_t,
1436 resource_size_t),
1437 void *alignf_data);
1438
1439
1440 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1441 resource_size_t size);
1442 unsigned long pci_address_to_pio(phys_addr_t addr);
1443 phys_addr_t pci_pio_to_address(unsigned long pio);
1444 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1445 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1446 phys_addr_t phys_addr);
1447 void pci_unmap_iospace(struct resource *res);
1448 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1449 resource_size_t offset,
1450 resource_size_t size);
1451 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1452 struct resource *res);
1453
pci_bus_address(struct pci_dev * pdev,int bar)1454 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1455 {
1456 struct pci_bus_region region;
1457
1458 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1459 return region.start;
1460 }
1461
1462 /* Proper probing supporting hot-pluggable devices */
1463 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1464 const char *mod_name);
1465
1466 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1467 #define pci_register_driver(driver) \
1468 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1469
1470 void pci_unregister_driver(struct pci_driver *dev);
1471
1472 /**
1473 * module_pci_driver() - Helper macro for registering a PCI driver
1474 * @__pci_driver: pci_driver struct
1475 *
1476 * Helper macro for PCI drivers which do not do anything special in module
1477 * init/exit. This eliminates a lot of boilerplate. Each module may only
1478 * use this macro once, and calling it replaces module_init() and module_exit()
1479 */
1480 #define module_pci_driver(__pci_driver) \
1481 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1482
1483 /**
1484 * builtin_pci_driver() - Helper macro for registering a PCI driver
1485 * @__pci_driver: pci_driver struct
1486 *
1487 * Helper macro for PCI drivers which do not do anything special in their
1488 * init code. This eliminates a lot of boilerplate. Each driver may only
1489 * use this macro once, and calling it replaces device_initcall(...)
1490 */
1491 #define builtin_pci_driver(__pci_driver) \
1492 builtin_driver(__pci_driver, pci_register_driver)
1493
1494 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1495 int pci_add_dynid(struct pci_driver *drv,
1496 unsigned int vendor, unsigned int device,
1497 unsigned int subvendor, unsigned int subdevice,
1498 unsigned int class, unsigned int class_mask,
1499 unsigned long driver_data);
1500 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1501 struct pci_dev *dev);
1502 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1503 int pass);
1504
1505 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1506 void *userdata);
1507 int pci_cfg_space_size(struct pci_dev *dev);
1508 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1509 void pci_setup_bridge(struct pci_bus *bus);
1510 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1511 unsigned long type);
1512
1513 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1514 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1515
1516 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1517 unsigned int command_bits, u32 flags);
1518
1519 /*
1520 * Virtual interrupts allow for more interrupts to be allocated
1521 * than the device has interrupts for. These are not programmed
1522 * into the device's MSI-X table and must be handled by some
1523 * other driver means.
1524 */
1525 #define PCI_IRQ_VIRTUAL (1 << 4)
1526
1527 #define PCI_IRQ_ALL_TYPES \
1528 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1529
1530 /* kmem_cache style wrapper around pci_alloc_consistent() */
1531
1532 #include <linux/dmapool.h>
1533
1534 #define pci_pool dma_pool
1535 #define pci_pool_create(name, pdev, size, align, allocation) \
1536 dma_pool_create(name, &pdev->dev, size, align, allocation)
1537 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1538 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1539 #define pci_pool_zalloc(pool, flags, handle) \
1540 dma_pool_zalloc(pool, flags, handle)
1541 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1542
1543 struct msix_entry {
1544 u32 vector; /* Kernel uses to write allocated vector */
1545 u16 entry; /* Driver uses to specify entry, OS writes */
1546 };
1547
1548 #ifdef CONFIG_PCI_MSI
1549 int pci_msi_vec_count(struct pci_dev *dev);
1550 void pci_disable_msi(struct pci_dev *dev);
1551 int pci_msix_vec_count(struct pci_dev *dev);
1552 void pci_disable_msix(struct pci_dev *dev);
1553 void pci_restore_msi_state(struct pci_dev *dev);
1554 int pci_msi_enabled(void);
1555 int pci_enable_msi(struct pci_dev *dev);
1556 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1557 int minvec, int maxvec);
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1558 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1559 struct msix_entry *entries, int nvec)
1560 {
1561 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1562 if (rc < 0)
1563 return rc;
1564 return 0;
1565 }
1566 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1567 unsigned int max_vecs, unsigned int flags,
1568 struct irq_affinity *affd);
1569
1570 void pci_free_irq_vectors(struct pci_dev *dev);
1571 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1572 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1573
1574 #else
pci_msi_vec_count(struct pci_dev * dev)1575 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msi(struct pci_dev * dev)1576 static inline void pci_disable_msi(struct pci_dev *dev) { }
pci_msix_vec_count(struct pci_dev * dev)1577 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msix(struct pci_dev * dev)1578 static inline void pci_disable_msix(struct pci_dev *dev) { }
pci_restore_msi_state(struct pci_dev * dev)1579 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
pci_msi_enabled(void)1580 static inline int pci_msi_enabled(void) { return 0; }
pci_enable_msi(struct pci_dev * dev)1581 static inline int pci_enable_msi(struct pci_dev *dev)
1582 { return -ENOSYS; }
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)1583 static inline int pci_enable_msix_range(struct pci_dev *dev,
1584 struct msix_entry *entries, int minvec, int maxvec)
1585 { return -ENOSYS; }
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1586 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1587 struct msix_entry *entries, int nvec)
1588 { return -ENOSYS; }
1589
1590 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1591 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1592 unsigned int max_vecs, unsigned int flags,
1593 struct irq_affinity *aff_desc)
1594 {
1595 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1596 return 1;
1597 return -ENOSPC;
1598 }
1599
pci_free_irq_vectors(struct pci_dev * dev)1600 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1601 {
1602 }
1603
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1604 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1605 {
1606 if (WARN_ON_ONCE(nr > 0))
1607 return -EINVAL;
1608 return dev->irq;
1609 }
pci_irq_get_affinity(struct pci_dev * pdev,int vec)1610 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1611 int vec)
1612 {
1613 return cpu_possible_mask;
1614 }
1615 #endif
1616
1617 /**
1618 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1619 * @d: the INTx IRQ domain
1620 * @node: the DT node for the device whose interrupt we're translating
1621 * @intspec: the interrupt specifier data from the DT
1622 * @intsize: the number of entries in @intspec
1623 * @out_hwirq: pointer at which to write the hwirq number
1624 * @out_type: pointer at which to write the interrupt type
1625 *
1626 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1627 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1628 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1629 * INTx value to obtain the hwirq number.
1630 *
1631 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1632 */
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1633 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1634 struct device_node *node,
1635 const u32 *intspec,
1636 unsigned int intsize,
1637 unsigned long *out_hwirq,
1638 unsigned int *out_type)
1639 {
1640 const u32 intx = intspec[0];
1641
1642 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1643 return -EINVAL;
1644
1645 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1646 return 0;
1647 }
1648
1649 #ifdef CONFIG_PCIEPORTBUS
1650 extern bool pcie_ports_disabled;
1651 extern bool pcie_ports_native;
1652 #else
1653 #define pcie_ports_disabled true
1654 #define pcie_ports_native false
1655 #endif
1656
1657 #define PCIE_LINK_STATE_L0S BIT(0)
1658 #define PCIE_LINK_STATE_L1 BIT(1)
1659 #define PCIE_LINK_STATE_CLKPM BIT(2)
1660 #define PCIE_LINK_STATE_L1_1 BIT(3)
1661 #define PCIE_LINK_STATE_L1_2 BIT(4)
1662 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1663 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1664
1665 #ifdef CONFIG_PCIEASPM
1666 int pci_disable_link_state(struct pci_dev *pdev, int state);
1667 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1668 void pcie_no_aspm(void);
1669 bool pcie_aspm_support_enabled(void);
1670 bool pcie_aspm_enabled(struct pci_dev *pdev);
1671 #else
pci_disable_link_state(struct pci_dev * pdev,int state)1672 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1673 { return 0; }
pci_disable_link_state_locked(struct pci_dev * pdev,int state)1674 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1675 { return 0; }
pcie_no_aspm(void)1676 static inline void pcie_no_aspm(void) { }
pcie_aspm_support_enabled(void)1677 static inline bool pcie_aspm_support_enabled(void) { return false; }
pcie_aspm_enabled(struct pci_dev * pdev)1678 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1679 #endif
1680
1681 #ifdef CONFIG_PCIEAER
1682 bool pci_aer_available(void);
1683 #else
pci_aer_available(void)1684 static inline bool pci_aer_available(void) { return false; }
1685 #endif
1686
1687 bool pci_ats_disabled(void);
1688
1689 #ifdef CONFIG_PCIE_PTM
1690 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1691 bool pcie_ptm_enabled(struct pci_dev *dev);
1692 #else
pci_enable_ptm(struct pci_dev * dev,u8 * granularity)1693 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1694 { return -EINVAL; }
pcie_ptm_enabled(struct pci_dev * dev)1695 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1696 { return false; }
1697 #endif
1698
1699 void pci_cfg_access_lock(struct pci_dev *dev);
1700 bool pci_cfg_access_trylock(struct pci_dev *dev);
1701 void pci_cfg_access_unlock(struct pci_dev *dev);
1702
1703 int pci_dev_trylock(struct pci_dev *dev);
1704 void pci_dev_unlock(struct pci_dev *dev);
1705
1706 /*
1707 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1708 * a PCI domain is defined to be a set of PCI buses which share
1709 * configuration space.
1710 */
1711 #ifdef CONFIG_PCI_DOMAINS
1712 extern int pci_domains_supported;
1713 #else
1714 enum { pci_domains_supported = 0 };
pci_domain_nr(struct pci_bus * bus)1715 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_proc_domain(struct pci_bus * bus)1716 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1717 #endif /* CONFIG_PCI_DOMAINS */
1718
1719 /*
1720 * Generic implementation for PCI domain support. If your
1721 * architecture does not need custom management of PCI
1722 * domains then this implementation will be used
1723 */
1724 #ifdef CONFIG_PCI_DOMAINS_GENERIC
pci_domain_nr(struct pci_bus * bus)1725 static inline int pci_domain_nr(struct pci_bus *bus)
1726 {
1727 return bus->domain_nr;
1728 }
1729 #ifdef CONFIG_ACPI
1730 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1731 #else
acpi_pci_bus_find_domain_nr(struct pci_bus * bus)1732 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1733 { return 0; }
1734 #endif
1735 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1736 #endif
1737
1738 /* Some architectures require additional setup to direct VGA traffic */
1739 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1740 unsigned int command_bits, u32 flags);
1741 void pci_register_set_vga_state(arch_set_vga_state_t func);
1742
1743 static inline int
pci_request_io_regions(struct pci_dev * pdev,const char * name)1744 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1745 {
1746 return pci_request_selected_regions(pdev,
1747 pci_select_bars(pdev, IORESOURCE_IO), name);
1748 }
1749
1750 static inline void
pci_release_io_regions(struct pci_dev * pdev)1751 pci_release_io_regions(struct pci_dev *pdev)
1752 {
1753 return pci_release_selected_regions(pdev,
1754 pci_select_bars(pdev, IORESOURCE_IO));
1755 }
1756
1757 static inline int
pci_request_mem_regions(struct pci_dev * pdev,const char * name)1758 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1759 {
1760 return pci_request_selected_regions(pdev,
1761 pci_select_bars(pdev, IORESOURCE_MEM), name);
1762 }
1763
1764 static inline void
pci_release_mem_regions(struct pci_dev * pdev)1765 pci_release_mem_regions(struct pci_dev *pdev)
1766 {
1767 return pci_release_selected_regions(pdev,
1768 pci_select_bars(pdev, IORESOURCE_MEM));
1769 }
1770
1771 #else /* CONFIG_PCI is not enabled */
1772
pci_set_flags(int flags)1773 static inline void pci_set_flags(int flags) { }
pci_add_flags(int flags)1774 static inline void pci_add_flags(int flags) { }
pci_clear_flags(int flags)1775 static inline void pci_clear_flags(int flags) { }
pci_has_flag(int flag)1776 static inline int pci_has_flag(int flag) { return 0; }
1777
1778 /*
1779 * If the system does not have PCI, clearly these return errors. Define
1780 * these as simple inline functions to avoid hair in drivers.
1781 */
1782 #define _PCI_NOP(o, s, t) \
1783 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1784 int where, t val) \
1785 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1786
1787 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1788 _PCI_NOP(o, word, u16 x) \
1789 _PCI_NOP(o, dword, u32 x)
1790 _PCI_NOP_ALL(read, *)
1791 _PCI_NOP_ALL(write,)
1792
pci_get_device(unsigned int vendor,unsigned int device,struct pci_dev * from)1793 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1794 unsigned int device,
1795 struct pci_dev *from)
1796 { return NULL; }
1797
pci_get_subsys(unsigned int vendor,unsigned int device,unsigned int ss_vendor,unsigned int ss_device,struct pci_dev * from)1798 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1799 unsigned int device,
1800 unsigned int ss_vendor,
1801 unsigned int ss_device,
1802 struct pci_dev *from)
1803 { return NULL; }
1804
pci_get_class(unsigned int class,struct pci_dev * from)1805 static inline struct pci_dev *pci_get_class(unsigned int class,
1806 struct pci_dev *from)
1807 { return NULL; }
1808
1809 #define pci_dev_present(ids) (0)
1810 #define no_pci_devices() (1)
1811 #define pci_dev_put(dev) do { } while (0)
1812
pci_set_master(struct pci_dev * dev)1813 static inline void pci_set_master(struct pci_dev *dev) { }
pci_clear_master(struct pci_dev * dev)1814 static inline void pci_clear_master(struct pci_dev *dev) { }
pci_enable_device(struct pci_dev * dev)1815 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
pci_disable_device(struct pci_dev * dev)1816 static inline void pci_disable_device(struct pci_dev *dev) { }
pcim_enable_device(struct pci_dev * pdev)1817 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
pci_assign_resource(struct pci_dev * dev,int i)1818 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1819 { return -EBUSY; }
__pci_register_driver(struct pci_driver * drv,struct module * owner,const char * mod_name)1820 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1821 struct module *owner,
1822 const char *mod_name)
1823 { return 0; }
pci_register_driver(struct pci_driver * drv)1824 static inline int pci_register_driver(struct pci_driver *drv)
1825 { return 0; }
pci_unregister_driver(struct pci_driver * drv)1826 static inline void pci_unregister_driver(struct pci_driver *drv) { }
pci_find_capability(struct pci_dev * dev,int cap)1827 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1828 { return 0; }
pci_find_next_capability(struct pci_dev * dev,u8 post,int cap)1829 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1830 int cap)
1831 { return 0; }
pci_find_ext_capability(struct pci_dev * dev,int cap)1832 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1833 { return 0; }
1834
pci_get_dsn(struct pci_dev * dev)1835 static inline u64 pci_get_dsn(struct pci_dev *dev)
1836 { return 0; }
1837
1838 /* Power management related routines */
pci_save_state(struct pci_dev * dev)1839 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
pci_restore_state(struct pci_dev * dev)1840 static inline void pci_restore_state(struct pci_dev *dev) { }
pci_set_power_state(struct pci_dev * dev,pci_power_t state)1841 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1842 { return 0; }
pci_wake_from_d3(struct pci_dev * dev,bool enable)1843 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1844 { return 0; }
pci_choose_state(struct pci_dev * dev,pm_message_t state)1845 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1846 pm_message_t state)
1847 { return PCI_D0; }
pci_enable_wake(struct pci_dev * dev,pci_power_t state,int enable)1848 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1849 int enable)
1850 { return 0; }
1851
pci_find_resource(struct pci_dev * dev,struct resource * res)1852 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1853 struct resource *res)
1854 { return NULL; }
pci_request_regions(struct pci_dev * dev,const char * res_name)1855 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1856 { return -EIO; }
pci_release_regions(struct pci_dev * dev)1857 static inline void pci_release_regions(struct pci_dev *dev) { }
1858
pci_register_io_range(struct fwnode_handle * fwnode,phys_addr_t addr,resource_size_t size)1859 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1860 phys_addr_t addr, resource_size_t size)
1861 { return -EINVAL; }
1862
pci_address_to_pio(phys_addr_t addr)1863 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1864
pci_find_next_bus(const struct pci_bus * from)1865 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1866 { return NULL; }
pci_get_slot(struct pci_bus * bus,unsigned int devfn)1867 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1868 unsigned int devfn)
1869 { return NULL; }
pci_get_domain_bus_and_slot(int domain,unsigned int bus,unsigned int devfn)1870 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1871 unsigned int bus, unsigned int devfn)
1872 { return NULL; }
1873
pci_domain_nr(struct pci_bus * bus)1874 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_dev_get(struct pci_dev * dev)1875 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1876
1877 #define dev_is_pci(d) (false)
1878 #define dev_is_pf(d) (false)
pci_acs_enabled(struct pci_dev * pdev,u16 acs_flags)1879 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1880 { return false; }
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1881 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1882 struct device_node *node,
1883 const u32 *intspec,
1884 unsigned int intsize,
1885 unsigned long *out_hwirq,
1886 unsigned int *out_type)
1887 { return -EINVAL; }
1888
pci_match_id(const struct pci_device_id * ids,struct pci_dev * dev)1889 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1890 struct pci_dev *dev)
1891 { return NULL; }
pci_ats_disabled(void)1892 static inline bool pci_ats_disabled(void) { return true; }
1893
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1894 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1895 {
1896 return -EINVAL;
1897 }
1898
1899 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1900 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1901 unsigned int max_vecs, unsigned int flags,
1902 struct irq_affinity *aff_desc)
1903 {
1904 return -ENOSPC;
1905 }
1906 #endif /* CONFIG_PCI */
1907
1908 static inline int
pci_alloc_irq_vectors(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags)1909 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1910 unsigned int max_vecs, unsigned int flags)
1911 {
1912 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1913 NULL);
1914 }
1915
1916 /* Include architecture-dependent settings and functions */
1917
1918 #include <asm/pci.h>
1919
1920 /* These two functions provide almost identical functionality. Depending
1921 * on the architecture, one will be implemented as a wrapper around the
1922 * other (in drivers/pci/mmap.c).
1923 *
1924 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1925 * is expected to be an offset within that region.
1926 *
1927 * pci_mmap_page_range() is the legacy architecture-specific interface,
1928 * which accepts a "user visible" resource address converted by
1929 * pci_resource_to_user(), as used in the legacy mmap() interface in
1930 * /proc/bus/pci/.
1931 */
1932 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1933 struct vm_area_struct *vma,
1934 enum pci_mmap_state mmap_state, int write_combine);
1935 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1936 struct vm_area_struct *vma,
1937 enum pci_mmap_state mmap_state, int write_combine);
1938
1939 #ifndef arch_can_pci_mmap_wc
1940 #define arch_can_pci_mmap_wc() 0
1941 #endif
1942
1943 #ifndef arch_can_pci_mmap_io
1944 #define arch_can_pci_mmap_io() 0
1945 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1946 #else
1947 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1948 #endif
1949
1950 #ifndef pci_root_bus_fwnode
1951 #define pci_root_bus_fwnode(bus) NULL
1952 #endif
1953
1954 /*
1955 * These helpers provide future and backwards compatibility
1956 * for accessing popular PCI BAR info
1957 */
1958 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1959 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1960 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1961 #define pci_resource_len(dev,bar) \
1962 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \
1963 \
1964 (pci_resource_end((dev), (bar)) - \
1965 pci_resource_start((dev), (bar)) + 1))
1966
1967 /*
1968 * Similar to the helpers above, these manipulate per-pci_dev
1969 * driver-specific data. They are really just a wrapper around
1970 * the generic device structure functions of these calls.
1971 */
pci_get_drvdata(struct pci_dev * pdev)1972 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1973 {
1974 return dev_get_drvdata(&pdev->dev);
1975 }
1976
pci_set_drvdata(struct pci_dev * pdev,void * data)1977 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1978 {
1979 dev_set_drvdata(&pdev->dev, data);
1980 }
1981
pci_name(const struct pci_dev * pdev)1982 static inline const char *pci_name(const struct pci_dev *pdev)
1983 {
1984 return dev_name(&pdev->dev);
1985 }
1986
1987 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1988 const struct resource *rsrc,
1989 resource_size_t *start, resource_size_t *end);
1990
1991 /*
1992 * The world is not perfect and supplies us with broken PCI devices.
1993 * For at least a part of these bugs we need a work-around, so both
1994 * generic (drivers/pci/quirks.c) and per-architecture code can define
1995 * fixup hooks to be called for particular buggy devices.
1996 */
1997
1998 struct pci_fixup {
1999 u16 vendor; /* Or PCI_ANY_ID */
2000 u16 device; /* Or PCI_ANY_ID */
2001 u32 class; /* Or PCI_ANY_ID */
2002 unsigned int class_shift; /* should be 0, 8, 16 */
2003 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2004 int hook_offset;
2005 #else
2006 void (*hook)(struct pci_dev *dev);
2007 #endif
2008 };
2009
2010 enum pci_fixup_pass {
2011 pci_fixup_early, /* Before probing BARs */
2012 pci_fixup_header, /* After reading configuration header */
2013 pci_fixup_final, /* Final phase of device fixups */
2014 pci_fixup_enable, /* pci_enable_device() time */
2015 pci_fixup_resume, /* pci_device_resume() */
2016 pci_fixup_suspend, /* pci_device_suspend() */
2017 pci_fixup_resume_early, /* pci_device_resume_early() */
2018 pci_fixup_suspend_late, /* pci_device_suspend_late() */
2019 };
2020
2021 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2022 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2023 class_shift, hook) \
2024 __ADDRESSABLE(hook) \
2025 asm(".section " #sec ", \"a\" \n" \
2026 ".balign 16 \n" \
2027 ".short " #vendor ", " #device " \n" \
2028 ".long " #class ", " #class_shift " \n" \
2029 ".long " #hook " - . \n" \
2030 ".previous \n");
2031
2032 /*
2033 * Clang's LTO may rename static functions in C, but has no way to
2034 * handle such renamings when referenced from inline asm. To work
2035 * around this, create global C stubs for these cases.
2036 */
2037 #ifdef CONFIG_LTO_CLANG
2038 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2039 class_shift, hook, stub) \
2040 void __cficanonical stub(struct pci_dev *dev); \
2041 void __cficanonical stub(struct pci_dev *dev) \
2042 { \
2043 hook(dev); \
2044 } \
2045 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2046 class_shift, stub)
2047 #else
2048 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2049 class_shift, hook, stub) \
2050 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2051 class_shift, hook)
2052 #endif
2053
2054 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2055 class_shift, hook) \
2056 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2057 class_shift, hook, __UNIQUE_ID(hook))
2058 #else
2059 /* Anonymous variables would be nice... */
2060 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2061 class_shift, hook) \
2062 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2063 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2064 = { vendor, device, class, class_shift, hook };
2065 #endif
2066
2067 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2068 class_shift, hook) \
2069 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2070 hook, vendor, device, class, class_shift, hook)
2071 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2072 class_shift, hook) \
2073 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2074 hook, vendor, device, class, class_shift, hook)
2075 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2076 class_shift, hook) \
2077 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2078 hook, vendor, device, class, class_shift, hook)
2079 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2080 class_shift, hook) \
2081 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2082 hook, vendor, device, class, class_shift, hook)
2083 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2084 class_shift, hook) \
2085 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2086 resume##hook, vendor, device, class, class_shift, hook)
2087 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2088 class_shift, hook) \
2089 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2090 resume_early##hook, vendor, device, class, class_shift, hook)
2091 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2092 class_shift, hook) \
2093 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2094 suspend##hook, vendor, device, class, class_shift, hook)
2095 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2096 class_shift, hook) \
2097 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2098 suspend_late##hook, vendor, device, class, class_shift, hook)
2099
2100 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2101 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2102 hook, vendor, device, PCI_ANY_ID, 0, hook)
2103 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2104 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2105 hook, vendor, device, PCI_ANY_ID, 0, hook)
2106 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2107 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2108 hook, vendor, device, PCI_ANY_ID, 0, hook)
2109 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2110 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2111 hook, vendor, device, PCI_ANY_ID, 0, hook)
2112 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2113 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2114 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2115 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2116 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2117 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2118 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2119 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2120 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2121 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2122 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2123 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2124
2125 #ifdef CONFIG_PCI_QUIRKS
2126 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2127 #else
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)2128 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2129 struct pci_dev *dev) { }
2130 #endif
2131
2132 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2133 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2134 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2135 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2136 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2137 const char *name);
2138 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2139
2140 extern int pci_pci_problems;
2141 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2142 #define PCIPCI_TRITON 2
2143 #define PCIPCI_NATOMA 4
2144 #define PCIPCI_VIAETBF 8
2145 #define PCIPCI_VSFX 16
2146 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2147 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2148
2149 extern unsigned long pci_cardbus_io_size;
2150 extern unsigned long pci_cardbus_mem_size;
2151 extern u8 pci_dfl_cache_line_size;
2152 extern u8 pci_cache_line_size;
2153
2154 /* Architecture-specific versions may override these (weak) */
2155 void pcibios_disable_device(struct pci_dev *dev);
2156 void pcibios_set_master(struct pci_dev *dev);
2157 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2158 enum pcie_reset_state state);
2159 int pcibios_add_device(struct pci_dev *dev);
2160 void pcibios_release_device(struct pci_dev *dev);
2161 #ifdef CONFIG_PCI
2162 void pcibios_penalize_isa_irq(int irq, int active);
2163 #else
pcibios_penalize_isa_irq(int irq,int active)2164 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2165 #endif
2166 int pcibios_alloc_irq(struct pci_dev *dev);
2167 void pcibios_free_irq(struct pci_dev *dev);
2168 resource_size_t pcibios_default_alignment(void);
2169
2170 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2171 void __init pci_mmcfg_early_init(void);
2172 void __init pci_mmcfg_late_init(void);
2173 #else
pci_mmcfg_early_init(void)2174 static inline void pci_mmcfg_early_init(void) { }
pci_mmcfg_late_init(void)2175 static inline void pci_mmcfg_late_init(void) { }
2176 #endif
2177
2178 int pci_ext_cfg_avail(void);
2179
2180 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2181 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2182
2183 #ifdef CONFIG_PCI_IOV
2184 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2185 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2186
2187 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2188 void pci_disable_sriov(struct pci_dev *dev);
2189
2190 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2191 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2192 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2193 int pci_num_vf(struct pci_dev *dev);
2194 int pci_vfs_assigned(struct pci_dev *dev);
2195 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2196 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2197 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2198 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2199 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2200
2201 /* Arch may override these (weak) */
2202 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2203 int pcibios_sriov_disable(struct pci_dev *pdev);
2204 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2205 #else
pci_iov_virtfn_bus(struct pci_dev * dev,int id)2206 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2207 {
2208 return -ENOSYS;
2209 }
pci_iov_virtfn_devfn(struct pci_dev * dev,int id)2210 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2211 {
2212 return -ENOSYS;
2213 }
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)2214 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2215 { return -ENODEV; }
2216
pci_iov_sysfs_link(struct pci_dev * dev,struct pci_dev * virtfn,int id)2217 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2218 struct pci_dev *virtfn, int id)
2219 {
2220 return -ENODEV;
2221 }
pci_iov_add_virtfn(struct pci_dev * dev,int id)2222 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2223 {
2224 return -ENOSYS;
2225 }
pci_iov_remove_virtfn(struct pci_dev * dev,int id)2226 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2227 int id) { }
pci_disable_sriov(struct pci_dev * dev)2228 static inline void pci_disable_sriov(struct pci_dev *dev) { }
pci_num_vf(struct pci_dev * dev)2229 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
pci_vfs_assigned(struct pci_dev * dev)2230 static inline int pci_vfs_assigned(struct pci_dev *dev)
2231 { return 0; }
pci_sriov_set_totalvfs(struct pci_dev * dev,u16 numvfs)2232 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2233 { return 0; }
pci_sriov_get_totalvfs(struct pci_dev * dev)2234 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2235 { return 0; }
2236 #define pci_sriov_configure_simple NULL
pci_iov_resource_size(struct pci_dev * dev,int resno)2237 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2238 { return 0; }
pci_vf_drivers_autoprobe(struct pci_dev * dev,bool probe)2239 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2240 #endif
2241
2242 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2243 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2244 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2245 #endif
2246
2247 /**
2248 * pci_pcie_cap - get the saved PCIe capability offset
2249 * @dev: PCI device
2250 *
2251 * PCIe capability offset is calculated at PCI device initialization
2252 * time and saved in the data structure. This function returns saved
2253 * PCIe capability offset. Using this instead of pci_find_capability()
2254 * reduces unnecessary search in the PCI configuration space. If you
2255 * need to calculate PCIe capability offset from raw device for some
2256 * reasons, please use pci_find_capability() instead.
2257 */
pci_pcie_cap(struct pci_dev * dev)2258 static inline int pci_pcie_cap(struct pci_dev *dev)
2259 {
2260 return dev->pcie_cap;
2261 }
2262
2263 /**
2264 * pci_is_pcie - check if the PCI device is PCI Express capable
2265 * @dev: PCI device
2266 *
2267 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2268 */
pci_is_pcie(struct pci_dev * dev)2269 static inline bool pci_is_pcie(struct pci_dev *dev)
2270 {
2271 return pci_pcie_cap(dev);
2272 }
2273
2274 /**
2275 * pcie_caps_reg - get the PCIe Capabilities Register
2276 * @dev: PCI device
2277 */
pcie_caps_reg(const struct pci_dev * dev)2278 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2279 {
2280 return dev->pcie_flags_reg;
2281 }
2282
2283 /**
2284 * pci_pcie_type - get the PCIe device/port type
2285 * @dev: PCI device
2286 */
pci_pcie_type(const struct pci_dev * dev)2287 static inline int pci_pcie_type(const struct pci_dev *dev)
2288 {
2289 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2290 }
2291
2292 /**
2293 * pcie_find_root_port - Get the PCIe root port device
2294 * @dev: PCI device
2295 *
2296 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2297 * for a given PCI/PCIe Device.
2298 */
pcie_find_root_port(struct pci_dev * dev)2299 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2300 {
2301 while (dev) {
2302 if (pci_is_pcie(dev) &&
2303 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2304 return dev;
2305 dev = pci_upstream_bridge(dev);
2306 }
2307
2308 return NULL;
2309 }
2310
2311 void pci_request_acs(void);
2312 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2313 bool pci_acs_path_enabled(struct pci_dev *start,
2314 struct pci_dev *end, u16 acs_flags);
2315 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2316
2317 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2318 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2319
2320 /* Large Resource Data Type Tag Item Names */
2321 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2322 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2323 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2324
2325 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2326 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2327 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2328
2329 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2330 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2331 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2332 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2333 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2334
2335 /**
2336 * pci_vpd_alloc - Allocate buffer and read VPD into it
2337 * @dev: PCI device
2338 * @size: pointer to field where VPD length is returned
2339 *
2340 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2341 */
2342 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2343
2344 /**
2345 * pci_vpd_find_id_string - Locate id string in VPD
2346 * @buf: Pointer to buffered VPD data
2347 * @len: The length of the buffer area in which to search
2348 * @size: Pointer to field where length of id string is returned
2349 *
2350 * Returns the index of the id string or -ENOENT if not found.
2351 */
2352 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2353
2354 /**
2355 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2356 * @buf: Pointer to buffered VPD data
2357 * @len: The length of the buffer area in which to search
2358 * @kw: The keyword to search for
2359 * @size: Pointer to field where length of found keyword data is returned
2360 *
2361 * Returns the index of the information field keyword data or -ENOENT if
2362 * not found.
2363 */
2364 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2365 const char *kw, unsigned int *size);
2366
2367 /**
2368 * pci_vpd_check_csum - Check VPD checksum
2369 * @buf: Pointer to buffered VPD data
2370 * @len: VPD size
2371 *
2372 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2373 */
2374 int pci_vpd_check_csum(const void *buf, unsigned int len);
2375
2376 /* PCI <-> OF binding helpers */
2377 #ifdef CONFIG_OF
2378 struct device_node;
2379 struct irq_domain;
2380 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2381 bool pci_host_of_has_msi_map(struct device *dev);
2382
2383 /* Arch may override this (weak) */
2384 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2385
2386 #else /* CONFIG_OF */
2387 static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus * bus)2388 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
pci_host_of_has_msi_map(struct device * dev)2389 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2390 #endif /* CONFIG_OF */
2391
2392 static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev * pdev)2393 pci_device_to_OF_node(const struct pci_dev *pdev)
2394 {
2395 return pdev ? pdev->dev.of_node : NULL;
2396 }
2397
pci_bus_to_OF_node(struct pci_bus * bus)2398 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2399 {
2400 return bus ? bus->dev.of_node : NULL;
2401 }
2402
2403 #ifdef CONFIG_ACPI
2404 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2405
2406 void
2407 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2408 bool pci_pr3_present(struct pci_dev *pdev);
2409 #else
2410 static inline struct irq_domain *
pci_host_bridge_acpi_msi_domain(struct pci_bus * bus)2411 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
pci_pr3_present(struct pci_dev * pdev)2412 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2413 #endif
2414
2415 #ifdef CONFIG_EEH
pci_dev_to_eeh_dev(struct pci_dev * pdev)2416 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2417 {
2418 return pdev->dev.archdata.edev;
2419 }
2420 #endif
2421
2422 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2423 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2424 int pci_for_each_dma_alias(struct pci_dev *pdev,
2425 int (*fn)(struct pci_dev *pdev,
2426 u16 alias, void *data), void *data);
2427
2428 /* Helper functions for operation of device flag */
pci_set_dev_assigned(struct pci_dev * pdev)2429 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2430 {
2431 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2432 }
pci_clear_dev_assigned(struct pci_dev * pdev)2433 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2434 {
2435 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2436 }
pci_is_dev_assigned(struct pci_dev * pdev)2437 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2438 {
2439 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2440 }
2441
2442 /**
2443 * pci_ari_enabled - query ARI forwarding status
2444 * @bus: the PCI bus
2445 *
2446 * Returns true if ARI forwarding is enabled.
2447 */
pci_ari_enabled(struct pci_bus * bus)2448 static inline bool pci_ari_enabled(struct pci_bus *bus)
2449 {
2450 return bus->self && bus->self->ari_enabled;
2451 }
2452
2453 /**
2454 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2455 * @pdev: PCI device to check
2456 *
2457 * Walk upwards from @pdev and check for each encountered bridge if it's part
2458 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2459 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2460 */
pci_is_thunderbolt_attached(struct pci_dev * pdev)2461 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2462 {
2463 struct pci_dev *parent = pdev;
2464
2465 if (pdev->is_thunderbolt)
2466 return true;
2467
2468 while ((parent = pci_upstream_bridge(parent)))
2469 if (parent->is_thunderbolt)
2470 return true;
2471
2472 return false;
2473 }
2474
2475 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2476 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2477 #endif
2478
2479 /* Provide the legacy pci_dma_* API */
2480 #include <linux/pci-dma-compat.h>
2481
2482 #define pci_printk(level, pdev, fmt, arg...) \
2483 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2484
2485 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2486 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2487 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2488 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2489 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2490 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2491 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2492 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2493
2494 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2495 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2496
2497 #define pci_info_ratelimited(pdev, fmt, arg...) \
2498 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2499
2500 #define pci_WARN(pdev, condition, fmt, arg...) \
2501 WARN(condition, "%s %s: " fmt, \
2502 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2503
2504 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2505 WARN_ONCE(condition, "%s %s: " fmt, \
2506 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2507
2508 #endif /* LINUX_PCI_H */
2509