1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #ifndef __SOC_TEGRA_FUSE_H__
7 #define __SOC_TEGRA_FUSE_H__
8
9 #define TEGRA20 0x20
10 #define TEGRA30 0x30
11 #define TEGRA114 0x35
12 #define TEGRA124 0x40
13 #define TEGRA132 0x13
14 #define TEGRA210 0x21
15 #define TEGRA186 0x18
16 #define TEGRA194 0x19
17 #define TEGRA234 0x23
18
19 #define TEGRA_FUSE_SKU_CALIB_0 0xf0
20 #define TEGRA30_FUSE_SATA_CALIB 0x124
21 #define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
22
23 #ifndef __ASSEMBLY__
24
25 u32 tegra_read_chipid(void);
26 u8 tegra_get_chip_id(void);
27 u8 tegra_get_platform(void);
28 bool tegra_is_silicon(void);
29
30 enum tegra_revision {
31 TEGRA_REVISION_UNKNOWN = 0,
32 TEGRA_REVISION_A01,
33 TEGRA_REVISION_A02,
34 TEGRA_REVISION_A03,
35 TEGRA_REVISION_A03p,
36 TEGRA_REVISION_A04,
37 TEGRA_REVISION_MAX,
38 };
39
40 struct tegra_sku_info {
41 int sku_id;
42 int cpu_process_id;
43 int cpu_speedo_id;
44 int cpu_speedo_value;
45 int cpu_iddq_value;
46 int soc_process_id;
47 int soc_speedo_id;
48 int soc_speedo_value;
49 int gpu_process_id;
50 int gpu_speedo_id;
51 int gpu_speedo_value;
52 enum tegra_revision revision;
53 };
54
55 #ifdef CONFIG_ARCH_TEGRA
56 extern struct tegra_sku_info tegra_sku_info;
57 u32 tegra_read_straps(void);
58 u32 tegra_read_ram_code(void);
59 int tegra_fuse_readl(unsigned long offset, u32 *value);
60 #else
61 static struct tegra_sku_info tegra_sku_info __maybe_unused;
62
tegra_read_straps(void)63 static inline u32 tegra_read_straps(void)
64 {
65 return 0;
66 }
67
tegra_read_ram_code(void)68 static inline u32 tegra_read_ram_code(void)
69 {
70 return 0;
71 }
72
tegra_fuse_readl(unsigned long offset,u32 * value)73 static inline int tegra_fuse_readl(unsigned long offset, u32 *value)
74 {
75 return -ENODEV;
76 }
77 #endif
78
79 struct device *tegra_soc_device_register(void);
80
81 #endif /* __ASSEMBLY__ */
82
83 #endif /* __SOC_TEGRA_FUSE_H__ */
84