1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mm-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8mm-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec1; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 gpio4 = &gpio5; 26 i2c0 = &i2c1; 27 i2c1 = &i2c2; 28 i2c2 = &i2c3; 29 i2c3 = &i2c4; 30 mmc0 = &usdhc1; 31 mmc1 = &usdhc2; 32 mmc2 = &usdhc3; 33 serial0 = &uart1; 34 serial1 = &uart2; 35 serial2 = &uart3; 36 serial3 = &uart4; 37 spi0 = &ecspi1; 38 spi1 = &ecspi2; 39 spi2 = &ecspi3; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 idle-states { 47 entry-method = "psci"; 48 49 cpu_pd_wait: cpu-pd-wait { 50 compatible = "arm,idle-state"; 51 arm,psci-suspend-param = <0x0010033>; 52 local-timer-stop; 53 entry-latency-us = <1000>; 54 exit-latency-us = <700>; 55 min-residency-us = <2700>; 56 }; 57 }; 58 59 A53_0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0>; 63 clock-latency = <61036>; /* two CLK32 periods */ 64 clocks = <&clk IMX8MM_CLK_ARM>; 65 enable-method = "psci"; 66 next-level-cache = <&A53_L2>; 67 operating-points-v2 = <&a53_opp_table>; 68 nvmem-cells = <&cpu_speed_grade>; 69 nvmem-cell-names = "speed_grade"; 70 cpu-idle-states = <&cpu_pd_wait>; 71 #cooling-cells = <2>; 72 }; 73 74 A53_1: cpu@1 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x1>; 78 clock-latency = <61036>; /* two CLK32 periods */ 79 clocks = <&clk IMX8MM_CLK_ARM>; 80 enable-method = "psci"; 81 next-level-cache = <&A53_L2>; 82 operating-points-v2 = <&a53_opp_table>; 83 cpu-idle-states = <&cpu_pd_wait>; 84 #cooling-cells = <2>; 85 }; 86 87 A53_2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x2>; 91 clock-latency = <61036>; /* two CLK32 periods */ 92 clocks = <&clk IMX8MM_CLK_ARM>; 93 enable-method = "psci"; 94 next-level-cache = <&A53_L2>; 95 operating-points-v2 = <&a53_opp_table>; 96 cpu-idle-states = <&cpu_pd_wait>; 97 #cooling-cells = <2>; 98 }; 99 100 A53_3: cpu@3 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x3>; 104 clock-latency = <61036>; /* two CLK32 periods */ 105 clocks = <&clk IMX8MM_CLK_ARM>; 106 enable-method = "psci"; 107 next-level-cache = <&A53_L2>; 108 operating-points-v2 = <&a53_opp_table>; 109 cpu-idle-states = <&cpu_pd_wait>; 110 #cooling-cells = <2>; 111 }; 112 113 A53_L2: l2-cache0 { 114 compatible = "cache"; 115 }; 116 }; 117 118 a53_opp_table: opp-table { 119 compatible = "operating-points-v2"; 120 opp-shared; 121 122 opp-1200000000 { 123 opp-hz = /bits/ 64 <1200000000>; 124 opp-microvolt = <850000>; 125 opp-supported-hw = <0xe>, <0x7>; 126 clock-latency-ns = <150000>; 127 opp-suspend; 128 }; 129 130 opp-1600000000 { 131 opp-hz = /bits/ 64 <1600000000>; 132 opp-microvolt = <950000>; 133 opp-supported-hw = <0xc>, <0x7>; 134 clock-latency-ns = <150000>; 135 opp-suspend; 136 }; 137 138 opp-1800000000 { 139 opp-hz = /bits/ 64 <1800000000>; 140 opp-microvolt = <1000000>; 141 opp-supported-hw = <0x8>, <0x3>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 }; 146 147 osc_32k: clock-osc-32k { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 clock-frequency = <32768>; 151 clock-output-names = "osc_32k"; 152 }; 153 154 osc_24m: clock-osc-24m { 155 compatible = "fixed-clock"; 156 #clock-cells = <0>; 157 clock-frequency = <24000000>; 158 clock-output-names = "osc_24m"; 159 }; 160 161 clk_ext1: clock-ext1 { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-frequency = <133000000>; 165 clock-output-names = "clk_ext1"; 166 }; 167 168 clk_ext2: clock-ext2 { 169 compatible = "fixed-clock"; 170 #clock-cells = <0>; 171 clock-frequency = <133000000>; 172 clock-output-names = "clk_ext2"; 173 }; 174 175 clk_ext3: clock-ext3 { 176 compatible = "fixed-clock"; 177 #clock-cells = <0>; 178 clock-frequency = <133000000>; 179 clock-output-names = "clk_ext3"; 180 }; 181 182 clk_ext4: clock-ext4 { 183 compatible = "fixed-clock"; 184 #clock-cells = <0>; 185 clock-frequency= <133000000>; 186 clock-output-names = "clk_ext4"; 187 }; 188 189 psci { 190 compatible = "arm,psci-1.0"; 191 method = "smc"; 192 }; 193 194 pmu { 195 compatible = "arm,cortex-a53-pmu"; 196 interrupts = <GIC_PPI 7 197 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 198 }; 199 200 timer { 201 compatible = "arm,armv8-timer"; 202 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 203 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 204 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 205 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 206 clock-frequency = <8000000>; 207 arm,no-tick-in-suspend; 208 }; 209 210 thermal-zones { 211 cpu-thermal { 212 polling-delay-passive = <250>; 213 polling-delay = <2000>; 214 thermal-sensors = <&tmu>; 215 trips { 216 cpu_alert0: trip0 { 217 temperature = <85000>; 218 hysteresis = <2000>; 219 type = "passive"; 220 }; 221 222 cpu_crit0: trip1 { 223 temperature = <95000>; 224 hysteresis = <2000>; 225 type = "critical"; 226 }; 227 }; 228 229 cooling-maps { 230 map0 { 231 trip = <&cpu_alert0>; 232 cooling-device = 233 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 234 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 235 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 236 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 237 }; 238 }; 239 }; 240 }; 241 242 usbphynop1: usbphynop1 { 243 #phy-cells = <0>; 244 compatible = "usb-nop-xceiv"; 245 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 246 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 247 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 248 clock-names = "main_clk"; 249 }; 250 251 usbphynop2: usbphynop2 { 252 #phy-cells = <0>; 253 compatible = "usb-nop-xceiv"; 254 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 255 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 256 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 257 clock-names = "main_clk"; 258 }; 259 260 soc@0 { 261 compatible = "fsl,imx8mm-soc", "simple-bus"; 262 #address-cells = <1>; 263 #size-cells = <1>; 264 ranges = <0x0 0x0 0x0 0x3e000000>; 265 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 266 nvmem-cells = <&imx8mm_uid>; 267 nvmem-cell-names = "soc_unique_id"; 268 269 aips1: bus@30000000 { 270 compatible = "fsl,aips-bus", "simple-bus"; 271 reg = <0x30000000 0x400000>; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 ranges = <0x30000000 0x30000000 0x400000>; 275 276 spba2: spba-bus@30000000 { 277 compatible = "fsl,spba-bus", "simple-bus"; 278 #address-cells = <1>; 279 #size-cells = <1>; 280 reg = <0x30000000 0x100000>; 281 ranges; 282 283 sai1: sai@30010000 { 284 #sound-dai-cells = <0>; 285 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 286 reg = <0x30010000 0x10000>; 287 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 289 <&clk IMX8MM_CLK_SAI1_ROOT>, 290 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 291 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 292 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 293 dma-names = "rx", "tx"; 294 status = "disabled"; 295 }; 296 297 sai2: sai@30020000 { 298 #sound-dai-cells = <0>; 299 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 300 reg = <0x30020000 0x10000>; 301 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&clk IMX8MM_CLK_SAI2_IPG>, 303 <&clk IMX8MM_CLK_SAI2_ROOT>, 304 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 305 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 306 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 307 dma-names = "rx", "tx"; 308 status = "disabled"; 309 }; 310 311 sai3: sai@30030000 { 312 #sound-dai-cells = <0>; 313 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 314 reg = <0x30030000 0x10000>; 315 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&clk IMX8MM_CLK_SAI3_IPG>, 317 <&clk IMX8MM_CLK_SAI3_ROOT>, 318 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 319 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 320 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 321 dma-names = "rx", "tx"; 322 status = "disabled"; 323 }; 324 325 sai5: sai@30050000 { 326 #sound-dai-cells = <0>; 327 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 328 reg = <0x30050000 0x10000>; 329 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&clk IMX8MM_CLK_SAI5_IPG>, 331 <&clk IMX8MM_CLK_SAI5_ROOT>, 332 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 333 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 334 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 335 dma-names = "rx", "tx"; 336 status = "disabled"; 337 }; 338 339 sai6: sai@30060000 { 340 #sound-dai-cells = <0>; 341 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 342 reg = <0x30060000 0x10000>; 343 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&clk IMX8MM_CLK_SAI6_IPG>, 345 <&clk IMX8MM_CLK_SAI6_ROOT>, 346 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 347 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 348 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 349 dma-names = "rx", "tx"; 350 status = "disabled"; 351 }; 352 353 micfil: audio-controller@30080000 { 354 compatible = "fsl,imx8mm-micfil"; 355 reg = <0x30080000 0x10000>; 356 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&clk IMX8MM_CLK_PDM_IPG>, 361 <&clk IMX8MM_CLK_PDM_ROOT>, 362 <&clk IMX8MM_AUDIO_PLL1_OUT>, 363 <&clk IMX8MM_AUDIO_PLL2_OUT>, 364 <&clk IMX8MM_CLK_EXT3>; 365 clock-names = "ipg_clk", "ipg_clk_app", 366 "pll8k", "pll11k", "clkext3"; 367 dmas = <&sdma2 24 25 0x80000000>; 368 dma-names = "rx"; 369 #sound-dai-cells = <0>; 370 status = "disabled"; 371 }; 372 373 spdif1: spdif@30090000 { 374 compatible = "fsl,imx35-spdif"; 375 reg = <0x30090000 0x10000>; 376 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ 378 <&clk IMX8MM_CLK_24M>, /* rxtx0 */ 379 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ 380 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ 381 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ 382 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ 383 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ 384 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ 385 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ 386 <&clk IMX8MM_CLK_DUMMY>; /* spba */ 387 clock-names = "core", "rxtx0", 388 "rxtx1", "rxtx2", 389 "rxtx3", "rxtx4", 390 "rxtx5", "rxtx6", 391 "rxtx7", "spba"; 392 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 393 dma-names = "rx", "tx"; 394 status = "disabled"; 395 }; 396 }; 397 398 gpio1: gpio@30200000 { 399 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 400 reg = <0x30200000 0x10000>; 401 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; 404 gpio-controller; 405 #gpio-cells = <2>; 406 interrupt-controller; 407 #interrupt-cells = <2>; 408 gpio-ranges = <&iomuxc 0 10 30>; 409 }; 410 411 gpio2: gpio@30210000 { 412 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 413 reg = <0x30210000 0x10000>; 414 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; 417 gpio-controller; 418 #gpio-cells = <2>; 419 interrupt-controller; 420 #interrupt-cells = <2>; 421 gpio-ranges = <&iomuxc 0 40 21>; 422 }; 423 424 gpio3: gpio@30220000 { 425 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 426 reg = <0x30220000 0x10000>; 427 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; 430 gpio-controller; 431 #gpio-cells = <2>; 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 gpio-ranges = <&iomuxc 0 61 26>; 435 }; 436 437 gpio4: gpio@30230000 { 438 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 439 reg = <0x30230000 0x10000>; 440 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; 443 gpio-controller; 444 #gpio-cells = <2>; 445 interrupt-controller; 446 #interrupt-cells = <2>; 447 gpio-ranges = <&iomuxc 0 87 32>; 448 }; 449 450 gpio5: gpio@30240000 { 451 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 452 reg = <0x30240000 0x10000>; 453 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; 456 gpio-controller; 457 #gpio-cells = <2>; 458 interrupt-controller; 459 #interrupt-cells = <2>; 460 gpio-ranges = <&iomuxc 0 119 30>; 461 }; 462 463 tmu: tmu@30260000 { 464 compatible = "fsl,imx8mm-tmu"; 465 reg = <0x30260000 0x10000>; 466 clocks = <&clk IMX8MM_CLK_TMU_ROOT>; 467 #thermal-sensor-cells = <0>; 468 }; 469 470 wdog1: watchdog@30280000 { 471 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 472 reg = <0x30280000 0x10000>; 473 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; 475 status = "disabled"; 476 }; 477 478 wdog2: watchdog@30290000 { 479 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 480 reg = <0x30290000 0x10000>; 481 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; 483 status = "disabled"; 484 }; 485 486 wdog3: watchdog@302a0000 { 487 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 488 reg = <0x302a0000 0x10000>; 489 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; 491 status = "disabled"; 492 }; 493 494 sdma2: dma-controller@302c0000 { 495 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 496 reg = <0x302c0000 0x10000>; 497 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, 499 <&clk IMX8MM_CLK_SDMA2_ROOT>; 500 clock-names = "ipg", "ahb"; 501 #dma-cells = <3>; 502 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 503 }; 504 505 sdma3: dma-controller@302b0000 { 506 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 507 reg = <0x302b0000 0x10000>; 508 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, 510 <&clk IMX8MM_CLK_SDMA3_ROOT>; 511 clock-names = "ipg", "ahb"; 512 #dma-cells = <3>; 513 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 514 }; 515 516 iomuxc: pinctrl@30330000 { 517 compatible = "fsl,imx8mm-iomuxc"; 518 reg = <0x30330000 0x10000>; 519 }; 520 521 gpr: iomuxc-gpr@30340000 { 522 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; 523 reg = <0x30340000 0x10000>; 524 }; 525 526 ocotp: efuse@30350000 { 527 compatible = "fsl,imx8mm-ocotp", "syscon"; 528 reg = <0x30350000 0x10000>; 529 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; 530 /* For nvmem subnodes */ 531 #address-cells = <1>; 532 #size-cells = <1>; 533 534 imx8mm_uid: unique-id@4 { 535 reg = <0x4 0x8>; 536 }; 537 538 cpu_speed_grade: speed-grade@10 { 539 reg = <0x10 4>; 540 }; 541 542 fec_mac_address: mac-address@90 { 543 reg = <0x90 6>; 544 }; 545 }; 546 547 anatop: anatop@30360000 { 548 compatible = "fsl,imx8mm-anatop", "syscon"; 549 reg = <0x30360000 0x10000>; 550 }; 551 552 snvs: snvs@30370000 { 553 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 554 reg = <0x30370000 0x10000>; 555 556 snvs_rtc: snvs-rtc-lp { 557 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 558 regmap = <&snvs>; 559 offset = <0x34>; 560 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 563 clock-names = "snvs-rtc"; 564 }; 565 566 snvs_pwrkey: snvs-powerkey { 567 compatible = "fsl,sec-v4.0-pwrkey"; 568 regmap = <&snvs>; 569 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 571 clock-names = "snvs-pwrkey"; 572 linux,keycode = <KEY_POWER>; 573 wakeup-source; 574 status = "disabled"; 575 }; 576 }; 577 578 clk: clock-controller@30380000 { 579 compatible = "fsl,imx8mm-ccm"; 580 reg = <0x30380000 0x10000>; 581 #clock-cells = <1>; 582 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 583 <&clk_ext3>, <&clk_ext4>; 584 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 585 "clk_ext3", "clk_ext4"; 586 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, 587 <&clk IMX8MM_CLK_A53_CORE>, 588 <&clk IMX8MM_CLK_NOC>, 589 <&clk IMX8MM_CLK_AUDIO_AHB>, 590 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, 591 <&clk IMX8MM_SYS_PLL3>, 592 <&clk IMX8MM_VIDEO_PLL1>, 593 <&clk IMX8MM_AUDIO_PLL1>, 594 <&clk IMX8MM_AUDIO_PLL2>; 595 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, 596 <&clk IMX8MM_ARM_PLL_OUT>, 597 <&clk IMX8MM_SYS_PLL3_OUT>, 598 <&clk IMX8MM_SYS_PLL1_800M>; 599 assigned-clock-rates = <0>, <0>, <0>, 600 <400000000>, 601 <400000000>, 602 <750000000>, 603 <594000000>, 604 <393216000>, 605 <361267200>; 606 }; 607 608 src: reset-controller@30390000 { 609 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; 610 reg = <0x30390000 0x10000>; 611 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 612 #reset-cells = <1>; 613 }; 614 }; 615 616 aips2: bus@30400000 { 617 compatible = "fsl,aips-bus", "simple-bus"; 618 reg = <0x30400000 0x400000>; 619 #address-cells = <1>; 620 #size-cells = <1>; 621 ranges = <0x30400000 0x30400000 0x400000>; 622 623 pwm1: pwm@30660000 { 624 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 625 reg = <0x30660000 0x10000>; 626 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, 628 <&clk IMX8MM_CLK_PWM1_ROOT>; 629 clock-names = "ipg", "per"; 630 #pwm-cells = <2>; 631 status = "disabled"; 632 }; 633 634 pwm2: pwm@30670000 { 635 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 636 reg = <0x30670000 0x10000>; 637 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, 639 <&clk IMX8MM_CLK_PWM2_ROOT>; 640 clock-names = "ipg", "per"; 641 #pwm-cells = <2>; 642 status = "disabled"; 643 }; 644 645 pwm3: pwm@30680000 { 646 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 647 reg = <0x30680000 0x10000>; 648 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, 650 <&clk IMX8MM_CLK_PWM3_ROOT>; 651 clock-names = "ipg", "per"; 652 #pwm-cells = <2>; 653 status = "disabled"; 654 }; 655 656 pwm4: pwm@30690000 { 657 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 658 reg = <0x30690000 0x10000>; 659 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, 661 <&clk IMX8MM_CLK_PWM4_ROOT>; 662 clock-names = "ipg", "per"; 663 #pwm-cells = <2>; 664 status = "disabled"; 665 }; 666 667 system_counter: timer@306a0000 { 668 compatible = "nxp,sysctr-timer"; 669 reg = <0x306a0000 0x20000>; 670 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&osc_24m>; 672 clock-names = "per"; 673 }; 674 }; 675 676 aips3: bus@30800000 { 677 compatible = "fsl,aips-bus", "simple-bus"; 678 reg = <0x30800000 0x400000>; 679 #address-cells = <1>; 680 #size-cells = <1>; 681 ranges = <0x30800000 0x30800000 0x400000>, 682 <0x8000000 0x8000000 0x10000000>; 683 684 spba1: spba-bus@30800000 { 685 compatible = "fsl,spba-bus", "simple-bus"; 686 #address-cells = <1>; 687 #size-cells = <1>; 688 reg = <0x30800000 0x100000>; 689 ranges; 690 691 ecspi1: spi@30820000 { 692 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 reg = <0x30820000 0x10000>; 696 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, 698 <&clk IMX8MM_CLK_ECSPI1_ROOT>; 699 clock-names = "ipg", "per"; 700 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 701 dma-names = "rx", "tx"; 702 status = "disabled"; 703 }; 704 705 ecspi2: spi@30830000 { 706 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 reg = <0x30830000 0x10000>; 710 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, 712 <&clk IMX8MM_CLK_ECSPI2_ROOT>; 713 clock-names = "ipg", "per"; 714 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 715 dma-names = "rx", "tx"; 716 status = "disabled"; 717 }; 718 719 ecspi3: spi@30840000 { 720 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 reg = <0x30840000 0x10000>; 724 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, 726 <&clk IMX8MM_CLK_ECSPI3_ROOT>; 727 clock-names = "ipg", "per"; 728 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 729 dma-names = "rx", "tx"; 730 status = "disabled"; 731 }; 732 733 uart1: serial@30860000 { 734 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 735 reg = <0x30860000 0x10000>; 736 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&clk IMX8MM_CLK_UART1_ROOT>, 738 <&clk IMX8MM_CLK_UART1_ROOT>; 739 clock-names = "ipg", "per"; 740 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 741 dma-names = "rx", "tx"; 742 status = "disabled"; 743 }; 744 745 uart3: serial@30880000 { 746 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 747 reg = <0x30880000 0x10000>; 748 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&clk IMX8MM_CLK_UART3_ROOT>, 750 <&clk IMX8MM_CLK_UART3_ROOT>; 751 clock-names = "ipg", "per"; 752 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 753 dma-names = "rx", "tx"; 754 status = "disabled"; 755 }; 756 757 uart2: serial@30890000 { 758 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 759 reg = <0x30890000 0x10000>; 760 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&clk IMX8MM_CLK_UART2_ROOT>, 762 <&clk IMX8MM_CLK_UART2_ROOT>; 763 clock-names = "ipg", "per"; 764 status = "disabled"; 765 }; 766 }; 767 768 crypto: crypto@30900000 { 769 compatible = "fsl,sec-v4.0"; 770 #address-cells = <1>; 771 #size-cells = <1>; 772 reg = <0x30900000 0x40000>; 773 ranges = <0 0x30900000 0x40000>; 774 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&clk IMX8MM_CLK_AHB>, 776 <&clk IMX8MM_CLK_IPG_ROOT>; 777 clock-names = "aclk", "ipg"; 778 779 sec_jr0: jr@1000 { 780 compatible = "fsl,sec-v4.0-job-ring"; 781 reg = <0x1000 0x1000>; 782 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 783 }; 784 785 sec_jr1: jr@2000 { 786 compatible = "fsl,sec-v4.0-job-ring"; 787 reg = <0x2000 0x1000>; 788 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 789 }; 790 791 sec_jr2: jr@3000 { 792 compatible = "fsl,sec-v4.0-job-ring"; 793 reg = <0x3000 0x1000>; 794 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 795 }; 796 }; 797 798 i2c1: i2c@30a20000 { 799 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 reg = <0x30a20000 0x10000>; 803 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; 805 status = "disabled"; 806 }; 807 808 i2c2: i2c@30a30000 { 809 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 reg = <0x30a30000 0x10000>; 813 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; 815 status = "disabled"; 816 }; 817 818 i2c3: i2c@30a40000 { 819 #address-cells = <1>; 820 #size-cells = <0>; 821 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 822 reg = <0x30a40000 0x10000>; 823 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; 825 status = "disabled"; 826 }; 827 828 i2c4: i2c@30a50000 { 829 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 reg = <0x30a50000 0x10000>; 833 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 834 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; 835 status = "disabled"; 836 }; 837 838 uart4: serial@30a60000 { 839 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 840 reg = <0x30a60000 0x10000>; 841 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&clk IMX8MM_CLK_UART4_ROOT>, 843 <&clk IMX8MM_CLK_UART4_ROOT>; 844 clock-names = "ipg", "per"; 845 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 846 dma-names = "rx", "tx"; 847 status = "disabled"; 848 }; 849 850 mu: mailbox@30aa0000 { 851 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; 852 reg = <0x30aa0000 0x10000>; 853 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&clk IMX8MM_CLK_MU_ROOT>; 855 #mbox-cells = <2>; 856 }; 857 858 usdhc1: mmc@30b40000 { 859 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 860 reg = <0x30b40000 0x10000>; 861 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 863 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 864 <&clk IMX8MM_CLK_USDHC1_ROOT>; 865 clock-names = "ipg", "ahb", "per"; 866 fsl,tuning-start-tap = <20>; 867 fsl,tuning-step= <2>; 868 bus-width = <4>; 869 status = "disabled"; 870 }; 871 872 usdhc2: mmc@30b50000 { 873 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 874 reg = <0x30b50000 0x10000>; 875 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 877 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 878 <&clk IMX8MM_CLK_USDHC2_ROOT>; 879 clock-names = "ipg", "ahb", "per"; 880 fsl,tuning-start-tap = <20>; 881 fsl,tuning-step= <2>; 882 bus-width = <4>; 883 status = "disabled"; 884 }; 885 886 usdhc3: mmc@30b60000 { 887 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 888 reg = <0x30b60000 0x10000>; 889 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 891 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 892 <&clk IMX8MM_CLK_USDHC3_ROOT>; 893 clock-names = "ipg", "ahb", "per"; 894 fsl,tuning-start-tap = <20>; 895 fsl,tuning-step= <2>; 896 bus-width = <4>; 897 status = "disabled"; 898 }; 899 900 flexspi: spi@30bb0000 { 901 #address-cells = <1>; 902 #size-cells = <0>; 903 compatible = "nxp,imx8mm-fspi"; 904 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 905 reg-names = "fspi_base", "fspi_mmap"; 906 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, 908 <&clk IMX8MM_CLK_QSPI_ROOT>; 909 clock-names = "fspi_en", "fspi"; 910 status = "disabled"; 911 }; 912 913 sdma1: dma-controller@30bd0000 { 914 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 915 reg = <0x30bd0000 0x10000>; 916 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 917 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, 918 <&clk IMX8MM_CLK_AHB>; 919 clock-names = "ipg", "ahb"; 920 #dma-cells = <3>; 921 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 922 }; 923 924 fec1: ethernet@30be0000 { 925 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 926 reg = <0x30be0000 0x10000>; 927 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, 932 <&clk IMX8MM_CLK_ENET1_ROOT>, 933 <&clk IMX8MM_CLK_ENET_TIMER>, 934 <&clk IMX8MM_CLK_ENET_REF>, 935 <&clk IMX8MM_CLK_ENET_PHY_REF>; 936 clock-names = "ipg", "ahb", "ptp", 937 "enet_clk_ref", "enet_out"; 938 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, 939 <&clk IMX8MM_CLK_ENET_TIMER>, 940 <&clk IMX8MM_CLK_ENET_REF>, 941 <&clk IMX8MM_CLK_ENET_PHY_REF>; 942 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 943 <&clk IMX8MM_SYS_PLL2_100M>, 944 <&clk IMX8MM_SYS_PLL2_125M>, 945 <&clk IMX8MM_SYS_PLL2_50M>; 946 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 947 fsl,num-tx-queues = <3>; 948 fsl,num-rx-queues = <3>; 949 nvmem-cells = <&fec_mac_address>; 950 nvmem-cell-names = "mac-address"; 951 nvmem_macaddr_swap; 952 fsl,stop-mode = <&gpr 0x10 3>; 953 status = "disabled"; 954 }; 955 956 }; 957 958 aips4: bus@32c00000 { 959 compatible = "fsl,aips-bus", "simple-bus"; 960 reg = <0x32c00000 0x400000>; 961 #address-cells = <1>; 962 #size-cells = <1>; 963 ranges = <0x32c00000 0x32c00000 0x400000>; 964 965 usbotg1: usb@32e40000 { 966 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 967 reg = <0x32e40000 0x200>; 968 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 970 clock-names = "usb1_ctrl_root_clk"; 971 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 972 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 973 phys = <&usbphynop1>; 974 fsl,usbmisc = <&usbmisc1 0>; 975 status = "disabled"; 976 }; 977 978 usbmisc1: usbmisc@32e40200 { 979 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 980 #index-cells = <1>; 981 reg = <0x32e40200 0x200>; 982 }; 983 984 usbotg2: usb@32e50000 { 985 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 986 reg = <0x32e50000 0x200>; 987 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 989 clock-names = "usb1_ctrl_root_clk"; 990 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 991 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 992 phys = <&usbphynop2>; 993 fsl,usbmisc = <&usbmisc2 0>; 994 status = "disabled"; 995 }; 996 997 usbmisc2: usbmisc@32e50200 { 998 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 999 #index-cells = <1>; 1000 reg = <0x32e50200 0x200>; 1001 }; 1002 1003 }; 1004 1005 dma_apbh: dma-controller@33000000 { 1006 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1007 reg = <0x33000000 0x2000>; 1008 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1012 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1013 #dma-cells = <1>; 1014 dma-channels = <4>; 1015 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1016 }; 1017 1018 gpmi: nand-controller@33002000 { 1019 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1023 reg-names = "gpmi-nand", "bch"; 1024 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1025 interrupt-names = "bch"; 1026 clocks = <&clk IMX8MM_CLK_NAND_ROOT>, 1027 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1028 clock-names = "gpmi_io", "gpmi_bch_apb"; 1029 dmas = <&dma_apbh 0>; 1030 dma-names = "rx-tx"; 1031 status = "disabled"; 1032 }; 1033 1034 gic: interrupt-controller@38800000 { 1035 compatible = "arm,gic-v3"; 1036 reg = <0x38800000 0x10000>, /* GIC Dist */ 1037 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ 1038 #interrupt-cells = <3>; 1039 interrupt-controller; 1040 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1041 }; 1042 1043 ddrc: memory-controller@3d400000 { 1044 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; 1045 reg = <0x3d400000 0x400000>; 1046 clock-names = "core", "pll", "alt", "apb"; 1047 clocks = <&clk IMX8MM_CLK_DRAM_CORE>, 1048 <&clk IMX8MM_DRAM_PLL>, 1049 <&clk IMX8MM_CLK_DRAM_ALT>, 1050 <&clk IMX8MM_CLK_DRAM_APB>; 1051 }; 1052 1053 ddr-pmu@3d800000 { 1054 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1055 reg = <0x3d800000 0x400000>; 1056 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1057 }; 1058 }; 1059}; 1060