1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mn-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8mn-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec1; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 gpio4 = &gpio5; 26 i2c0 = &i2c1; 27 i2c1 = &i2c2; 28 i2c2 = &i2c3; 29 i2c3 = &i2c4; 30 mmc0 = &usdhc1; 31 mmc1 = &usdhc2; 32 mmc2 = &usdhc3; 33 serial0 = &uart1; 34 serial1 = &uart2; 35 serial2 = &uart3; 36 serial3 = &uart4; 37 spi0 = &ecspi1; 38 spi1 = &ecspi2; 39 spi2 = &ecspi3; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 idle-states { 47 entry-method = "psci"; 48 49 cpu_pd_wait: cpu-pd-wait { 50 compatible = "arm,idle-state"; 51 arm,psci-suspend-param = <0x0010033>; 52 local-timer-stop; 53 entry-latency-us = <1000>; 54 exit-latency-us = <700>; 55 min-residency-us = <2700>; 56 }; 57 }; 58 59 A53_0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0>; 63 clock-latency = <61036>; 64 clocks = <&clk IMX8MN_CLK_ARM>; 65 enable-method = "psci"; 66 next-level-cache = <&A53_L2>; 67 operating-points-v2 = <&a53_opp_table>; 68 nvmem-cells = <&cpu_speed_grade>; 69 nvmem-cell-names = "speed_grade"; 70 cpu-idle-states = <&cpu_pd_wait>; 71 #cooling-cells = <2>; 72 }; 73 74 A53_1: cpu@1 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x1>; 78 clock-latency = <61036>; 79 clocks = <&clk IMX8MN_CLK_ARM>; 80 enable-method = "psci"; 81 next-level-cache = <&A53_L2>; 82 operating-points-v2 = <&a53_opp_table>; 83 cpu-idle-states = <&cpu_pd_wait>; 84 #cooling-cells = <2>; 85 }; 86 87 A53_2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x2>; 91 clock-latency = <61036>; 92 clocks = <&clk IMX8MN_CLK_ARM>; 93 enable-method = "psci"; 94 next-level-cache = <&A53_L2>; 95 operating-points-v2 = <&a53_opp_table>; 96 cpu-idle-states = <&cpu_pd_wait>; 97 #cooling-cells = <2>; 98 }; 99 100 A53_3: cpu@3 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x3>; 104 clock-latency = <61036>; 105 clocks = <&clk IMX8MN_CLK_ARM>; 106 enable-method = "psci"; 107 next-level-cache = <&A53_L2>; 108 operating-points-v2 = <&a53_opp_table>; 109 cpu-idle-states = <&cpu_pd_wait>; 110 #cooling-cells = <2>; 111 }; 112 113 A53_L2: l2-cache0 { 114 compatible = "cache"; 115 }; 116 }; 117 118 a53_opp_table: opp-table { 119 compatible = "operating-points-v2"; 120 opp-shared; 121 122 opp-1200000000 { 123 opp-hz = /bits/ 64 <1200000000>; 124 opp-microvolt = <850000>; 125 opp-supported-hw = <0xb00>, <0x7>; 126 clock-latency-ns = <150000>; 127 opp-suspend; 128 }; 129 130 opp-1400000000 { 131 opp-hz = /bits/ 64 <1400000000>; 132 opp-microvolt = <950000>; 133 opp-supported-hw = <0x300>, <0x7>; 134 clock-latency-ns = <150000>; 135 opp-suspend; 136 }; 137 138 opp-1500000000 { 139 opp-hz = /bits/ 64 <1500000000>; 140 opp-microvolt = <1000000>; 141 opp-supported-hw = <0x100>, <0x3>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 }; 146 147 osc_32k: clock-osc-32k { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 clock-frequency = <32768>; 151 clock-output-names = "osc_32k"; 152 }; 153 154 osc_24m: clock-osc-24m { 155 compatible = "fixed-clock"; 156 #clock-cells = <0>; 157 clock-frequency = <24000000>; 158 clock-output-names = "osc_24m"; 159 }; 160 161 clk_ext1: clock-ext1 { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-frequency = <133000000>; 165 clock-output-names = "clk_ext1"; 166 }; 167 168 clk_ext2: clock-ext2 { 169 compatible = "fixed-clock"; 170 #clock-cells = <0>; 171 clock-frequency = <133000000>; 172 clock-output-names = "clk_ext2"; 173 }; 174 175 clk_ext3: clock-ext3 { 176 compatible = "fixed-clock"; 177 #clock-cells = <0>; 178 clock-frequency = <133000000>; 179 clock-output-names = "clk_ext3"; 180 }; 181 182 clk_ext4: clock-ext4 { 183 compatible = "fixed-clock"; 184 #clock-cells = <0>; 185 clock-frequency= <133000000>; 186 clock-output-names = "clk_ext4"; 187 }; 188 189 pmu { 190 compatible = "arm,cortex-a53-pmu"; 191 interrupts = <GIC_PPI 7 192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 193 }; 194 195 psci { 196 compatible = "arm,psci-1.0"; 197 method = "smc"; 198 }; 199 200 thermal-zones { 201 cpu-thermal { 202 polling-delay-passive = <250>; 203 polling-delay = <2000>; 204 thermal-sensors = <&tmu>; 205 trips { 206 cpu_alert0: trip0 { 207 temperature = <85000>; 208 hysteresis = <2000>; 209 type = "passive"; 210 }; 211 212 cpu_crit0: trip1 { 213 temperature = <95000>; 214 hysteresis = <2000>; 215 type = "critical"; 216 }; 217 }; 218 219 cooling-maps { 220 map0 { 221 trip = <&cpu_alert0>; 222 cooling-device = 223 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 224 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 225 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 226 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 227 }; 228 }; 229 }; 230 }; 231 232 timer { 233 compatible = "arm,armv8-timer"; 234 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 235 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 236 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 237 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 238 clock-frequency = <8000000>; 239 arm,no-tick-in-suspend; 240 }; 241 242 soc@0 { 243 compatible = "fsl,imx8mn-soc", "simple-bus"; 244 #address-cells = <1>; 245 #size-cells = <1>; 246 ranges = <0x0 0x0 0x0 0x3e000000>; 247 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 248 nvmem-cells = <&imx8mn_uid>; 249 nvmem-cell-names = "soc_unique_id"; 250 251 aips1: bus@30000000 { 252 compatible = "fsl,aips-bus", "simple-bus"; 253 reg = <0x30000000 0x400000>; 254 #address-cells = <1>; 255 #size-cells = <1>; 256 ranges; 257 258 spba2: spba-bus@30000000 { 259 compatible = "fsl,spba-bus", "simple-bus"; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 reg = <0x30000000 0x100000>; 263 ranges; 264 265 sai2: sai@30020000 { 266 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 267 reg = <0x30020000 0x10000>; 268 #sound-dai-cells = <0>; 269 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&clk IMX8MN_CLK_SAI2_IPG>, 271 <&clk IMX8MN_CLK_DUMMY>, 272 <&clk IMX8MN_CLK_SAI2_ROOT>, 273 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 274 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 275 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 276 dma-names = "rx", "tx"; 277 status = "disabled"; 278 }; 279 280 sai3: sai@30030000 { 281 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 282 reg = <0x30030000 0x10000>; 283 #sound-dai-cells = <0>; 284 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&clk IMX8MN_CLK_SAI3_IPG>, 286 <&clk IMX8MN_CLK_DUMMY>, 287 <&clk IMX8MN_CLK_SAI3_ROOT>, 288 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 289 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 290 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 291 dma-names = "rx", "tx"; 292 status = "disabled"; 293 }; 294 295 sai5: sai@30050000 { 296 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 297 reg = <0x30050000 0x10000>; 298 #sound-dai-cells = <0>; 299 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&clk IMX8MN_CLK_SAI5_IPG>, 301 <&clk IMX8MN_CLK_DUMMY>, 302 <&clk IMX8MN_CLK_SAI5_ROOT>, 303 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 304 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 305 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 306 dma-names = "rx", "tx"; 307 fsl,shared-interrupt; 308 fsl,dataline = <0 0xf 0xf>; 309 status = "disabled"; 310 }; 311 312 sai6: sai@30060000 { 313 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 314 reg = <0x30060000 0x10000>; 315 #sound-dai-cells = <0>; 316 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&clk IMX8MN_CLK_SAI6_IPG>, 318 <&clk IMX8MN_CLK_DUMMY>, 319 <&clk IMX8MN_CLK_SAI6_ROOT>, 320 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 321 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 322 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 323 dma-names = "rx", "tx"; 324 status = "disabled"; 325 }; 326 327 micfil: audio-controller@30080000 { 328 compatible = "fsl,imx8mm-micfil"; 329 reg = <0x30080000 0x10000>; 330 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&clk IMX8MN_CLK_PDM_IPG>, 335 <&clk IMX8MN_CLK_PDM_ROOT>, 336 <&clk IMX8MN_AUDIO_PLL1_OUT>, 337 <&clk IMX8MN_AUDIO_PLL2_OUT>, 338 <&clk IMX8MN_CLK_EXT3>; 339 clock-names = "ipg_clk", "ipg_clk_app", 340 "pll8k", "pll11k", "clkext3"; 341 dmas = <&sdma2 24 25 0x80000000>; 342 dma-names = "rx"; 343 #sound-dai-cells = <0>; 344 status = "disabled"; 345 }; 346 347 spdif1: spdif@30090000 { 348 compatible = "fsl,imx35-spdif"; 349 reg = <0x30090000 0x10000>; 350 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ 352 <&clk IMX8MN_CLK_24M>, /* rxtx0 */ 353 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ 354 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ 355 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ 356 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ 357 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ 358 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ 359 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ 360 <&clk IMX8MN_CLK_DUMMY>; /* spba */ 361 clock-names = "core", "rxtx0", 362 "rxtx1", "rxtx2", 363 "rxtx3", "rxtx4", 364 "rxtx5", "rxtx6", 365 "rxtx7", "spba"; 366 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 367 dma-names = "rx", "tx"; 368 status = "disabled"; 369 }; 370 371 sai7: sai@300b0000 { 372 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 373 reg = <0x300b0000 0x10000>; 374 #sound-dai-cells = <0>; 375 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&clk IMX8MN_CLK_SAI7_IPG>, 377 <&clk IMX8MN_CLK_DUMMY>, 378 <&clk IMX8MN_CLK_SAI7_ROOT>, 379 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 380 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 381 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 382 dma-names = "rx", "tx"; 383 status = "disabled"; 384 }; 385 386 easrc: easrc@300c0000 { 387 compatible = "fsl,imx8mn-easrc"; 388 reg = <0x300c0000 0x10000>; 389 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; 391 clock-names = "mem"; 392 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 393 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 394 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 395 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 396 dma-names = "ctx0_rx", "ctx0_tx", 397 "ctx1_rx", "ctx1_tx", 398 "ctx2_rx", "ctx2_tx", 399 "ctx3_rx", "ctx3_tx"; 400 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 401 fsl,asrc-rate = <8000>; 402 fsl,asrc-format = <2>; 403 status = "disabled"; 404 }; 405 }; 406 407 gpio1: gpio@30200000 { 408 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 409 reg = <0x30200000 0x10000>; 410 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; 413 gpio-controller; 414 #gpio-cells = <2>; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 gpio-ranges = <&iomuxc 0 10 30>; 418 }; 419 420 gpio2: gpio@30210000 { 421 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 422 reg = <0x30210000 0x10000>; 423 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; 426 gpio-controller; 427 #gpio-cells = <2>; 428 interrupt-controller; 429 #interrupt-cells = <2>; 430 gpio-ranges = <&iomuxc 0 40 21>; 431 }; 432 433 gpio3: gpio@30220000 { 434 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 435 reg = <0x30220000 0x10000>; 436 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; 439 gpio-controller; 440 #gpio-cells = <2>; 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 gpio-ranges = <&iomuxc 0 61 26>; 444 }; 445 446 gpio4: gpio@30230000 { 447 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 448 reg = <0x30230000 0x10000>; 449 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; 452 gpio-controller; 453 #gpio-cells = <2>; 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 gpio-ranges = <&iomuxc 21 108 11>; 457 }; 458 459 gpio5: gpio@30240000 { 460 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 461 reg = <0x30240000 0x10000>; 462 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; 465 gpio-controller; 466 #gpio-cells = <2>; 467 interrupt-controller; 468 #interrupt-cells = <2>; 469 gpio-ranges = <&iomuxc 0 119 30>; 470 }; 471 472 tmu: tmu@30260000 { 473 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; 474 reg = <0x30260000 0x10000>; 475 clocks = <&clk IMX8MN_CLK_TMU_ROOT>; 476 #thermal-sensor-cells = <0>; 477 }; 478 479 wdog1: watchdog@30280000 { 480 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 481 reg = <0x30280000 0x10000>; 482 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; 484 status = "disabled"; 485 }; 486 487 wdog2: watchdog@30290000 { 488 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 489 reg = <0x30290000 0x10000>; 490 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; 492 status = "disabled"; 493 }; 494 495 wdog3: watchdog@302a0000 { 496 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 497 reg = <0x302a0000 0x10000>; 498 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; 500 status = "disabled"; 501 }; 502 503 sdma3: dma-controller@302b0000 { 504 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 505 reg = <0x302b0000 0x10000>; 506 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, 508 <&clk IMX8MN_CLK_SDMA3_ROOT>; 509 clock-names = "ipg", "ahb"; 510 #dma-cells = <3>; 511 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 512 }; 513 514 sdma2: dma-controller@302c0000 { 515 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 516 reg = <0x302c0000 0x10000>; 517 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, 519 <&clk IMX8MN_CLK_SDMA2_ROOT>; 520 clock-names = "ipg", "ahb"; 521 #dma-cells = <3>; 522 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 523 }; 524 525 iomuxc: pinctrl@30330000 { 526 compatible = "fsl,imx8mn-iomuxc"; 527 reg = <0x30330000 0x10000>; 528 }; 529 530 gpr: iomuxc-gpr@30340000 { 531 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; 532 reg = <0x30340000 0x10000>; 533 }; 534 535 ocotp: efuse@30350000 { 536 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; 537 reg = <0x30350000 0x10000>; 538 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; 539 #address-cells = <1>; 540 #size-cells = <1>; 541 542 imx8mn_uid: unique-id@4 { 543 reg = <0x4 0x8>; 544 }; 545 546 cpu_speed_grade: speed-grade@10 { 547 reg = <0x10 4>; 548 }; 549 550 fec_mac_address: mac-address@90 { 551 reg = <0x90 6>; 552 }; 553 }; 554 555 anatop: anatop@30360000 { 556 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", 557 "syscon"; 558 reg = <0x30360000 0x10000>; 559 }; 560 561 snvs: snvs@30370000 { 562 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 563 reg = <0x30370000 0x10000>; 564 565 snvs_rtc: snvs-rtc-lp { 566 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 567 regmap = <&snvs>; 568 offset = <0x34>; 569 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 572 clock-names = "snvs-rtc"; 573 }; 574 575 snvs_pwrkey: snvs-powerkey { 576 compatible = "fsl,sec-v4.0-pwrkey"; 577 regmap = <&snvs>; 578 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 580 clock-names = "snvs-pwrkey"; 581 linux,keycode = <KEY_POWER>; 582 wakeup-source; 583 status = "disabled"; 584 }; 585 }; 586 587 clk: clock-controller@30380000 { 588 compatible = "fsl,imx8mn-ccm"; 589 reg = <0x30380000 0x10000>; 590 #clock-cells = <1>; 591 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 592 <&clk_ext3>, <&clk_ext4>; 593 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 594 "clk_ext3", "clk_ext4"; 595 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, 596 <&clk IMX8MN_CLK_A53_CORE>, 597 <&clk IMX8MN_CLK_NOC>, 598 <&clk IMX8MN_CLK_AUDIO_AHB>, 599 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, 600 <&clk IMX8MN_SYS_PLL3>, 601 <&clk IMX8MN_AUDIO_PLL1>, 602 <&clk IMX8MN_AUDIO_PLL2>; 603 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, 604 <&clk IMX8MN_ARM_PLL_OUT>, 605 <&clk IMX8MN_SYS_PLL3_OUT>, 606 <&clk IMX8MN_SYS_PLL1_800M>; 607 assigned-clock-rates = <0>, <0>, <0>, 608 <400000000>, 609 <400000000>, 610 <600000000>, 611 <393216000>, 612 <361267200>; 613 }; 614 615 src: reset-controller@30390000 { 616 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; 617 reg = <0x30390000 0x10000>; 618 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 619 #reset-cells = <1>; 620 }; 621 }; 622 623 aips2: bus@30400000 { 624 compatible = "fsl,aips-bus", "simple-bus"; 625 reg = <0x30400000 0x400000>; 626 #address-cells = <1>; 627 #size-cells = <1>; 628 ranges; 629 630 pwm1: pwm@30660000 { 631 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 632 reg = <0x30660000 0x10000>; 633 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, 635 <&clk IMX8MN_CLK_PWM1_ROOT>; 636 clock-names = "ipg", "per"; 637 #pwm-cells = <2>; 638 status = "disabled"; 639 }; 640 641 pwm2: pwm@30670000 { 642 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 643 reg = <0x30670000 0x10000>; 644 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, 646 <&clk IMX8MN_CLK_PWM2_ROOT>; 647 clock-names = "ipg", "per"; 648 #pwm-cells = <2>; 649 status = "disabled"; 650 }; 651 652 pwm3: pwm@30680000 { 653 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 654 reg = <0x30680000 0x10000>; 655 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, 657 <&clk IMX8MN_CLK_PWM3_ROOT>; 658 clock-names = "ipg", "per"; 659 #pwm-cells = <2>; 660 status = "disabled"; 661 }; 662 663 pwm4: pwm@30690000 { 664 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 665 reg = <0x30690000 0x10000>; 666 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, 668 <&clk IMX8MN_CLK_PWM4_ROOT>; 669 clock-names = "ipg", "per"; 670 #pwm-cells = <2>; 671 status = "disabled"; 672 }; 673 674 system_counter: timer@306a0000 { 675 compatible = "nxp,sysctr-timer"; 676 reg = <0x306a0000 0x20000>; 677 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&osc_24m>; 679 clock-names = "per"; 680 }; 681 }; 682 683 aips3: bus@30800000 { 684 compatible = "fsl,aips-bus", "simple-bus"; 685 reg = <0x30800000 0x400000>; 686 #address-cells = <1>; 687 #size-cells = <1>; 688 ranges; 689 690 spba1: spba-bus@30800000 { 691 compatible = "fsl,spba-bus", "simple-bus"; 692 #address-cells = <1>; 693 #size-cells = <1>; 694 reg = <0x30800000 0x100000>; 695 ranges; 696 697 ecspi1: spi@30820000 { 698 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 reg = <0x30820000 0x10000>; 702 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, 704 <&clk IMX8MN_CLK_ECSPI1_ROOT>; 705 clock-names = "ipg", "per"; 706 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 707 dma-names = "rx", "tx"; 708 status = "disabled"; 709 }; 710 711 ecspi2: spi@30830000 { 712 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 reg = <0x30830000 0x10000>; 716 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, 718 <&clk IMX8MN_CLK_ECSPI2_ROOT>; 719 clock-names = "ipg", "per"; 720 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 721 dma-names = "rx", "tx"; 722 status = "disabled"; 723 }; 724 725 ecspi3: spi@30840000 { 726 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 reg = <0x30840000 0x10000>; 730 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, 732 <&clk IMX8MN_CLK_ECSPI3_ROOT>; 733 clock-names = "ipg", "per"; 734 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 735 dma-names = "rx", "tx"; 736 status = "disabled"; 737 }; 738 739 uart1: serial@30860000 { 740 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 741 reg = <0x30860000 0x10000>; 742 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&clk IMX8MN_CLK_UART1_ROOT>, 744 <&clk IMX8MN_CLK_UART1_ROOT>; 745 clock-names = "ipg", "per"; 746 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 747 dma-names = "rx", "tx"; 748 status = "disabled"; 749 }; 750 751 uart3: serial@30880000 { 752 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 753 reg = <0x30880000 0x10000>; 754 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&clk IMX8MN_CLK_UART3_ROOT>, 756 <&clk IMX8MN_CLK_UART3_ROOT>; 757 clock-names = "ipg", "per"; 758 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 759 dma-names = "rx", "tx"; 760 status = "disabled"; 761 }; 762 763 uart2: serial@30890000 { 764 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 765 reg = <0x30890000 0x10000>; 766 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&clk IMX8MN_CLK_UART2_ROOT>, 768 <&clk IMX8MN_CLK_UART2_ROOT>; 769 clock-names = "ipg", "per"; 770 status = "disabled"; 771 }; 772 }; 773 774 crypto: crypto@30900000 { 775 compatible = "fsl,sec-v4.0"; 776 #address-cells = <1>; 777 #size-cells = <1>; 778 reg = <0x30900000 0x40000>; 779 ranges = <0 0x30900000 0x40000>; 780 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&clk IMX8MN_CLK_AHB>, 782 <&clk IMX8MN_CLK_IPG_ROOT>; 783 clock-names = "aclk", "ipg"; 784 785 sec_jr0: jr@1000 { 786 compatible = "fsl,sec-v4.0-job-ring"; 787 reg = <0x1000 0x1000>; 788 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 789 }; 790 791 sec_jr1: jr@2000 { 792 compatible = "fsl,sec-v4.0-job-ring"; 793 reg = <0x2000 0x1000>; 794 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 795 }; 796 797 sec_jr2: jr@3000 { 798 compatible = "fsl,sec-v4.0-job-ring"; 799 reg = <0x3000 0x1000>; 800 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 801 }; 802 }; 803 804 i2c1: i2c@30a20000 { 805 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 reg = <0x30a20000 0x10000>; 809 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; 811 status = "disabled"; 812 }; 813 814 i2c2: i2c@30a30000 { 815 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 reg = <0x30a30000 0x10000>; 819 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; 821 status = "disabled"; 822 }; 823 824 i2c3: i2c@30a40000 { 825 #address-cells = <1>; 826 #size-cells = <0>; 827 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 828 reg = <0x30a40000 0x10000>; 829 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 830 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; 831 status = "disabled"; 832 }; 833 834 i2c4: i2c@30a50000 { 835 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 reg = <0x30a50000 0x10000>; 839 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; 841 status = "disabled"; 842 }; 843 844 uart4: serial@30a60000 { 845 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 846 reg = <0x30a60000 0x10000>; 847 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&clk IMX8MN_CLK_UART4_ROOT>, 849 <&clk IMX8MN_CLK_UART4_ROOT>; 850 clock-names = "ipg", "per"; 851 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 852 dma-names = "rx", "tx"; 853 status = "disabled"; 854 }; 855 856 mu: mailbox@30aa0000 { 857 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; 858 reg = <0x30aa0000 0x10000>; 859 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 860 clocks = <&clk IMX8MN_CLK_MU_ROOT>; 861 #mbox-cells = <2>; 862 }; 863 864 usdhc1: mmc@30b40000 { 865 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 866 reg = <0x30b40000 0x10000>; 867 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 869 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 870 <&clk IMX8MN_CLK_USDHC1_ROOT>; 871 clock-names = "ipg", "ahb", "per"; 872 fsl,tuning-start-tap = <20>; 873 fsl,tuning-step= <2>; 874 bus-width = <4>; 875 status = "disabled"; 876 }; 877 878 usdhc2: mmc@30b50000 { 879 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 880 reg = <0x30b50000 0x10000>; 881 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 883 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 884 <&clk IMX8MN_CLK_USDHC2_ROOT>; 885 clock-names = "ipg", "ahb", "per"; 886 fsl,tuning-start-tap = <20>; 887 fsl,tuning-step= <2>; 888 bus-width = <4>; 889 status = "disabled"; 890 }; 891 892 usdhc3: mmc@30b60000 { 893 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 894 reg = <0x30b60000 0x10000>; 895 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 897 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 898 <&clk IMX8MN_CLK_USDHC3_ROOT>; 899 clock-names = "ipg", "ahb", "per"; 900 fsl,tuning-start-tap = <20>; 901 fsl,tuning-step= <2>; 902 bus-width = <4>; 903 status = "disabled"; 904 }; 905 906 flexspi: spi@30bb0000 { 907 #address-cells = <1>; 908 #size-cells = <0>; 909 compatible = "nxp,imx8mm-fspi"; 910 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 911 reg-names = "fspi_base", "fspi_mmap"; 912 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, 914 <&clk IMX8MN_CLK_QSPI_ROOT>; 915 clock-names = "fspi_en", "fspi"; 916 status = "disabled"; 917 }; 918 919 sdma1: dma-controller@30bd0000 { 920 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 921 reg = <0x30bd0000 0x10000>; 922 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 923 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, 924 <&clk IMX8MN_CLK_AHB>; 925 clock-names = "ipg", "ahb"; 926 #dma-cells = <3>; 927 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 928 }; 929 930 fec1: ethernet@30be0000 { 931 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 932 reg = <0x30be0000 0x10000>; 933 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, 938 <&clk IMX8MN_CLK_ENET1_ROOT>, 939 <&clk IMX8MN_CLK_ENET_TIMER>, 940 <&clk IMX8MN_CLK_ENET_REF>, 941 <&clk IMX8MN_CLK_ENET_PHY_REF>; 942 clock-names = "ipg", "ahb", "ptp", 943 "enet_clk_ref", "enet_out"; 944 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, 945 <&clk IMX8MN_CLK_ENET_TIMER>, 946 <&clk IMX8MN_CLK_ENET_REF>, 947 <&clk IMX8MN_CLK_ENET_PHY_REF>; 948 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 949 <&clk IMX8MN_SYS_PLL2_100M>, 950 <&clk IMX8MN_SYS_PLL2_125M>, 951 <&clk IMX8MN_SYS_PLL2_50M>; 952 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 953 fsl,num-tx-queues = <3>; 954 fsl,num-rx-queues = <3>; 955 nvmem-cells = <&fec_mac_address>; 956 nvmem-cell-names = "mac-address"; 957 nvmem_macaddr_swap; 958 fsl,stop-mode = <&gpr 0x10 3>; 959 status = "disabled"; 960 }; 961 962 }; 963 964 aips4: bus@32c00000 { 965 compatible = "fsl,aips-bus", "simple-bus"; 966 reg = <0x32c00000 0x400000>; 967 #address-cells = <1>; 968 #size-cells = <1>; 969 ranges; 970 971 usbotg1: usb@32e40000 { 972 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; 973 reg = <0x32e40000 0x200>; 974 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 975 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 976 clock-names = "usb1_ctrl_root_clk"; 977 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; 978 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; 979 phys = <&usbphynop1>; 980 fsl,usbmisc = <&usbmisc1 0>; 981 status = "disabled"; 982 }; 983 984 usbmisc1: usbmisc@32e40200 { 985 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; 986 #index-cells = <1>; 987 reg = <0x32e40200 0x200>; 988 }; 989 }; 990 991 dma_apbh: dma-controller@33000000 { 992 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 993 reg = <0x33000000 0x2000>; 994 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 998 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 999 #dma-cells = <1>; 1000 dma-channels = <4>; 1001 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1002 }; 1003 1004 gpmi: nand-controller@33002000 { 1005 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1009 reg-names = "gpmi-nand", "bch"; 1010 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1011 interrupt-names = "bch"; 1012 clocks = <&clk IMX8MN_CLK_NAND_ROOT>, 1013 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1014 clock-names = "gpmi_io", "gpmi_bch_apb"; 1015 dmas = <&dma_apbh 0>; 1016 dma-names = "rx-tx"; 1017 status = "disabled"; 1018 }; 1019 1020 gic: interrupt-controller@38800000 { 1021 compatible = "arm,gic-v3"; 1022 reg = <0x38800000 0x10000>, 1023 <0x38880000 0xc0000>; 1024 #interrupt-cells = <3>; 1025 interrupt-controller; 1026 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1027 }; 1028 1029 ddrc: memory-controller@3d400000 { 1030 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; 1031 reg = <0x3d400000 0x400000>; 1032 clock-names = "core", "pll", "alt", "apb"; 1033 clocks = <&clk IMX8MN_CLK_DRAM_CORE>, 1034 <&clk IMX8MN_DRAM_PLL>, 1035 <&clk IMX8MN_CLK_DRAM_ALT>, 1036 <&clk IMX8MN_CLK_DRAM_APB>; 1037 }; 1038 1039 ddr-pmu@3d800000 { 1040 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1041 reg = <0x3d800000 0x400000>; 1042 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1043 }; 1044 }; 1045 1046 usbphynop1: usbphynop1 { 1047 #phy-cells = <0>; 1048 compatible = "usb-nop-xceiv"; 1049 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1050 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1051 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 1052 clock-names = "main_clk"; 1053 }; 1054}; 1055