1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH 4 * Author: Teresa Remmet <t.remmet@phytec.de> 5 */ 6 7#include <dt-bindings/net/ti-dp83867.h> 8#include "imx8mp.dtsi" 9 10/ { 11 model = "PHYTEC phyCORE-i.MX8MP"; 12 compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp"; 13 14 aliases { 15 rtc0 = &rv3028; 16 rtc1 = &snvs_rtc; 17 }; 18 19 memory@40000000 { 20 device_type = "memory"; 21 reg = <0x0 0x40000000 0 0x80000000>; 22 }; 23}; 24 25&A53_0 { 26 cpu-supply = <&buck2>; 27}; 28 29&A53_1 { 30 cpu-supply = <&buck2>; 31}; 32 33&A53_2 { 34 cpu-supply = <&buck2>; 35}; 36 37&A53_3 { 38 cpu-supply = <&buck2>; 39}; 40 41/* ethernet 1 */ 42&fec { 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_fec>; 45 phy-mode = "rgmii-id"; 46 phy-handle = <ðphy1>; 47 fsl,magic-packet; 48 status = "okay"; 49 50 mdio { 51 #address-cells = <1>; 52 #size-cells = <0>; 53 54 ethphy1: ethernet-phy@0 { 55 compatible = "ethernet-phy-ieee802.3-c22"; 56 reg = <0>; 57 interrupt-parent = <&gpio1>; 58 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 59 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 60 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 61 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 62 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 63 enet-phy-lane-no-swap; 64 }; 65 }; 66}; 67 68&flexspi { 69 pinctrl-names = "default"; 70 pinctrl-0 = <&pinctrl_flexspi0>; 71 status = "okay"; 72 73 som_flash: flash@0 { 74 compatible = "jedec,spi-nor"; 75 reg = <0>; 76 spi-max-frequency = <80000000>; 77 spi-tx-bus-width = <1>; 78 spi-rx-bus-width = <4>; 79 }; 80}; 81 82&i2c1 { 83 clock-frequency = <400000>; 84 pinctrl-names = "default", "gpio"; 85 pinctrl-0 = <&pinctrl_i2c1>; 86 pinctrl-1 = <&pinctrl_i2c1_gpio>; 87 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 88 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 89 status = "okay"; 90 91 pmic: pmic@25 { 92 reg = <0x25>; 93 compatible = "nxp,pca9450c"; 94 pinctrl-names = "default"; 95 pinctrl-0 = <&pinctrl_pmic>; 96 interrupt-parent = <&gpio4>; 97 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 98 99 regulators { 100 buck1: BUCK1 { 101 regulator-min-microvolt = <600000>; 102 regulator-max-microvolt = <2187500>; 103 regulator-boot-on; 104 regulator-always-on; 105 regulator-ramp-delay = <3125>; 106 }; 107 108 buck2: BUCK2 { 109 regulator-min-microvolt = <600000>; 110 regulator-max-microvolt = <2187500>; 111 regulator-boot-on; 112 regulator-always-on; 113 regulator-ramp-delay = <3125>; 114 }; 115 116 buck4: BUCK4 { 117 regulator-min-microvolt = <600000>; 118 regulator-max-microvolt = <3400000>; 119 regulator-boot-on; 120 regulator-always-on; 121 }; 122 123 buck5: BUCK5 { 124 regulator-min-microvolt = <600000>; 125 regulator-max-microvolt = <3400000>; 126 regulator-boot-on; 127 regulator-always-on; 128 }; 129 130 buck6: BUCK6 { 131 regulator-min-microvolt = <600000>; 132 regulator-max-microvolt = <3400000>; 133 regulator-boot-on; 134 regulator-always-on; 135 }; 136 137 ldo1: LDO1 { 138 regulator-min-microvolt = <1600000>; 139 regulator-max-microvolt = <3300000>; 140 regulator-boot-on; 141 regulator-always-on; 142 }; 143 144 ldo2: LDO2 { 145 regulator-min-microvolt = <800000>; 146 regulator-max-microvolt = <1150000>; 147 regulator-boot-on; 148 regulator-always-on; 149 }; 150 151 ldo3: LDO3 { 152 regulator-min-microvolt = <800000>; 153 regulator-max-microvolt = <3300000>; 154 regulator-boot-on; 155 regulator-always-on; 156 }; 157 158 ldo4: LDO4 { 159 regulator-min-microvolt = <800000>; 160 regulator-max-microvolt = <3300000>; 161 regulator-boot-on; 162 regulator-always-on; 163 }; 164 165 ldo5: LDO5 { 166 regulator-min-microvolt = <1800000>; 167 regulator-max-microvolt = <3300000>; 168 }; 169 }; 170 }; 171 172 eeprom@51 { 173 compatible = "atmel,24c32"; 174 reg = <0x51>; 175 pagesize = <32>; 176 }; 177 178 rv3028: rtc@52 { 179 compatible = "microcrystal,rv3028"; 180 reg = <0x52>; 181 trickle-resistor-ohms = <3000>; 182 }; 183}; 184 185/* eMMC */ 186&usdhc3 { 187 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 188 pinctrl-0 = <&pinctrl_usdhc3>; 189 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 190 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 191 bus-width = <8>; 192 non-removable; 193 status = "okay"; 194}; 195 196&wdog1 { 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_wdog>; 199 fsl,ext-reset-output; 200 status = "okay"; 201}; 202 203&iomuxc { 204 pinctrl_fec: fecgrp { 205 fsl,pins = < 206 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 207 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 208 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 209 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 210 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 211 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 212 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 213 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 214 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 215 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 216 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f 217 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f 218 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 219 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f 220 MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11 221 >; 222 }; 223 224 pinctrl_flexspi0: flexspi0grp { 225 fsl,pins = < 226 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 227 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 228 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 229 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 230 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 231 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 232 >; 233 }; 234 235 pinctrl_i2c1: i2c1grp { 236 fsl,pins = < 237 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 238 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 239 >; 240 }; 241 242 pinctrl_i2c1_gpio: i2c1gpiogrp { 243 fsl,pins = < 244 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3 245 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3 246 >; 247 }; 248 249 pinctrl_pmic: pmicirqgrp { 250 fsl,pins = < 251 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141 252 >; 253 }; 254 255 pinctrl_usdhc3: usdhc3grp { 256 fsl,pins = < 257 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 258 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 259 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 260 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 261 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 262 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 263 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 264 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 265 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 266 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 267 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 268 >; 269 }; 270 271 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 272 fsl,pins = < 273 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 274 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 275 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 276 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 277 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 278 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 279 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 280 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 281 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 282 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 283 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 284 >; 285 }; 286 287 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 288 fsl,pins = < 289 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 290 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 291 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 292 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 293 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 294 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 295 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 296 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 297 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 298 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 299 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 300 >; 301 }; 302 303 pinctrl_wdog: wdoggrp { 304 fsl,pins = < 305 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 306 >; 307 }; 308}; 309