1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include "mt8183.dtsi" 11#include "mt6358.dtsi" 12 13/ { 14 aliases { 15 serial0 = &uart0; 16 mmc0 = &mmc0; 17 mmc1 = &mmc1; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 backlight_lcd0: backlight_lcd0 { 25 compatible = "pwm-backlight"; 26 pwms = <&pwm0 0 500000>; 27 power-supply = <&bl_pp5000>; 28 enable-gpios = <&pio 176 0>; 29 brightness-levels = <0 1023>; 30 num-interpolated-steps = <1023>; 31 default-brightness-level = <576>; 32 status = "okay"; 33 }; 34 35 memory@40000000 { 36 device_type = "memory"; 37 reg = <0 0x40000000 0 0x80000000>; 38 }; 39 40 clk32k: oscillator1 { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32768>; 44 clock-output-names = "clk32k"; 45 }; 46 47 it6505_pp18_reg: regulator0 { 48 compatible = "regulator-fixed"; 49 regulator-name = "it6505_pp18"; 50 regulator-min-microvolt = <1800000>; 51 regulator-max-microvolt = <1800000>; 52 gpio = <&pio 178 0>; 53 enable-active-high; 54 }; 55 56 lcd_pp3300: regulator1 { 57 compatible = "regulator-fixed"; 58 regulator-name = "lcd_pp3300"; 59 regulator-min-microvolt = <3300000>; 60 regulator-max-microvolt = <3300000>; 61 regulator-always-on; 62 regulator-boot-on; 63 }; 64 65 bl_pp5000: regulator2 { 66 compatible = "regulator-fixed"; 67 regulator-name = "bl_pp5000"; 68 regulator-min-microvolt = <5000000>; 69 regulator-max-microvolt = <5000000>; 70 regulator-always-on; 71 regulator-boot-on; 72 }; 73 74 mmc1_fixed_power: regulator3 { 75 compatible = "regulator-fixed"; 76 regulator-name = "mmc1_power"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 }; 80 81 mmc1_fixed_io: regulator4 { 82 compatible = "regulator-fixed"; 83 regulator-name = "mmc1_io"; 84 regulator-min-microvolt = <1800000>; 85 regulator-max-microvolt = <1800000>; 86 }; 87 88 pp1800_alw: regulator5 { 89 compatible = "regulator-fixed"; 90 regulator-name = "pp1800_alw"; 91 regulator-always-on; 92 regulator-boot-on; 93 regulator-min-microvolt = <1800000>; 94 regulator-max-microvolt = <1800000>; 95 }; 96 97 pp3300_alw: regulator6 { 98 compatible = "regulator-fixed"; 99 regulator-name = "pp3300_alw"; 100 regulator-always-on; 101 regulator-boot-on; 102 regulator-min-microvolt = <3300000>; 103 regulator-max-microvolt = <3300000>; 104 }; 105 106 reserved_memory: reserved-memory { 107 #address-cells = <2>; 108 #size-cells = <2>; 109 ranges; 110 111 scp_mem_reserved: memory@50000000 { 112 compatible = "shared-dma-pool"; 113 reg = <0 0x50000000 0 0x2900000>; 114 no-map; 115 }; 116 }; 117 118 max98357a: codec0 { 119 compatible = "maxim,max98357a"; 120 sdmode-gpios = <&pio 175 0>; 121 }; 122 123 btsco: codec1 { 124 compatible = "linux,bt-sco"; 125 }; 126 127 wifi_pwrseq: wifi-pwrseq { 128 compatible = "mmc-pwrseq-simple"; 129 pinctrl-names = "default"; 130 pinctrl-0 = <&wifi_pins_pwrseq>; 131 132 /* Toggle WIFI_ENABLE to reset the chip. */ 133 reset-gpios = <&pio 119 1>; 134 }; 135 136 wifi_wakeup: wifi-wakeup { 137 compatible = "gpio-keys"; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&wifi_pins_wakeup>; 140 141 wowlan { 142 label = "Wake on WiFi"; 143 gpios = <&pio 113 GPIO_ACTIVE_HIGH>; 144 linux,code = <KEY_WAKEUP>; 145 wakeup-source; 146 }; 147 }; 148 149 tboard_thermistor1: thermal-sensor1 { 150 compatible = "generic-adc-thermal"; 151 #thermal-sensor-cells = <0>; 152 io-channels = <&auxadc 0>; 153 io-channel-names = "sensor-channel"; 154 temperature-lookup-table = < (-5000) 4241 155 0 4063 156 5000 3856 157 10000 3621 158 15000 3364 159 20000 3091 160 25000 2810 161 30000 2526 162 35000 2247 163 40000 1982 164 45000 1734 165 50000 1507 166 55000 1305 167 60000 1122 168 65000 964 169 70000 827 170 75000 710 171 80000 606 172 85000 519 173 90000 445 174 95000 382 175 100000 330 176 105000 284 177 110000 245 178 115000 213 179 120000 183 180 125000 161>; 181 }; 182 183 tboard_thermistor2: thermal-sensor2 { 184 compatible = "generic-adc-thermal"; 185 #thermal-sensor-cells = <0>; 186 io-channels = <&auxadc 1>; 187 io-channel-names = "sensor-channel"; 188 temperature-lookup-table = < (-5000) 4241 189 0 4063 190 5000 3856 191 10000 3621 192 15000 3364 193 20000 3091 194 25000 2810 195 30000 2526 196 35000 2247 197 40000 1982 198 45000 1734 199 50000 1507 200 55000 1305 201 60000 1122 202 65000 964 203 70000 827 204 75000 710 205 80000 606 206 85000 519 207 90000 445 208 95000 382 209 100000 330 210 105000 284 211 110000 245 212 115000 213 213 120000 183 214 125000 161>; 215 }; 216}; 217 218&auxadc { 219 status = "okay"; 220}; 221 222&cpu0 { 223 proc-supply = <&mt6358_vproc12_reg>; 224}; 225 226&cpu1 { 227 proc-supply = <&mt6358_vproc12_reg>; 228}; 229 230&cpu2 { 231 proc-supply = <&mt6358_vproc12_reg>; 232}; 233 234&cpu3 { 235 proc-supply = <&mt6358_vproc12_reg>; 236}; 237 238&cpu4 { 239 proc-supply = <&mt6358_vproc11_reg>; 240}; 241 242&cpu5 { 243 proc-supply = <&mt6358_vproc11_reg>; 244}; 245 246&cpu6 { 247 proc-supply = <&mt6358_vproc11_reg>; 248}; 249 250&cpu7 { 251 proc-supply = <&mt6358_vproc11_reg>; 252}; 253 254&dsi0 { 255 status = "okay"; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 panel: panel@0 { 259 /* compatible will be set in board dts */ 260 reg = <0>; 261 enable-gpios = <&pio 45 0>; 262 pinctrl-names = "default"; 263 pinctrl-0 = <&panel_pins_default>; 264 avdd-supply = <&ppvarn_lcd>; 265 avee-supply = <&ppvarp_lcd>; 266 pp1800-supply = <&pp1800_lcd>; 267 backlight = <&backlight_lcd0>; 268 port { 269 panel_in: endpoint { 270 remote-endpoint = <&dsi_out>; 271 }; 272 }; 273 }; 274 275 ports { 276 port { 277 dsi_out: endpoint { 278 remote-endpoint = <&panel_in>; 279 }; 280 }; 281 }; 282}; 283 284&gic { 285 mediatek,broken-save-restore-fw; 286}; 287 288&gpu { 289 mali-supply = <&mt6358_vgpu_reg>; 290 sram-supply = <&mt6358_vsram_gpu_reg>; 291}; 292 293&i2c0 { 294 pinctrl-names = "default"; 295 pinctrl-0 = <&i2c0_pins>; 296 status = "okay"; 297 clock-frequency = <400000>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300}; 301 302&i2c1 { 303 pinctrl-names = "default"; 304 pinctrl-0 = <&i2c1_pins>; 305 status = "okay"; 306 clock-frequency = <100000>; 307}; 308 309&i2c3 { 310 pinctrl-names = "default"; 311 pinctrl-0 = <&i2c3_pins>; 312 status = "okay"; 313 clock-frequency = <100000>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316}; 317 318&i2c5 { 319 pinctrl-names = "default"; 320 pinctrl-0 = <&i2c5_pins>; 321 status = "okay"; 322 clock-frequency = <100000>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325}; 326 327&i2c6 { 328 pinctrl-names = "default"; 329 pinctrl-0 = <&i2c6_pins>; 330 status = "okay"; 331 clock-frequency = <100000>; 332}; 333 334&mipi_tx0 { 335 status = "okay"; 336}; 337 338&mmc0 { 339 status = "okay"; 340 pinctrl-names = "default", "state_uhs"; 341 pinctrl-0 = <&mmc0_pins_default>; 342 pinctrl-1 = <&mmc0_pins_uhs>; 343 bus-width = <8>; 344 max-frequency = <200000000>; 345 cap-mmc-highspeed; 346 mmc-hs200-1_8v; 347 mmc-hs400-1_8v; 348 cap-mmc-hw-reset; 349 no-sdio; 350 no-sd; 351 hs400-ds-delay = <0x12814>; 352 vmmc-supply = <&mt6358_vemc_reg>; 353 vqmmc-supply = <&mt6358_vio18_reg>; 354 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; 355 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; 356 non-removable; 357}; 358 359&mmc1 { 360 status = "okay"; 361 pinctrl-names = "default", "state_uhs"; 362 pinctrl-0 = <&mmc1_pins_default>; 363 pinctrl-1 = <&mmc1_pins_uhs>; 364 vmmc-supply = <&mmc1_fixed_power>; 365 vqmmc-supply = <&mmc1_fixed_io>; 366 mmc-pwrseq = <&wifi_pwrseq>; 367 bus-width = <4>; 368 max-frequency = <200000000>; 369 drv-type = <2>; 370 cap-sd-highspeed; 371 sd-uhs-sdr50; 372 sd-uhs-sdr104; 373 keep-power-in-suspend; 374 enable-sdio-wakeup; 375 cap-sdio-irq; 376 non-removable; 377 no-mmc; 378 no-sd; 379 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>; 380 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 384 qca_wifi: qca-wifi@1 { 385 compatible = "qcom,ath10k"; 386 reg = <1>; 387 }; 388}; 389 390&mt6358_vdram2_reg { 391 regulator-always-on; 392}; 393 394&mt6358codec { 395 Avdd-supply = <&mt6358_vaud28_reg>; 396}; 397 398&mt6358_vsim1_reg { 399 regulator-min-microvolt = <2700000>; 400 regulator-max-microvolt = <2700000>; 401}; 402 403&mt6358_vsim2_reg { 404 regulator-min-microvolt = <2700000>; 405 regulator-max-microvolt = <2700000>; 406}; 407 408&pio { 409 bt_pins: bt-pins { 410 pins-bt-en { 411 pinmux = <PINMUX_GPIO120__FUNC_GPIO120>; 412 output-low; 413 }; 414 }; 415 416 ec_ap_int_odl: ec-ap-int-odl { 417 pins1 { 418 pinmux = <PINMUX_GPIO151__FUNC_GPIO151>; 419 input-enable; 420 bias-pull-up; 421 }; 422 }; 423 424 h1_int_od_l: h1-int-od-l { 425 pins1 { 426 pinmux = <PINMUX_GPIO153__FUNC_GPIO153>; 427 input-enable; 428 }; 429 }; 430 431 i2c0_pins: i2c0 { 432 pins-bus { 433 pinmux = <PINMUX_GPIO82__FUNC_SDA0>, 434 <PINMUX_GPIO83__FUNC_SCL0>; 435 mediatek,pull-up-adv = <3>; 436 mediatek,drive-strength-adv = <00>; 437 }; 438 }; 439 440 i2c1_pins: i2c1 { 441 pins-bus { 442 pinmux = <PINMUX_GPIO81__FUNC_SDA1>, 443 <PINMUX_GPIO84__FUNC_SCL1>; 444 mediatek,pull-up-adv = <3>; 445 mediatek,drive-strength-adv = <00>; 446 }; 447 }; 448 449 i2c2_pins: i2c2 { 450 pins-bus { 451 pinmux = <PINMUX_GPIO103__FUNC_SCL2>, 452 <PINMUX_GPIO104__FUNC_SDA2>; 453 bias-disable; 454 mediatek,drive-strength-adv = <00>; 455 }; 456 }; 457 458 i2c3_pins: i2c3 { 459 pins-bus { 460 pinmux = <PINMUX_GPIO50__FUNC_SCL3>, 461 <PINMUX_GPIO51__FUNC_SDA3>; 462 mediatek,pull-up-adv = <3>; 463 mediatek,drive-strength-adv = <00>; 464 }; 465 }; 466 467 i2c4_pins: i2c4 { 468 pins-bus { 469 pinmux = <PINMUX_GPIO105__FUNC_SCL4>, 470 <PINMUX_GPIO106__FUNC_SDA4>; 471 bias-disable; 472 mediatek,drive-strength-adv = <00>; 473 }; 474 }; 475 476 i2c5_pins: i2c5 { 477 pins-bus { 478 pinmux = <PINMUX_GPIO48__FUNC_SCL5>, 479 <PINMUX_GPIO49__FUNC_SDA5>; 480 mediatek,pull-up-adv = <3>; 481 mediatek,drive-strength-adv = <00>; 482 }; 483 }; 484 485 i2c6_pins: i2c6 { 486 pins-bus { 487 pinmux = <PINMUX_GPIO11__FUNC_SCL6>, 488 <PINMUX_GPIO12__FUNC_SDA6>; 489 bias-disable; 490 }; 491 }; 492 493 mmc0_pins_default: mmc0-pins-default { 494 pins-cmd-dat { 495 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 496 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 497 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 498 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 499 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 500 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 501 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 502 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 503 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 504 input-enable; 505 drive-strength = <MTK_DRIVE_14mA>; 506 mediatek,pull-up-adv = <01>; 507 }; 508 509 pins-clk { 510 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 511 drive-strength = <MTK_DRIVE_14mA>; 512 mediatek,pull-down-adv = <10>; 513 }; 514 515 pins-rst { 516 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 517 drive-strength = <MTK_DRIVE_14mA>; 518 mediatek,pull-down-adv = <01>; 519 }; 520 }; 521 522 mmc0_pins_uhs: mmc0-pins-uhs { 523 pins-cmd-dat { 524 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, 525 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, 526 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, 527 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, 528 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, 529 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, 530 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, 531 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, 532 <PINMUX_GPIO122__FUNC_MSDC0_CMD>; 533 input-enable; 534 drive-strength = <MTK_DRIVE_14mA>; 535 mediatek,pull-up-adv = <01>; 536 }; 537 538 pins-clk { 539 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; 540 drive-strength = <MTK_DRIVE_14mA>; 541 mediatek,pull-down-adv = <10>; 542 }; 543 544 pins-ds { 545 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; 546 drive-strength = <MTK_DRIVE_14mA>; 547 mediatek,pull-down-adv = <10>; 548 }; 549 550 pins-rst { 551 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; 552 drive-strength = <MTK_DRIVE_14mA>; 553 mediatek,pull-up-adv = <01>; 554 }; 555 }; 556 557 mmc1_pins_default: mmc1-pins-default { 558 pins-cmd-dat { 559 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 560 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 561 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 562 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 563 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 564 input-enable; 565 mediatek,pull-up-adv = <10>; 566 }; 567 568 pins-clk { 569 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 570 input-enable; 571 mediatek,pull-down-adv = <10>; 572 }; 573 }; 574 575 mmc1_pins_uhs: mmc1-pins-uhs { 576 pins-cmd-dat { 577 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, 578 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, 579 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, 580 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, 581 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; 582 drive-strength = <MTK_DRIVE_6mA>; 583 input-enable; 584 mediatek,pull-up-adv = <10>; 585 }; 586 587 pins-clk { 588 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; 589 drive-strength = <MTK_DRIVE_8mA>; 590 mediatek,pull-down-adv = <10>; 591 input-enable; 592 }; 593 }; 594 595 panel_pins_default: panel-pins-default { 596 panel-reset { 597 pinmux = <PINMUX_GPIO45__FUNC_GPIO45>; 598 output-low; 599 bias-pull-up; 600 }; 601 }; 602 603 pwm0_pin_default: pwm0-pin-default { 604 pins1 { 605 pinmux = <PINMUX_GPIO176__FUNC_GPIO176>; 606 output-high; 607 bias-pull-up; 608 }; 609 pins2 { 610 pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>; 611 }; 612 }; 613 614 scp_pins: scp { 615 pins-scp-uart { 616 pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>, 617 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>; 618 }; 619 }; 620 621 spi0_pins: spi0 { 622 pins-spi { 623 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, 624 <PINMUX_GPIO86__FUNC_GPIO86>, 625 <PINMUX_GPIO87__FUNC_SPI0_MO>, 626 <PINMUX_GPIO88__FUNC_SPI0_CLK>; 627 bias-disable; 628 }; 629 }; 630 631 spi1_pins: spi1 { 632 pins-spi { 633 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, 634 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, 635 <PINMUX_GPIO163__FUNC_SPI1_A_MO>, 636 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; 637 bias-disable; 638 }; 639 }; 640 641 spi2_pins: spi2 { 642 pins-spi { 643 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, 644 <PINMUX_GPIO1__FUNC_SPI2_MO>, 645 <PINMUX_GPIO2__FUNC_SPI2_CLK>; 646 bias-disable; 647 }; 648 pins-spi-mi { 649 pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>; 650 mediatek,pull-down-adv = <00>; 651 }; 652 }; 653 654 spi3_pins: spi3 { 655 pins-spi { 656 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, 657 <PINMUX_GPIO22__FUNC_SPI3_CSB>, 658 <PINMUX_GPIO23__FUNC_SPI3_MO>, 659 <PINMUX_GPIO24__FUNC_SPI3_CLK>; 660 bias-disable; 661 }; 662 }; 663 664 spi4_pins: spi4 { 665 pins-spi { 666 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, 667 <PINMUX_GPIO18__FUNC_SPI4_CSB>, 668 <PINMUX_GPIO19__FUNC_SPI4_MO>, 669 <PINMUX_GPIO20__FUNC_SPI4_CLK>; 670 bias-disable; 671 }; 672 }; 673 674 spi5_pins: spi5 { 675 pins-spi { 676 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, 677 <PINMUX_GPIO14__FUNC_SPI5_CSB>, 678 <PINMUX_GPIO15__FUNC_SPI5_MO>, 679 <PINMUX_GPIO16__FUNC_SPI5_CLK>; 680 bias-disable; 681 }; 682 }; 683 684 uart0_pins_default: uart0-pins-default { 685 pins-rx { 686 pinmux = <PINMUX_GPIO95__FUNC_URXD0>; 687 input-enable; 688 bias-pull-up; 689 }; 690 pins-tx { 691 pinmux = <PINMUX_GPIO96__FUNC_UTXD0>; 692 }; 693 }; 694 695 uart1_pins_default: uart1-pins-default { 696 pins-rx { 697 pinmux = <PINMUX_GPIO121__FUNC_URXD1>; 698 input-enable; 699 bias-pull-up; 700 }; 701 pins-tx { 702 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 703 }; 704 pins-rts { 705 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 706 output-enable; 707 }; 708 pins-cts { 709 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 710 input-enable; 711 }; 712 }; 713 714 uart1_pins_sleep: uart1-pins-sleep { 715 pins-rx { 716 pinmux = <PINMUX_GPIO121__FUNC_GPIO121>; 717 input-enable; 718 bias-pull-up; 719 }; 720 pins-tx { 721 pinmux = <PINMUX_GPIO115__FUNC_UTXD1>; 722 }; 723 pins-rts { 724 pinmux = <PINMUX_GPIO47__FUNC_URTS1>; 725 output-enable; 726 }; 727 pins-cts { 728 pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; 729 input-enable; 730 }; 731 }; 732 733 wifi_pins_pwrseq: wifi-pins-pwrseq { 734 pins-wifi-enable { 735 pinmux = <PINMUX_GPIO119__FUNC_GPIO119>; 736 output-low; 737 }; 738 }; 739 740 wifi_pins_wakeup: wifi-pins-wakeup { 741 pins-wifi-wakeup { 742 pinmux = <PINMUX_GPIO113__FUNC_GPIO113>; 743 input-enable; 744 }; 745 }; 746}; 747 748&pwm0 { 749 status = "okay"; 750 pinctrl-names = "default"; 751 pinctrl-0 = <&pwm0_pin_default>; 752}; 753 754&scp { 755 status = "okay"; 756 pinctrl-names = "default"; 757 pinctrl-0 = <&scp_pins>; 758 759 cros_ec { 760 compatible = "google,cros-ec-rpmsg"; 761 mtk,rpmsg-name = "cros-ec-rpmsg"; 762 }; 763}; 764 765&mfg { 766 domain-supply = <&mt6358_vgpu_reg>; 767}; 768 769&soc_data { 770 status = "okay"; 771}; 772 773&spi0 { 774 pinctrl-names = "default"; 775 pinctrl-0 = <&spi0_pins>; 776 mediatek,pad-select = <0>; 777 status = "okay"; 778 cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; 779 780 cr50@0 { 781 compatible = "google,cr50"; 782 reg = <0>; 783 spi-max-frequency = <1000000>; 784 pinctrl-names = "default"; 785 pinctrl-0 = <&h1_int_od_l>; 786 interrupt-parent = <&pio>; 787 interrupts = <153 IRQ_TYPE_EDGE_RISING>; 788 }; 789}; 790 791&spi1 { 792 pinctrl-names = "default"; 793 pinctrl-0 = <&spi1_pins>; 794 mediatek,pad-select = <0>; 795 status = "okay"; 796 797 w25q64dw: spi-flash@0 { 798 compatible = "winbond,w25q64dw", "jedec,spi-nor"; 799 reg = <0>; 800 spi-max-frequency = <25000000>; 801 }; 802}; 803 804&spi2 { 805 pinctrl-names = "default"; 806 pinctrl-0 = <&spi2_pins>; 807 mediatek,pad-select = <0>; 808 status = "okay"; 809 810 cros_ec: cros-ec@0 { 811 compatible = "google,cros-ec-spi"; 812 reg = <0>; 813 spi-max-frequency = <3000000>; 814 interrupt-parent = <&pio>; 815 interrupts = <151 IRQ_TYPE_LEVEL_LOW>; 816 pinctrl-names = "default"; 817 pinctrl-0 = <&ec_ap_int_odl>; 818 819 i2c_tunnel: i2c-tunnel { 820 compatible = "google,cros-ec-i2c-tunnel"; 821 google,remote-bus = <1>; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 }; 825 826 usbc_extcon: extcon0 { 827 compatible = "google,extcon-usbc-cros-ec"; 828 google,usb-port-id = <0>; 829 }; 830 831 cbas { 832 compatible = "google,cros-cbas"; 833 }; 834 }; 835}; 836 837&spi3 { 838 pinctrl-names = "default"; 839 pinctrl-0 = <&spi3_pins>; 840 mediatek,pad-select = <0>; 841 status = "disabled"; 842}; 843 844&spi4 { 845 pinctrl-names = "default"; 846 pinctrl-0 = <&spi4_pins>; 847 mediatek,pad-select = <0>; 848 status = "disabled"; 849}; 850 851&spi5 { 852 pinctrl-names = "default"; 853 pinctrl-0 = <&spi5_pins>; 854 mediatek,pad-select = <0>; 855 status = "disabled"; 856}; 857 858&ssusb { 859 dr_mode = "host"; 860 wakeup-source; 861 vusb33-supply = <&mt6358_vusb_reg>; 862 status = "okay"; 863}; 864 865&thermal_zones { 866 tboard1 { 867 polling-delay = <1000>; /* milliseconds */ 868 polling-delay-passive = <0>; /* milliseconds */ 869 thermal-sensors = <&tboard_thermistor1>; 870 }; 871 872 tboard2 { 873 polling-delay = <1000>; /* milliseconds */ 874 polling-delay-passive = <0>; /* milliseconds */ 875 thermal-sensors = <&tboard_thermistor2>; 876 }; 877}; 878 879&u3phy { 880 status = "okay"; 881}; 882 883&uart0 { 884 pinctrl-names = "default"; 885 pinctrl-0 = <&uart0_pins_default>; 886 status = "okay"; 887}; 888 889&uart1 { 890 pinctrl-names = "default", "sleep"; 891 pinctrl-0 = <&uart1_pins_default>; 892 pinctrl-1 = <&uart1_pins_sleep>; 893 status = "okay"; 894 interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>, 895 <&pio 121 IRQ_TYPE_EDGE_FALLING>; 896 897 bluetooth: bluetooth { 898 pinctrl-names = "default"; 899 pinctrl-0 = <&bt_pins>; 900 status = "okay"; 901 compatible = "qcom,qca6174-bt"; 902 enable-gpios = <&pio 120 0>; 903 clocks = <&clk32k>; 904 firmware-name = "nvm_00440302_i2s.bin"; 905 }; 906}; 907 908&usb_host { 909 #address-cells = <1>; 910 #size-cells = <0>; 911 vusb33-supply = <&mt6358_vusb_reg>; 912 status = "okay"; 913 914 hub@1 { 915 compatible = "usb5e3,610"; 916 reg = <1>; 917 }; 918}; 919 920#include <arm/cros-ec-keyboard.dtsi> 921#include <arm/cros-ec-sbs.dtsi> 922