1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,gpucc-msm8998.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/power/qcom-rpmpd.h> 9#include <dt-bindings/gpio/gpio.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 qcom,msm-id = <292 0x0>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 memory@80000000 { 22 device_type = "memory"; 23 /* We expect the bootloader to fill in the reg */ 24 reg = <0x0 0x80000000 0x0 0x0>; 25 }; 26 27 reserved-memory { 28 #address-cells = <2>; 29 #size-cells = <2>; 30 ranges; 31 32 hyp_mem: memory@85800000 { 33 reg = <0x0 0x85800000 0x0 0x600000>; 34 no-map; 35 }; 36 37 xbl_mem: memory@85e00000 { 38 reg = <0x0 0x85e00000 0x0 0x100000>; 39 no-map; 40 }; 41 42 smem_mem: smem-mem@86000000 { 43 reg = <0x0 0x86000000 0x0 0x200000>; 44 no-map; 45 }; 46 47 tz_mem: memory@86200000 { 48 reg = <0x0 0x86200000 0x0 0x2d00000>; 49 no-map; 50 }; 51 52 rmtfs_mem: memory@88f00000 { 53 compatible = "qcom,rmtfs-mem"; 54 reg = <0x0 0x88f00000 0x0 0x200000>; 55 no-map; 56 57 qcom,client-id = <1>; 58 qcom,vmid = <15>; 59 }; 60 61 spss_mem: memory@8ab00000 { 62 reg = <0x0 0x8ab00000 0x0 0x700000>; 63 no-map; 64 }; 65 66 adsp_mem: memory@8b200000 { 67 reg = <0x0 0x8b200000 0x0 0x1a00000>; 68 no-map; 69 }; 70 71 mpss_mem: memory@8cc00000 { 72 reg = <0x0 0x8cc00000 0x0 0x7000000>; 73 no-map; 74 }; 75 76 venus_mem: memory@93c00000 { 77 reg = <0x0 0x93c00000 0x0 0x500000>; 78 no-map; 79 }; 80 81 mba_mem: memory@94100000 { 82 reg = <0x0 0x94100000 0x0 0x200000>; 83 no-map; 84 }; 85 86 slpi_mem: memory@94300000 { 87 reg = <0x0 0x94300000 0x0 0xf00000>; 88 no-map; 89 }; 90 91 ipa_fw_mem: memory@95200000 { 92 reg = <0x0 0x95200000 0x0 0x10000>; 93 no-map; 94 }; 95 96 ipa_gsi_mem: memory@95210000 { 97 reg = <0x0 0x95210000 0x0 0x5000>; 98 no-map; 99 }; 100 101 gpu_mem: memory@95600000 { 102 reg = <0x0 0x95600000 0x0 0x100000>; 103 no-map; 104 }; 105 106 wlan_msa_mem: memory@95700000 { 107 reg = <0x0 0x95700000 0x0 0x100000>; 108 no-map; 109 }; 110 }; 111 112 clocks { 113 xo: xo-board { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 clock-frequency = <19200000>; 117 clock-output-names = "xo_board"; 118 }; 119 120 sleep_clk { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 clock-frequency = <32764>; 124 }; 125 }; 126 127 cpus { 128 #address-cells = <2>; 129 #size-cells = <0>; 130 131 CPU0: cpu@0 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo280"; 134 reg = <0x0 0x0>; 135 enable-method = "psci"; 136 capacity-dmips-mhz = <1024>; 137 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 138 next-level-cache = <&L2_0>; 139 L2_0: l2-cache { 140 compatible = "arm,arch-cache"; 141 cache-level = <2>; 142 }; 143 L1_I_0: l1-icache { 144 compatible = "arm,arch-cache"; 145 }; 146 L1_D_0: l1-dcache { 147 compatible = "arm,arch-cache"; 148 }; 149 }; 150 151 CPU1: cpu@1 { 152 device_type = "cpu"; 153 compatible = "qcom,kryo280"; 154 reg = <0x0 0x1>; 155 enable-method = "psci"; 156 capacity-dmips-mhz = <1024>; 157 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 158 next-level-cache = <&L2_0>; 159 L1_I_1: l1-icache { 160 compatible = "arm,arch-cache"; 161 }; 162 L1_D_1: l1-dcache { 163 compatible = "arm,arch-cache"; 164 }; 165 }; 166 167 CPU2: cpu@2 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo280"; 170 reg = <0x0 0x2>; 171 enable-method = "psci"; 172 capacity-dmips-mhz = <1024>; 173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 174 next-level-cache = <&L2_0>; 175 L1_I_2: l1-icache { 176 compatible = "arm,arch-cache"; 177 }; 178 L1_D_2: l1-dcache { 179 compatible = "arm,arch-cache"; 180 }; 181 }; 182 183 CPU3: cpu@3 { 184 device_type = "cpu"; 185 compatible = "qcom,kryo280"; 186 reg = <0x0 0x3>; 187 enable-method = "psci"; 188 capacity-dmips-mhz = <1024>; 189 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 190 next-level-cache = <&L2_0>; 191 L1_I_3: l1-icache { 192 compatible = "arm,arch-cache"; 193 }; 194 L1_D_3: l1-dcache { 195 compatible = "arm,arch-cache"; 196 }; 197 }; 198 199 CPU4: cpu@100 { 200 device_type = "cpu"; 201 compatible = "qcom,kryo280"; 202 reg = <0x0 0x100>; 203 enable-method = "psci"; 204 capacity-dmips-mhz = <1536>; 205 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 206 next-level-cache = <&L2_1>; 207 L2_1: l2-cache { 208 compatible = "arm,arch-cache"; 209 cache-level = <2>; 210 }; 211 L1_I_100: l1-icache { 212 compatible = "arm,arch-cache"; 213 }; 214 L1_D_100: l1-dcache { 215 compatible = "arm,arch-cache"; 216 }; 217 }; 218 219 CPU5: cpu@101 { 220 device_type = "cpu"; 221 compatible = "qcom,kryo280"; 222 reg = <0x0 0x101>; 223 enable-method = "psci"; 224 capacity-dmips-mhz = <1536>; 225 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 226 next-level-cache = <&L2_1>; 227 L1_I_101: l1-icache { 228 compatible = "arm,arch-cache"; 229 }; 230 L1_D_101: l1-dcache { 231 compatible = "arm,arch-cache"; 232 }; 233 }; 234 235 CPU6: cpu@102 { 236 device_type = "cpu"; 237 compatible = "qcom,kryo280"; 238 reg = <0x0 0x102>; 239 enable-method = "psci"; 240 capacity-dmips-mhz = <1536>; 241 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 242 next-level-cache = <&L2_1>; 243 L1_I_102: l1-icache { 244 compatible = "arm,arch-cache"; 245 }; 246 L1_D_102: l1-dcache { 247 compatible = "arm,arch-cache"; 248 }; 249 }; 250 251 CPU7: cpu@103 { 252 device_type = "cpu"; 253 compatible = "qcom,kryo280"; 254 reg = <0x0 0x103>; 255 enable-method = "psci"; 256 capacity-dmips-mhz = <1536>; 257 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 258 next-level-cache = <&L2_1>; 259 L1_I_103: l1-icache { 260 compatible = "arm,arch-cache"; 261 }; 262 L1_D_103: l1-dcache { 263 compatible = "arm,arch-cache"; 264 }; 265 }; 266 267 cpu-map { 268 cluster0 { 269 core0 { 270 cpu = <&CPU0>; 271 }; 272 273 core1 { 274 cpu = <&CPU1>; 275 }; 276 277 core2 { 278 cpu = <&CPU2>; 279 }; 280 281 core3 { 282 cpu = <&CPU3>; 283 }; 284 }; 285 286 cluster1 { 287 core0 { 288 cpu = <&CPU4>; 289 }; 290 291 core1 { 292 cpu = <&CPU5>; 293 }; 294 295 core2 { 296 cpu = <&CPU6>; 297 }; 298 299 core3 { 300 cpu = <&CPU7>; 301 }; 302 }; 303 }; 304 305 idle-states { 306 entry-method = "psci"; 307 308 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 309 compatible = "arm,idle-state"; 310 idle-state-name = "little-retention"; 311 /* CPU Retention (C2D), L2 Active */ 312 arm,psci-suspend-param = <0x00000002>; 313 entry-latency-us = <81>; 314 exit-latency-us = <86>; 315 min-residency-us = <504>; 316 }; 317 318 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 319 compatible = "arm,idle-state"; 320 idle-state-name = "little-power-collapse"; 321 /* CPU + L2 Power Collapse (C3, D4) */ 322 arm,psci-suspend-param = <0x40000003>; 323 entry-latency-us = <814>; 324 exit-latency-us = <4562>; 325 min-residency-us = <9183>; 326 local-timer-stop; 327 }; 328 329 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 330 compatible = "arm,idle-state"; 331 idle-state-name = "big-retention"; 332 /* CPU Retention (C2D), L2 Active */ 333 arm,psci-suspend-param = <0x00000002>; 334 entry-latency-us = <79>; 335 exit-latency-us = <82>; 336 min-residency-us = <1302>; 337 }; 338 339 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 340 compatible = "arm,idle-state"; 341 idle-state-name = "big-power-collapse"; 342 /* CPU + L2 Power Collapse (C3, D4) */ 343 arm,psci-suspend-param = <0x40000003>; 344 entry-latency-us = <724>; 345 exit-latency-us = <2027>; 346 min-residency-us = <9419>; 347 local-timer-stop; 348 }; 349 }; 350 }; 351 352 firmware { 353 scm { 354 compatible = "qcom,scm-msm8998", "qcom,scm"; 355 }; 356 }; 357 358 tcsr_mutex: hwlock { 359 compatible = "qcom,tcsr-mutex"; 360 syscon = <&tcsr_mutex_regs 0 0x1000>; 361 #hwlock-cells = <1>; 362 }; 363 364 psci { 365 compatible = "arm,psci-1.0"; 366 method = "smc"; 367 }; 368 369 rpm-glink { 370 compatible = "qcom,glink-rpm"; 371 372 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 373 qcom,rpm-msg-ram = <&rpm_msg_ram>; 374 mboxes = <&apcs_glb 0>; 375 376 rpm_requests: rpm-requests { 377 compatible = "qcom,rpm-msm8998"; 378 qcom,glink-channels = "rpm_requests"; 379 380 rpmcc: clock-controller { 381 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 382 #clock-cells = <1>; 383 }; 384 385 rpmpd: power-controller { 386 compatible = "qcom,msm8998-rpmpd"; 387 #power-domain-cells = <1>; 388 operating-points-v2 = <&rpmpd_opp_table>; 389 390 rpmpd_opp_table: opp-table { 391 compatible = "operating-points-v2"; 392 393 rpmpd_opp_ret: opp1 { 394 opp-level = <RPM_SMD_LEVEL_RETENTION>; 395 }; 396 397 rpmpd_opp_ret_plus: opp2 { 398 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 399 }; 400 401 rpmpd_opp_min_svs: opp3 { 402 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 403 }; 404 405 rpmpd_opp_low_svs: opp4 { 406 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 407 }; 408 409 rpmpd_opp_svs: opp5 { 410 opp-level = <RPM_SMD_LEVEL_SVS>; 411 }; 412 413 rpmpd_opp_svs_plus: opp6 { 414 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 415 }; 416 417 rpmpd_opp_nom: opp7 { 418 opp-level = <RPM_SMD_LEVEL_NOM>; 419 }; 420 421 rpmpd_opp_nom_plus: opp8 { 422 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 423 }; 424 425 rpmpd_opp_turbo: opp9 { 426 opp-level = <RPM_SMD_LEVEL_TURBO>; 427 }; 428 429 rpmpd_opp_turbo_plus: opp10 { 430 opp-level = <RPM_SMD_LEVEL_BINNING>; 431 }; 432 }; 433 }; 434 }; 435 }; 436 437 smem { 438 compatible = "qcom,smem"; 439 memory-region = <&smem_mem>; 440 hwlocks = <&tcsr_mutex 3>; 441 }; 442 443 smp2p-lpass { 444 compatible = "qcom,smp2p"; 445 qcom,smem = <443>, <429>; 446 447 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 448 449 mboxes = <&apcs_glb 10>; 450 451 qcom,local-pid = <0>; 452 qcom,remote-pid = <2>; 453 454 adsp_smp2p_out: master-kernel { 455 qcom,entry-name = "master-kernel"; 456 #qcom,smem-state-cells = <1>; 457 }; 458 459 adsp_smp2p_in: slave-kernel { 460 qcom,entry-name = "slave-kernel"; 461 462 interrupt-controller; 463 #interrupt-cells = <2>; 464 }; 465 }; 466 467 smp2p-mpss { 468 compatible = "qcom,smp2p"; 469 qcom,smem = <435>, <428>; 470 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 471 mboxes = <&apcs_glb 14>; 472 qcom,local-pid = <0>; 473 qcom,remote-pid = <1>; 474 475 modem_smp2p_out: master-kernel { 476 qcom,entry-name = "master-kernel"; 477 #qcom,smem-state-cells = <1>; 478 }; 479 480 modem_smp2p_in: slave-kernel { 481 qcom,entry-name = "slave-kernel"; 482 interrupt-controller; 483 #interrupt-cells = <2>; 484 }; 485 }; 486 487 smp2p-slpi { 488 compatible = "qcom,smp2p"; 489 qcom,smem = <481>, <430>; 490 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 491 mboxes = <&apcs_glb 26>; 492 qcom,local-pid = <0>; 493 qcom,remote-pid = <3>; 494 495 slpi_smp2p_out: master-kernel { 496 qcom,entry-name = "master-kernel"; 497 #qcom,smem-state-cells = <1>; 498 }; 499 500 slpi_smp2p_in: slave-kernel { 501 qcom,entry-name = "slave-kernel"; 502 interrupt-controller; 503 #interrupt-cells = <2>; 504 }; 505 }; 506 507 thermal-zones { 508 cpu0-thermal { 509 polling-delay-passive = <250>; 510 polling-delay = <1000>; 511 512 thermal-sensors = <&tsens0 1>; 513 514 trips { 515 cpu0_alert0: trip-point0 { 516 temperature = <75000>; 517 hysteresis = <2000>; 518 type = "passive"; 519 }; 520 521 cpu0_crit: cpu_crit { 522 temperature = <110000>; 523 hysteresis = <2000>; 524 type = "critical"; 525 }; 526 }; 527 }; 528 529 cpu1-thermal { 530 polling-delay-passive = <250>; 531 polling-delay = <1000>; 532 533 thermal-sensors = <&tsens0 2>; 534 535 trips { 536 cpu1_alert0: trip-point0 { 537 temperature = <75000>; 538 hysteresis = <2000>; 539 type = "passive"; 540 }; 541 542 cpu1_crit: cpu_crit { 543 temperature = <110000>; 544 hysteresis = <2000>; 545 type = "critical"; 546 }; 547 }; 548 }; 549 550 cpu2-thermal { 551 polling-delay-passive = <250>; 552 polling-delay = <1000>; 553 554 thermal-sensors = <&tsens0 3>; 555 556 trips { 557 cpu2_alert0: trip-point0 { 558 temperature = <75000>; 559 hysteresis = <2000>; 560 type = "passive"; 561 }; 562 563 cpu2_crit: cpu_crit { 564 temperature = <110000>; 565 hysteresis = <2000>; 566 type = "critical"; 567 }; 568 }; 569 }; 570 571 cpu3-thermal { 572 polling-delay-passive = <250>; 573 polling-delay = <1000>; 574 575 thermal-sensors = <&tsens0 4>; 576 577 trips { 578 cpu3_alert0: trip-point0 { 579 temperature = <75000>; 580 hysteresis = <2000>; 581 type = "passive"; 582 }; 583 584 cpu3_crit: cpu_crit { 585 temperature = <110000>; 586 hysteresis = <2000>; 587 type = "critical"; 588 }; 589 }; 590 }; 591 592 cpu4-thermal { 593 polling-delay-passive = <250>; 594 polling-delay = <1000>; 595 596 thermal-sensors = <&tsens0 7>; 597 598 trips { 599 cpu4_alert0: trip-point0 { 600 temperature = <75000>; 601 hysteresis = <2000>; 602 type = "passive"; 603 }; 604 605 cpu4_crit: cpu_crit { 606 temperature = <110000>; 607 hysteresis = <2000>; 608 type = "critical"; 609 }; 610 }; 611 }; 612 613 cpu5-thermal { 614 polling-delay-passive = <250>; 615 polling-delay = <1000>; 616 617 thermal-sensors = <&tsens0 8>; 618 619 trips { 620 cpu5_alert0: trip-point0 { 621 temperature = <75000>; 622 hysteresis = <2000>; 623 type = "passive"; 624 }; 625 626 cpu5_crit: cpu_crit { 627 temperature = <110000>; 628 hysteresis = <2000>; 629 type = "critical"; 630 }; 631 }; 632 }; 633 634 cpu6-thermal { 635 polling-delay-passive = <250>; 636 polling-delay = <1000>; 637 638 thermal-sensors = <&tsens0 9>; 639 640 trips { 641 cpu6_alert0: trip-point0 { 642 temperature = <75000>; 643 hysteresis = <2000>; 644 type = "passive"; 645 }; 646 647 cpu6_crit: cpu_crit { 648 temperature = <110000>; 649 hysteresis = <2000>; 650 type = "critical"; 651 }; 652 }; 653 }; 654 655 cpu7-thermal { 656 polling-delay-passive = <250>; 657 polling-delay = <1000>; 658 659 thermal-sensors = <&tsens0 10>; 660 661 trips { 662 cpu7_alert0: trip-point0 { 663 temperature = <75000>; 664 hysteresis = <2000>; 665 type = "passive"; 666 }; 667 668 cpu7_crit: cpu_crit { 669 temperature = <110000>; 670 hysteresis = <2000>; 671 type = "critical"; 672 }; 673 }; 674 }; 675 676 gpu-thermal-bottom { 677 polling-delay-passive = <250>; 678 polling-delay = <1000>; 679 680 thermal-sensors = <&tsens0 12>; 681 682 trips { 683 gpu1_alert0: trip-point0 { 684 temperature = <90000>; 685 hysteresis = <2000>; 686 type = "hot"; 687 }; 688 }; 689 }; 690 691 gpu-thermal-top { 692 polling-delay-passive = <250>; 693 polling-delay = <1000>; 694 695 thermal-sensors = <&tsens0 13>; 696 697 trips { 698 gpu2_alert0: trip-point0 { 699 temperature = <90000>; 700 hysteresis = <2000>; 701 type = "hot"; 702 }; 703 }; 704 }; 705 706 clust0-mhm-thermal { 707 polling-delay-passive = <250>; 708 polling-delay = <1000>; 709 710 thermal-sensors = <&tsens0 5>; 711 712 trips { 713 cluster0_mhm_alert0: trip-point0 { 714 temperature = <90000>; 715 hysteresis = <2000>; 716 type = "hot"; 717 }; 718 }; 719 }; 720 721 clust1-mhm-thermal { 722 polling-delay-passive = <250>; 723 polling-delay = <1000>; 724 725 thermal-sensors = <&tsens0 6>; 726 727 trips { 728 cluster1_mhm_alert0: trip-point0 { 729 temperature = <90000>; 730 hysteresis = <2000>; 731 type = "hot"; 732 }; 733 }; 734 }; 735 736 cluster1-l2-thermal { 737 polling-delay-passive = <250>; 738 polling-delay = <1000>; 739 740 thermal-sensors = <&tsens0 11>; 741 742 trips { 743 cluster1_l2_alert0: trip-point0 { 744 temperature = <90000>; 745 hysteresis = <2000>; 746 type = "hot"; 747 }; 748 }; 749 }; 750 751 modem-thermal { 752 polling-delay-passive = <250>; 753 polling-delay = <1000>; 754 755 thermal-sensors = <&tsens1 1>; 756 757 trips { 758 modem_alert0: trip-point0 { 759 temperature = <90000>; 760 hysteresis = <2000>; 761 type = "hot"; 762 }; 763 }; 764 }; 765 766 mem-thermal { 767 polling-delay-passive = <250>; 768 polling-delay = <1000>; 769 770 thermal-sensors = <&tsens1 2>; 771 772 trips { 773 mem_alert0: trip-point0 { 774 temperature = <90000>; 775 hysteresis = <2000>; 776 type = "hot"; 777 }; 778 }; 779 }; 780 781 wlan-thermal { 782 polling-delay-passive = <250>; 783 polling-delay = <1000>; 784 785 thermal-sensors = <&tsens1 3>; 786 787 trips { 788 wlan_alert0: trip-point0 { 789 temperature = <90000>; 790 hysteresis = <2000>; 791 type = "hot"; 792 }; 793 }; 794 }; 795 796 q6-dsp-thermal { 797 polling-delay-passive = <250>; 798 polling-delay = <1000>; 799 800 thermal-sensors = <&tsens1 4>; 801 802 trips { 803 q6_dsp_alert0: trip-point0 { 804 temperature = <90000>; 805 hysteresis = <2000>; 806 type = "hot"; 807 }; 808 }; 809 }; 810 811 camera-thermal { 812 polling-delay-passive = <250>; 813 polling-delay = <1000>; 814 815 thermal-sensors = <&tsens1 5>; 816 817 trips { 818 camera_alert0: trip-point0 { 819 temperature = <90000>; 820 hysteresis = <2000>; 821 type = "hot"; 822 }; 823 }; 824 }; 825 826 multimedia-thermal { 827 polling-delay-passive = <250>; 828 polling-delay = <1000>; 829 830 thermal-sensors = <&tsens1 6>; 831 832 trips { 833 multimedia_alert0: trip-point0 { 834 temperature = <90000>; 835 hysteresis = <2000>; 836 type = "hot"; 837 }; 838 }; 839 }; 840 }; 841 842 timer { 843 compatible = "arm,armv8-timer"; 844 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 845 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 846 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 847 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 848 }; 849 850 soc: soc { 851 #address-cells = <1>; 852 #size-cells = <1>; 853 ranges = <0 0 0 0xffffffff>; 854 compatible = "simple-bus"; 855 856 gcc: clock-controller@100000 { 857 compatible = "qcom,gcc-msm8998"; 858 #clock-cells = <1>; 859 #reset-cells = <1>; 860 #power-domain-cells = <1>; 861 reg = <0x00100000 0xb0000>; 862 }; 863 864 rpm_msg_ram: sram@778000 { 865 compatible = "qcom,rpm-msg-ram"; 866 reg = <0x00778000 0x7000>; 867 }; 868 869 qfprom: qfprom@780000 { 870 compatible = "qcom,qfprom"; 871 reg = <0x00780000 0x621c>; 872 #address-cells = <1>; 873 #size-cells = <1>; 874 875 qusb2_hstx_trim: hstx-trim@423a { 876 reg = <0x423a 0x1>; 877 bits = <0 4>; 878 }; 879 }; 880 881 tsens0: thermal@10ab000 { 882 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 883 reg = <0x010ab000 0x1000>, /* TM */ 884 <0x010aa000 0x1000>; /* SROT */ 885 #qcom,sensors = <14>; 886 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 888 interrupt-names = "uplow", "critical"; 889 #thermal-sensor-cells = <1>; 890 }; 891 892 tsens1: thermal@10ae000 { 893 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 894 reg = <0x010ae000 0x1000>, /* TM */ 895 <0x010ad000 0x1000>; /* SROT */ 896 #qcom,sensors = <8>; 897 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 899 interrupt-names = "uplow", "critical"; 900 #thermal-sensor-cells = <1>; 901 }; 902 903 anoc1_smmu: iommu@1680000 { 904 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 905 reg = <0x01680000 0x10000>; 906 #iommu-cells = <1>; 907 908 #global-interrupts = <0>; 909 interrupts = 910 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 911 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 912 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 913 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 914 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 915 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 916 }; 917 918 anoc2_smmu: iommu@16c0000 { 919 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 920 reg = <0x016c0000 0x40000>; 921 #iommu-cells = <1>; 922 923 #global-interrupts = <0>; 924 interrupts = 925 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 926 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 927 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 928 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 929 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 930 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 931 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, 932 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, 933 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 934 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; 935 }; 936 937 pcie0: pci@1c00000 { 938 compatible = "qcom,pcie-msm8996"; 939 reg = <0x01c00000 0x2000>, 940 <0x1b000000 0xf1d>, 941 <0x1b000f20 0xa8>, 942 <0x1b100000 0x100000>; 943 reg-names = "parf", "dbi", "elbi", "config"; 944 device_type = "pci"; 945 linux,pci-domain = <0>; 946 bus-range = <0x00 0xff>; 947 #address-cells = <3>; 948 #size-cells = <2>; 949 num-lanes = <1>; 950 phys = <&pciephy>; 951 phy-names = "pciephy"; 952 status = "disabled"; 953 954 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, 955 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 956 957 #interrupt-cells = <1>; 958 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 959 interrupt-names = "msi"; 960 interrupt-map-mask = <0 0 0 0x7>; 961 interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>, 962 <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>, 963 <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>, 964 <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>; 965 966 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 967 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 968 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 969 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 970 <&gcc GCC_PCIE_0_AUX_CLK>; 971 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux"; 972 973 power-domains = <&gcc PCIE_0_GDSC>; 974 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 975 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 976 }; 977 978 pcie_phy: phy@1c06000 { 979 compatible = "qcom,msm8998-qmp-pcie-phy"; 980 reg = <0x01c06000 0x18c>; 981 #address-cells = <1>; 982 #size-cells = <1>; 983 status = "disabled"; 984 ranges; 985 986 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 987 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 988 <&gcc GCC_PCIE_CLKREF_CLK>; 989 clock-names = "aux", "cfg_ahb", "ref"; 990 991 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 992 reset-names = "phy", "common"; 993 994 vdda-phy-supply = <&vreg_l1a_0p875>; 995 vdda-pll-supply = <&vreg_l2a_1p2>; 996 997 pciephy: phy@1c06800 { 998 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; 999 #phy-cells = <0>; 1000 1001 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1002 clock-names = "pipe0"; 1003 clock-output-names = "pcie_0_pipe_clk_src"; 1004 #clock-cells = <0>; 1005 }; 1006 }; 1007 1008 ufshc: ufshc@1da4000 { 1009 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1010 reg = <0x01da4000 0x2500>; 1011 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1012 phys = <&ufsphy_lanes>; 1013 phy-names = "ufsphy"; 1014 lanes-per-direction = <2>; 1015 power-domains = <&gcc UFS_GDSC>; 1016 status = "disabled"; 1017 #reset-cells = <1>; 1018 1019 clock-names = 1020 "core_clk", 1021 "bus_aggr_clk", 1022 "iface_clk", 1023 "core_clk_unipro", 1024 "ref_clk", 1025 "tx_lane0_sync_clk", 1026 "rx_lane0_sync_clk", 1027 "rx_lane1_sync_clk"; 1028 clocks = 1029 <&gcc GCC_UFS_AXI_CLK>, 1030 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1031 <&gcc GCC_UFS_AHB_CLK>, 1032 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1033 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1034 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1035 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1036 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1037 freq-table-hz = 1038 <50000000 200000000>, 1039 <0 0>, 1040 <0 0>, 1041 <37500000 150000000>, 1042 <0 0>, 1043 <0 0>, 1044 <0 0>, 1045 <0 0>; 1046 1047 resets = <&gcc GCC_UFS_BCR>; 1048 reset-names = "rst"; 1049 }; 1050 1051 ufsphy: phy@1da7000 { 1052 compatible = "qcom,msm8998-qmp-ufs-phy"; 1053 reg = <0x01da7000 0x18c>; 1054 #address-cells = <1>; 1055 #size-cells = <1>; 1056 status = "disabled"; 1057 ranges; 1058 1059 clock-names = 1060 "ref", 1061 "ref_aux"; 1062 clocks = 1063 <&gcc GCC_UFS_CLKREF_CLK>, 1064 <&gcc GCC_UFS_PHY_AUX_CLK>; 1065 1066 reset-names = "ufsphy"; 1067 resets = <&ufshc 0>; 1068 1069 ufsphy_lanes: phy@1da7400 { 1070 reg = <0x01da7400 0x128>, 1071 <0x01da7600 0x1fc>, 1072 <0x01da7c00 0x1dc>, 1073 <0x01da7800 0x128>, 1074 <0x01da7a00 0x1fc>; 1075 #phy-cells = <0>; 1076 }; 1077 }; 1078 1079 tcsr_mutex_regs: syscon@1f40000 { 1080 compatible = "syscon"; 1081 reg = <0x01f40000 0x40000>; 1082 }; 1083 1084 tlmm: pinctrl@3400000 { 1085 compatible = "qcom,msm8998-pinctrl"; 1086 reg = <0x03400000 0xc00000>; 1087 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1088 gpio-controller; 1089 #gpio-cells = <0x2>; 1090 interrupt-controller; 1091 #interrupt-cells = <0x2>; 1092 1093 sdc2_clk_on: sdc2_clk_on { 1094 config { 1095 pins = "sdc2_clk"; 1096 bias-disable; 1097 drive-strength = <16>; 1098 }; 1099 }; 1100 1101 sdc2_clk_off: sdc2_clk_off { 1102 config { 1103 pins = "sdc2_clk"; 1104 bias-disable; 1105 drive-strength = <2>; 1106 }; 1107 }; 1108 1109 sdc2_cmd_on: sdc2_cmd_on { 1110 config { 1111 pins = "sdc2_cmd"; 1112 bias-pull-up; 1113 drive-strength = <10>; 1114 }; 1115 }; 1116 1117 sdc2_cmd_off: sdc2_cmd_off { 1118 config { 1119 pins = "sdc2_cmd"; 1120 bias-pull-up; 1121 drive-strength = <2>; 1122 }; 1123 }; 1124 1125 sdc2_data_on: sdc2_data_on { 1126 config { 1127 pins = "sdc2_data"; 1128 bias-pull-up; 1129 drive-strength = <10>; 1130 }; 1131 }; 1132 1133 sdc2_data_off: sdc2_data_off { 1134 config { 1135 pins = "sdc2_data"; 1136 bias-pull-up; 1137 drive-strength = <2>; 1138 }; 1139 }; 1140 1141 sdc2_cd_on: sdc2_cd_on { 1142 mux { 1143 pins = "gpio95"; 1144 function = "gpio"; 1145 }; 1146 1147 config { 1148 pins = "gpio95"; 1149 bias-pull-up; 1150 drive-strength = <2>; 1151 }; 1152 }; 1153 1154 sdc2_cd_off: sdc2_cd_off { 1155 mux { 1156 pins = "gpio95"; 1157 function = "gpio"; 1158 }; 1159 1160 config { 1161 pins = "gpio95"; 1162 bias-pull-up; 1163 drive-strength = <2>; 1164 }; 1165 }; 1166 1167 blsp1_uart3_on: blsp1_uart3_on { 1168 tx { 1169 pins = "gpio45"; 1170 function = "blsp_uart3_a"; 1171 drive-strength = <2>; 1172 bias-disable; 1173 }; 1174 1175 rx { 1176 pins = "gpio46"; 1177 function = "blsp_uart3_a"; 1178 drive-strength = <2>; 1179 bias-disable; 1180 }; 1181 1182 cts { 1183 pins = "gpio47"; 1184 function = "blsp_uart3_a"; 1185 drive-strength = <2>; 1186 bias-disable; 1187 }; 1188 1189 rfr { 1190 pins = "gpio48"; 1191 function = "blsp_uart3_a"; 1192 drive-strength = <2>; 1193 bias-disable; 1194 }; 1195 }; 1196 1197 blsp1_i2c1_default: blsp1-i2c1-default { 1198 pins = "gpio2", "gpio3"; 1199 function = "blsp_i2c1"; 1200 drive-strength = <2>; 1201 bias-disable; 1202 }; 1203 1204 blsp1_i2c1_sleep: blsp1-i2c1-sleep { 1205 pins = "gpio2", "gpio3"; 1206 function = "blsp_i2c1"; 1207 drive-strength = <2>; 1208 bias-pull-up; 1209 }; 1210 1211 blsp1_i2c2_default: blsp1-i2c2-default { 1212 pins = "gpio32", "gpio33"; 1213 function = "blsp_i2c2"; 1214 drive-strength = <2>; 1215 bias-disable; 1216 }; 1217 1218 blsp1_i2c2_sleep: blsp1-i2c2-sleep { 1219 pins = "gpio32", "gpio33"; 1220 function = "blsp_i2c2"; 1221 drive-strength = <2>; 1222 bias-pull-up; 1223 }; 1224 1225 blsp1_i2c3_default: blsp1-i2c3-default { 1226 pins = "gpio47", "gpio48"; 1227 function = "blsp_i2c3"; 1228 drive-strength = <2>; 1229 bias-disable; 1230 }; 1231 1232 blsp1_i2c3_sleep: blsp1-i2c3-sleep { 1233 pins = "gpio47", "gpio48"; 1234 function = "blsp_i2c3"; 1235 drive-strength = <2>; 1236 bias-pull-up; 1237 }; 1238 1239 blsp1_i2c4_default: blsp1-i2c4-default { 1240 pins = "gpio10", "gpio11"; 1241 function = "blsp_i2c4"; 1242 drive-strength = <2>; 1243 bias-disable; 1244 }; 1245 1246 blsp1_i2c4_sleep: blsp1-i2c4-sleep { 1247 pins = "gpio10", "gpio11"; 1248 function = "blsp_i2c4"; 1249 drive-strength = <2>; 1250 bias-pull-up; 1251 }; 1252 1253 blsp1_i2c5_default: blsp1-i2c5-default { 1254 pins = "gpio87", "gpio88"; 1255 function = "blsp_i2c5"; 1256 drive-strength = <2>; 1257 bias-disable; 1258 }; 1259 1260 blsp1_i2c5_sleep: blsp1-i2c5-sleep { 1261 pins = "gpio87", "gpio88"; 1262 function = "blsp_i2c5"; 1263 drive-strength = <2>; 1264 bias-pull-up; 1265 }; 1266 1267 blsp1_i2c6_default: blsp1-i2c6-default { 1268 pins = "gpio43", "gpio44"; 1269 function = "blsp_i2c6"; 1270 drive-strength = <2>; 1271 bias-disable; 1272 }; 1273 1274 blsp1_i2c6_sleep: blsp1-i2c6-sleep { 1275 pins = "gpio43", "gpio44"; 1276 function = "blsp_i2c6"; 1277 drive-strength = <2>; 1278 bias-pull-up; 1279 }; 1280 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1281 blsp2_i2c1_default: blsp2-i2c1-default { 1282 pins = "gpio55", "gpio56"; 1283 function = "blsp_i2c7"; 1284 drive-strength = <2>; 1285 bias-disable; 1286 }; 1287 1288 blsp2_i2c1_sleep: blsp2-i2c1-sleep { 1289 pins = "gpio55", "gpio56"; 1290 function = "blsp_i2c7"; 1291 drive-strength = <2>; 1292 bias-pull-up; 1293 }; 1294 1295 blsp2_i2c2_default: blsp2-i2c2-default { 1296 pins = "gpio6", "gpio7"; 1297 function = "blsp_i2c8"; 1298 drive-strength = <2>; 1299 bias-disable; 1300 }; 1301 1302 blsp2_i2c2_sleep: blsp2-i2c2-sleep { 1303 pins = "gpio6", "gpio7"; 1304 function = "blsp_i2c8"; 1305 drive-strength = <2>; 1306 bias-pull-up; 1307 }; 1308 1309 blsp2_i2c3_default: blsp2-i2c3-default { 1310 pins = "gpio51", "gpio52"; 1311 function = "blsp_i2c9"; 1312 drive-strength = <2>; 1313 bias-disable; 1314 }; 1315 1316 blsp2_i2c3_sleep: blsp2-i2c3-sleep { 1317 pins = "gpio51", "gpio52"; 1318 function = "blsp_i2c9"; 1319 drive-strength = <2>; 1320 bias-pull-up; 1321 }; 1322 1323 blsp2_i2c4_default: blsp2-i2c4-default { 1324 pins = "gpio67", "gpio68"; 1325 function = "blsp_i2c10"; 1326 drive-strength = <2>; 1327 bias-disable; 1328 }; 1329 1330 blsp2_i2c4_sleep: blsp2-i2c4-sleep { 1331 pins = "gpio67", "gpio68"; 1332 function = "blsp_i2c10"; 1333 drive-strength = <2>; 1334 bias-pull-up; 1335 }; 1336 1337 blsp2_i2c5_default: blsp2-i2c5-default { 1338 pins = "gpio60", "gpio61"; 1339 function = "blsp_i2c11"; 1340 drive-strength = <2>; 1341 bias-disable; 1342 }; 1343 1344 blsp2_i2c5_sleep: blsp2-i2c5-sleep { 1345 pins = "gpio60", "gpio61"; 1346 function = "blsp_i2c11"; 1347 drive-strength = <2>; 1348 bias-pull-up; 1349 }; 1350 1351 blsp2_i2c6_default: blsp2-i2c6-default { 1352 pins = "gpio83", "gpio84"; 1353 function = "blsp_i2c12"; 1354 drive-strength = <2>; 1355 bias-disable; 1356 }; 1357 1358 blsp2_i2c6_sleep: blsp2-i2c6-sleep { 1359 pins = "gpio83", "gpio84"; 1360 function = "blsp_i2c12"; 1361 drive-strength = <2>; 1362 bias-pull-up; 1363 }; 1364 }; 1365 1366 remoteproc_mss: remoteproc@4080000 { 1367 compatible = "qcom,msm8998-mss-pil"; 1368 reg = <0x04080000 0x100>, <0x04180000 0x20>; 1369 reg-names = "qdsp6", "rmb"; 1370 1371 interrupts-extended = 1372 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1373 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1374 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1375 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1376 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1377 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1378 interrupt-names = "wdog", "fatal", "ready", 1379 "handover", "stop-ack", 1380 "shutdown-ack"; 1381 1382 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1383 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1384 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1385 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1386 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1387 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1388 <&rpmcc RPM_SMD_QDSS_CLK>, 1389 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1390 clock-names = "iface", "bus", "mem", "gpll0_mss", 1391 "snoc_axi", "mnoc_axi", "qdss", "xo"; 1392 1393 qcom,smem-states = <&modem_smp2p_out 0>; 1394 qcom,smem-state-names = "stop"; 1395 1396 resets = <&gcc GCC_MSS_RESTART>; 1397 reset-names = "mss_restart"; 1398 1399 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 1400 1401 power-domains = <&rpmpd MSM8998_VDDCX>, 1402 <&rpmpd MSM8998_VDDMX>; 1403 power-domain-names = "cx", "mx"; 1404 1405 status = "disabled"; 1406 1407 mba { 1408 memory-region = <&mba_mem>; 1409 }; 1410 1411 mpss { 1412 memory-region = <&mpss_mem>; 1413 }; 1414 1415 glink-edge { 1416 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1417 label = "modem"; 1418 qcom,remote-pid = <1>; 1419 mboxes = <&apcs_glb 15>; 1420 }; 1421 }; 1422 1423 gpucc: clock-controller@5065000 { 1424 compatible = "qcom,msm8998-gpucc"; 1425 #clock-cells = <1>; 1426 #reset-cells = <1>; 1427 #power-domain-cells = <1>; 1428 reg = <0x05065000 0x9000>; 1429 1430 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1431 <&gcc GPLL0_OUT_MAIN>; 1432 clock-names = "xo", 1433 "gpll0"; 1434 }; 1435 1436 remoteproc_slpi: remoteproc@5800000 { 1437 compatible = "qcom,msm8998-slpi-pas"; 1438 reg = <0x05800000 0x4040>; 1439 1440 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, 1441 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1442 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1443 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1444 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1445 interrupt-names = "wdog", "fatal", "ready", 1446 "handover", "stop-ack"; 1447 1448 px-supply = <&vreg_lvs2a_1p8>; 1449 1450 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1451 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1452 clock-names = "xo", "aggre2"; 1453 1454 memory-region = <&slpi_mem>; 1455 1456 qcom,smem-states = <&slpi_smp2p_out 0>; 1457 qcom,smem-state-names = "stop"; 1458 1459 power-domains = <&rpmpd MSM8998_SSCCX>; 1460 power-domain-names = "ssc_cx"; 1461 1462 status = "disabled"; 1463 1464 glink-edge { 1465 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 1466 label = "dsps"; 1467 qcom,remote-pid = <3>; 1468 mboxes = <&apcs_glb 27>; 1469 }; 1470 }; 1471 1472 stm: stm@6002000 { 1473 compatible = "arm,coresight-stm", "arm,primecell"; 1474 reg = <0x06002000 0x1000>, 1475 <0x16280000 0x180000>; 1476 reg-names = "stm-base", "stm-stimulus-base"; 1477 status = "disabled"; 1478 1479 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1480 clock-names = "apb_pclk", "atclk"; 1481 1482 out-ports { 1483 port { 1484 stm_out: endpoint { 1485 remote-endpoint = <&funnel0_in7>; 1486 }; 1487 }; 1488 }; 1489 }; 1490 1491 funnel1: funnel@6041000 { 1492 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1493 reg = <0x06041000 0x1000>; 1494 status = "disabled"; 1495 1496 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1497 clock-names = "apb_pclk", "atclk"; 1498 1499 out-ports { 1500 port { 1501 funnel0_out: endpoint { 1502 remote-endpoint = 1503 <&merge_funnel_in0>; 1504 }; 1505 }; 1506 }; 1507 1508 in-ports { 1509 #address-cells = <1>; 1510 #size-cells = <0>; 1511 1512 port@7 { 1513 reg = <7>; 1514 funnel0_in7: endpoint { 1515 remote-endpoint = <&stm_out>; 1516 }; 1517 }; 1518 }; 1519 }; 1520 1521 funnel2: funnel@6042000 { 1522 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1523 reg = <0x06042000 0x1000>; 1524 status = "disabled"; 1525 1526 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1527 clock-names = "apb_pclk", "atclk"; 1528 1529 out-ports { 1530 port { 1531 funnel1_out: endpoint { 1532 remote-endpoint = 1533 <&merge_funnel_in1>; 1534 }; 1535 }; 1536 }; 1537 1538 in-ports { 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 1542 port@6 { 1543 reg = <6>; 1544 funnel1_in6: endpoint { 1545 remote-endpoint = 1546 <&apss_merge_funnel_out>; 1547 }; 1548 }; 1549 }; 1550 }; 1551 1552 funnel3: funnel@6045000 { 1553 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1554 reg = <0x06045000 0x1000>; 1555 status = "disabled"; 1556 1557 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1558 clock-names = "apb_pclk", "atclk"; 1559 1560 out-ports { 1561 port { 1562 merge_funnel_out: endpoint { 1563 remote-endpoint = 1564 <&etf_in>; 1565 }; 1566 }; 1567 }; 1568 1569 in-ports { 1570 #address-cells = <1>; 1571 #size-cells = <0>; 1572 1573 port@0 { 1574 reg = <0>; 1575 merge_funnel_in0: endpoint { 1576 remote-endpoint = 1577 <&funnel0_out>; 1578 }; 1579 }; 1580 1581 port@1 { 1582 reg = <1>; 1583 merge_funnel_in1: endpoint { 1584 remote-endpoint = 1585 <&funnel1_out>; 1586 }; 1587 }; 1588 }; 1589 }; 1590 1591 replicator1: replicator@6046000 { 1592 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1593 reg = <0x06046000 0x1000>; 1594 status = "disabled"; 1595 1596 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1597 clock-names = "apb_pclk", "atclk"; 1598 1599 out-ports { 1600 port { 1601 replicator_out: endpoint { 1602 remote-endpoint = <&etr_in>; 1603 }; 1604 }; 1605 }; 1606 1607 in-ports { 1608 port { 1609 replicator_in: endpoint { 1610 remote-endpoint = <&etf_out>; 1611 }; 1612 }; 1613 }; 1614 }; 1615 1616 etf: etf@6047000 { 1617 compatible = "arm,coresight-tmc", "arm,primecell"; 1618 reg = <0x06047000 0x1000>; 1619 status = "disabled"; 1620 1621 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1622 clock-names = "apb_pclk", "atclk"; 1623 1624 out-ports { 1625 port { 1626 etf_out: endpoint { 1627 remote-endpoint = 1628 <&replicator_in>; 1629 }; 1630 }; 1631 }; 1632 1633 in-ports { 1634 port { 1635 etf_in: endpoint { 1636 remote-endpoint = 1637 <&merge_funnel_out>; 1638 }; 1639 }; 1640 }; 1641 }; 1642 1643 etr: etr@6048000 { 1644 compatible = "arm,coresight-tmc", "arm,primecell"; 1645 reg = <0x06048000 0x1000>; 1646 status = "disabled"; 1647 1648 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1649 clock-names = "apb_pclk", "atclk"; 1650 arm,scatter-gather; 1651 1652 in-ports { 1653 port { 1654 etr_in: endpoint { 1655 remote-endpoint = 1656 <&replicator_out>; 1657 }; 1658 }; 1659 }; 1660 }; 1661 1662 etm1: etm@7840000 { 1663 compatible = "arm,coresight-etm4x", "arm,primecell"; 1664 reg = <0x07840000 0x1000>; 1665 status = "disabled"; 1666 1667 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1668 clock-names = "apb_pclk", "atclk"; 1669 1670 cpu = <&CPU0>; 1671 1672 out-ports { 1673 port { 1674 etm0_out: endpoint { 1675 remote-endpoint = 1676 <&apss_funnel_in0>; 1677 }; 1678 }; 1679 }; 1680 }; 1681 1682 etm2: etm@7940000 { 1683 compatible = "arm,coresight-etm4x", "arm,primecell"; 1684 reg = <0x07940000 0x1000>; 1685 status = "disabled"; 1686 1687 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1688 clock-names = "apb_pclk", "atclk"; 1689 1690 cpu = <&CPU1>; 1691 1692 out-ports { 1693 port { 1694 etm1_out: endpoint { 1695 remote-endpoint = 1696 <&apss_funnel_in1>; 1697 }; 1698 }; 1699 }; 1700 }; 1701 1702 etm3: etm@7a40000 { 1703 compatible = "arm,coresight-etm4x", "arm,primecell"; 1704 reg = <0x07a40000 0x1000>; 1705 status = "disabled"; 1706 1707 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1708 clock-names = "apb_pclk", "atclk"; 1709 1710 cpu = <&CPU2>; 1711 1712 out-ports { 1713 port { 1714 etm2_out: endpoint { 1715 remote-endpoint = 1716 <&apss_funnel_in2>; 1717 }; 1718 }; 1719 }; 1720 }; 1721 1722 etm4: etm@7b40000 { 1723 compatible = "arm,coresight-etm4x", "arm,primecell"; 1724 reg = <0x07b40000 0x1000>; 1725 status = "disabled"; 1726 1727 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1728 clock-names = "apb_pclk", "atclk"; 1729 1730 cpu = <&CPU3>; 1731 1732 out-ports { 1733 port { 1734 etm3_out: endpoint { 1735 remote-endpoint = 1736 <&apss_funnel_in3>; 1737 }; 1738 }; 1739 }; 1740 }; 1741 1742 funnel4: funnel@7b60000 { /* APSS Funnel */ 1743 compatible = "arm,coresight-etm4x", "arm,primecell"; 1744 reg = <0x07b60000 0x1000>; 1745 status = "disabled"; 1746 1747 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1748 clock-names = "apb_pclk", "atclk"; 1749 1750 out-ports { 1751 port { 1752 apss_funnel_out: endpoint { 1753 remote-endpoint = 1754 <&apss_merge_funnel_in>; 1755 }; 1756 }; 1757 }; 1758 1759 in-ports { 1760 #address-cells = <1>; 1761 #size-cells = <0>; 1762 1763 port@0 { 1764 reg = <0>; 1765 apss_funnel_in0: endpoint { 1766 remote-endpoint = 1767 <&etm0_out>; 1768 }; 1769 }; 1770 1771 port@1 { 1772 reg = <1>; 1773 apss_funnel_in1: endpoint { 1774 remote-endpoint = 1775 <&etm1_out>; 1776 }; 1777 }; 1778 1779 port@2 { 1780 reg = <2>; 1781 apss_funnel_in2: endpoint { 1782 remote-endpoint = 1783 <&etm2_out>; 1784 }; 1785 }; 1786 1787 port@3 { 1788 reg = <3>; 1789 apss_funnel_in3: endpoint { 1790 remote-endpoint = 1791 <&etm3_out>; 1792 }; 1793 }; 1794 1795 port@4 { 1796 reg = <4>; 1797 apss_funnel_in4: endpoint { 1798 remote-endpoint = 1799 <&etm4_out>; 1800 }; 1801 }; 1802 1803 port@5 { 1804 reg = <5>; 1805 apss_funnel_in5: endpoint { 1806 remote-endpoint = 1807 <&etm5_out>; 1808 }; 1809 }; 1810 1811 port@6 { 1812 reg = <6>; 1813 apss_funnel_in6: endpoint { 1814 remote-endpoint = 1815 <&etm6_out>; 1816 }; 1817 }; 1818 1819 port@7 { 1820 reg = <7>; 1821 apss_funnel_in7: endpoint { 1822 remote-endpoint = 1823 <&etm7_out>; 1824 }; 1825 }; 1826 }; 1827 }; 1828 1829 funnel5: funnel@7b70000 { 1830 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1831 reg = <0x07b70000 0x1000>; 1832 status = "disabled"; 1833 1834 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1835 clock-names = "apb_pclk", "atclk"; 1836 1837 out-ports { 1838 port { 1839 apss_merge_funnel_out: endpoint { 1840 remote-endpoint = 1841 <&funnel1_in6>; 1842 }; 1843 }; 1844 }; 1845 1846 in-ports { 1847 port { 1848 apss_merge_funnel_in: endpoint { 1849 remote-endpoint = 1850 <&apss_funnel_out>; 1851 }; 1852 }; 1853 }; 1854 }; 1855 1856 etm5: etm@7c40000 { 1857 compatible = "arm,coresight-etm4x", "arm,primecell"; 1858 reg = <0x07c40000 0x1000>; 1859 status = "disabled"; 1860 1861 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1862 clock-names = "apb_pclk", "atclk"; 1863 1864 cpu = <&CPU4>; 1865 1866 out-ports { 1867 port{ 1868 etm4_out: endpoint { 1869 remote-endpoint = <&apss_funnel_in4>; 1870 }; 1871 }; 1872 }; 1873 }; 1874 1875 etm6: etm@7d40000 { 1876 compatible = "arm,coresight-etm4x", "arm,primecell"; 1877 reg = <0x07d40000 0x1000>; 1878 status = "disabled"; 1879 1880 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1881 clock-names = "apb_pclk", "atclk"; 1882 1883 cpu = <&CPU5>; 1884 1885 out-ports { 1886 port{ 1887 etm5_out: endpoint { 1888 remote-endpoint = <&apss_funnel_in5>; 1889 }; 1890 }; 1891 }; 1892 }; 1893 1894 etm7: etm@7e40000 { 1895 compatible = "arm,coresight-etm4x", "arm,primecell"; 1896 reg = <0x07e40000 0x1000>; 1897 status = "disabled"; 1898 1899 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1900 clock-names = "apb_pclk", "atclk"; 1901 1902 cpu = <&CPU6>; 1903 1904 out-ports { 1905 port{ 1906 etm6_out: endpoint { 1907 remote-endpoint = <&apss_funnel_in6>; 1908 }; 1909 }; 1910 }; 1911 }; 1912 1913 etm8: etm@7f40000 { 1914 compatible = "arm,coresight-etm4x", "arm,primecell"; 1915 reg = <0x07f40000 0x1000>; 1916 status = "disabled"; 1917 1918 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1919 clock-names = "apb_pclk", "atclk"; 1920 1921 cpu = <&CPU7>; 1922 1923 out-ports { 1924 port{ 1925 etm7_out: endpoint { 1926 remote-endpoint = <&apss_funnel_in7>; 1927 }; 1928 }; 1929 }; 1930 }; 1931 1932 spmi_bus: spmi@800f000 { 1933 compatible = "qcom,spmi-pmic-arb"; 1934 reg = <0x0800f000 0x1000>, 1935 <0x08400000 0x1000000>, 1936 <0x09400000 0x1000000>, 1937 <0x0a400000 0x220000>, 1938 <0x0800a000 0x3000>; 1939 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1940 interrupt-names = "periph_irq"; 1941 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1942 qcom,ee = <0>; 1943 qcom,channel = <0>; 1944 #address-cells = <2>; 1945 #size-cells = <0>; 1946 interrupt-controller; 1947 #interrupt-cells = <4>; 1948 cell-index = <0>; 1949 }; 1950 1951 usb3: usb@a8f8800 { 1952 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 1953 reg = <0x0a8f8800 0x400>; 1954 status = "disabled"; 1955 #address-cells = <1>; 1956 #size-cells = <1>; 1957 ranges; 1958 1959 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1960 <&gcc GCC_USB30_MASTER_CLK>, 1961 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 1962 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1963 <&gcc GCC_USB30_SLEEP_CLK>; 1964 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1965 "sleep"; 1966 1967 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1968 <&gcc GCC_USB30_MASTER_CLK>; 1969 assigned-clock-rates = <19200000>, <120000000>; 1970 1971 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1973 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1974 1975 power-domains = <&gcc USB_30_GDSC>; 1976 1977 resets = <&gcc GCC_USB_30_BCR>; 1978 1979 usb3_dwc3: dwc3@a800000 { 1980 compatible = "snps,dwc3"; 1981 reg = <0x0a800000 0xcd00>; 1982 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1983 snps,dis_u2_susphy_quirk; 1984 snps,dis_enblslpm_quirk; 1985 phys = <&qusb2phy>, <&usb1_ssphy>; 1986 phy-names = "usb2-phy", "usb3-phy"; 1987 snps,has-lpm-erratum; 1988 snps,hird-threshold = /bits/ 8 <0x10>; 1989 }; 1990 }; 1991 1992 usb3phy: phy@c010000 { 1993 compatible = "qcom,msm8998-qmp-usb3-phy"; 1994 reg = <0x0c010000 0x18c>; 1995 status = "disabled"; 1996 #clock-cells = <1>; 1997 #address-cells = <1>; 1998 #size-cells = <1>; 1999 ranges; 2000 2001 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2002 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2003 <&gcc GCC_USB3_CLKREF_CLK>; 2004 clock-names = "aux", "cfg_ahb", "ref"; 2005 2006 resets = <&gcc GCC_USB3_PHY_BCR>, 2007 <&gcc GCC_USB3PHY_PHY_BCR>; 2008 reset-names = "phy", "common"; 2009 2010 usb1_ssphy: phy@c010200 { 2011 reg = <0xc010200 0x128>, 2012 <0xc010400 0x200>, 2013 <0xc010c00 0x20c>, 2014 <0xc010600 0x128>, 2015 <0xc010800 0x200>; 2016 #phy-cells = <0>; 2017 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 2018 clock-names = "pipe0"; 2019 clock-output-names = "usb3_phy_pipe_clk_src"; 2020 }; 2021 }; 2022 2023 qusb2phy: phy@c012000 { 2024 compatible = "qcom,msm8998-qusb2-phy"; 2025 reg = <0x0c012000 0x2a8>; 2026 status = "disabled"; 2027 #phy-cells = <0>; 2028 2029 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2030 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 2031 clock-names = "cfg_ahb", "ref"; 2032 2033 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2034 2035 nvmem-cells = <&qusb2_hstx_trim>; 2036 }; 2037 2038 sdhc2: sdhci@c0a4900 { 2039 compatible = "qcom,sdhci-msm-v4"; 2040 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 2041 reg-names = "hc_mem", "core_mem"; 2042 2043 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2045 interrupt-names = "hc_irq", "pwr_irq"; 2046 2047 clock-names = "iface", "core", "xo"; 2048 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2049 <&gcc GCC_SDCC2_APPS_CLK>, 2050 <&xo>; 2051 bus-width = <4>; 2052 status = "disabled"; 2053 }; 2054 2055 blsp1_dma: dma-controller@c144000 { 2056 compatible = "qcom,bam-v1.7.0"; 2057 reg = <0x0c144000 0x25000>; 2058 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2059 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2060 clock-names = "bam_clk"; 2061 #dma-cells = <1>; 2062 qcom,ee = <0>; 2063 qcom,controlled-remotely; 2064 num-channels = <18>; 2065 qcom,num-ees = <4>; 2066 }; 2067 2068 blsp1_uart3: serial@c171000 { 2069 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2070 reg = <0x0c171000 0x1000>; 2071 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 2072 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 2073 <&gcc GCC_BLSP1_AHB_CLK>; 2074 clock-names = "core", "iface"; 2075 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 2076 dma-names = "tx", "rx"; 2077 pinctrl-names = "default"; 2078 pinctrl-0 = <&blsp1_uart3_on>; 2079 status = "disabled"; 2080 }; 2081 2082 blsp1_i2c1: i2c@c175000 { 2083 compatible = "qcom,i2c-qup-v2.2.1"; 2084 reg = <0x0c175000 0x600>; 2085 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2086 2087 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2088 <&gcc GCC_BLSP1_AHB_CLK>; 2089 clock-names = "core", "iface"; 2090 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2091 dma-names = "tx", "rx"; 2092 pinctrl-names = "default", "sleep"; 2093 pinctrl-0 = <&blsp1_i2c1_default>; 2094 pinctrl-1 = <&blsp1_i2c1_sleep>; 2095 clock-frequency = <400000>; 2096 2097 status = "disabled"; 2098 #address-cells = <1>; 2099 #size-cells = <0>; 2100 }; 2101 2102 blsp1_i2c2: i2c@c176000 { 2103 compatible = "qcom,i2c-qup-v2.2.1"; 2104 reg = <0x0c176000 0x600>; 2105 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2106 2107 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2108 <&gcc GCC_BLSP1_AHB_CLK>; 2109 clock-names = "core", "iface"; 2110 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2111 dma-names = "tx", "rx"; 2112 pinctrl-names = "default", "sleep"; 2113 pinctrl-0 = <&blsp1_i2c2_default>; 2114 pinctrl-1 = <&blsp1_i2c2_sleep>; 2115 clock-frequency = <400000>; 2116 2117 status = "disabled"; 2118 #address-cells = <1>; 2119 #size-cells = <0>; 2120 }; 2121 2122 blsp1_i2c3: i2c@c177000 { 2123 compatible = "qcom,i2c-qup-v2.2.1"; 2124 reg = <0x0c177000 0x600>; 2125 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2126 2127 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2128 <&gcc GCC_BLSP1_AHB_CLK>; 2129 clock-names = "core", "iface"; 2130 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2131 dma-names = "tx", "rx"; 2132 pinctrl-names = "default", "sleep"; 2133 pinctrl-0 = <&blsp1_i2c3_default>; 2134 pinctrl-1 = <&blsp1_i2c3_sleep>; 2135 clock-frequency = <400000>; 2136 2137 status = "disabled"; 2138 #address-cells = <1>; 2139 #size-cells = <0>; 2140 }; 2141 2142 blsp1_i2c4: i2c@c178000 { 2143 compatible = "qcom,i2c-qup-v2.2.1"; 2144 reg = <0x0c178000 0x600>; 2145 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2146 2147 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2148 <&gcc GCC_BLSP1_AHB_CLK>; 2149 clock-names = "core", "iface"; 2150 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2151 dma-names = "tx", "rx"; 2152 pinctrl-names = "default", "sleep"; 2153 pinctrl-0 = <&blsp1_i2c4_default>; 2154 pinctrl-1 = <&blsp1_i2c4_sleep>; 2155 clock-frequency = <400000>; 2156 2157 status = "disabled"; 2158 #address-cells = <1>; 2159 #size-cells = <0>; 2160 }; 2161 2162 blsp1_i2c5: i2c@c179000 { 2163 compatible = "qcom,i2c-qup-v2.2.1"; 2164 reg = <0x0c179000 0x600>; 2165 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2166 2167 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2168 <&gcc GCC_BLSP1_AHB_CLK>; 2169 clock-names = "core", "iface"; 2170 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2171 dma-names = "tx", "rx"; 2172 pinctrl-names = "default", "sleep"; 2173 pinctrl-0 = <&blsp1_i2c5_default>; 2174 pinctrl-1 = <&blsp1_i2c5_sleep>; 2175 clock-frequency = <400000>; 2176 2177 status = "disabled"; 2178 #address-cells = <1>; 2179 #size-cells = <0>; 2180 }; 2181 2182 blsp1_i2c6: i2c@c17a000 { 2183 compatible = "qcom,i2c-qup-v2.2.1"; 2184 reg = <0x0c17a000 0x600>; 2185 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2186 2187 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2188 <&gcc GCC_BLSP1_AHB_CLK>; 2189 clock-names = "core", "iface"; 2190 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2191 dma-names = "tx", "rx"; 2192 pinctrl-names = "default", "sleep"; 2193 pinctrl-0 = <&blsp1_i2c6_default>; 2194 pinctrl-1 = <&blsp1_i2c6_sleep>; 2195 clock-frequency = <400000>; 2196 2197 status = "disabled"; 2198 #address-cells = <1>; 2199 #size-cells = <0>; 2200 }; 2201 2202 blsp2_dma: dma@c184000 { 2203 compatible = "qcom,bam-v1.7.0"; 2204 reg = <0x0c184000 0x25000>; 2205 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 2206 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 2207 clock-names = "bam_clk"; 2208 #dma-cells = <1>; 2209 qcom,ee = <0>; 2210 qcom,controlled-remotely; 2211 num-channels = <18>; 2212 qcom,num-ees = <4>; 2213 }; 2214 2215 blsp2_uart1: serial@c1b0000 { 2216 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2217 reg = <0x0c1b0000 0x1000>; 2218 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2219 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 2220 <&gcc GCC_BLSP2_AHB_CLK>; 2221 clock-names = "core", "iface"; 2222 status = "disabled"; 2223 }; 2224 2225 blsp2_i2c1: i2c@c1b5000 { 2226 compatible = "qcom,i2c-qup-v2.2.1"; 2227 reg = <0x0c1b5000 0x600>; 2228 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2229 2230 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 2231 <&gcc GCC_BLSP2_AHB_CLK>; 2232 clock-names = "core", "iface"; 2233 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2234 dma-names = "tx", "rx"; 2235 pinctrl-names = "default", "sleep"; 2236 pinctrl-0 = <&blsp2_i2c1_default>; 2237 pinctrl-1 = <&blsp2_i2c1_sleep>; 2238 clock-frequency = <400000>; 2239 2240 status = "disabled"; 2241 #address-cells = <1>; 2242 #size-cells = <0>; 2243 }; 2244 2245 blsp2_i2c2: i2c@c1b6000 { 2246 compatible = "qcom,i2c-qup-v2.2.1"; 2247 reg = <0x0c1b6000 0x600>; 2248 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2249 2250 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 2251 <&gcc GCC_BLSP2_AHB_CLK>; 2252 clock-names = "core", "iface"; 2253 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2254 dma-names = "tx", "rx"; 2255 pinctrl-names = "default", "sleep"; 2256 pinctrl-0 = <&blsp2_i2c2_default>; 2257 pinctrl-1 = <&blsp2_i2c2_sleep>; 2258 clock-frequency = <400000>; 2259 2260 status = "disabled"; 2261 #address-cells = <1>; 2262 #size-cells = <0>; 2263 }; 2264 2265 blsp2_i2c3: i2c@c1b7000 { 2266 compatible = "qcom,i2c-qup-v2.2.1"; 2267 reg = <0x0c1b7000 0x600>; 2268 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2269 2270 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 2271 <&gcc GCC_BLSP2_AHB_CLK>; 2272 clock-names = "core", "iface"; 2273 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2274 dma-names = "tx", "rx"; 2275 pinctrl-names = "default", "sleep"; 2276 pinctrl-0 = <&blsp2_i2c3_default>; 2277 pinctrl-1 = <&blsp2_i2c3_sleep>; 2278 clock-frequency = <400000>; 2279 2280 status = "disabled"; 2281 #address-cells = <1>; 2282 #size-cells = <0>; 2283 }; 2284 2285 blsp2_i2c4: i2c@c1b8000 { 2286 compatible = "qcom,i2c-qup-v2.2.1"; 2287 reg = <0x0c1b8000 0x600>; 2288 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2289 2290 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 2291 <&gcc GCC_BLSP2_AHB_CLK>; 2292 clock-names = "core", "iface"; 2293 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2294 dma-names = "tx", "rx"; 2295 pinctrl-names = "default", "sleep"; 2296 pinctrl-0 = <&blsp2_i2c4_default>; 2297 pinctrl-1 = <&blsp2_i2c4_sleep>; 2298 clock-frequency = <400000>; 2299 2300 status = "disabled"; 2301 #address-cells = <1>; 2302 #size-cells = <0>; 2303 }; 2304 2305 blsp2_i2c5: i2c@c1b9000 { 2306 compatible = "qcom,i2c-qup-v2.2.1"; 2307 reg = <0x0c1b9000 0x600>; 2308 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2309 2310 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 2311 <&gcc GCC_BLSP2_AHB_CLK>; 2312 clock-names = "core", "iface"; 2313 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2314 dma-names = "tx", "rx"; 2315 pinctrl-names = "default", "sleep"; 2316 pinctrl-0 = <&blsp2_i2c5_default>; 2317 pinctrl-1 = <&blsp2_i2c5_sleep>; 2318 clock-frequency = <400000>; 2319 2320 status = "disabled"; 2321 #address-cells = <1>; 2322 #size-cells = <0>; 2323 }; 2324 2325 blsp2_i2c6: i2c@c1ba000 { 2326 compatible = "qcom,i2c-qup-v2.2.1"; 2327 reg = <0x0c1ba000 0x600>; 2328 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2329 2330 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 2331 <&gcc GCC_BLSP2_AHB_CLK>; 2332 clock-names = "core", "iface"; 2333 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2334 dma-names = "tx", "rx"; 2335 pinctrl-names = "default", "sleep"; 2336 pinctrl-0 = <&blsp2_i2c6_default>; 2337 pinctrl-1 = <&blsp2_i2c6_sleep>; 2338 clock-frequency = <400000>; 2339 2340 status = "disabled"; 2341 #address-cells = <1>; 2342 #size-cells = <0>; 2343 }; 2344 2345 remoteproc_adsp: remoteproc@17300000 { 2346 compatible = "qcom,msm8998-adsp-pas"; 2347 reg = <0x17300000 0x4040>; 2348 2349 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2350 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2351 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2352 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2353 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2354 interrupt-names = "wdog", "fatal", "ready", 2355 "handover", "stop-ack"; 2356 2357 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2358 clock-names = "xo"; 2359 2360 memory-region = <&adsp_mem>; 2361 2362 qcom,smem-states = <&adsp_smp2p_out 0>; 2363 qcom,smem-state-names = "stop"; 2364 2365 power-domains = <&rpmpd MSM8998_VDDCX>; 2366 power-domain-names = "cx"; 2367 2368 status = "disabled"; 2369 2370 glink-edge { 2371 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2372 label = "lpass"; 2373 qcom,remote-pid = <2>; 2374 mboxes = <&apcs_glb 9>; 2375 }; 2376 }; 2377 2378 apcs_glb: mailbox@17911000 { 2379 compatible = "qcom,msm8998-apcs-hmss-global"; 2380 reg = <0x17911000 0x1000>; 2381 2382 #mbox-cells = <1>; 2383 }; 2384 2385 timer@17920000 { 2386 #address-cells = <1>; 2387 #size-cells = <1>; 2388 ranges; 2389 compatible = "arm,armv7-timer-mem"; 2390 reg = <0x17920000 0x1000>; 2391 2392 frame@17921000 { 2393 frame-number = <0>; 2394 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2395 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2396 reg = <0x17921000 0x1000>, 2397 <0x17922000 0x1000>; 2398 }; 2399 2400 frame@17923000 { 2401 frame-number = <1>; 2402 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2403 reg = <0x17923000 0x1000>; 2404 status = "disabled"; 2405 }; 2406 2407 frame@17924000 { 2408 frame-number = <2>; 2409 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2410 reg = <0x17924000 0x1000>; 2411 status = "disabled"; 2412 }; 2413 2414 frame@17925000 { 2415 frame-number = <3>; 2416 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2417 reg = <0x17925000 0x1000>; 2418 status = "disabled"; 2419 }; 2420 2421 frame@17926000 { 2422 frame-number = <4>; 2423 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2424 reg = <0x17926000 0x1000>; 2425 status = "disabled"; 2426 }; 2427 2428 frame@17927000 { 2429 frame-number = <5>; 2430 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2431 reg = <0x17927000 0x1000>; 2432 status = "disabled"; 2433 }; 2434 2435 frame@17928000 { 2436 frame-number = <6>; 2437 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2438 reg = <0x17928000 0x1000>; 2439 status = "disabled"; 2440 }; 2441 }; 2442 2443 intc: interrupt-controller@17a00000 { 2444 compatible = "arm,gic-v3"; 2445 reg = <0x17a00000 0x10000>, /* GICD */ 2446 <0x17b00000 0x100000>; /* GICR * 8 */ 2447 #interrupt-cells = <3>; 2448 #address-cells = <1>; 2449 #size-cells = <1>; 2450 ranges; 2451 interrupt-controller; 2452 #redistributor-regions = <1>; 2453 redistributor-stride = <0x0 0x20000>; 2454 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2455 }; 2456 2457 wifi: wifi@18800000 { 2458 compatible = "qcom,wcn3990-wifi"; 2459 status = "disabled"; 2460 reg = <0x18800000 0x800000>; 2461 reg-names = "membase"; 2462 memory-region = <&wlan_msa_mem>; 2463 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; 2464 clock-names = "cxo_ref_clk_pin"; 2465 interrupts = 2466 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 2467 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2468 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2469 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2470 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2471 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2478 iommus = <&anoc2_smmu 0x1900>, 2479 <&anoc2_smmu 0x1901>; 2480 qcom,snoc-host-cap-8bit-quirk; 2481 }; 2482 }; 2483}; 2484