1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7180.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qusb2.h> 18#include <dt-bindings/power/qcom-aoss-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/reset/qcom,sdm845-aoss.h> 21#include <dt-bindings/reset/qcom,sdm845-pdc.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 aliases { 34 mmc1 = &sdhc_1; 35 mmc2 = &sdhc_2; 36 i2c0 = &i2c0; 37 i2c1 = &i2c1; 38 i2c2 = &i2c2; 39 i2c3 = &i2c3; 40 i2c4 = &i2c4; 41 i2c5 = &i2c5; 42 i2c6 = &i2c6; 43 i2c7 = &i2c7; 44 i2c8 = &i2c8; 45 i2c9 = &i2c9; 46 i2c10 = &i2c10; 47 i2c11 = &i2c11; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi3 = &spi3; 51 spi5 = &spi5; 52 spi6 = &spi6; 53 spi8 = &spi8; 54 spi10 = &spi10; 55 spi11 = &spi11; 56 }; 57 58 clocks { 59 xo_board: xo-board { 60 compatible = "fixed-clock"; 61 clock-frequency = <38400000>; 62 #clock-cells = <0>; 63 }; 64 65 sleep_clk: sleep-clk { 66 compatible = "fixed-clock"; 67 clock-frequency = <32764>; 68 #clock-cells = <0>; 69 }; 70 }; 71 72 reserved_memory: reserved-memory { 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 77 hyp_mem: memory@80000000 { 78 reg = <0x0 0x80000000 0x0 0x600000>; 79 no-map; 80 }; 81 82 xbl_mem: memory@80600000 { 83 reg = <0x0 0x80600000 0x0 0x200000>; 84 no-map; 85 }; 86 87 aop_mem: memory@80800000 { 88 reg = <0x0 0x80800000 0x0 0x20000>; 89 no-map; 90 }; 91 92 aop_cmd_db_mem: memory@80820000 { 93 reg = <0x0 0x80820000 0x0 0x20000>; 94 compatible = "qcom,cmd-db"; 95 no-map; 96 }; 97 98 sec_apps_mem: memory@808ff000 { 99 reg = <0x0 0x808ff000 0x0 0x1000>; 100 no-map; 101 }; 102 103 smem_mem: memory@80900000 { 104 reg = <0x0 0x80900000 0x0 0x200000>; 105 no-map; 106 }; 107 108 tz_mem: memory@80b00000 { 109 reg = <0x0 0x80b00000 0x0 0x3900000>; 110 no-map; 111 }; 112 113 ipa_fw_mem: memory@8b700000 { 114 reg = <0 0x8b700000 0 0x10000>; 115 no-map; 116 }; 117 118 rmtfs_mem: memory@94600000 { 119 compatible = "qcom,rmtfs-mem"; 120 reg = <0x0 0x94600000 0x0 0x200000>; 121 no-map; 122 123 qcom,client-id = <1>; 124 qcom,vmid = <15>; 125 }; 126 }; 127 128 cpus { 129 #address-cells = <2>; 130 #size-cells = <0>; 131 132 CPU0: cpu@0 { 133 device_type = "cpu"; 134 compatible = "qcom,kryo468"; 135 reg = <0x0 0x0>; 136 enable-method = "psci"; 137 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 138 &LITTLE_CPU_SLEEP_1 139 &CLUSTER_SLEEP_0>; 140 capacity-dmips-mhz = <415>; 141 dynamic-power-coefficient = <137>; 142 operating-points-v2 = <&cpu0_opp_table>; 143 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 144 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 145 next-level-cache = <&L2_0>; 146 #cooling-cells = <2>; 147 qcom,freq-domain = <&cpufreq_hw 0>; 148 L2_0: l2-cache { 149 compatible = "cache"; 150 next-level-cache = <&L3_0>; 151 L3_0: l3-cache { 152 compatible = "cache"; 153 }; 154 }; 155 }; 156 157 CPU1: cpu@100 { 158 device_type = "cpu"; 159 compatible = "qcom,kryo468"; 160 reg = <0x0 0x100>; 161 enable-method = "psci"; 162 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 163 &LITTLE_CPU_SLEEP_1 164 &CLUSTER_SLEEP_0>; 165 capacity-dmips-mhz = <415>; 166 dynamic-power-coefficient = <137>; 167 next-level-cache = <&L2_100>; 168 operating-points-v2 = <&cpu0_opp_table>; 169 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 170 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 171 #cooling-cells = <2>; 172 qcom,freq-domain = <&cpufreq_hw 0>; 173 L2_100: l2-cache { 174 compatible = "cache"; 175 next-level-cache = <&L3_0>; 176 }; 177 }; 178 179 CPU2: cpu@200 { 180 device_type = "cpu"; 181 compatible = "qcom,kryo468"; 182 reg = <0x0 0x200>; 183 enable-method = "psci"; 184 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 185 &LITTLE_CPU_SLEEP_1 186 &CLUSTER_SLEEP_0>; 187 capacity-dmips-mhz = <415>; 188 dynamic-power-coefficient = <137>; 189 next-level-cache = <&L2_200>; 190 operating-points-v2 = <&cpu0_opp_table>; 191 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 192 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 193 #cooling-cells = <2>; 194 qcom,freq-domain = <&cpufreq_hw 0>; 195 L2_200: l2-cache { 196 compatible = "cache"; 197 next-level-cache = <&L3_0>; 198 }; 199 }; 200 201 CPU3: cpu@300 { 202 device_type = "cpu"; 203 compatible = "qcom,kryo468"; 204 reg = <0x0 0x300>; 205 enable-method = "psci"; 206 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 207 &LITTLE_CPU_SLEEP_1 208 &CLUSTER_SLEEP_0>; 209 capacity-dmips-mhz = <415>; 210 dynamic-power-coefficient = <137>; 211 next-level-cache = <&L2_300>; 212 operating-points-v2 = <&cpu0_opp_table>; 213 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 214 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 215 #cooling-cells = <2>; 216 qcom,freq-domain = <&cpufreq_hw 0>; 217 L2_300: l2-cache { 218 compatible = "cache"; 219 next-level-cache = <&L3_0>; 220 }; 221 }; 222 223 CPU4: cpu@400 { 224 device_type = "cpu"; 225 compatible = "qcom,kryo468"; 226 reg = <0x0 0x400>; 227 enable-method = "psci"; 228 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 229 &LITTLE_CPU_SLEEP_1 230 &CLUSTER_SLEEP_0>; 231 capacity-dmips-mhz = <415>; 232 dynamic-power-coefficient = <137>; 233 next-level-cache = <&L2_400>; 234 operating-points-v2 = <&cpu0_opp_table>; 235 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 236 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 237 #cooling-cells = <2>; 238 qcom,freq-domain = <&cpufreq_hw 0>; 239 L2_400: l2-cache { 240 compatible = "cache"; 241 next-level-cache = <&L3_0>; 242 }; 243 }; 244 245 CPU5: cpu@500 { 246 device_type = "cpu"; 247 compatible = "qcom,kryo468"; 248 reg = <0x0 0x500>; 249 enable-method = "psci"; 250 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 251 &LITTLE_CPU_SLEEP_1 252 &CLUSTER_SLEEP_0>; 253 capacity-dmips-mhz = <415>; 254 dynamic-power-coefficient = <137>; 255 next-level-cache = <&L2_500>; 256 operating-points-v2 = <&cpu0_opp_table>; 257 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 258 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 259 #cooling-cells = <2>; 260 qcom,freq-domain = <&cpufreq_hw 0>; 261 L2_500: l2-cache { 262 compatible = "cache"; 263 next-level-cache = <&L3_0>; 264 }; 265 }; 266 267 CPU6: cpu@600 { 268 device_type = "cpu"; 269 compatible = "qcom,kryo468"; 270 reg = <0x0 0x600>; 271 enable-method = "psci"; 272 cpu-idle-states = <&BIG_CPU_SLEEP_0 273 &BIG_CPU_SLEEP_1 274 &CLUSTER_SLEEP_0>; 275 capacity-dmips-mhz = <1024>; 276 dynamic-power-coefficient = <480>; 277 next-level-cache = <&L2_600>; 278 operating-points-v2 = <&cpu6_opp_table>; 279 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 280 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 281 #cooling-cells = <2>; 282 qcom,freq-domain = <&cpufreq_hw 1>; 283 L2_600: l2-cache { 284 compatible = "cache"; 285 next-level-cache = <&L3_0>; 286 }; 287 }; 288 289 CPU7: cpu@700 { 290 device_type = "cpu"; 291 compatible = "qcom,kryo468"; 292 reg = <0x0 0x700>; 293 enable-method = "psci"; 294 cpu-idle-states = <&BIG_CPU_SLEEP_0 295 &BIG_CPU_SLEEP_1 296 &CLUSTER_SLEEP_0>; 297 capacity-dmips-mhz = <1024>; 298 dynamic-power-coefficient = <480>; 299 next-level-cache = <&L2_700>; 300 operating-points-v2 = <&cpu6_opp_table>; 301 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 302 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 303 #cooling-cells = <2>; 304 qcom,freq-domain = <&cpufreq_hw 1>; 305 L2_700: l2-cache { 306 compatible = "cache"; 307 next-level-cache = <&L3_0>; 308 }; 309 }; 310 311 cpu-map { 312 cluster0 { 313 core0 { 314 cpu = <&CPU0>; 315 }; 316 317 core1 { 318 cpu = <&CPU1>; 319 }; 320 321 core2 { 322 cpu = <&CPU2>; 323 }; 324 325 core3 { 326 cpu = <&CPU3>; 327 }; 328 329 core4 { 330 cpu = <&CPU4>; 331 }; 332 333 core5 { 334 cpu = <&CPU5>; 335 }; 336 337 core6 { 338 cpu = <&CPU6>; 339 }; 340 341 core7 { 342 cpu = <&CPU7>; 343 }; 344 }; 345 }; 346 347 idle-states { 348 entry-method = "psci"; 349 350 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 351 compatible = "arm,idle-state"; 352 idle-state-name = "little-power-down"; 353 arm,psci-suspend-param = <0x40000003>; 354 entry-latency-us = <549>; 355 exit-latency-us = <901>; 356 min-residency-us = <1774>; 357 local-timer-stop; 358 }; 359 360 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 361 compatible = "arm,idle-state"; 362 idle-state-name = "little-rail-power-down"; 363 arm,psci-suspend-param = <0x40000004>; 364 entry-latency-us = <702>; 365 exit-latency-us = <915>; 366 min-residency-us = <4001>; 367 local-timer-stop; 368 }; 369 370 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 371 compatible = "arm,idle-state"; 372 idle-state-name = "big-power-down"; 373 arm,psci-suspend-param = <0x40000003>; 374 entry-latency-us = <523>; 375 exit-latency-us = <1244>; 376 min-residency-us = <2207>; 377 local-timer-stop; 378 }; 379 380 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 381 compatible = "arm,idle-state"; 382 idle-state-name = "big-rail-power-down"; 383 arm,psci-suspend-param = <0x40000004>; 384 entry-latency-us = <526>; 385 exit-latency-us = <1854>; 386 min-residency-us = <5555>; 387 local-timer-stop; 388 }; 389 390 CLUSTER_SLEEP_0: cluster-sleep-0 { 391 compatible = "arm,idle-state"; 392 idle-state-name = "cluster-power-down"; 393 arm,psci-suspend-param = <0x40003444>; 394 entry-latency-us = <3263>; 395 exit-latency-us = <6562>; 396 min-residency-us = <9926>; 397 local-timer-stop; 398 }; 399 }; 400 }; 401 402 cpu0_opp_table: cpu0_opp_table { 403 compatible = "operating-points-v2"; 404 opp-shared; 405 406 cpu0_opp1: opp-300000000 { 407 opp-hz = /bits/ 64 <300000000>; 408 opp-peak-kBps = <1200000 4800000>; 409 }; 410 411 cpu0_opp2: opp-576000000 { 412 opp-hz = /bits/ 64 <576000000>; 413 opp-peak-kBps = <1200000 4800000>; 414 }; 415 416 cpu0_opp3: opp-768000000 { 417 opp-hz = /bits/ 64 <768000000>; 418 opp-peak-kBps = <1200000 4800000>; 419 }; 420 421 cpu0_opp4: opp-1017600000 { 422 opp-hz = /bits/ 64 <1017600000>; 423 opp-peak-kBps = <1804000 8908800>; 424 }; 425 426 cpu0_opp5: opp-1248000000 { 427 opp-hz = /bits/ 64 <1248000000>; 428 opp-peak-kBps = <2188000 12902400>; 429 }; 430 431 cpu0_opp6: opp-1324800000 { 432 opp-hz = /bits/ 64 <1324800000>; 433 opp-peak-kBps = <2188000 12902400>; 434 }; 435 436 cpu0_opp7: opp-1516800000 { 437 opp-hz = /bits/ 64 <1516800000>; 438 opp-peak-kBps = <3072000 15052800>; 439 }; 440 441 cpu0_opp8: opp-1612800000 { 442 opp-hz = /bits/ 64 <1612800000>; 443 opp-peak-kBps = <3072000 15052800>; 444 }; 445 446 cpu0_opp9: opp-1708800000 { 447 opp-hz = /bits/ 64 <1708800000>; 448 opp-peak-kBps = <3072000 15052800>; 449 }; 450 451 cpu0_opp10: opp-1804800000 { 452 opp-hz = /bits/ 64 <1804800000>; 453 opp-peak-kBps = <4068000 22425600>; 454 }; 455 }; 456 457 cpu6_opp_table: cpu6_opp_table { 458 compatible = "operating-points-v2"; 459 opp-shared; 460 461 cpu6_opp1: opp-300000000 { 462 opp-hz = /bits/ 64 <300000000>; 463 opp-peak-kBps = <2188000 8908800>; 464 }; 465 466 cpu6_opp2: opp-652800000 { 467 opp-hz = /bits/ 64 <652800000>; 468 opp-peak-kBps = <2188000 8908800>; 469 }; 470 471 cpu6_opp3: opp-825600000 { 472 opp-hz = /bits/ 64 <825600000>; 473 opp-peak-kBps = <2188000 8908800>; 474 }; 475 476 cpu6_opp4: opp-979200000 { 477 opp-hz = /bits/ 64 <979200000>; 478 opp-peak-kBps = <2188000 8908800>; 479 }; 480 481 cpu6_opp5: opp-1113600000 { 482 opp-hz = /bits/ 64 <1113600000>; 483 opp-peak-kBps = <2188000 8908800>; 484 }; 485 486 cpu6_opp6: opp-1267200000 { 487 opp-hz = /bits/ 64 <1267200000>; 488 opp-peak-kBps = <4068000 12902400>; 489 }; 490 491 cpu6_opp7: opp-1555200000 { 492 opp-hz = /bits/ 64 <1555200000>; 493 opp-peak-kBps = <4068000 15052800>; 494 }; 495 496 cpu6_opp8: opp-1708800000 { 497 opp-hz = /bits/ 64 <1708800000>; 498 opp-peak-kBps = <6220000 19353600>; 499 }; 500 501 cpu6_opp9: opp-1843200000 { 502 opp-hz = /bits/ 64 <1843200000>; 503 opp-peak-kBps = <6220000 19353600>; 504 }; 505 506 cpu6_opp10: opp-1900800000 { 507 opp-hz = /bits/ 64 <1900800000>; 508 opp-peak-kBps = <6220000 22425600>; 509 }; 510 511 cpu6_opp11: opp-1996800000 { 512 opp-hz = /bits/ 64 <1996800000>; 513 opp-peak-kBps = <6220000 22425600>; 514 }; 515 516 cpu6_opp12: opp-2112000000 { 517 opp-hz = /bits/ 64 <2112000000>; 518 opp-peak-kBps = <6220000 22425600>; 519 }; 520 521 cpu6_opp13: opp-2208000000 { 522 opp-hz = /bits/ 64 <2208000000>; 523 opp-peak-kBps = <7216000 22425600>; 524 }; 525 526 cpu6_opp14: opp-2323200000 { 527 opp-hz = /bits/ 64 <2323200000>; 528 opp-peak-kBps = <7216000 22425600>; 529 }; 530 531 cpu6_opp15: opp-2400000000 { 532 opp-hz = /bits/ 64 <2400000000>; 533 opp-peak-kBps = <8532000 23347200>; 534 }; 535 536 cpu6_opp16: opp-2553600000 { 537 opp-hz = /bits/ 64 <2553600000>; 538 opp-peak-kBps = <8532000 23347200>; 539 }; 540 }; 541 542 memory@80000000 { 543 device_type = "memory"; 544 /* We expect the bootloader to fill in the size */ 545 reg = <0 0x80000000 0 0>; 546 }; 547 548 pmu { 549 compatible = "arm,armv8-pmuv3"; 550 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 551 }; 552 553 firmware { 554 scm { 555 compatible = "qcom,scm-sc7180", "qcom,scm"; 556 }; 557 }; 558 559 tcsr_mutex: hwlock { 560 compatible = "qcom,tcsr-mutex"; 561 syscon = <&tcsr_mutex_regs 0 0x1000>; 562 #hwlock-cells = <1>; 563 }; 564 565 smem { 566 compatible = "qcom,smem"; 567 memory-region = <&smem_mem>; 568 hwlocks = <&tcsr_mutex 3>; 569 }; 570 571 smp2p-cdsp { 572 compatible = "qcom,smp2p"; 573 qcom,smem = <94>, <432>; 574 575 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 576 577 mboxes = <&apss_shared 6>; 578 579 qcom,local-pid = <0>; 580 qcom,remote-pid = <5>; 581 582 cdsp_smp2p_out: master-kernel { 583 qcom,entry-name = "master-kernel"; 584 #qcom,smem-state-cells = <1>; 585 }; 586 587 cdsp_smp2p_in: slave-kernel { 588 qcom,entry-name = "slave-kernel"; 589 590 interrupt-controller; 591 #interrupt-cells = <2>; 592 }; 593 }; 594 595 smp2p-lpass { 596 compatible = "qcom,smp2p"; 597 qcom,smem = <443>, <429>; 598 599 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 600 601 mboxes = <&apss_shared 10>; 602 603 qcom,local-pid = <0>; 604 qcom,remote-pid = <2>; 605 606 adsp_smp2p_out: master-kernel { 607 qcom,entry-name = "master-kernel"; 608 #qcom,smem-state-cells = <1>; 609 }; 610 611 adsp_smp2p_in: slave-kernel { 612 qcom,entry-name = "slave-kernel"; 613 614 interrupt-controller; 615 #interrupt-cells = <2>; 616 }; 617 }; 618 619 smp2p-mpss { 620 compatible = "qcom,smp2p"; 621 qcom,smem = <435>, <428>; 622 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 623 mboxes = <&apss_shared 14>; 624 qcom,local-pid = <0>; 625 qcom,remote-pid = <1>; 626 627 modem_smp2p_out: master-kernel { 628 qcom,entry-name = "master-kernel"; 629 #qcom,smem-state-cells = <1>; 630 }; 631 632 modem_smp2p_in: slave-kernel { 633 qcom,entry-name = "slave-kernel"; 634 interrupt-controller; 635 #interrupt-cells = <2>; 636 }; 637 638 ipa_smp2p_out: ipa-ap-to-modem { 639 qcom,entry-name = "ipa"; 640 #qcom,smem-state-cells = <1>; 641 }; 642 643 ipa_smp2p_in: ipa-modem-to-ap { 644 qcom,entry-name = "ipa"; 645 interrupt-controller; 646 #interrupt-cells = <2>; 647 }; 648 }; 649 650 psci { 651 compatible = "arm,psci-1.0"; 652 method = "smc"; 653 }; 654 655 soc: soc@0 { 656 #address-cells = <2>; 657 #size-cells = <2>; 658 ranges = <0 0 0 0 0x10 0>; 659 dma-ranges = <0 0 0 0 0x10 0>; 660 compatible = "simple-bus"; 661 662 gcc: clock-controller@100000 { 663 compatible = "qcom,gcc-sc7180"; 664 reg = <0 0x00100000 0 0x1f0000>; 665 clocks = <&rpmhcc RPMH_CXO_CLK>, 666 <&rpmhcc RPMH_CXO_CLK_A>, 667 <&sleep_clk>; 668 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 669 #clock-cells = <1>; 670 #reset-cells = <1>; 671 #power-domain-cells = <1>; 672 }; 673 674 qfprom: efuse@784000 { 675 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 676 reg = <0 0x00784000 0 0x7a0>, 677 <0 0x00780000 0 0x7a0>, 678 <0 0x00782000 0 0x100>, 679 <0 0x00786000 0 0x1fff>; 680 681 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 682 clock-names = "core"; 683 #address-cells = <1>; 684 #size-cells = <1>; 685 686 qusb2p_hstx_trim: hstx-trim-primary@25b { 687 reg = <0x25b 0x1>; 688 bits = <1 3>; 689 }; 690 691 gpu_speed_bin: gpu_speed_bin@1d2 { 692 reg = <0x1d2 0x2>; 693 bits = <5 8>; 694 }; 695 }; 696 697 sdhc_1: sdhci@7c4000 { 698 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 699 reg = <0 0x7c4000 0 0x1000>, 700 <0 0x07c5000 0 0x1000>; 701 reg-names = "hc", "cqhci"; 702 703 iommus = <&apps_smmu 0x60 0x0>; 704 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 706 interrupt-names = "hc_irq", "pwr_irq"; 707 708 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 709 <&gcc GCC_SDCC1_AHB_CLK>, 710 <&rpmhcc RPMH_CXO_CLK>; 711 clock-names = "core", "iface", "xo"; 712 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 713 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 714 interconnect-names = "sdhc-ddr","cpu-sdhc"; 715 power-domains = <&rpmhpd SC7180_CX>; 716 operating-points-v2 = <&sdhc1_opp_table>; 717 718 bus-width = <8>; 719 non-removable; 720 supports-cqe; 721 722 mmc-ddr-1_8v; 723 mmc-hs200-1_8v; 724 mmc-hs400-1_8v; 725 mmc-hs400-enhanced-strobe; 726 727 status = "disabled"; 728 729 sdhc1_opp_table: sdhc1-opp-table { 730 compatible = "operating-points-v2"; 731 732 opp-100000000 { 733 opp-hz = /bits/ 64 <100000000>; 734 required-opps = <&rpmhpd_opp_low_svs>; 735 opp-peak-kBps = <1800000 600000>; 736 opp-avg-kBps = <100000 0>; 737 }; 738 739 opp-384000000 { 740 opp-hz = /bits/ 64 <384000000>; 741 required-opps = <&rpmhpd_opp_nom>; 742 opp-peak-kBps = <5400000 1600000>; 743 opp-avg-kBps = <390000 0>; 744 }; 745 }; 746 }; 747 748 qup_opp_table: qup-opp-table { 749 compatible = "operating-points-v2"; 750 751 opp-75000000 { 752 opp-hz = /bits/ 64 <75000000>; 753 required-opps = <&rpmhpd_opp_low_svs>; 754 }; 755 756 opp-100000000 { 757 opp-hz = /bits/ 64 <100000000>; 758 required-opps = <&rpmhpd_opp_svs>; 759 }; 760 761 opp-128000000 { 762 opp-hz = /bits/ 64 <128000000>; 763 required-opps = <&rpmhpd_opp_nom>; 764 }; 765 }; 766 767 qupv3_id_0: geniqup@8c0000 { 768 compatible = "qcom,geni-se-qup"; 769 reg = <0 0x008c0000 0 0x6000>; 770 clock-names = "m-ahb", "s-ahb"; 771 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 772 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 773 #address-cells = <2>; 774 #size-cells = <2>; 775 ranges; 776 iommus = <&apps_smmu 0x43 0x0>; 777 status = "disabled"; 778 779 i2c0: i2c@880000 { 780 compatible = "qcom,geni-i2c"; 781 reg = <0 0x00880000 0 0x4000>; 782 clock-names = "se"; 783 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 784 pinctrl-names = "default"; 785 pinctrl-0 = <&qup_i2c0_default>; 786 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 790 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 791 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 792 interconnect-names = "qup-core", "qup-config", 793 "qup-memory"; 794 power-domains = <&rpmhpd SC7180_CX>; 795 required-opps = <&rpmhpd_opp_low_svs>; 796 status = "disabled"; 797 }; 798 799 spi0: spi@880000 { 800 compatible = "qcom,geni-spi"; 801 reg = <0 0x00880000 0 0x4000>; 802 clock-names = "se"; 803 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 804 pinctrl-names = "default"; 805 pinctrl-0 = <&qup_spi0_default>; 806 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 power-domains = <&rpmhpd SC7180_CX>; 810 operating-points-v2 = <&qup_opp_table>; 811 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 812 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 813 interconnect-names = "qup-core", "qup-config"; 814 status = "disabled"; 815 }; 816 817 uart0: serial@880000 { 818 compatible = "qcom,geni-uart"; 819 reg = <0 0x00880000 0 0x4000>; 820 clock-names = "se"; 821 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 822 pinctrl-names = "default"; 823 pinctrl-0 = <&qup_uart0_default>; 824 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 825 power-domains = <&rpmhpd SC7180_CX>; 826 operating-points-v2 = <&qup_opp_table>; 827 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 828 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 829 interconnect-names = "qup-core", "qup-config"; 830 status = "disabled"; 831 }; 832 833 i2c1: i2c@884000 { 834 compatible = "qcom,geni-i2c"; 835 reg = <0 0x00884000 0 0x4000>; 836 clock-names = "se"; 837 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 838 pinctrl-names = "default"; 839 pinctrl-0 = <&qup_i2c1_default>; 840 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 841 #address-cells = <1>; 842 #size-cells = <0>; 843 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 844 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 845 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 846 interconnect-names = "qup-core", "qup-config", 847 "qup-memory"; 848 power-domains = <&rpmhpd SC7180_CX>; 849 required-opps = <&rpmhpd_opp_low_svs>; 850 status = "disabled"; 851 }; 852 853 spi1: spi@884000 { 854 compatible = "qcom,geni-spi"; 855 reg = <0 0x00884000 0 0x4000>; 856 clock-names = "se"; 857 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 858 pinctrl-names = "default"; 859 pinctrl-0 = <&qup_spi1_default>; 860 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 861 #address-cells = <1>; 862 #size-cells = <0>; 863 power-domains = <&rpmhpd SC7180_CX>; 864 operating-points-v2 = <&qup_opp_table>; 865 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 866 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 867 interconnect-names = "qup-core", "qup-config"; 868 status = "disabled"; 869 }; 870 871 uart1: serial@884000 { 872 compatible = "qcom,geni-uart"; 873 reg = <0 0x00884000 0 0x4000>; 874 clock-names = "se"; 875 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 876 pinctrl-names = "default"; 877 pinctrl-0 = <&qup_uart1_default>; 878 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 879 power-domains = <&rpmhpd SC7180_CX>; 880 operating-points-v2 = <&qup_opp_table>; 881 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 882 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 883 interconnect-names = "qup-core", "qup-config"; 884 status = "disabled"; 885 }; 886 887 i2c2: i2c@888000 { 888 compatible = "qcom,geni-i2c"; 889 reg = <0 0x00888000 0 0x4000>; 890 clock-names = "se"; 891 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 892 pinctrl-names = "default"; 893 pinctrl-0 = <&qup_i2c2_default>; 894 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 898 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 899 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 900 interconnect-names = "qup-core", "qup-config", 901 "qup-memory"; 902 power-domains = <&rpmhpd SC7180_CX>; 903 required-opps = <&rpmhpd_opp_low_svs>; 904 status = "disabled"; 905 }; 906 907 uart2: serial@888000 { 908 compatible = "qcom,geni-uart"; 909 reg = <0 0x00888000 0 0x4000>; 910 clock-names = "se"; 911 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_uart2_default>; 914 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 915 power-domains = <&rpmhpd SC7180_CX>; 916 operating-points-v2 = <&qup_opp_table>; 917 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 918 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 919 interconnect-names = "qup-core", "qup-config"; 920 status = "disabled"; 921 }; 922 923 i2c3: i2c@88c000 { 924 compatible = "qcom,geni-i2c"; 925 reg = <0 0x0088c000 0 0x4000>; 926 clock-names = "se"; 927 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 928 pinctrl-names = "default"; 929 pinctrl-0 = <&qup_i2c3_default>; 930 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 931 #address-cells = <1>; 932 #size-cells = <0>; 933 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 934 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 935 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 936 interconnect-names = "qup-core", "qup-config", 937 "qup-memory"; 938 power-domains = <&rpmhpd SC7180_CX>; 939 required-opps = <&rpmhpd_opp_low_svs>; 940 status = "disabled"; 941 }; 942 943 spi3: spi@88c000 { 944 compatible = "qcom,geni-spi"; 945 reg = <0 0x0088c000 0 0x4000>; 946 clock-names = "se"; 947 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&qup_spi3_default>; 950 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 power-domains = <&rpmhpd SC7180_CX>; 954 operating-points-v2 = <&qup_opp_table>; 955 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 956 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 957 interconnect-names = "qup-core", "qup-config"; 958 status = "disabled"; 959 }; 960 961 uart3: serial@88c000 { 962 compatible = "qcom,geni-uart"; 963 reg = <0 0x0088c000 0 0x4000>; 964 clock-names = "se"; 965 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&qup_uart3_default>; 968 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 969 power-domains = <&rpmhpd SC7180_CX>; 970 operating-points-v2 = <&qup_opp_table>; 971 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 972 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 973 interconnect-names = "qup-core", "qup-config"; 974 status = "disabled"; 975 }; 976 977 i2c4: i2c@890000 { 978 compatible = "qcom,geni-i2c"; 979 reg = <0 0x00890000 0 0x4000>; 980 clock-names = "se"; 981 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 982 pinctrl-names = "default"; 983 pinctrl-0 = <&qup_i2c4_default>; 984 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 989 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 990 interconnect-names = "qup-core", "qup-config", 991 "qup-memory"; 992 power-domains = <&rpmhpd SC7180_CX>; 993 required-opps = <&rpmhpd_opp_low_svs>; 994 status = "disabled"; 995 }; 996 997 uart4: serial@890000 { 998 compatible = "qcom,geni-uart"; 999 reg = <0 0x00890000 0 0x4000>; 1000 clock-names = "se"; 1001 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&qup_uart4_default>; 1004 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1005 power-domains = <&rpmhpd SC7180_CX>; 1006 operating-points-v2 = <&qup_opp_table>; 1007 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1008 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1009 interconnect-names = "qup-core", "qup-config"; 1010 status = "disabled"; 1011 }; 1012 1013 i2c5: i2c@894000 { 1014 compatible = "qcom,geni-i2c"; 1015 reg = <0 0x00894000 0 0x4000>; 1016 clock-names = "se"; 1017 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_i2c5_default>; 1020 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1024 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1025 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1026 interconnect-names = "qup-core", "qup-config", 1027 "qup-memory"; 1028 power-domains = <&rpmhpd SC7180_CX>; 1029 required-opps = <&rpmhpd_opp_low_svs>; 1030 status = "disabled"; 1031 }; 1032 1033 spi5: spi@894000 { 1034 compatible = "qcom,geni-spi"; 1035 reg = <0 0x00894000 0 0x4000>; 1036 clock-names = "se"; 1037 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1038 pinctrl-names = "default"; 1039 pinctrl-0 = <&qup_spi5_default>; 1040 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 power-domains = <&rpmhpd SC7180_CX>; 1044 operating-points-v2 = <&qup_opp_table>; 1045 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1047 interconnect-names = "qup-core", "qup-config"; 1048 status = "disabled"; 1049 }; 1050 1051 uart5: serial@894000 { 1052 compatible = "qcom,geni-uart"; 1053 reg = <0 0x00894000 0 0x4000>; 1054 clock-names = "se"; 1055 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1056 pinctrl-names = "default"; 1057 pinctrl-0 = <&qup_uart5_default>; 1058 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1059 power-domains = <&rpmhpd SC7180_CX>; 1060 operating-points-v2 = <&qup_opp_table>; 1061 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1062 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1063 interconnect-names = "qup-core", "qup-config"; 1064 status = "disabled"; 1065 }; 1066 }; 1067 1068 qupv3_id_1: geniqup@ac0000 { 1069 compatible = "qcom,geni-se-qup"; 1070 reg = <0 0x00ac0000 0 0x6000>; 1071 clock-names = "m-ahb", "s-ahb"; 1072 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1073 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1074 #address-cells = <2>; 1075 #size-cells = <2>; 1076 ranges; 1077 iommus = <&apps_smmu 0x4c3 0x0>; 1078 status = "disabled"; 1079 1080 i2c6: i2c@a80000 { 1081 compatible = "qcom,geni-i2c"; 1082 reg = <0 0x00a80000 0 0x4000>; 1083 clock-names = "se"; 1084 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1085 pinctrl-names = "default"; 1086 pinctrl-0 = <&qup_i2c6_default>; 1087 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1091 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1092 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1093 interconnect-names = "qup-core", "qup-config", 1094 "qup-memory"; 1095 power-domains = <&rpmhpd SC7180_CX>; 1096 required-opps = <&rpmhpd_opp_low_svs>; 1097 status = "disabled"; 1098 }; 1099 1100 spi6: spi@a80000 { 1101 compatible = "qcom,geni-spi"; 1102 reg = <0 0x00a80000 0 0x4000>; 1103 clock-names = "se"; 1104 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1105 pinctrl-names = "default"; 1106 pinctrl-0 = <&qup_spi6_default>; 1107 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 power-domains = <&rpmhpd SC7180_CX>; 1111 operating-points-v2 = <&qup_opp_table>; 1112 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1113 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1114 interconnect-names = "qup-core", "qup-config"; 1115 status = "disabled"; 1116 }; 1117 1118 uart6: serial@a80000 { 1119 compatible = "qcom,geni-uart"; 1120 reg = <0 0x00a80000 0 0x4000>; 1121 clock-names = "se"; 1122 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1123 pinctrl-names = "default"; 1124 pinctrl-0 = <&qup_uart6_default>; 1125 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1126 power-domains = <&rpmhpd SC7180_CX>; 1127 operating-points-v2 = <&qup_opp_table>; 1128 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1129 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1130 interconnect-names = "qup-core", "qup-config"; 1131 status = "disabled"; 1132 }; 1133 1134 i2c7: i2c@a84000 { 1135 compatible = "qcom,geni-i2c"; 1136 reg = <0 0x00a84000 0 0x4000>; 1137 clock-names = "se"; 1138 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1139 pinctrl-names = "default"; 1140 pinctrl-0 = <&qup_i2c7_default>; 1141 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1145 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1146 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1147 interconnect-names = "qup-core", "qup-config", 1148 "qup-memory"; 1149 power-domains = <&rpmhpd SC7180_CX>; 1150 required-opps = <&rpmhpd_opp_low_svs>; 1151 status = "disabled"; 1152 }; 1153 1154 uart7: serial@a84000 { 1155 compatible = "qcom,geni-uart"; 1156 reg = <0 0x00a84000 0 0x4000>; 1157 clock-names = "se"; 1158 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1159 pinctrl-names = "default"; 1160 pinctrl-0 = <&qup_uart7_default>; 1161 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1162 power-domains = <&rpmhpd SC7180_CX>; 1163 operating-points-v2 = <&qup_opp_table>; 1164 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1165 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1166 interconnect-names = "qup-core", "qup-config"; 1167 status = "disabled"; 1168 }; 1169 1170 i2c8: i2c@a88000 { 1171 compatible = "qcom,geni-i2c"; 1172 reg = <0 0x00a88000 0 0x4000>; 1173 clock-names = "se"; 1174 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&qup_i2c8_default>; 1177 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1181 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1182 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1183 interconnect-names = "qup-core", "qup-config", 1184 "qup-memory"; 1185 power-domains = <&rpmhpd SC7180_CX>; 1186 required-opps = <&rpmhpd_opp_low_svs>; 1187 status = "disabled"; 1188 }; 1189 1190 spi8: spi@a88000 { 1191 compatible = "qcom,geni-spi"; 1192 reg = <0 0x00a88000 0 0x4000>; 1193 clock-names = "se"; 1194 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&qup_spi8_default>; 1197 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 power-domains = <&rpmhpd SC7180_CX>; 1201 operating-points-v2 = <&qup_opp_table>; 1202 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1203 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1204 interconnect-names = "qup-core", "qup-config"; 1205 status = "disabled"; 1206 }; 1207 1208 uart8: serial@a88000 { 1209 compatible = "qcom,geni-debug-uart"; 1210 reg = <0 0x00a88000 0 0x4000>; 1211 clock-names = "se"; 1212 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1213 pinctrl-names = "default"; 1214 pinctrl-0 = <&qup_uart8_default>; 1215 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1216 power-domains = <&rpmhpd SC7180_CX>; 1217 operating-points-v2 = <&qup_opp_table>; 1218 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1219 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1220 interconnect-names = "qup-core", "qup-config"; 1221 status = "disabled"; 1222 }; 1223 1224 i2c9: i2c@a8c000 { 1225 compatible = "qcom,geni-i2c"; 1226 reg = <0 0x00a8c000 0 0x4000>; 1227 clock-names = "se"; 1228 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1229 pinctrl-names = "default"; 1230 pinctrl-0 = <&qup_i2c9_default>; 1231 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1235 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1236 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1237 interconnect-names = "qup-core", "qup-config", 1238 "qup-memory"; 1239 power-domains = <&rpmhpd SC7180_CX>; 1240 required-opps = <&rpmhpd_opp_low_svs>; 1241 status = "disabled"; 1242 }; 1243 1244 uart9: serial@a8c000 { 1245 compatible = "qcom,geni-uart"; 1246 reg = <0 0x00a8c000 0 0x4000>; 1247 clock-names = "se"; 1248 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&qup_uart9_default>; 1251 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1252 power-domains = <&rpmhpd SC7180_CX>; 1253 operating-points-v2 = <&qup_opp_table>; 1254 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1255 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1256 interconnect-names = "qup-core", "qup-config"; 1257 status = "disabled"; 1258 }; 1259 1260 i2c10: i2c@a90000 { 1261 compatible = "qcom,geni-i2c"; 1262 reg = <0 0x00a90000 0 0x4000>; 1263 clock-names = "se"; 1264 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1265 pinctrl-names = "default"; 1266 pinctrl-0 = <&qup_i2c10_default>; 1267 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1271 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1272 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1273 interconnect-names = "qup-core", "qup-config", 1274 "qup-memory"; 1275 power-domains = <&rpmhpd SC7180_CX>; 1276 required-opps = <&rpmhpd_opp_low_svs>; 1277 status = "disabled"; 1278 }; 1279 1280 spi10: spi@a90000 { 1281 compatible = "qcom,geni-spi"; 1282 reg = <0 0x00a90000 0 0x4000>; 1283 clock-names = "se"; 1284 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1285 pinctrl-names = "default"; 1286 pinctrl-0 = <&qup_spi10_default>; 1287 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 power-domains = <&rpmhpd SC7180_CX>; 1291 operating-points-v2 = <&qup_opp_table>; 1292 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1293 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1294 interconnect-names = "qup-core", "qup-config"; 1295 status = "disabled"; 1296 }; 1297 1298 uart10: serial@a90000 { 1299 compatible = "qcom,geni-uart"; 1300 reg = <0 0x00a90000 0 0x4000>; 1301 clock-names = "se"; 1302 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&qup_uart10_default>; 1305 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1306 power-domains = <&rpmhpd SC7180_CX>; 1307 operating-points-v2 = <&qup_opp_table>; 1308 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1309 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1310 interconnect-names = "qup-core", "qup-config"; 1311 status = "disabled"; 1312 }; 1313 1314 i2c11: i2c@a94000 { 1315 compatible = "qcom,geni-i2c"; 1316 reg = <0 0x00a94000 0 0x4000>; 1317 clock-names = "se"; 1318 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1319 pinctrl-names = "default"; 1320 pinctrl-0 = <&qup_i2c11_default>; 1321 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1325 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1326 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1327 interconnect-names = "qup-core", "qup-config", 1328 "qup-memory"; 1329 power-domains = <&rpmhpd SC7180_CX>; 1330 required-opps = <&rpmhpd_opp_low_svs>; 1331 status = "disabled"; 1332 }; 1333 1334 spi11: spi@a94000 { 1335 compatible = "qcom,geni-spi"; 1336 reg = <0 0x00a94000 0 0x4000>; 1337 clock-names = "se"; 1338 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1339 pinctrl-names = "default"; 1340 pinctrl-0 = <&qup_spi11_default>; 1341 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 power-domains = <&rpmhpd SC7180_CX>; 1345 operating-points-v2 = <&qup_opp_table>; 1346 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1347 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1348 interconnect-names = "qup-core", "qup-config"; 1349 status = "disabled"; 1350 }; 1351 1352 uart11: serial@a94000 { 1353 compatible = "qcom,geni-uart"; 1354 reg = <0 0x00a94000 0 0x4000>; 1355 clock-names = "se"; 1356 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1357 pinctrl-names = "default"; 1358 pinctrl-0 = <&qup_uart11_default>; 1359 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1360 power-domains = <&rpmhpd SC7180_CX>; 1361 operating-points-v2 = <&qup_opp_table>; 1362 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1363 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1364 interconnect-names = "qup-core", "qup-config"; 1365 status = "disabled"; 1366 }; 1367 }; 1368 1369 config_noc: interconnect@1500000 { 1370 compatible = "qcom,sc7180-config-noc"; 1371 reg = <0 0x01500000 0 0x28000>; 1372 #interconnect-cells = <2>; 1373 qcom,bcm-voters = <&apps_bcm_voter>; 1374 }; 1375 1376 system_noc: interconnect@1620000 { 1377 compatible = "qcom,sc7180-system-noc"; 1378 reg = <0 0x01620000 0 0x17080>; 1379 #interconnect-cells = <2>; 1380 qcom,bcm-voters = <&apps_bcm_voter>; 1381 }; 1382 1383 mc_virt: interconnect@1638000 { 1384 compatible = "qcom,sc7180-mc-virt"; 1385 reg = <0 0x01638000 0 0x1000>; 1386 #interconnect-cells = <2>; 1387 qcom,bcm-voters = <&apps_bcm_voter>; 1388 }; 1389 1390 qup_virt: interconnect@1650000 { 1391 compatible = "qcom,sc7180-qup-virt"; 1392 reg = <0 0x01650000 0 0x1000>; 1393 #interconnect-cells = <2>; 1394 qcom,bcm-voters = <&apps_bcm_voter>; 1395 }; 1396 1397 aggre1_noc: interconnect@16e0000 { 1398 compatible = "qcom,sc7180-aggre1-noc"; 1399 reg = <0 0x016e0000 0 0x15080>; 1400 #interconnect-cells = <2>; 1401 qcom,bcm-voters = <&apps_bcm_voter>; 1402 }; 1403 1404 aggre2_noc: interconnect@1705000 { 1405 compatible = "qcom,sc7180-aggre2-noc"; 1406 reg = <0 0x01705000 0 0x9000>; 1407 #interconnect-cells = <2>; 1408 qcom,bcm-voters = <&apps_bcm_voter>; 1409 }; 1410 1411 compute_noc: interconnect@170e000 { 1412 compatible = "qcom,sc7180-compute-noc"; 1413 reg = <0 0x0170e000 0 0x6000>; 1414 #interconnect-cells = <2>; 1415 qcom,bcm-voters = <&apps_bcm_voter>; 1416 }; 1417 1418 mmss_noc: interconnect@1740000 { 1419 compatible = "qcom,sc7180-mmss-noc"; 1420 reg = <0 0x01740000 0 0x1c100>; 1421 #interconnect-cells = <2>; 1422 qcom,bcm-voters = <&apps_bcm_voter>; 1423 }; 1424 1425 ipa_virt: interconnect@1e00000 { 1426 compatible = "qcom,sc7180-ipa-virt"; 1427 reg = <0 0x01e00000 0 0x1000>; 1428 #interconnect-cells = <2>; 1429 qcom,bcm-voters = <&apps_bcm_voter>; 1430 }; 1431 1432 ipa: ipa@1e40000 { 1433 compatible = "qcom,sc7180-ipa"; 1434 1435 iommus = <&apps_smmu 0x440 0x0>, 1436 <&apps_smmu 0x442 0x0>; 1437 reg = <0 0x1e40000 0 0x7000>, 1438 <0 0x1e47000 0 0x2000>, 1439 <0 0x1e04000 0 0x2c000>; 1440 reg-names = "ipa-reg", 1441 "ipa-shared", 1442 "gsi"; 1443 1444 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1445 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1446 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1447 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1448 interrupt-names = "ipa", 1449 "gsi", 1450 "ipa-clock-query", 1451 "ipa-setup-ready"; 1452 1453 clocks = <&rpmhcc RPMH_IPA_CLK>; 1454 clock-names = "core"; 1455 1456 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1457 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1458 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1459 interconnect-names = "memory", 1460 "imem", 1461 "config"; 1462 1463 qcom,qmp = <&aoss_qmp>; 1464 1465 qcom,smem-states = <&ipa_smp2p_out 0>, 1466 <&ipa_smp2p_out 1>; 1467 qcom,smem-state-names = "ipa-clock-enabled-valid", 1468 "ipa-clock-enabled"; 1469 1470 status = "disabled"; 1471 }; 1472 1473 tcsr_mutex_regs: syscon@1f40000 { 1474 compatible = "syscon"; 1475 reg = <0 0x01f40000 0 0x40000>; 1476 }; 1477 1478 tcsr_regs: syscon@1fc0000 { 1479 compatible = "syscon"; 1480 reg = <0 0x01fc0000 0 0x40000>; 1481 }; 1482 1483 tlmm: pinctrl@3500000 { 1484 compatible = "qcom,sc7180-pinctrl"; 1485 reg = <0 0x03500000 0 0x300000>, 1486 <0 0x03900000 0 0x300000>, 1487 <0 0x03d00000 0 0x300000>; 1488 reg-names = "west", "north", "south"; 1489 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1490 gpio-controller; 1491 #gpio-cells = <2>; 1492 interrupt-controller; 1493 #interrupt-cells = <2>; 1494 gpio-ranges = <&tlmm 0 0 120>; 1495 wakeup-parent = <&pdc>; 1496 1497 dp_hot_plug_det: dp-hot-plug-det { 1498 pinmux { 1499 pins = "gpio117"; 1500 function = "dp_hot"; 1501 }; 1502 }; 1503 1504 qspi_clk: qspi-clk { 1505 pinmux { 1506 pins = "gpio63"; 1507 function = "qspi_clk"; 1508 }; 1509 }; 1510 1511 qspi_cs0: qspi-cs0 { 1512 pinmux { 1513 pins = "gpio68"; 1514 function = "qspi_cs"; 1515 }; 1516 }; 1517 1518 qspi_cs1: qspi-cs1 { 1519 pinmux { 1520 pins = "gpio72"; 1521 function = "qspi_cs"; 1522 }; 1523 }; 1524 1525 qspi_data01: qspi-data01 { 1526 pinmux-data { 1527 pins = "gpio64", "gpio65"; 1528 function = "qspi_data"; 1529 }; 1530 }; 1531 1532 qspi_data12: qspi-data12 { 1533 pinmux-data { 1534 pins = "gpio66", "gpio67"; 1535 function = "qspi_data"; 1536 }; 1537 }; 1538 1539 qup_i2c0_default: qup-i2c0-default { 1540 pinmux { 1541 pins = "gpio34", "gpio35"; 1542 function = "qup00"; 1543 }; 1544 }; 1545 1546 qup_i2c1_default: qup-i2c1-default { 1547 pinmux { 1548 pins = "gpio0", "gpio1"; 1549 function = "qup01"; 1550 }; 1551 }; 1552 1553 qup_i2c2_default: qup-i2c2-default { 1554 pinmux { 1555 pins = "gpio15", "gpio16"; 1556 function = "qup02_i2c"; 1557 }; 1558 }; 1559 1560 qup_i2c3_default: qup-i2c3-default { 1561 pinmux { 1562 pins = "gpio38", "gpio39"; 1563 function = "qup03"; 1564 }; 1565 }; 1566 1567 qup_i2c4_default: qup-i2c4-default { 1568 pinmux { 1569 pins = "gpio115", "gpio116"; 1570 function = "qup04_i2c"; 1571 }; 1572 }; 1573 1574 qup_i2c5_default: qup-i2c5-default { 1575 pinmux { 1576 pins = "gpio25", "gpio26"; 1577 function = "qup05"; 1578 }; 1579 }; 1580 1581 qup_i2c6_default: qup-i2c6-default { 1582 pinmux { 1583 pins = "gpio59", "gpio60"; 1584 function = "qup10"; 1585 }; 1586 }; 1587 1588 qup_i2c7_default: qup-i2c7-default { 1589 pinmux { 1590 pins = "gpio6", "gpio7"; 1591 function = "qup11_i2c"; 1592 }; 1593 }; 1594 1595 qup_i2c8_default: qup-i2c8-default { 1596 pinmux { 1597 pins = "gpio42", "gpio43"; 1598 function = "qup12"; 1599 }; 1600 }; 1601 1602 qup_i2c9_default: qup-i2c9-default { 1603 pinmux { 1604 pins = "gpio46", "gpio47"; 1605 function = "qup13_i2c"; 1606 }; 1607 }; 1608 1609 qup_i2c10_default: qup-i2c10-default { 1610 pinmux { 1611 pins = "gpio86", "gpio87"; 1612 function = "qup14"; 1613 }; 1614 }; 1615 1616 qup_i2c11_default: qup-i2c11-default { 1617 pinmux { 1618 pins = "gpio53", "gpio54"; 1619 function = "qup15"; 1620 }; 1621 }; 1622 1623 qup_spi0_default: qup-spi0-default { 1624 pinmux { 1625 pins = "gpio34", "gpio35", 1626 "gpio36", "gpio37"; 1627 function = "qup00"; 1628 }; 1629 }; 1630 1631 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 1632 pinmux { 1633 pins = "gpio34", "gpio35", 1634 "gpio36"; 1635 function = "qup00"; 1636 }; 1637 1638 pinmux-cs { 1639 pins = "gpio37"; 1640 function = "gpio"; 1641 }; 1642 }; 1643 1644 qup_spi1_default: qup-spi1-default { 1645 pinmux { 1646 pins = "gpio0", "gpio1", 1647 "gpio2", "gpio3"; 1648 function = "qup01"; 1649 }; 1650 }; 1651 1652 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 1653 pinmux { 1654 pins = "gpio0", "gpio1", 1655 "gpio2"; 1656 function = "qup01"; 1657 }; 1658 1659 pinmux-cs { 1660 pins = "gpio3"; 1661 function = "gpio"; 1662 }; 1663 }; 1664 1665 qup_spi3_default: qup-spi3-default { 1666 pinmux { 1667 pins = "gpio38", "gpio39", 1668 "gpio40", "gpio41"; 1669 function = "qup03"; 1670 }; 1671 }; 1672 1673 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 1674 pinmux { 1675 pins = "gpio38", "gpio39", 1676 "gpio40"; 1677 function = "qup03"; 1678 }; 1679 1680 pinmux-cs { 1681 pins = "gpio41"; 1682 function = "gpio"; 1683 }; 1684 }; 1685 1686 qup_spi5_default: qup-spi5-default { 1687 pinmux { 1688 pins = "gpio25", "gpio26", 1689 "gpio27", "gpio28"; 1690 function = "qup05"; 1691 }; 1692 }; 1693 1694 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 1695 pinmux { 1696 pins = "gpio25", "gpio26", 1697 "gpio27"; 1698 function = "qup05"; 1699 }; 1700 1701 pinmux-cs { 1702 pins = "gpio28"; 1703 function = "gpio"; 1704 }; 1705 }; 1706 1707 qup_spi6_default: qup-spi6-default { 1708 pinmux { 1709 pins = "gpio59", "gpio60", 1710 "gpio61", "gpio62"; 1711 function = "qup10"; 1712 }; 1713 }; 1714 1715 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 1716 pinmux { 1717 pins = "gpio59", "gpio60", 1718 "gpio61"; 1719 function = "qup10"; 1720 }; 1721 1722 pinmux-cs { 1723 pins = "gpio62"; 1724 function = "gpio"; 1725 }; 1726 }; 1727 1728 qup_spi8_default: qup-spi8-default { 1729 pinmux { 1730 pins = "gpio42", "gpio43", 1731 "gpio44", "gpio45"; 1732 function = "qup12"; 1733 }; 1734 }; 1735 1736 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 1737 pinmux { 1738 pins = "gpio42", "gpio43", 1739 "gpio44"; 1740 function = "qup12"; 1741 }; 1742 1743 pinmux-cs { 1744 pins = "gpio45"; 1745 function = "gpio"; 1746 }; 1747 }; 1748 1749 qup_spi10_default: qup-spi10-default { 1750 pinmux { 1751 pins = "gpio86", "gpio87", 1752 "gpio88", "gpio89"; 1753 function = "qup14"; 1754 }; 1755 }; 1756 1757 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 1758 pinmux { 1759 pins = "gpio86", "gpio87", 1760 "gpio88"; 1761 function = "qup14"; 1762 }; 1763 1764 pinmux-cs { 1765 pins = "gpio89"; 1766 function = "gpio"; 1767 }; 1768 }; 1769 1770 qup_spi11_default: qup-spi11-default { 1771 pinmux { 1772 pins = "gpio53", "gpio54", 1773 "gpio55", "gpio56"; 1774 function = "qup15"; 1775 }; 1776 }; 1777 1778 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 1779 pinmux { 1780 pins = "gpio53", "gpio54", 1781 "gpio55"; 1782 function = "qup15"; 1783 }; 1784 1785 pinmux-cs { 1786 pins = "gpio56"; 1787 function = "gpio"; 1788 }; 1789 }; 1790 1791 qup_uart0_default: qup-uart0-default { 1792 pinmux { 1793 pins = "gpio34", "gpio35", 1794 "gpio36", "gpio37"; 1795 function = "qup00"; 1796 }; 1797 }; 1798 1799 qup_uart1_default: qup-uart1-default { 1800 pinmux { 1801 pins = "gpio0", "gpio1", 1802 "gpio2", "gpio3"; 1803 function = "qup01"; 1804 }; 1805 }; 1806 1807 qup_uart2_default: qup-uart2-default { 1808 pinmux { 1809 pins = "gpio15", "gpio16"; 1810 function = "qup02_uart"; 1811 }; 1812 }; 1813 1814 qup_uart3_default: qup-uart3-default { 1815 pinmux { 1816 pins = "gpio38", "gpio39", 1817 "gpio40", "gpio41"; 1818 function = "qup03"; 1819 }; 1820 }; 1821 1822 qup_uart4_default: qup-uart4-default { 1823 pinmux { 1824 pins = "gpio115", "gpio116"; 1825 function = "qup04_uart"; 1826 }; 1827 }; 1828 1829 qup_uart5_default: qup-uart5-default { 1830 pinmux { 1831 pins = "gpio25", "gpio26", 1832 "gpio27", "gpio28"; 1833 function = "qup05"; 1834 }; 1835 }; 1836 1837 qup_uart6_default: qup-uart6-default { 1838 pinmux { 1839 pins = "gpio59", "gpio60", 1840 "gpio61", "gpio62"; 1841 function = "qup10"; 1842 }; 1843 }; 1844 1845 qup_uart7_default: qup-uart7-default { 1846 pinmux { 1847 pins = "gpio6", "gpio7"; 1848 function = "qup11_uart"; 1849 }; 1850 }; 1851 1852 qup_uart8_default: qup-uart8-default { 1853 pinmux { 1854 pins = "gpio44", "gpio45"; 1855 function = "qup12"; 1856 }; 1857 }; 1858 1859 qup_uart9_default: qup-uart9-default { 1860 pinmux { 1861 pins = "gpio46", "gpio47"; 1862 function = "qup13_uart"; 1863 }; 1864 }; 1865 1866 qup_uart10_default: qup-uart10-default { 1867 pinmux { 1868 pins = "gpio86", "gpio87", 1869 "gpio88", "gpio89"; 1870 function = "qup14"; 1871 }; 1872 }; 1873 1874 qup_uart11_default: qup-uart11-default { 1875 pinmux { 1876 pins = "gpio53", "gpio54", 1877 "gpio55", "gpio56"; 1878 function = "qup15"; 1879 }; 1880 }; 1881 1882 sec_mi2s_active: sec-mi2s-active { 1883 pinmux { 1884 pins = "gpio49", "gpio50", "gpio51"; 1885 function = "mi2s_1"; 1886 }; 1887 }; 1888 1889 pri_mi2s_active: pri-mi2s-active { 1890 pinmux { 1891 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1892 function = "mi2s_0"; 1893 }; 1894 }; 1895 1896 pri_mi2s_mclk_active: pri-mi2s-mclk-active { 1897 pinmux { 1898 pins = "gpio57"; 1899 function = "lpass_ext"; 1900 }; 1901 }; 1902 }; 1903 1904 remoteproc_mpss: remoteproc@4080000 { 1905 compatible = "qcom,sc7180-mpss-pas"; 1906 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; 1907 reg-names = "qdsp6", "rmb"; 1908 1909 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1910 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1911 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1912 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1913 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1914 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1915 interrupt-names = "wdog", "fatal", "ready", "handover", 1916 "stop-ack", "shutdown-ack"; 1917 1918 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1919 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 1920 <&gcc GCC_MSS_NAV_AXI_CLK>, 1921 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1922 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 1923 <&rpmhcc RPMH_CXO_CLK>; 1924 clock-names = "iface", "bus", "nav", "snoc_axi", 1925 "mnoc_axi", "xo"; 1926 1927 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 1928 <&rpmhpd SC7180_CX>, 1929 <&rpmhpd SC7180_MX>, 1930 <&rpmhpd SC7180_MSS>; 1931 power-domain-names = "load_state", "cx", "mx", "mss"; 1932 1933 memory-region = <&mpss_mem>; 1934 1935 qcom,smem-states = <&modem_smp2p_out 0>; 1936 qcom,smem-state-names = "stop"; 1937 1938 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1939 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1940 reset-names = "mss_restart", "pdc_reset"; 1941 1942 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 1943 qcom,spare-regs = <&tcsr_regs 0xb3e4>; 1944 1945 status = "disabled"; 1946 1947 glink-edge { 1948 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 1949 label = "modem"; 1950 qcom,remote-pid = <1>; 1951 mboxes = <&apss_shared 12>; 1952 }; 1953 }; 1954 1955 gpu: gpu@5000000 { 1956 compatible = "qcom,adreno-618.0", "qcom,adreno"; 1957 #stream-id-cells = <16>; 1958 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 1959 <0 0x05061000 0 0x800>; 1960 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 1961 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1962 iommus = <&adreno_smmu 0>; 1963 operating-points-v2 = <&gpu_opp_table>; 1964 qcom,gmu = <&gmu>; 1965 1966 #cooling-cells = <2>; 1967 1968 nvmem-cells = <&gpu_speed_bin>; 1969 nvmem-cell-names = "speed_bin"; 1970 1971 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 1972 interconnect-names = "gfx-mem"; 1973 1974 gpu_opp_table: opp-table { 1975 compatible = "operating-points-v2"; 1976 1977 opp-825000000 { 1978 opp-hz = /bits/ 64 <825000000>; 1979 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1980 opp-peak-kBps = <8532000>; 1981 opp-supported-hw = <0x04>; 1982 }; 1983 1984 opp-800000000 { 1985 opp-hz = /bits/ 64 <800000000>; 1986 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1987 opp-peak-kBps = <8532000>; 1988 opp-supported-hw = <0x07>; 1989 }; 1990 1991 opp-650000000 { 1992 opp-hz = /bits/ 64 <650000000>; 1993 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1994 opp-peak-kBps = <7216000>; 1995 opp-supported-hw = <0x07>; 1996 }; 1997 1998 opp-565000000 { 1999 opp-hz = /bits/ 64 <565000000>; 2000 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2001 opp-peak-kBps = <5412000>; 2002 opp-supported-hw = <0x07>; 2003 }; 2004 2005 opp-430000000 { 2006 opp-hz = /bits/ 64 <430000000>; 2007 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2008 opp-peak-kBps = <5412000>; 2009 opp-supported-hw = <0x07>; 2010 }; 2011 2012 opp-355000000 { 2013 opp-hz = /bits/ 64 <355000000>; 2014 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2015 opp-peak-kBps = <3072000>; 2016 opp-supported-hw = <0x07>; 2017 }; 2018 2019 opp-267000000 { 2020 opp-hz = /bits/ 64 <267000000>; 2021 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2022 opp-peak-kBps = <3072000>; 2023 opp-supported-hw = <0x07>; 2024 }; 2025 2026 opp-180000000 { 2027 opp-hz = /bits/ 64 <180000000>; 2028 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2029 opp-peak-kBps = <1804000>; 2030 opp-supported-hw = <0x07>; 2031 }; 2032 }; 2033 }; 2034 2035 adreno_smmu: iommu@5040000 { 2036 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2037 reg = <0 0x05040000 0 0x10000>; 2038 #iommu-cells = <1>; 2039 #global-interrupts = <2>; 2040 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2048 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2049 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2050 2051 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2052 <&gcc GCC_GPU_CFG_AHB_CLK>; 2053 clock-names = "bus", "iface"; 2054 2055 power-domains = <&gpucc CX_GDSC>; 2056 }; 2057 2058 gmu: gmu@506a000 { 2059 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2060 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2061 <0 0x0b490000 0 0x10000>; 2062 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2063 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2065 interrupt-names = "hfi", "gmu"; 2066 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2067 <&gpucc GPU_CC_CXO_CLK>, 2068 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2069 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2070 clock-names = "gmu", "cxo", "axi", "memnoc"; 2071 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2072 power-domain-names = "cx", "gx"; 2073 iommus = <&adreno_smmu 5>; 2074 operating-points-v2 = <&gmu_opp_table>; 2075 2076 gmu_opp_table: opp-table { 2077 compatible = "operating-points-v2"; 2078 2079 opp-200000000 { 2080 opp-hz = /bits/ 64 <200000000>; 2081 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2082 }; 2083 }; 2084 }; 2085 2086 gpucc: clock-controller@5090000 { 2087 compatible = "qcom,sc7180-gpucc"; 2088 reg = <0 0x05090000 0 0x9000>; 2089 clocks = <&rpmhcc RPMH_CXO_CLK>, 2090 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2091 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2092 clock-names = "bi_tcxo", 2093 "gcc_gpu_gpll0_clk_src", 2094 "gcc_gpu_gpll0_div_clk_src"; 2095 #clock-cells = <1>; 2096 #reset-cells = <1>; 2097 #power-domain-cells = <1>; 2098 }; 2099 2100 stm@6002000 { 2101 compatible = "arm,coresight-stm", "arm,primecell"; 2102 reg = <0 0x06002000 0 0x1000>, 2103 <0 0x16280000 0 0x180000>; 2104 reg-names = "stm-base", "stm-stimulus-base"; 2105 2106 clocks = <&aoss_qmp>; 2107 clock-names = "apb_pclk"; 2108 2109 out-ports { 2110 port { 2111 stm_out: endpoint { 2112 remote-endpoint = <&funnel0_in7>; 2113 }; 2114 }; 2115 }; 2116 }; 2117 2118 funnel@6041000 { 2119 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2120 reg = <0 0x06041000 0 0x1000>; 2121 2122 clocks = <&aoss_qmp>; 2123 clock-names = "apb_pclk"; 2124 2125 out-ports { 2126 port { 2127 funnel0_out: endpoint { 2128 remote-endpoint = <&merge_funnel_in0>; 2129 }; 2130 }; 2131 }; 2132 2133 in-ports { 2134 #address-cells = <1>; 2135 #size-cells = <0>; 2136 2137 port@7 { 2138 reg = <7>; 2139 funnel0_in7: endpoint { 2140 remote-endpoint = <&stm_out>; 2141 }; 2142 }; 2143 }; 2144 }; 2145 2146 funnel@6042000 { 2147 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2148 reg = <0 0x06042000 0 0x1000>; 2149 2150 clocks = <&aoss_qmp>; 2151 clock-names = "apb_pclk"; 2152 2153 out-ports { 2154 port { 2155 funnel1_out: endpoint { 2156 remote-endpoint = <&merge_funnel_in1>; 2157 }; 2158 }; 2159 }; 2160 2161 in-ports { 2162 #address-cells = <1>; 2163 #size-cells = <0>; 2164 2165 port@4 { 2166 reg = <4>; 2167 funnel1_in4: endpoint { 2168 remote-endpoint = <&apss_merge_funnel_out>; 2169 }; 2170 }; 2171 }; 2172 }; 2173 2174 funnel@6045000 { 2175 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2176 reg = <0 0x06045000 0 0x1000>; 2177 2178 clocks = <&aoss_qmp>; 2179 clock-names = "apb_pclk"; 2180 2181 out-ports { 2182 port { 2183 merge_funnel_out: endpoint { 2184 remote-endpoint = <&swao_funnel_in>; 2185 }; 2186 }; 2187 }; 2188 2189 in-ports { 2190 #address-cells = <1>; 2191 #size-cells = <0>; 2192 2193 port@0 { 2194 reg = <0>; 2195 merge_funnel_in0: endpoint { 2196 remote-endpoint = <&funnel0_out>; 2197 }; 2198 }; 2199 2200 port@1 { 2201 reg = <1>; 2202 merge_funnel_in1: endpoint { 2203 remote-endpoint = <&funnel1_out>; 2204 }; 2205 }; 2206 }; 2207 }; 2208 2209 replicator@6046000 { 2210 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2211 reg = <0 0x06046000 0 0x1000>; 2212 2213 clocks = <&aoss_qmp>; 2214 clock-names = "apb_pclk"; 2215 2216 out-ports { 2217 port { 2218 replicator_out: endpoint { 2219 remote-endpoint = <&etr_in>; 2220 }; 2221 }; 2222 }; 2223 2224 in-ports { 2225 port { 2226 replicator_in: endpoint { 2227 remote-endpoint = <&swao_replicator_out>; 2228 }; 2229 }; 2230 }; 2231 }; 2232 2233 etr@6048000 { 2234 compatible = "arm,coresight-tmc", "arm,primecell"; 2235 reg = <0 0x06048000 0 0x1000>; 2236 iommus = <&apps_smmu 0x04a0 0x20>; 2237 2238 clocks = <&aoss_qmp>; 2239 clock-names = "apb_pclk"; 2240 arm,scatter-gather; 2241 2242 in-ports { 2243 port { 2244 etr_in: endpoint { 2245 remote-endpoint = <&replicator_out>; 2246 }; 2247 }; 2248 }; 2249 }; 2250 2251 funnel@6b04000 { 2252 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2253 reg = <0 0x06b04000 0 0x1000>; 2254 2255 clocks = <&aoss_qmp>; 2256 clock-names = "apb_pclk"; 2257 2258 out-ports { 2259 port { 2260 swao_funnel_out: endpoint { 2261 remote-endpoint = <&etf_in>; 2262 }; 2263 }; 2264 }; 2265 2266 in-ports { 2267 #address-cells = <1>; 2268 #size-cells = <0>; 2269 2270 port@7 { 2271 reg = <7>; 2272 swao_funnel_in: endpoint { 2273 remote-endpoint = <&merge_funnel_out>; 2274 }; 2275 }; 2276 }; 2277 }; 2278 2279 etf@6b05000 { 2280 compatible = "arm,coresight-tmc", "arm,primecell"; 2281 reg = <0 0x06b05000 0 0x1000>; 2282 2283 clocks = <&aoss_qmp>; 2284 clock-names = "apb_pclk"; 2285 2286 out-ports { 2287 port { 2288 etf_out: endpoint { 2289 remote-endpoint = <&swao_replicator_in>; 2290 }; 2291 }; 2292 }; 2293 2294 in-ports { 2295 port { 2296 etf_in: endpoint { 2297 remote-endpoint = <&swao_funnel_out>; 2298 }; 2299 }; 2300 }; 2301 }; 2302 2303 replicator@6b06000 { 2304 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2305 reg = <0 0x06b06000 0 0x1000>; 2306 2307 clocks = <&aoss_qmp>; 2308 clock-names = "apb_pclk"; 2309 qcom,replicator-loses-context; 2310 2311 out-ports { 2312 port { 2313 swao_replicator_out: endpoint { 2314 remote-endpoint = <&replicator_in>; 2315 }; 2316 }; 2317 }; 2318 2319 in-ports { 2320 port { 2321 swao_replicator_in: endpoint { 2322 remote-endpoint = <&etf_out>; 2323 }; 2324 }; 2325 }; 2326 }; 2327 2328 etm@7040000 { 2329 compatible = "arm,coresight-etm4x", "arm,primecell"; 2330 reg = <0 0x07040000 0 0x1000>; 2331 2332 cpu = <&CPU0>; 2333 2334 clocks = <&aoss_qmp>; 2335 clock-names = "apb_pclk"; 2336 arm,coresight-loses-context-with-cpu; 2337 qcom,skip-power-up; 2338 2339 out-ports { 2340 port { 2341 etm0_out: endpoint { 2342 remote-endpoint = <&apss_funnel_in0>; 2343 }; 2344 }; 2345 }; 2346 }; 2347 2348 etm@7140000 { 2349 compatible = "arm,coresight-etm4x", "arm,primecell"; 2350 reg = <0 0x07140000 0 0x1000>; 2351 2352 cpu = <&CPU1>; 2353 2354 clocks = <&aoss_qmp>; 2355 clock-names = "apb_pclk"; 2356 arm,coresight-loses-context-with-cpu; 2357 qcom,skip-power-up; 2358 2359 out-ports { 2360 port { 2361 etm1_out: endpoint { 2362 remote-endpoint = <&apss_funnel_in1>; 2363 }; 2364 }; 2365 }; 2366 }; 2367 2368 etm@7240000 { 2369 compatible = "arm,coresight-etm4x", "arm,primecell"; 2370 reg = <0 0x07240000 0 0x1000>; 2371 2372 cpu = <&CPU2>; 2373 2374 clocks = <&aoss_qmp>; 2375 clock-names = "apb_pclk"; 2376 arm,coresight-loses-context-with-cpu; 2377 qcom,skip-power-up; 2378 2379 out-ports { 2380 port { 2381 etm2_out: endpoint { 2382 remote-endpoint = <&apss_funnel_in2>; 2383 }; 2384 }; 2385 }; 2386 }; 2387 2388 etm@7340000 { 2389 compatible = "arm,coresight-etm4x", "arm,primecell"; 2390 reg = <0 0x07340000 0 0x1000>; 2391 2392 cpu = <&CPU3>; 2393 2394 clocks = <&aoss_qmp>; 2395 clock-names = "apb_pclk"; 2396 arm,coresight-loses-context-with-cpu; 2397 qcom,skip-power-up; 2398 2399 out-ports { 2400 port { 2401 etm3_out: endpoint { 2402 remote-endpoint = <&apss_funnel_in3>; 2403 }; 2404 }; 2405 }; 2406 }; 2407 2408 etm@7440000 { 2409 compatible = "arm,coresight-etm4x", "arm,primecell"; 2410 reg = <0 0x07440000 0 0x1000>; 2411 2412 cpu = <&CPU4>; 2413 2414 clocks = <&aoss_qmp>; 2415 clock-names = "apb_pclk"; 2416 arm,coresight-loses-context-with-cpu; 2417 qcom,skip-power-up; 2418 2419 out-ports { 2420 port { 2421 etm4_out: endpoint { 2422 remote-endpoint = <&apss_funnel_in4>; 2423 }; 2424 }; 2425 }; 2426 }; 2427 2428 etm@7540000 { 2429 compatible = "arm,coresight-etm4x", "arm,primecell"; 2430 reg = <0 0x07540000 0 0x1000>; 2431 2432 cpu = <&CPU5>; 2433 2434 clocks = <&aoss_qmp>; 2435 clock-names = "apb_pclk"; 2436 arm,coresight-loses-context-with-cpu; 2437 qcom,skip-power-up; 2438 2439 out-ports { 2440 port { 2441 etm5_out: endpoint { 2442 remote-endpoint = <&apss_funnel_in5>; 2443 }; 2444 }; 2445 }; 2446 }; 2447 2448 etm@7640000 { 2449 compatible = "arm,coresight-etm4x", "arm,primecell"; 2450 reg = <0 0x07640000 0 0x1000>; 2451 2452 cpu = <&CPU6>; 2453 2454 clocks = <&aoss_qmp>; 2455 clock-names = "apb_pclk"; 2456 arm,coresight-loses-context-with-cpu; 2457 qcom,skip-power-up; 2458 2459 out-ports { 2460 port { 2461 etm6_out: endpoint { 2462 remote-endpoint = <&apss_funnel_in6>; 2463 }; 2464 }; 2465 }; 2466 }; 2467 2468 etm@7740000 { 2469 compatible = "arm,coresight-etm4x", "arm,primecell"; 2470 reg = <0 0x07740000 0 0x1000>; 2471 2472 cpu = <&CPU7>; 2473 2474 clocks = <&aoss_qmp>; 2475 clock-names = "apb_pclk"; 2476 arm,coresight-loses-context-with-cpu; 2477 qcom,skip-power-up; 2478 2479 out-ports { 2480 port { 2481 etm7_out: endpoint { 2482 remote-endpoint = <&apss_funnel_in7>; 2483 }; 2484 }; 2485 }; 2486 }; 2487 2488 funnel@7800000 { /* APSS Funnel */ 2489 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2490 reg = <0 0x07800000 0 0x1000>; 2491 2492 clocks = <&aoss_qmp>; 2493 clock-names = "apb_pclk"; 2494 2495 out-ports { 2496 port { 2497 apss_funnel_out: endpoint { 2498 remote-endpoint = <&apss_merge_funnel_in>; 2499 }; 2500 }; 2501 }; 2502 2503 in-ports { 2504 #address-cells = <1>; 2505 #size-cells = <0>; 2506 2507 port@0 { 2508 reg = <0>; 2509 apss_funnel_in0: endpoint { 2510 remote-endpoint = <&etm0_out>; 2511 }; 2512 }; 2513 2514 port@1 { 2515 reg = <1>; 2516 apss_funnel_in1: endpoint { 2517 remote-endpoint = <&etm1_out>; 2518 }; 2519 }; 2520 2521 port@2 { 2522 reg = <2>; 2523 apss_funnel_in2: endpoint { 2524 remote-endpoint = <&etm2_out>; 2525 }; 2526 }; 2527 2528 port@3 { 2529 reg = <3>; 2530 apss_funnel_in3: endpoint { 2531 remote-endpoint = <&etm3_out>; 2532 }; 2533 }; 2534 2535 port@4 { 2536 reg = <4>; 2537 apss_funnel_in4: endpoint { 2538 remote-endpoint = <&etm4_out>; 2539 }; 2540 }; 2541 2542 port@5 { 2543 reg = <5>; 2544 apss_funnel_in5: endpoint { 2545 remote-endpoint = <&etm5_out>; 2546 }; 2547 }; 2548 2549 port@6 { 2550 reg = <6>; 2551 apss_funnel_in6: endpoint { 2552 remote-endpoint = <&etm6_out>; 2553 }; 2554 }; 2555 2556 port@7 { 2557 reg = <7>; 2558 apss_funnel_in7: endpoint { 2559 remote-endpoint = <&etm7_out>; 2560 }; 2561 }; 2562 }; 2563 }; 2564 2565 funnel@7810000 { 2566 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2567 reg = <0 0x07810000 0 0x1000>; 2568 2569 clocks = <&aoss_qmp>; 2570 clock-names = "apb_pclk"; 2571 2572 out-ports { 2573 port { 2574 apss_merge_funnel_out: endpoint { 2575 remote-endpoint = <&funnel1_in4>; 2576 }; 2577 }; 2578 }; 2579 2580 in-ports { 2581 port { 2582 apss_merge_funnel_in: endpoint { 2583 remote-endpoint = <&apss_funnel_out>; 2584 }; 2585 }; 2586 }; 2587 }; 2588 2589 sdhc_2: sdhci@8804000 { 2590 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2591 reg = <0 0x08804000 0 0x1000>; 2592 2593 iommus = <&apps_smmu 0x80 0>; 2594 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2595 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2596 interrupt-names = "hc_irq", "pwr_irq"; 2597 2598 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2599 <&gcc GCC_SDCC2_AHB_CLK>, 2600 <&rpmhcc RPMH_CXO_CLK>; 2601 clock-names = "core", "iface", "xo"; 2602 2603 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2604 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2605 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2606 power-domains = <&rpmhpd SC7180_CX>; 2607 operating-points-v2 = <&sdhc2_opp_table>; 2608 2609 bus-width = <4>; 2610 2611 status = "disabled"; 2612 2613 sdhc2_opp_table: sdhc2-opp-table { 2614 compatible = "operating-points-v2"; 2615 2616 opp-100000000 { 2617 opp-hz = /bits/ 64 <100000000>; 2618 required-opps = <&rpmhpd_opp_low_svs>; 2619 opp-peak-kBps = <1800000 600000>; 2620 opp-avg-kBps = <100000 0>; 2621 }; 2622 2623 opp-202000000 { 2624 opp-hz = /bits/ 64 <202000000>; 2625 required-opps = <&rpmhpd_opp_nom>; 2626 opp-peak-kBps = <5400000 1600000>; 2627 opp-avg-kBps = <200000 0>; 2628 }; 2629 }; 2630 }; 2631 2632 qspi_opp_table: qspi-opp-table { 2633 compatible = "operating-points-v2"; 2634 2635 opp-75000000 { 2636 opp-hz = /bits/ 64 <75000000>; 2637 required-opps = <&rpmhpd_opp_low_svs>; 2638 }; 2639 2640 opp-150000000 { 2641 opp-hz = /bits/ 64 <150000000>; 2642 required-opps = <&rpmhpd_opp_svs>; 2643 }; 2644 2645 opp-300000000 { 2646 opp-hz = /bits/ 64 <300000000>; 2647 required-opps = <&rpmhpd_opp_nom>; 2648 }; 2649 }; 2650 2651 qspi: spi@88dc000 { 2652 compatible = "qcom,qspi-v1"; 2653 reg = <0 0x088dc000 0 0x600>; 2654 #address-cells = <1>; 2655 #size-cells = <0>; 2656 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2657 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2658 <&gcc GCC_QSPI_CORE_CLK>; 2659 clock-names = "iface", "core"; 2660 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2661 &config_noc SLAVE_QSPI_0 0>; 2662 interconnect-names = "qspi-config"; 2663 power-domains = <&rpmhpd SC7180_CX>; 2664 operating-points-v2 = <&qspi_opp_table>; 2665 status = "disabled"; 2666 }; 2667 2668 usb_1_hsphy: phy@88e3000 { 2669 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2670 reg = <0 0x088e3000 0 0x400>; 2671 status = "disabled"; 2672 #phy-cells = <0>; 2673 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2674 <&rpmhcc RPMH_CXO_CLK>; 2675 clock-names = "cfg_ahb", "ref"; 2676 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2677 2678 nvmem-cells = <&qusb2p_hstx_trim>; 2679 }; 2680 2681 usb_1_qmpphy: phy-wrapper@88e9000 { 2682 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2683 reg = <0 0x088e9000 0 0x18c>, 2684 <0 0x088e8000 0 0x3c>, 2685 <0 0x088ea000 0 0x18c>; 2686 status = "disabled"; 2687 #address-cells = <2>; 2688 #size-cells = <2>; 2689 ranges; 2690 2691 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2692 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2693 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2694 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2695 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2696 2697 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2698 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2699 reset-names = "phy", "common"; 2700 2701 usb_1_ssphy: usb3-phy@88e9200 { 2702 reg = <0 0x088e9200 0 0x128>, 2703 <0 0x088e9400 0 0x200>, 2704 <0 0x088e9c00 0 0x218>, 2705 <0 0x088e9600 0 0x128>, 2706 <0 0x088e9800 0 0x200>, 2707 <0 0x088e9a00 0 0x18>; 2708 #clock-cells = <0>; 2709 #phy-cells = <0>; 2710 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2711 clock-names = "pipe0"; 2712 clock-output-names = "usb3_phy_pipe_clk_src"; 2713 }; 2714 2715 dp_phy: dp-phy@88ea200 { 2716 reg = <0 0x088ea200 0 0x200>, 2717 <0 0x088ea400 0 0x200>, 2718 <0 0x088eaa00 0 0x200>, 2719 <0 0x088ea600 0 0x200>, 2720 <0 0x088ea800 0 0x200>; 2721 #clock-cells = <1>; 2722 #phy-cells = <0>; 2723 }; 2724 }; 2725 2726 dc_noc: interconnect@9160000 { 2727 compatible = "qcom,sc7180-dc-noc"; 2728 reg = <0 0x09160000 0 0x03200>; 2729 #interconnect-cells = <2>; 2730 qcom,bcm-voters = <&apps_bcm_voter>; 2731 }; 2732 2733 system-cache-controller@9200000 { 2734 compatible = "qcom,sc7180-llcc"; 2735 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2736 reg-names = "llcc_base", "llcc_broadcast_base"; 2737 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2738 }; 2739 2740 gem_noc: interconnect@9680000 { 2741 compatible = "qcom,sc7180-gem-noc"; 2742 reg = <0 0x09680000 0 0x3e200>; 2743 #interconnect-cells = <2>; 2744 qcom,bcm-voters = <&apps_bcm_voter>; 2745 }; 2746 2747 npu_noc: interconnect@9990000 { 2748 compatible = "qcom,sc7180-npu-noc"; 2749 reg = <0 0x09990000 0 0x1600>; 2750 #interconnect-cells = <2>; 2751 qcom,bcm-voters = <&apps_bcm_voter>; 2752 }; 2753 2754 usb_1: usb@a6f8800 { 2755 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2756 reg = <0 0x0a6f8800 0 0x400>; 2757 status = "disabled"; 2758 #address-cells = <2>; 2759 #size-cells = <2>; 2760 ranges; 2761 dma-ranges; 2762 2763 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2764 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2765 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2766 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2767 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2768 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2769 "sleep"; 2770 2771 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2772 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2773 assigned-clock-rates = <19200000>, <150000000>; 2774 2775 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2776 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2777 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 2778 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 2779 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2780 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2781 2782 power-domains = <&gcc USB30_PRIM_GDSC>; 2783 2784 resets = <&gcc GCC_USB30_PRIM_BCR>; 2785 2786 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 2787 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 2788 interconnect-names = "usb-ddr", "apps-usb"; 2789 2790 usb_1_dwc3: dwc3@a600000 { 2791 compatible = "snps,dwc3"; 2792 reg = <0 0x0a600000 0 0xe000>; 2793 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2794 iommus = <&apps_smmu 0x540 0>; 2795 snps,dis_u2_susphy_quirk; 2796 snps,dis_enblslpm_quirk; 2797 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2798 phy-names = "usb2-phy", "usb3-phy"; 2799 maximum-speed = "super-speed"; 2800 }; 2801 }; 2802 2803 venus: video-codec@aa00000 { 2804 compatible = "qcom,sc7180-venus"; 2805 reg = <0 0x0aa00000 0 0xff000>; 2806 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2807 power-domains = <&videocc VENUS_GDSC>, 2808 <&videocc VCODEC0_GDSC>, 2809 <&rpmhpd SC7180_CX>; 2810 power-domain-names = "venus", "vcodec0", "cx"; 2811 operating-points-v2 = <&venus_opp_table>; 2812 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2813 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2814 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2815 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2816 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2817 clock-names = "core", "iface", "bus", 2818 "vcodec0_core", "vcodec0_bus"; 2819 iommus = <&apps_smmu 0x0c00 0x60>; 2820 memory-region = <&venus_mem>; 2821 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 2822 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 2823 interconnect-names = "video-mem", "cpu-cfg"; 2824 2825 video-decoder { 2826 compatible = "venus-decoder"; 2827 }; 2828 2829 video-encoder { 2830 compatible = "venus-encoder"; 2831 }; 2832 2833 venus_opp_table: venus-opp-table { 2834 compatible = "operating-points-v2"; 2835 2836 opp-150000000 { 2837 opp-hz = /bits/ 64 <150000000>; 2838 required-opps = <&rpmhpd_opp_low_svs>; 2839 }; 2840 2841 opp-270000000 { 2842 opp-hz = /bits/ 64 <270000000>; 2843 required-opps = <&rpmhpd_opp_svs>; 2844 }; 2845 2846 opp-340000000 { 2847 opp-hz = /bits/ 64 <340000000>; 2848 required-opps = <&rpmhpd_opp_svs_l1>; 2849 }; 2850 2851 opp-434000000 { 2852 opp-hz = /bits/ 64 <434000000>; 2853 required-opps = <&rpmhpd_opp_nom>; 2854 }; 2855 2856 opp-500000097 { 2857 opp-hz = /bits/ 64 <500000097>; 2858 required-opps = <&rpmhpd_opp_turbo>; 2859 }; 2860 }; 2861 }; 2862 2863 videocc: clock-controller@ab00000 { 2864 compatible = "qcom,sc7180-videocc"; 2865 reg = <0 0x0ab00000 0 0x10000>; 2866 clocks = <&rpmhcc RPMH_CXO_CLK>; 2867 clock-names = "bi_tcxo"; 2868 #clock-cells = <1>; 2869 #reset-cells = <1>; 2870 #power-domain-cells = <1>; 2871 }; 2872 2873 camnoc_virt: interconnect@ac00000 { 2874 compatible = "qcom,sc7180-camnoc-virt"; 2875 reg = <0 0x0ac00000 0 0x1000>; 2876 #interconnect-cells = <2>; 2877 qcom,bcm-voters = <&apps_bcm_voter>; 2878 }; 2879 2880 camcc: clock-controller@ad00000 { 2881 compatible = "qcom,sc7180-camcc"; 2882 reg = <0 0x0ad00000 0 0x10000>; 2883 clocks = <&rpmhcc RPMH_CXO_CLK>, 2884 <&gcc GCC_CAMERA_AHB_CLK>, 2885 <&gcc GCC_CAMERA_XO_CLK>; 2886 clock-names = "bi_tcxo", "iface", "xo"; 2887 #clock-cells = <1>; 2888 #reset-cells = <1>; 2889 #power-domain-cells = <1>; 2890 }; 2891 2892 mdss: mdss@ae00000 { 2893 compatible = "qcom,sc7180-mdss"; 2894 reg = <0 0x0ae00000 0 0x1000>; 2895 reg-names = "mdss"; 2896 2897 power-domains = <&dispcc MDSS_GDSC>; 2898 2899 clocks = <&gcc GCC_DISP_AHB_CLK>, 2900 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2901 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2902 clock-names = "iface", "ahb", "core"; 2903 2904 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2905 assigned-clock-rates = <300000000>; 2906 2907 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2908 interrupt-controller; 2909 #interrupt-cells = <1>; 2910 2911 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2912 interconnect-names = "mdp0-mem"; 2913 2914 iommus = <&apps_smmu 0x800 0x2>; 2915 2916 #address-cells = <2>; 2917 #size-cells = <2>; 2918 ranges; 2919 2920 status = "disabled"; 2921 2922 mdp: mdp@ae01000 { 2923 compatible = "qcom,sc7180-dpu"; 2924 reg = <0 0x0ae01000 0 0x8f000>, 2925 <0 0x0aeb0000 0 0x2008>; 2926 reg-names = "mdp", "vbif"; 2927 2928 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2929 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2930 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2931 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2932 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2933 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2934 clock-names = "bus", "iface", "rot", "lut", "core", 2935 "vsync"; 2936 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2937 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2938 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2939 <&dispcc DISP_CC_MDSS_AHB_CLK>; 2940 assigned-clock-rates = <300000000>, 2941 <19200000>, 2942 <19200000>, 2943 <19200000>; 2944 operating-points-v2 = <&mdp_opp_table>; 2945 power-domains = <&rpmhpd SC7180_CX>; 2946 2947 interrupt-parent = <&mdss>; 2948 interrupts = <0>; 2949 2950 status = "disabled"; 2951 2952 ports { 2953 #address-cells = <1>; 2954 #size-cells = <0>; 2955 2956 port@0 { 2957 reg = <0>; 2958 dpu_intf1_out: endpoint { 2959 remote-endpoint = <&dsi0_in>; 2960 }; 2961 }; 2962 2963 port@2 { 2964 reg = <2>; 2965 dpu_intf0_out: endpoint { 2966 remote-endpoint = <&dp_in>; 2967 }; 2968 }; 2969 }; 2970 2971 mdp_opp_table: mdp-opp-table { 2972 compatible = "operating-points-v2"; 2973 2974 opp-200000000 { 2975 opp-hz = /bits/ 64 <200000000>; 2976 required-opps = <&rpmhpd_opp_low_svs>; 2977 }; 2978 2979 opp-300000000 { 2980 opp-hz = /bits/ 64 <300000000>; 2981 required-opps = <&rpmhpd_opp_svs>; 2982 }; 2983 2984 opp-345000000 { 2985 opp-hz = /bits/ 64 <345000000>; 2986 required-opps = <&rpmhpd_opp_svs_l1>; 2987 }; 2988 2989 opp-460000000 { 2990 opp-hz = /bits/ 64 <460000000>; 2991 required-opps = <&rpmhpd_opp_nom>; 2992 }; 2993 }; 2994 2995 }; 2996 2997 dsi0: dsi@ae94000 { 2998 compatible = "qcom,mdss-dsi-ctrl"; 2999 reg = <0 0x0ae94000 0 0x400>; 3000 reg-names = "dsi_ctrl"; 3001 3002 interrupt-parent = <&mdss>; 3003 interrupts = <4>; 3004 3005 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3006 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3007 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3008 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3009 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3010 <&gcc GCC_DISP_HF_AXI_CLK>; 3011 clock-names = "byte", 3012 "byte_intf", 3013 "pixel", 3014 "core", 3015 "iface", 3016 "bus"; 3017 3018 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3019 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 3020 3021 operating-points-v2 = <&dsi_opp_table>; 3022 power-domains = <&rpmhpd SC7180_CX>; 3023 3024 phys = <&dsi_phy>; 3025 phy-names = "dsi"; 3026 3027 #address-cells = <1>; 3028 #size-cells = <0>; 3029 3030 status = "disabled"; 3031 3032 ports { 3033 #address-cells = <1>; 3034 #size-cells = <0>; 3035 3036 port@0 { 3037 reg = <0>; 3038 dsi0_in: endpoint { 3039 remote-endpoint = <&dpu_intf1_out>; 3040 }; 3041 }; 3042 3043 port@1 { 3044 reg = <1>; 3045 dsi0_out: endpoint { 3046 }; 3047 }; 3048 }; 3049 3050 dsi_opp_table: dsi-opp-table { 3051 compatible = "operating-points-v2"; 3052 3053 opp-187500000 { 3054 opp-hz = /bits/ 64 <187500000>; 3055 required-opps = <&rpmhpd_opp_low_svs>; 3056 }; 3057 3058 opp-300000000 { 3059 opp-hz = /bits/ 64 <300000000>; 3060 required-opps = <&rpmhpd_opp_svs>; 3061 }; 3062 3063 opp-358000000 { 3064 opp-hz = /bits/ 64 <358000000>; 3065 required-opps = <&rpmhpd_opp_svs_l1>; 3066 }; 3067 }; 3068 }; 3069 3070 dsi_phy: dsi-phy@ae94400 { 3071 compatible = "qcom,dsi-phy-10nm"; 3072 reg = <0 0x0ae94400 0 0x200>, 3073 <0 0x0ae94600 0 0x280>, 3074 <0 0x0ae94a00 0 0x1e0>; 3075 reg-names = "dsi_phy", 3076 "dsi_phy_lane", 3077 "dsi_pll"; 3078 3079 #clock-cells = <1>; 3080 #phy-cells = <0>; 3081 3082 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3083 <&rpmhcc RPMH_CXO_CLK>; 3084 clock-names = "iface", "ref"; 3085 3086 status = "disabled"; 3087 }; 3088 3089 mdss_dp: displayport-controller@ae90000 { 3090 compatible = "qcom,sc7180-dp"; 3091 status = "disabled"; 3092 3093 reg = <0 0x0ae90000 0 0x1400>; 3094 3095 interrupt-parent = <&mdss>; 3096 interrupts = <12>; 3097 3098 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3099 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3100 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3101 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3102 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3103 clock-names = "core_iface", "core_aux", "ctrl_link", 3104 "ctrl_link_iface", "stream_pixel"; 3105 #clock-cells = <1>; 3106 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3107 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3108 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 3109 phys = <&dp_phy>; 3110 phy-names = "dp"; 3111 3112 operating-points-v2 = <&dp_opp_table>; 3113 power-domains = <&rpmhpd SC7180_CX>; 3114 3115 #sound-dai-cells = <0>; 3116 3117 ports { 3118 #address-cells = <1>; 3119 #size-cells = <0>; 3120 port@0 { 3121 reg = <0>; 3122 dp_in: endpoint { 3123 remote-endpoint = <&dpu_intf0_out>; 3124 }; 3125 }; 3126 3127 port@1 { 3128 reg = <1>; 3129 dp_out: endpoint { }; 3130 }; 3131 }; 3132 3133 dp_opp_table: opp-table { 3134 compatible = "operating-points-v2"; 3135 3136 opp-160000000 { 3137 opp-hz = /bits/ 64 <160000000>; 3138 required-opps = <&rpmhpd_opp_low_svs>; 3139 }; 3140 3141 opp-270000000 { 3142 opp-hz = /bits/ 64 <270000000>; 3143 required-opps = <&rpmhpd_opp_svs>; 3144 }; 3145 3146 opp-540000000 { 3147 opp-hz = /bits/ 64 <540000000>; 3148 required-opps = <&rpmhpd_opp_svs_l1>; 3149 }; 3150 3151 opp-810000000 { 3152 opp-hz = /bits/ 64 <810000000>; 3153 required-opps = <&rpmhpd_opp_nom>; 3154 }; 3155 }; 3156 }; 3157 }; 3158 3159 dispcc: clock-controller@af00000 { 3160 compatible = "qcom,sc7180-dispcc"; 3161 reg = <0 0x0af00000 0 0x200000>; 3162 clocks = <&rpmhcc RPMH_CXO_CLK>, 3163 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3164 <&dsi_phy 0>, 3165 <&dsi_phy 1>, 3166 <&dp_phy 0>, 3167 <&dp_phy 1>; 3168 clock-names = "bi_tcxo", 3169 "gcc_disp_gpll0_clk_src", 3170 "dsi0_phy_pll_out_byteclk", 3171 "dsi0_phy_pll_out_dsiclk", 3172 "dp_phy_pll_link_clk", 3173 "dp_phy_pll_vco_div_clk"; 3174 #clock-cells = <1>; 3175 #reset-cells = <1>; 3176 #power-domain-cells = <1>; 3177 }; 3178 3179 pdc: interrupt-controller@b220000 { 3180 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3181 reg = <0 0x0b220000 0 0x30000>; 3182 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3183 #interrupt-cells = <2>; 3184 interrupt-parent = <&intc>; 3185 interrupt-controller; 3186 }; 3187 3188 pdc_reset: reset-controller@b2e0000 { 3189 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3190 reg = <0 0x0b2e0000 0 0x20000>; 3191 #reset-cells = <1>; 3192 }; 3193 3194 tsens0: thermal-sensor@c263000 { 3195 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3196 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3197 <0 0x0c222000 0 0x1ff>; /* SROT */ 3198 #qcom,sensors = <15>; 3199 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3200 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3201 interrupt-names = "uplow","critical"; 3202 #thermal-sensor-cells = <1>; 3203 }; 3204 3205 tsens1: thermal-sensor@c265000 { 3206 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3207 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3208 <0 0x0c223000 0 0x1ff>; /* SROT */ 3209 #qcom,sensors = <10>; 3210 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3211 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3212 interrupt-names = "uplow","critical"; 3213 #thermal-sensor-cells = <1>; 3214 }; 3215 3216 aoss_reset: reset-controller@c2a0000 { 3217 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3218 reg = <0 0x0c2a0000 0 0x31000>; 3219 #reset-cells = <1>; 3220 }; 3221 3222 aoss_qmp: power-controller@c300000 { 3223 compatible = "qcom,sc7180-aoss-qmp"; 3224 reg = <0 0x0c300000 0 0x100000>; 3225 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3226 mboxes = <&apss_shared 0>; 3227 3228 #clock-cells = <0>; 3229 #power-domain-cells = <1>; 3230 }; 3231 3232 spmi_bus: spmi@c440000 { 3233 compatible = "qcom,spmi-pmic-arb"; 3234 reg = <0 0x0c440000 0 0x1100>, 3235 <0 0x0c600000 0 0x2000000>, 3236 <0 0x0e600000 0 0x100000>, 3237 <0 0x0e700000 0 0xa0000>, 3238 <0 0x0c40a000 0 0x26000>; 3239 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3240 interrupt-names = "periph_irq"; 3241 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3242 qcom,ee = <0>; 3243 qcom,channel = <0>; 3244 #address-cells = <2>; 3245 #size-cells = <0>; 3246 interrupt-controller; 3247 #interrupt-cells = <4>; 3248 cell-index = <0>; 3249 }; 3250 3251 apps_smmu: iommu@15000000 { 3252 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3253 reg = <0 0x15000000 0 0x100000>; 3254 #iommu-cells = <2>; 3255 #global-interrupts = <1>; 3256 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3259 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3263 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3271 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3274 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3277 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3278 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3279 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3281 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3303 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3337 }; 3338 3339 intc: interrupt-controller@17a00000 { 3340 compatible = "arm,gic-v3"; 3341 #address-cells = <2>; 3342 #size-cells = <2>; 3343 ranges; 3344 #interrupt-cells = <3>; 3345 interrupt-controller; 3346 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3347 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3348 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3349 3350 msi-controller@17a40000 { 3351 compatible = "arm,gic-v3-its"; 3352 msi-controller; 3353 #msi-cells = <1>; 3354 reg = <0 0x17a40000 0 0x20000>; 3355 status = "disabled"; 3356 }; 3357 }; 3358 3359 apss_shared: mailbox@17c00000 { 3360 compatible = "qcom,sc7180-apss-shared"; 3361 reg = <0 0x17c00000 0 0x10000>; 3362 #mbox-cells = <1>; 3363 }; 3364 3365 watchdog@17c10000 { 3366 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3367 reg = <0 0x17c10000 0 0x1000>; 3368 clocks = <&sleep_clk>; 3369 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 3370 }; 3371 3372 timer@17c20000{ 3373 #address-cells = <2>; 3374 #size-cells = <2>; 3375 ranges; 3376 compatible = "arm,armv7-timer-mem"; 3377 reg = <0 0x17c20000 0 0x1000>; 3378 3379 frame@17c21000 { 3380 frame-number = <0>; 3381 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3383 reg = <0 0x17c21000 0 0x1000>, 3384 <0 0x17c22000 0 0x1000>; 3385 }; 3386 3387 frame@17c23000 { 3388 frame-number = <1>; 3389 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3390 reg = <0 0x17c23000 0 0x1000>; 3391 status = "disabled"; 3392 }; 3393 3394 frame@17c25000 { 3395 frame-number = <2>; 3396 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3397 reg = <0 0x17c25000 0 0x1000>; 3398 status = "disabled"; 3399 }; 3400 3401 frame@17c27000 { 3402 frame-number = <3>; 3403 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3404 reg = <0 0x17c27000 0 0x1000>; 3405 status = "disabled"; 3406 }; 3407 3408 frame@17c29000 { 3409 frame-number = <4>; 3410 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3411 reg = <0 0x17c29000 0 0x1000>; 3412 status = "disabled"; 3413 }; 3414 3415 frame@17c2b000 { 3416 frame-number = <5>; 3417 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3418 reg = <0 0x17c2b000 0 0x1000>; 3419 status = "disabled"; 3420 }; 3421 3422 frame@17c2d000 { 3423 frame-number = <6>; 3424 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3425 reg = <0 0x17c2d000 0 0x1000>; 3426 status = "disabled"; 3427 }; 3428 }; 3429 3430 apps_rsc: rsc@18200000 { 3431 compatible = "qcom,rpmh-rsc"; 3432 reg = <0 0x18200000 0 0x10000>, 3433 <0 0x18210000 0 0x10000>, 3434 <0 0x18220000 0 0x10000>; 3435 reg-names = "drv-0", "drv-1", "drv-2"; 3436 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3437 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3438 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3439 qcom,tcs-offset = <0xd00>; 3440 qcom,drv-id = <2>; 3441 qcom,tcs-config = <ACTIVE_TCS 2>, 3442 <SLEEP_TCS 3>, 3443 <WAKE_TCS 3>, 3444 <CONTROL_TCS 1>; 3445 3446 rpmhcc: clock-controller { 3447 compatible = "qcom,sc7180-rpmh-clk"; 3448 clocks = <&xo_board>; 3449 clock-names = "xo"; 3450 #clock-cells = <1>; 3451 }; 3452 3453 rpmhpd: power-controller { 3454 compatible = "qcom,sc7180-rpmhpd"; 3455 #power-domain-cells = <1>; 3456 operating-points-v2 = <&rpmhpd_opp_table>; 3457 3458 rpmhpd_opp_table: opp-table { 3459 compatible = "operating-points-v2"; 3460 3461 rpmhpd_opp_ret: opp1 { 3462 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3463 }; 3464 3465 rpmhpd_opp_min_svs: opp2 { 3466 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3467 }; 3468 3469 rpmhpd_opp_low_svs: opp3 { 3470 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3471 }; 3472 3473 rpmhpd_opp_svs: opp4 { 3474 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3475 }; 3476 3477 rpmhpd_opp_svs_l1: opp5 { 3478 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3479 }; 3480 3481 rpmhpd_opp_svs_l2: opp6 { 3482 opp-level = <224>; 3483 }; 3484 3485 rpmhpd_opp_nom: opp7 { 3486 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3487 }; 3488 3489 rpmhpd_opp_nom_l1: opp8 { 3490 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3491 }; 3492 3493 rpmhpd_opp_nom_l2: opp9 { 3494 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3495 }; 3496 3497 rpmhpd_opp_turbo: opp10 { 3498 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3499 }; 3500 3501 rpmhpd_opp_turbo_l1: opp11 { 3502 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3503 }; 3504 }; 3505 }; 3506 3507 apps_bcm_voter: bcm_voter { 3508 compatible = "qcom,bcm-voter"; 3509 }; 3510 }; 3511 3512 osm_l3: interconnect@18321000 { 3513 compatible = "qcom,sc7180-osm-l3"; 3514 reg = <0 0x18321000 0 0x1400>; 3515 3516 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3517 clock-names = "xo", "alternate"; 3518 3519 #interconnect-cells = <1>; 3520 }; 3521 3522 cpufreq_hw: cpufreq@18323000 { 3523 compatible = "qcom,cpufreq-hw"; 3524 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3525 reg-names = "freq-domain0", "freq-domain1"; 3526 3527 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3528 clock-names = "xo", "alternate"; 3529 3530 #freq-domain-cells = <1>; 3531 }; 3532 3533 wifi: wifi@18800000 { 3534 compatible = "qcom,wcn3990-wifi"; 3535 reg = <0 0x18800000 0 0x800000>; 3536 reg-names = "membase"; 3537 iommus = <&apps_smmu 0xc0 0x1>; 3538 interrupts = 3539 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3540 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3541 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3542 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3543 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3544 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3545 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3546 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3547 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3548 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3549 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3550 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3551 memory-region = <&wlan_mem>; 3552 qcom,msa-fixed-perm; 3553 status = "disabled"; 3554 }; 3555 3556 lpasscc: clock-controller@62d00000 { 3557 compatible = "qcom,sc7180-lpasscorecc"; 3558 reg = <0 0x62d00000 0 0x50000>, 3559 <0 0x62780000 0 0x30000>; 3560 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3561 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3562 <&rpmhcc RPMH_CXO_CLK>; 3563 clock-names = "iface", "bi_tcxo"; 3564 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3565 #clock-cells = <1>; 3566 #power-domain-cells = <1>; 3567 }; 3568 3569 lpass_cpu: lpass@62d87000 { 3570 compatible = "qcom,sc7180-lpass-cpu"; 3571 3572 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; 3573 reg-names = "lpass-hdmiif", "lpass-lpaif"; 3574 3575 iommus = <&apps_smmu 0x1020 0>, 3576 <&apps_smmu 0x1021 0>, 3577 <&apps_smmu 0x1032 0>; 3578 3579 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3580 3581 status = "disabled"; 3582 3583 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3584 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 3585 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 3586 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 3587 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 3588 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 3589 3590 clock-names = "pcnoc-sway-clk", "audio-core", 3591 "mclk0", "pcnoc-mport-clk", 3592 "mi2s-bit-clk0", "mi2s-bit-clk1"; 3593 3594 3595 #sound-dai-cells = <1>; 3596 #address-cells = <1>; 3597 #size-cells = <0>; 3598 3599 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 3600 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 3601 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; 3602 }; 3603 3604 lpass_hm: clock-controller@63000000 { 3605 compatible = "qcom,sc7180-lpasshm"; 3606 reg = <0 0x63000000 0 0x28>; 3607 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3608 <&rpmhcc RPMH_CXO_CLK>; 3609 clock-names = "iface", "bi_tcxo"; 3610 #clock-cells = <1>; 3611 #power-domain-cells = <1>; 3612 }; 3613 }; 3614 3615 thermal-zones { 3616 cpu0_thermal: cpu0-thermal { 3617 polling-delay-passive = <250>; 3618 polling-delay = <0>; 3619 3620 thermal-sensors = <&tsens0 1>; 3621 sustainable-power = <1052>; 3622 3623 trips { 3624 cpu0_alert0: trip-point0 { 3625 temperature = <90000>; 3626 hysteresis = <2000>; 3627 type = "passive"; 3628 }; 3629 3630 cpu0_alert1: trip-point1 { 3631 temperature = <95000>; 3632 hysteresis = <2000>; 3633 type = "passive"; 3634 }; 3635 3636 cpu0_crit: cpu_crit { 3637 temperature = <110000>; 3638 hysteresis = <1000>; 3639 type = "critical"; 3640 }; 3641 }; 3642 3643 cooling-maps { 3644 map0 { 3645 trip = <&cpu0_alert0>; 3646 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3647 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3648 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3649 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3650 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3651 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3652 }; 3653 map1 { 3654 trip = <&cpu0_alert1>; 3655 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3656 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3657 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3658 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3659 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3660 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3661 }; 3662 }; 3663 }; 3664 3665 cpu1_thermal: cpu1-thermal { 3666 polling-delay-passive = <250>; 3667 polling-delay = <0>; 3668 3669 thermal-sensors = <&tsens0 2>; 3670 sustainable-power = <1052>; 3671 3672 trips { 3673 cpu1_alert0: trip-point0 { 3674 temperature = <90000>; 3675 hysteresis = <2000>; 3676 type = "passive"; 3677 }; 3678 3679 cpu1_alert1: trip-point1 { 3680 temperature = <95000>; 3681 hysteresis = <2000>; 3682 type = "passive"; 3683 }; 3684 3685 cpu1_crit: cpu_crit { 3686 temperature = <110000>; 3687 hysteresis = <1000>; 3688 type = "critical"; 3689 }; 3690 }; 3691 3692 cooling-maps { 3693 map0 { 3694 trip = <&cpu1_alert0>; 3695 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3696 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3697 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3698 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3699 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3700 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3701 }; 3702 map1 { 3703 trip = <&cpu1_alert1>; 3704 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3705 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3706 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3707 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3708 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3709 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3710 }; 3711 }; 3712 }; 3713 3714 cpu2_thermal: cpu2-thermal { 3715 polling-delay-passive = <250>; 3716 polling-delay = <0>; 3717 3718 thermal-sensors = <&tsens0 3>; 3719 sustainable-power = <1052>; 3720 3721 trips { 3722 cpu2_alert0: trip-point0 { 3723 temperature = <90000>; 3724 hysteresis = <2000>; 3725 type = "passive"; 3726 }; 3727 3728 cpu2_alert1: trip-point1 { 3729 temperature = <95000>; 3730 hysteresis = <2000>; 3731 type = "passive"; 3732 }; 3733 3734 cpu2_crit: cpu_crit { 3735 temperature = <110000>; 3736 hysteresis = <1000>; 3737 type = "critical"; 3738 }; 3739 }; 3740 3741 cooling-maps { 3742 map0 { 3743 trip = <&cpu2_alert0>; 3744 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3745 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3746 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3747 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3748 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3749 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3750 }; 3751 map1 { 3752 trip = <&cpu2_alert1>; 3753 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3754 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3755 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3756 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3757 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3758 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3759 }; 3760 }; 3761 }; 3762 3763 cpu3_thermal: cpu3-thermal { 3764 polling-delay-passive = <250>; 3765 polling-delay = <0>; 3766 3767 thermal-sensors = <&tsens0 4>; 3768 sustainable-power = <1052>; 3769 3770 trips { 3771 cpu3_alert0: trip-point0 { 3772 temperature = <90000>; 3773 hysteresis = <2000>; 3774 type = "passive"; 3775 }; 3776 3777 cpu3_alert1: trip-point1 { 3778 temperature = <95000>; 3779 hysteresis = <2000>; 3780 type = "passive"; 3781 }; 3782 3783 cpu3_crit: cpu_crit { 3784 temperature = <110000>; 3785 hysteresis = <1000>; 3786 type = "critical"; 3787 }; 3788 }; 3789 3790 cooling-maps { 3791 map0 { 3792 trip = <&cpu3_alert0>; 3793 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3794 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3795 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3796 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3797 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3798 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3799 }; 3800 map1 { 3801 trip = <&cpu3_alert1>; 3802 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3803 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3804 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3805 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3806 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3807 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3808 }; 3809 }; 3810 }; 3811 3812 cpu4_thermal: cpu4-thermal { 3813 polling-delay-passive = <250>; 3814 polling-delay = <0>; 3815 3816 thermal-sensors = <&tsens0 5>; 3817 sustainable-power = <1052>; 3818 3819 trips { 3820 cpu4_alert0: trip-point0 { 3821 temperature = <90000>; 3822 hysteresis = <2000>; 3823 type = "passive"; 3824 }; 3825 3826 cpu4_alert1: trip-point1 { 3827 temperature = <95000>; 3828 hysteresis = <2000>; 3829 type = "passive"; 3830 }; 3831 3832 cpu4_crit: cpu_crit { 3833 temperature = <110000>; 3834 hysteresis = <1000>; 3835 type = "critical"; 3836 }; 3837 }; 3838 3839 cooling-maps { 3840 map0 { 3841 trip = <&cpu4_alert0>; 3842 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3843 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3844 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3845 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3846 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3847 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3848 }; 3849 map1 { 3850 trip = <&cpu4_alert1>; 3851 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3852 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3853 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3854 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3855 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3856 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3857 }; 3858 }; 3859 }; 3860 3861 cpu5_thermal: cpu5-thermal { 3862 polling-delay-passive = <250>; 3863 polling-delay = <0>; 3864 3865 thermal-sensors = <&tsens0 6>; 3866 sustainable-power = <1052>; 3867 3868 trips { 3869 cpu5_alert0: trip-point0 { 3870 temperature = <90000>; 3871 hysteresis = <2000>; 3872 type = "passive"; 3873 }; 3874 3875 cpu5_alert1: trip-point1 { 3876 temperature = <95000>; 3877 hysteresis = <2000>; 3878 type = "passive"; 3879 }; 3880 3881 cpu5_crit: cpu_crit { 3882 temperature = <110000>; 3883 hysteresis = <1000>; 3884 type = "critical"; 3885 }; 3886 }; 3887 3888 cooling-maps { 3889 map0 { 3890 trip = <&cpu5_alert0>; 3891 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3892 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3893 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3894 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3895 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3896 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3897 }; 3898 map1 { 3899 trip = <&cpu5_alert1>; 3900 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3901 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3902 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3903 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3904 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3905 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3906 }; 3907 }; 3908 }; 3909 3910 cpu6_thermal: cpu6-thermal { 3911 polling-delay-passive = <250>; 3912 polling-delay = <0>; 3913 3914 thermal-sensors = <&tsens0 9>; 3915 sustainable-power = <1425>; 3916 3917 trips { 3918 cpu6_alert0: trip-point0 { 3919 temperature = <90000>; 3920 hysteresis = <2000>; 3921 type = "passive"; 3922 }; 3923 3924 cpu6_alert1: trip-point1 { 3925 temperature = <95000>; 3926 hysteresis = <2000>; 3927 type = "passive"; 3928 }; 3929 3930 cpu6_crit: cpu_crit { 3931 temperature = <110000>; 3932 hysteresis = <1000>; 3933 type = "critical"; 3934 }; 3935 }; 3936 3937 cooling-maps { 3938 map0 { 3939 trip = <&cpu6_alert0>; 3940 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3941 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3942 }; 3943 map1 { 3944 trip = <&cpu6_alert1>; 3945 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3946 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3947 }; 3948 }; 3949 }; 3950 3951 cpu7_thermal: cpu7-thermal { 3952 polling-delay-passive = <250>; 3953 polling-delay = <0>; 3954 3955 thermal-sensors = <&tsens0 10>; 3956 sustainable-power = <1425>; 3957 3958 trips { 3959 cpu7_alert0: trip-point0 { 3960 temperature = <90000>; 3961 hysteresis = <2000>; 3962 type = "passive"; 3963 }; 3964 3965 cpu7_alert1: trip-point1 { 3966 temperature = <95000>; 3967 hysteresis = <2000>; 3968 type = "passive"; 3969 }; 3970 3971 cpu7_crit: cpu_crit { 3972 temperature = <110000>; 3973 hysteresis = <1000>; 3974 type = "critical"; 3975 }; 3976 }; 3977 3978 cooling-maps { 3979 map0 { 3980 trip = <&cpu7_alert0>; 3981 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3982 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3983 }; 3984 map1 { 3985 trip = <&cpu7_alert1>; 3986 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3987 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3988 }; 3989 }; 3990 }; 3991 3992 cpu8_thermal: cpu8-thermal { 3993 polling-delay-passive = <250>; 3994 polling-delay = <0>; 3995 3996 thermal-sensors = <&tsens0 11>; 3997 sustainable-power = <1425>; 3998 3999 trips { 4000 cpu8_alert0: trip-point0 { 4001 temperature = <90000>; 4002 hysteresis = <2000>; 4003 type = "passive"; 4004 }; 4005 4006 cpu8_alert1: trip-point1 { 4007 temperature = <95000>; 4008 hysteresis = <2000>; 4009 type = "passive"; 4010 }; 4011 4012 cpu8_crit: cpu_crit { 4013 temperature = <110000>; 4014 hysteresis = <1000>; 4015 type = "critical"; 4016 }; 4017 }; 4018 4019 cooling-maps { 4020 map0 { 4021 trip = <&cpu8_alert0>; 4022 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4023 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4024 }; 4025 map1 { 4026 trip = <&cpu8_alert1>; 4027 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4028 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4029 }; 4030 }; 4031 }; 4032 4033 cpu9_thermal: cpu9-thermal { 4034 polling-delay-passive = <250>; 4035 polling-delay = <0>; 4036 4037 thermal-sensors = <&tsens0 12>; 4038 sustainable-power = <1425>; 4039 4040 trips { 4041 cpu9_alert0: trip-point0 { 4042 temperature = <90000>; 4043 hysteresis = <2000>; 4044 type = "passive"; 4045 }; 4046 4047 cpu9_alert1: trip-point1 { 4048 temperature = <95000>; 4049 hysteresis = <2000>; 4050 type = "passive"; 4051 }; 4052 4053 cpu9_crit: cpu_crit { 4054 temperature = <110000>; 4055 hysteresis = <1000>; 4056 type = "critical"; 4057 }; 4058 }; 4059 4060 cooling-maps { 4061 map0 { 4062 trip = <&cpu9_alert0>; 4063 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4064 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4065 }; 4066 map1 { 4067 trip = <&cpu9_alert1>; 4068 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4069 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4070 }; 4071 }; 4072 }; 4073 4074 aoss0-thermal { 4075 polling-delay-passive = <250>; 4076 polling-delay = <0>; 4077 4078 thermal-sensors = <&tsens0 0>; 4079 4080 trips { 4081 aoss0_alert0: trip-point0 { 4082 temperature = <90000>; 4083 hysteresis = <2000>; 4084 type = "hot"; 4085 }; 4086 4087 aoss0_crit: aoss0_crit { 4088 temperature = <110000>; 4089 hysteresis = <2000>; 4090 type = "critical"; 4091 }; 4092 }; 4093 }; 4094 4095 cpuss0-thermal { 4096 polling-delay-passive = <250>; 4097 polling-delay = <0>; 4098 4099 thermal-sensors = <&tsens0 7>; 4100 4101 trips { 4102 cpuss0_alert0: trip-point0 { 4103 temperature = <90000>; 4104 hysteresis = <2000>; 4105 type = "hot"; 4106 }; 4107 cpuss0_crit: cluster0_crit { 4108 temperature = <110000>; 4109 hysteresis = <2000>; 4110 type = "critical"; 4111 }; 4112 }; 4113 }; 4114 4115 cpuss1-thermal { 4116 polling-delay-passive = <250>; 4117 polling-delay = <0>; 4118 4119 thermal-sensors = <&tsens0 8>; 4120 4121 trips { 4122 cpuss1_alert0: trip-point0 { 4123 temperature = <90000>; 4124 hysteresis = <2000>; 4125 type = "hot"; 4126 }; 4127 cpuss1_crit: cluster0_crit { 4128 temperature = <110000>; 4129 hysteresis = <2000>; 4130 type = "critical"; 4131 }; 4132 }; 4133 }; 4134 4135 gpuss0-thermal { 4136 polling-delay-passive = <250>; 4137 polling-delay = <0>; 4138 4139 thermal-sensors = <&tsens0 13>; 4140 4141 trips { 4142 gpuss0_alert0: trip-point0 { 4143 temperature = <95000>; 4144 hysteresis = <2000>; 4145 type = "passive"; 4146 }; 4147 4148 gpuss0_crit: gpuss0_crit { 4149 temperature = <110000>; 4150 hysteresis = <2000>; 4151 type = "critical"; 4152 }; 4153 }; 4154 4155 cooling-maps { 4156 map0 { 4157 trip = <&gpuss0_alert0>; 4158 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4159 }; 4160 }; 4161 }; 4162 4163 gpuss1-thermal { 4164 polling-delay-passive = <250>; 4165 polling-delay = <0>; 4166 4167 thermal-sensors = <&tsens0 14>; 4168 4169 trips { 4170 gpuss1_alert0: trip-point0 { 4171 temperature = <95000>; 4172 hysteresis = <2000>; 4173 type = "passive"; 4174 }; 4175 4176 gpuss1_crit: gpuss1_crit { 4177 temperature = <110000>; 4178 hysteresis = <2000>; 4179 type = "critical"; 4180 }; 4181 }; 4182 4183 cooling-maps { 4184 map0 { 4185 trip = <&gpuss1_alert0>; 4186 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4187 }; 4188 }; 4189 }; 4190 4191 aoss1-thermal { 4192 polling-delay-passive = <250>; 4193 polling-delay = <0>; 4194 4195 thermal-sensors = <&tsens1 0>; 4196 4197 trips { 4198 aoss1_alert0: trip-point0 { 4199 temperature = <90000>; 4200 hysteresis = <2000>; 4201 type = "hot"; 4202 }; 4203 4204 aoss1_crit: aoss1_crit { 4205 temperature = <110000>; 4206 hysteresis = <2000>; 4207 type = "critical"; 4208 }; 4209 }; 4210 }; 4211 4212 cwlan-thermal { 4213 polling-delay-passive = <250>; 4214 polling-delay = <0>; 4215 4216 thermal-sensors = <&tsens1 1>; 4217 4218 trips { 4219 cwlan_alert0: trip-point0 { 4220 temperature = <90000>; 4221 hysteresis = <2000>; 4222 type = "hot"; 4223 }; 4224 4225 cwlan_crit: cwlan_crit { 4226 temperature = <110000>; 4227 hysteresis = <2000>; 4228 type = "critical"; 4229 }; 4230 }; 4231 }; 4232 4233 audio-thermal { 4234 polling-delay-passive = <250>; 4235 polling-delay = <0>; 4236 4237 thermal-sensors = <&tsens1 2>; 4238 4239 trips { 4240 audio_alert0: trip-point0 { 4241 temperature = <90000>; 4242 hysteresis = <2000>; 4243 type = "hot"; 4244 }; 4245 4246 audio_crit: audio_crit { 4247 temperature = <110000>; 4248 hysteresis = <2000>; 4249 type = "critical"; 4250 }; 4251 }; 4252 }; 4253 4254 ddr-thermal { 4255 polling-delay-passive = <250>; 4256 polling-delay = <0>; 4257 4258 thermal-sensors = <&tsens1 3>; 4259 4260 trips { 4261 ddr_alert0: trip-point0 { 4262 temperature = <90000>; 4263 hysteresis = <2000>; 4264 type = "hot"; 4265 }; 4266 4267 ddr_crit: ddr_crit { 4268 temperature = <110000>; 4269 hysteresis = <2000>; 4270 type = "critical"; 4271 }; 4272 }; 4273 }; 4274 4275 q6-hvx-thermal { 4276 polling-delay-passive = <250>; 4277 polling-delay = <0>; 4278 4279 thermal-sensors = <&tsens1 4>; 4280 4281 trips { 4282 q6_hvx_alert0: trip-point0 { 4283 temperature = <90000>; 4284 hysteresis = <2000>; 4285 type = "hot"; 4286 }; 4287 4288 q6_hvx_crit: q6_hvx_crit { 4289 temperature = <110000>; 4290 hysteresis = <2000>; 4291 type = "critical"; 4292 }; 4293 }; 4294 }; 4295 4296 camera-thermal { 4297 polling-delay-passive = <250>; 4298 polling-delay = <0>; 4299 4300 thermal-sensors = <&tsens1 5>; 4301 4302 trips { 4303 camera_alert0: trip-point0 { 4304 temperature = <90000>; 4305 hysteresis = <2000>; 4306 type = "hot"; 4307 }; 4308 4309 camera_crit: camera_crit { 4310 temperature = <110000>; 4311 hysteresis = <2000>; 4312 type = "critical"; 4313 }; 4314 }; 4315 }; 4316 4317 mdm-core-thermal { 4318 polling-delay-passive = <250>; 4319 polling-delay = <0>; 4320 4321 thermal-sensors = <&tsens1 6>; 4322 4323 trips { 4324 mdm_alert0: trip-point0 { 4325 temperature = <90000>; 4326 hysteresis = <2000>; 4327 type = "hot"; 4328 }; 4329 4330 mdm_crit: mdm_crit { 4331 temperature = <110000>; 4332 hysteresis = <2000>; 4333 type = "critical"; 4334 }; 4335 }; 4336 }; 4337 4338 mdm-dsp-thermal { 4339 polling-delay-passive = <250>; 4340 polling-delay = <0>; 4341 4342 thermal-sensors = <&tsens1 7>; 4343 4344 trips { 4345 mdm_dsp_alert0: trip-point0 { 4346 temperature = <90000>; 4347 hysteresis = <2000>; 4348 type = "hot"; 4349 }; 4350 4351 mdm_dsp_crit: mdm_dsp_crit { 4352 temperature = <110000>; 4353 hysteresis = <2000>; 4354 type = "critical"; 4355 }; 4356 }; 4357 }; 4358 4359 npu-thermal { 4360 polling-delay-passive = <250>; 4361 polling-delay = <0>; 4362 4363 thermal-sensors = <&tsens1 8>; 4364 4365 trips { 4366 npu_alert0: trip-point0 { 4367 temperature = <90000>; 4368 hysteresis = <2000>; 4369 type = "hot"; 4370 }; 4371 4372 npu_crit: npu_crit { 4373 temperature = <110000>; 4374 hysteresis = <2000>; 4375 type = "critical"; 4376 }; 4377 }; 4378 }; 4379 4380 video-thermal { 4381 polling-delay-passive = <250>; 4382 polling-delay = <0>; 4383 4384 thermal-sensors = <&tsens1 9>; 4385 4386 trips { 4387 video_alert0: trip-point0 { 4388 temperature = <90000>; 4389 hysteresis = <2000>; 4390 type = "hot"; 4391 }; 4392 4393 video_crit: video_crit { 4394 temperature = <110000>; 4395 hysteresis = <2000>; 4396 type = "critical"; 4397 }; 4398 }; 4399 }; 4400 }; 4401 4402 timer { 4403 compatible = "arm,armv8-timer"; 4404 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4405 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4406 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4407 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4408 }; 4409}; 4410