1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interconnect/qcom,sc7280.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/mailbox/qcom-ipcc.h> 13#include <dt-bindings/power/qcom-aoss-qmp.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/reset/qcom,sdm845-aoss.h> 16#include <dt-bindings/reset/qcom,sdm845-pdc.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/thermal/thermal.h> 19 20/ { 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 chosen { }; 27 28 aliases { 29 mmc1 = &sdhc_1; 30 mmc2 = &sdhc_2; 31 }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 clock-frequency = <76800000>; 37 #clock-cells = <0>; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 clock-frequency = <32000>; 43 #clock-cells = <0>; 44 }; 45 }; 46 47 reserved-memory { 48 #address-cells = <2>; 49 #size-cells = <2>; 50 ranges; 51 52 aop_mem: memory@80800000 { 53 reg = <0x0 0x80800000 0x0 0x60000>; 54 no-map; 55 }; 56 57 aop_cmd_db_mem: memory@80860000 { 58 reg = <0x0 0x80860000 0x0 0x20000>; 59 compatible = "qcom,cmd-db"; 60 no-map; 61 }; 62 63 smem_mem: memory@80900000 { 64 reg = <0x0 0x80900000 0x0 0x200000>; 65 no-map; 66 }; 67 68 cpucp_mem: memory@80b00000 { 69 no-map; 70 reg = <0x0 0x80b00000 0x0 0x100000>; 71 }; 72 73 ipa_fw_mem: memory@8b700000 { 74 reg = <0 0x8b700000 0 0x10000>; 75 no-map; 76 }; 77 }; 78 79 cpus { 80 #address-cells = <2>; 81 #size-cells = <0>; 82 83 CPU0: cpu@0 { 84 device_type = "cpu"; 85 compatible = "arm,kryo"; 86 reg = <0x0 0x0>; 87 enable-method = "psci"; 88 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 89 &LITTLE_CPU_SLEEP_1 90 &CLUSTER_SLEEP_0>; 91 next-level-cache = <&L2_0>; 92 qcom,freq-domain = <&cpufreq_hw 0>; 93 #cooling-cells = <2>; 94 L2_0: l2-cache { 95 compatible = "cache"; 96 next-level-cache = <&L3_0>; 97 L3_0: l3-cache { 98 compatible = "cache"; 99 }; 100 }; 101 }; 102 103 CPU1: cpu@100 { 104 device_type = "cpu"; 105 compatible = "arm,kryo"; 106 reg = <0x0 0x100>; 107 enable-method = "psci"; 108 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 109 &LITTLE_CPU_SLEEP_1 110 &CLUSTER_SLEEP_0>; 111 next-level-cache = <&L2_100>; 112 qcom,freq-domain = <&cpufreq_hw 0>; 113 #cooling-cells = <2>; 114 L2_100: l2-cache { 115 compatible = "cache"; 116 next-level-cache = <&L3_0>; 117 }; 118 }; 119 120 CPU2: cpu@200 { 121 device_type = "cpu"; 122 compatible = "arm,kryo"; 123 reg = <0x0 0x200>; 124 enable-method = "psci"; 125 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 126 &LITTLE_CPU_SLEEP_1 127 &CLUSTER_SLEEP_0>; 128 next-level-cache = <&L2_200>; 129 qcom,freq-domain = <&cpufreq_hw 0>; 130 #cooling-cells = <2>; 131 L2_200: l2-cache { 132 compatible = "cache"; 133 next-level-cache = <&L3_0>; 134 }; 135 }; 136 137 CPU3: cpu@300 { 138 device_type = "cpu"; 139 compatible = "arm,kryo"; 140 reg = <0x0 0x300>; 141 enable-method = "psci"; 142 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 143 &LITTLE_CPU_SLEEP_1 144 &CLUSTER_SLEEP_0>; 145 next-level-cache = <&L2_300>; 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 #cooling-cells = <2>; 148 L2_300: l2-cache { 149 compatible = "cache"; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU4: cpu@400 { 155 device_type = "cpu"; 156 compatible = "arm,kryo"; 157 reg = <0x0 0x400>; 158 enable-method = "psci"; 159 cpu-idle-states = <&BIG_CPU_SLEEP_0 160 &BIG_CPU_SLEEP_1 161 &CLUSTER_SLEEP_0>; 162 next-level-cache = <&L2_400>; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 #cooling-cells = <2>; 165 L2_400: l2-cache { 166 compatible = "cache"; 167 next-level-cache = <&L3_0>; 168 }; 169 }; 170 171 CPU5: cpu@500 { 172 device_type = "cpu"; 173 compatible = "arm,kryo"; 174 reg = <0x0 0x500>; 175 enable-method = "psci"; 176 cpu-idle-states = <&BIG_CPU_SLEEP_0 177 &BIG_CPU_SLEEP_1 178 &CLUSTER_SLEEP_0>; 179 next-level-cache = <&L2_500>; 180 qcom,freq-domain = <&cpufreq_hw 1>; 181 #cooling-cells = <2>; 182 L2_500: l2-cache { 183 compatible = "cache"; 184 next-level-cache = <&L3_0>; 185 }; 186 }; 187 188 CPU6: cpu@600 { 189 device_type = "cpu"; 190 compatible = "arm,kryo"; 191 reg = <0x0 0x600>; 192 enable-method = "psci"; 193 cpu-idle-states = <&BIG_CPU_SLEEP_0 194 &BIG_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 next-level-cache = <&L2_600>; 197 qcom,freq-domain = <&cpufreq_hw 1>; 198 #cooling-cells = <2>; 199 L2_600: l2-cache { 200 compatible = "cache"; 201 next-level-cache = <&L3_0>; 202 }; 203 }; 204 205 CPU7: cpu@700 { 206 device_type = "cpu"; 207 compatible = "arm,kryo"; 208 reg = <0x0 0x700>; 209 enable-method = "psci"; 210 cpu-idle-states = <&BIG_CPU_SLEEP_0 211 &BIG_CPU_SLEEP_1 212 &CLUSTER_SLEEP_0>; 213 next-level-cache = <&L2_700>; 214 qcom,freq-domain = <&cpufreq_hw 2>; 215 #cooling-cells = <2>; 216 L2_700: l2-cache { 217 compatible = "cache"; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 idle-states { 223 entry-method = "psci"; 224 225 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 226 compatible = "arm,idle-state"; 227 idle-state-name = "little-power-down"; 228 arm,psci-suspend-param = <0x40000003>; 229 entry-latency-us = <549>; 230 exit-latency-us = <901>; 231 min-residency-us = <1774>; 232 local-timer-stop; 233 }; 234 235 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 236 compatible = "arm,idle-state"; 237 idle-state-name = "little-rail-power-down"; 238 arm,psci-suspend-param = <0x40000004>; 239 entry-latency-us = <702>; 240 exit-latency-us = <915>; 241 min-residency-us = <4001>; 242 local-timer-stop; 243 }; 244 245 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 246 compatible = "arm,idle-state"; 247 idle-state-name = "big-power-down"; 248 arm,psci-suspend-param = <0x40000003>; 249 entry-latency-us = <523>; 250 exit-latency-us = <1244>; 251 min-residency-us = <2207>; 252 local-timer-stop; 253 }; 254 255 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 256 compatible = "arm,idle-state"; 257 idle-state-name = "big-rail-power-down"; 258 arm,psci-suspend-param = <0x40000004>; 259 entry-latency-us = <526>; 260 exit-latency-us = <1854>; 261 min-residency-us = <5555>; 262 local-timer-stop; 263 }; 264 265 CLUSTER_SLEEP_0: cluster-sleep-0 { 266 compatible = "arm,idle-state"; 267 idle-state-name = "cluster-power-down"; 268 arm,psci-suspend-param = <0x40003444>; 269 entry-latency-us = <3263>; 270 exit-latency-us = <6562>; 271 min-residency-us = <9926>; 272 local-timer-stop; 273 }; 274 }; 275 }; 276 277 memory@80000000 { 278 device_type = "memory"; 279 /* We expect the bootloader to fill in the size */ 280 reg = <0 0x80000000 0 0>; 281 }; 282 283 firmware { 284 scm { 285 compatible = "qcom,scm-sc7280", "qcom,scm"; 286 }; 287 }; 288 289 clk_virt: interconnect { 290 compatible = "qcom,sc7280-clk-virt"; 291 #interconnect-cells = <2>; 292 qcom,bcm-voters = <&apps_bcm_voter>; 293 }; 294 295 smem { 296 compatible = "qcom,smem"; 297 memory-region = <&smem_mem>; 298 hwlocks = <&tcsr_mutex 3>; 299 }; 300 301 smp2p-adsp { 302 compatible = "qcom,smp2p"; 303 qcom,smem = <443>, <429>; 304 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 305 IPCC_MPROC_SIGNAL_SMP2P 306 IRQ_TYPE_EDGE_RISING>; 307 mboxes = <&ipcc IPCC_CLIENT_LPASS 308 IPCC_MPROC_SIGNAL_SMP2P>; 309 310 qcom,local-pid = <0>; 311 qcom,remote-pid = <2>; 312 313 adsp_smp2p_out: master-kernel { 314 qcom,entry-name = "master-kernel"; 315 #qcom,smem-state-cells = <1>; 316 }; 317 318 adsp_smp2p_in: slave-kernel { 319 qcom,entry-name = "slave-kernel"; 320 interrupt-controller; 321 #interrupt-cells = <2>; 322 }; 323 }; 324 325 smp2p-cdsp { 326 compatible = "qcom,smp2p"; 327 qcom,smem = <94>, <432>; 328 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 329 IPCC_MPROC_SIGNAL_SMP2P 330 IRQ_TYPE_EDGE_RISING>; 331 mboxes = <&ipcc IPCC_CLIENT_CDSP 332 IPCC_MPROC_SIGNAL_SMP2P>; 333 334 qcom,local-pid = <0>; 335 qcom,remote-pid = <5>; 336 337 cdsp_smp2p_out: master-kernel { 338 qcom,entry-name = "master-kernel"; 339 #qcom,smem-state-cells = <1>; 340 }; 341 342 cdsp_smp2p_in: slave-kernel { 343 qcom,entry-name = "slave-kernel"; 344 interrupt-controller; 345 #interrupt-cells = <2>; 346 }; 347 }; 348 349 smp2p-mpss { 350 compatible = "qcom,smp2p"; 351 qcom,smem = <435>, <428>; 352 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 353 IPCC_MPROC_SIGNAL_SMP2P 354 IRQ_TYPE_EDGE_RISING>; 355 mboxes = <&ipcc IPCC_CLIENT_MPSS 356 IPCC_MPROC_SIGNAL_SMP2P>; 357 358 qcom,local-pid = <0>; 359 qcom,remote-pid = <1>; 360 361 modem_smp2p_out: master-kernel { 362 qcom,entry-name = "master-kernel"; 363 #qcom,smem-state-cells = <1>; 364 }; 365 366 modem_smp2p_in: slave-kernel { 367 qcom,entry-name = "slave-kernel"; 368 interrupt-controller; 369 #interrupt-cells = <2>; 370 }; 371 372 ipa_smp2p_out: ipa-ap-to-modem { 373 qcom,entry-name = "ipa"; 374 #qcom,smem-state-cells = <1>; 375 }; 376 377 ipa_smp2p_in: ipa-modem-to-ap { 378 qcom,entry-name = "ipa"; 379 interrupt-controller; 380 #interrupt-cells = <2>; 381 }; 382 }; 383 384 smp2p-wpss { 385 compatible = "qcom,smp2p"; 386 qcom,smem = <617>, <616>; 387 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 388 IPCC_MPROC_SIGNAL_SMP2P 389 IRQ_TYPE_EDGE_RISING>; 390 mboxes = <&ipcc IPCC_CLIENT_WPSS 391 IPCC_MPROC_SIGNAL_SMP2P>; 392 393 qcom,local-pid = <0>; 394 qcom,remote-pid = <13>; 395 396 wpss_smp2p_out: master-kernel { 397 qcom,entry-name = "master-kernel"; 398 #qcom,smem-state-cells = <1>; 399 }; 400 401 wpss_smp2p_in: slave-kernel { 402 qcom,entry-name = "slave-kernel"; 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 }; 406 }; 407 408 pmu { 409 compatible = "arm,armv8-pmuv3"; 410 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 411 }; 412 413 psci { 414 compatible = "arm,psci-1.0"; 415 method = "smc"; 416 }; 417 418 soc: soc@0 { 419 #address-cells = <2>; 420 #size-cells = <2>; 421 ranges = <0 0 0 0 0x10 0>; 422 dma-ranges = <0 0 0 0 0x10 0>; 423 compatible = "simple-bus"; 424 425 gcc: clock-controller@100000 { 426 compatible = "qcom,gcc-sc7280"; 427 reg = <0 0x00100000 0 0x1f0000>; 428 clocks = <&rpmhcc RPMH_CXO_CLK>, 429 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 430 <0>, <0>, <0>, <0>, <0>, <0>; 431 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 432 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 433 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 434 "ufs_phy_tx_symbol_0_clk", 435 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 436 #clock-cells = <1>; 437 #reset-cells = <1>; 438 #power-domain-cells = <1>; 439 }; 440 441 ipcc: mailbox@408000 { 442 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 443 reg = <0 0x00408000 0 0x1000>; 444 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 445 interrupt-controller; 446 #interrupt-cells = <3>; 447 #mbox-cells = <2>; 448 }; 449 450 qfprom: efuse@784000 { 451 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 452 reg = <0 0x00784000 0 0xa20>, 453 <0 0x00780000 0 0xa20>, 454 <0 0x00782000 0 0x120>, 455 <0 0x00786000 0 0x1fff>; 456 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 457 clock-names = "core"; 458 power-domains = <&rpmhpd SC7280_MX>; 459 #address-cells = <1>; 460 #size-cells = <1>; 461 }; 462 463 sdhc_1: sdhci@7c4000 { 464 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 465 status = "disabled"; 466 467 reg = <0 0x007c4000 0 0x1000>, 468 <0 0x007c5000 0 0x1000>; 469 reg-names = "hc", "cqhci"; 470 471 iommus = <&apps_smmu 0xc0 0x0>; 472 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 474 interrupt-names = "hc_irq", "pwr_irq"; 475 476 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 477 <&gcc GCC_SDCC1_AHB_CLK>, 478 <&rpmhcc RPMH_CXO_CLK>; 479 clock-names = "core", "iface", "xo"; 480 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 481 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 482 interconnect-names = "sdhc-ddr","cpu-sdhc"; 483 power-domains = <&rpmhpd SC7280_CX>; 484 operating-points-v2 = <&sdhc1_opp_table>; 485 486 bus-width = <8>; 487 supports-cqe; 488 dma-coherent; 489 490 qcom,dll-config = <0x0007642c>; 491 qcom,ddr-config = <0x80040868>; 492 493 mmc-ddr-1_8v; 494 mmc-hs200-1_8v; 495 mmc-hs400-1_8v; 496 mmc-hs400-enhanced-strobe; 497 498 sdhc1_opp_table: opp-table { 499 compatible = "operating-points-v2"; 500 501 opp-100000000 { 502 opp-hz = /bits/ 64 <100000000>; 503 required-opps = <&rpmhpd_opp_low_svs>; 504 opp-peak-kBps = <1800000 400000>; 505 opp-avg-kBps = <100000 0>; 506 }; 507 508 opp-384000000 { 509 opp-hz = /bits/ 64 <384000000>; 510 required-opps = <&rpmhpd_opp_nom>; 511 opp-peak-kBps = <5400000 1600000>; 512 opp-avg-kBps = <390000 0>; 513 }; 514 }; 515 516 }; 517 518 qupv3_id_0: geniqup@9c0000 { 519 compatible = "qcom,geni-se-qup"; 520 reg = <0 0x009c0000 0 0x2000>; 521 clock-names = "m-ahb", "s-ahb"; 522 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 523 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 524 #address-cells = <2>; 525 #size-cells = <2>; 526 ranges; 527 status = "disabled"; 528 529 uart5: serial@994000 { 530 compatible = "qcom,geni-debug-uart"; 531 reg = <0 0x00994000 0 0x4000>; 532 clock-names = "se"; 533 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&qup_uart5_default>; 536 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 537 status = "disabled"; 538 }; 539 }; 540 541 cnoc2: interconnect@1500000 { 542 reg = <0 0x01500000 0 0x1000>; 543 compatible = "qcom,sc7280-cnoc2"; 544 #interconnect-cells = <2>; 545 qcom,bcm-voters = <&apps_bcm_voter>; 546 }; 547 548 cnoc3: interconnect@1502000 { 549 reg = <0 0x01502000 0 0x1000>; 550 compatible = "qcom,sc7280-cnoc3"; 551 #interconnect-cells = <2>; 552 qcom,bcm-voters = <&apps_bcm_voter>; 553 }; 554 555 mc_virt: interconnect@1580000 { 556 reg = <0 0x01580000 0 0x4>; 557 compatible = "qcom,sc7280-mc-virt"; 558 #interconnect-cells = <2>; 559 qcom,bcm-voters = <&apps_bcm_voter>; 560 }; 561 562 system_noc: interconnect@1680000 { 563 reg = <0 0x01680000 0 0x15480>; 564 compatible = "qcom,sc7280-system-noc"; 565 #interconnect-cells = <2>; 566 qcom,bcm-voters = <&apps_bcm_voter>; 567 }; 568 569 aggre1_noc: interconnect@16e0000 { 570 compatible = "qcom,sc7280-aggre1-noc"; 571 reg = <0 0x016e0000 0 0x1c080>; 572 #interconnect-cells = <2>; 573 qcom,bcm-voters = <&apps_bcm_voter>; 574 }; 575 576 aggre2_noc: interconnect@1700000 { 577 reg = <0 0x01700000 0 0x2b080>; 578 compatible = "qcom,sc7280-aggre2-noc"; 579 #interconnect-cells = <2>; 580 qcom,bcm-voters = <&apps_bcm_voter>; 581 }; 582 583 mmss_noc: interconnect@1740000 { 584 reg = <0 0x01740000 0 0x1e080>; 585 compatible = "qcom,sc7280-mmss-noc"; 586 #interconnect-cells = <2>; 587 qcom,bcm-voters = <&apps_bcm_voter>; 588 }; 589 590 ipa: ipa@1e40000 { 591 compatible = "qcom,sc7280-ipa"; 592 593 iommus = <&apps_smmu 0x480 0x0>, 594 <&apps_smmu 0x482 0x0>; 595 reg = <0 0x1e40000 0 0x8000>, 596 <0 0x1e50000 0 0x4ad0>, 597 <0 0x1e04000 0 0x23000>; 598 reg-names = "ipa-reg", 599 "ipa-shared", 600 "gsi"; 601 602 interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>, 603 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, 604 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 605 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 606 interrupt-names = "ipa", 607 "gsi", 608 "ipa-clock-query", 609 "ipa-setup-ready"; 610 611 clocks = <&rpmhcc RPMH_IPA_CLK>; 612 clock-names = "core"; 613 614 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 615 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 616 interconnect-names = "memory", 617 "config"; 618 619 qcom,qmp = <&aoss_qmp>; 620 621 qcom,smem-states = <&ipa_smp2p_out 0>, 622 <&ipa_smp2p_out 1>; 623 qcom,smem-state-names = "ipa-clock-enabled-valid", 624 "ipa-clock-enabled"; 625 626 status = "disabled"; 627 }; 628 629 tcsr_mutex: hwlock@1f40000 { 630 compatible = "qcom,tcsr-mutex", "syscon"; 631 reg = <0 0x01f40000 0 0x40000>; 632 #hwlock-cells = <1>; 633 }; 634 635 lpasscc: lpasscc@3000000 { 636 compatible = "qcom,sc7280-lpasscc"; 637 reg = <0 0x03000000 0 0x40>, 638 <0 0x03c04000 0 0x4>, 639 <0 0x03389000 0 0x24>; 640 reg-names = "qdsp6ss", "top_cc", "cc"; 641 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 642 clock-names = "iface"; 643 #clock-cells = <1>; 644 }; 645 646 lpass_ag_noc: interconnect@3c40000 { 647 reg = <0 0x03c40000 0 0xf080>; 648 compatible = "qcom,sc7280-lpass-ag-noc"; 649 #interconnect-cells = <2>; 650 qcom,bcm-voters = <&apps_bcm_voter>; 651 }; 652 653 gpucc: clock-controller@3d90000 { 654 compatible = "qcom,sc7280-gpucc"; 655 reg = <0 0x03d90000 0 0x9000>; 656 clocks = <&rpmhcc RPMH_CXO_CLK>, 657 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 658 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 659 clock-names = "bi_tcxo", 660 "gcc_gpu_gpll0_clk_src", 661 "gcc_gpu_gpll0_div_clk_src"; 662 #clock-cells = <1>; 663 #reset-cells = <1>; 664 #power-domain-cells = <1>; 665 }; 666 667 stm@6002000 { 668 compatible = "arm,coresight-stm", "arm,primecell"; 669 reg = <0 0x06002000 0 0x1000>, 670 <0 0x16280000 0 0x180000>; 671 reg-names = "stm-base", "stm-stimulus-base"; 672 673 clocks = <&aoss_qmp>; 674 clock-names = "apb_pclk"; 675 676 out-ports { 677 port { 678 stm_out: endpoint { 679 remote-endpoint = <&funnel0_in7>; 680 }; 681 }; 682 }; 683 }; 684 685 funnel@6041000 { 686 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 687 reg = <0 0x06041000 0 0x1000>; 688 689 clocks = <&aoss_qmp>; 690 clock-names = "apb_pclk"; 691 692 out-ports { 693 port { 694 funnel0_out: endpoint { 695 remote-endpoint = <&merge_funnel_in0>; 696 }; 697 }; 698 }; 699 700 in-ports { 701 #address-cells = <1>; 702 #size-cells = <0>; 703 704 port@7 { 705 reg = <7>; 706 funnel0_in7: endpoint { 707 remote-endpoint = <&stm_out>; 708 }; 709 }; 710 }; 711 }; 712 713 funnel@6042000 { 714 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 715 reg = <0 0x06042000 0 0x1000>; 716 717 clocks = <&aoss_qmp>; 718 clock-names = "apb_pclk"; 719 720 out-ports { 721 port { 722 funnel1_out: endpoint { 723 remote-endpoint = <&merge_funnel_in1>; 724 }; 725 }; 726 }; 727 728 in-ports { 729 #address-cells = <1>; 730 #size-cells = <0>; 731 732 port@4 { 733 reg = <4>; 734 funnel1_in4: endpoint { 735 remote-endpoint = <&apss_merge_funnel_out>; 736 }; 737 }; 738 }; 739 }; 740 741 funnel@6045000 { 742 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 743 reg = <0 0x06045000 0 0x1000>; 744 745 clocks = <&aoss_qmp>; 746 clock-names = "apb_pclk"; 747 748 out-ports { 749 port { 750 merge_funnel_out: endpoint { 751 remote-endpoint = <&swao_funnel_in>; 752 }; 753 }; 754 }; 755 756 in-ports { 757 #address-cells = <1>; 758 #size-cells = <0>; 759 760 port@0 { 761 reg = <0>; 762 merge_funnel_in0: endpoint { 763 remote-endpoint = <&funnel0_out>; 764 }; 765 }; 766 767 port@1 { 768 reg = <1>; 769 merge_funnel_in1: endpoint { 770 remote-endpoint = <&funnel1_out>; 771 }; 772 }; 773 }; 774 }; 775 776 replicator@6046000 { 777 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 778 reg = <0 0x06046000 0 0x1000>; 779 780 clocks = <&aoss_qmp>; 781 clock-names = "apb_pclk"; 782 783 out-ports { 784 port { 785 replicator_out: endpoint { 786 remote-endpoint = <&etr_in>; 787 }; 788 }; 789 }; 790 791 in-ports { 792 port { 793 replicator_in: endpoint { 794 remote-endpoint = <&swao_replicator_out>; 795 }; 796 }; 797 }; 798 }; 799 800 etr@6048000 { 801 compatible = "arm,coresight-tmc", "arm,primecell"; 802 reg = <0 0x06048000 0 0x1000>; 803 iommus = <&apps_smmu 0x04c0 0>; 804 805 clocks = <&aoss_qmp>; 806 clock-names = "apb_pclk"; 807 arm,scatter-gather; 808 809 in-ports { 810 port { 811 etr_in: endpoint { 812 remote-endpoint = <&replicator_out>; 813 }; 814 }; 815 }; 816 }; 817 818 funnel@6b04000 { 819 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 820 reg = <0 0x06b04000 0 0x1000>; 821 822 clocks = <&aoss_qmp>; 823 clock-names = "apb_pclk"; 824 825 out-ports { 826 port { 827 swao_funnel_out: endpoint { 828 remote-endpoint = <&etf_in>; 829 }; 830 }; 831 }; 832 833 in-ports { 834 #address-cells = <1>; 835 #size-cells = <0>; 836 837 port@7 { 838 reg = <7>; 839 swao_funnel_in: endpoint { 840 remote-endpoint = <&merge_funnel_out>; 841 }; 842 }; 843 }; 844 }; 845 846 etf@6b05000 { 847 compatible = "arm,coresight-tmc", "arm,primecell"; 848 reg = <0 0x06b05000 0 0x1000>; 849 850 clocks = <&aoss_qmp>; 851 clock-names = "apb_pclk"; 852 853 out-ports { 854 port { 855 etf_out: endpoint { 856 remote-endpoint = <&swao_replicator_in>; 857 }; 858 }; 859 }; 860 861 in-ports { 862 port { 863 etf_in: endpoint { 864 remote-endpoint = <&swao_funnel_out>; 865 }; 866 }; 867 }; 868 }; 869 870 replicator@6b06000 { 871 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 872 reg = <0 0x06b06000 0 0x1000>; 873 874 clocks = <&aoss_qmp>; 875 clock-names = "apb_pclk"; 876 qcom,replicator-loses-context; 877 878 out-ports { 879 port { 880 swao_replicator_out: endpoint { 881 remote-endpoint = <&replicator_in>; 882 }; 883 }; 884 }; 885 886 in-ports { 887 port { 888 swao_replicator_in: endpoint { 889 remote-endpoint = <&etf_out>; 890 }; 891 }; 892 }; 893 }; 894 895 etm@7040000 { 896 compatible = "arm,coresight-etm4x", "arm,primecell"; 897 reg = <0 0x07040000 0 0x1000>; 898 899 cpu = <&CPU0>; 900 901 clocks = <&aoss_qmp>; 902 clock-names = "apb_pclk"; 903 arm,coresight-loses-context-with-cpu; 904 qcom,skip-power-up; 905 906 out-ports { 907 port { 908 etm0_out: endpoint { 909 remote-endpoint = <&apss_funnel_in0>; 910 }; 911 }; 912 }; 913 }; 914 915 etm@7140000 { 916 compatible = "arm,coresight-etm4x", "arm,primecell"; 917 reg = <0 0x07140000 0 0x1000>; 918 919 cpu = <&CPU1>; 920 921 clocks = <&aoss_qmp>; 922 clock-names = "apb_pclk"; 923 arm,coresight-loses-context-with-cpu; 924 qcom,skip-power-up; 925 926 out-ports { 927 port { 928 etm1_out: endpoint { 929 remote-endpoint = <&apss_funnel_in1>; 930 }; 931 }; 932 }; 933 }; 934 935 etm@7240000 { 936 compatible = "arm,coresight-etm4x", "arm,primecell"; 937 reg = <0 0x07240000 0 0x1000>; 938 939 cpu = <&CPU2>; 940 941 clocks = <&aoss_qmp>; 942 clock-names = "apb_pclk"; 943 arm,coresight-loses-context-with-cpu; 944 qcom,skip-power-up; 945 946 out-ports { 947 port { 948 etm2_out: endpoint { 949 remote-endpoint = <&apss_funnel_in2>; 950 }; 951 }; 952 }; 953 }; 954 955 etm@7340000 { 956 compatible = "arm,coresight-etm4x", "arm,primecell"; 957 reg = <0 0x07340000 0 0x1000>; 958 959 cpu = <&CPU3>; 960 961 clocks = <&aoss_qmp>; 962 clock-names = "apb_pclk"; 963 arm,coresight-loses-context-with-cpu; 964 qcom,skip-power-up; 965 966 out-ports { 967 port { 968 etm3_out: endpoint { 969 remote-endpoint = <&apss_funnel_in3>; 970 }; 971 }; 972 }; 973 }; 974 975 etm@7440000 { 976 compatible = "arm,coresight-etm4x", "arm,primecell"; 977 reg = <0 0x07440000 0 0x1000>; 978 979 cpu = <&CPU4>; 980 981 clocks = <&aoss_qmp>; 982 clock-names = "apb_pclk"; 983 arm,coresight-loses-context-with-cpu; 984 qcom,skip-power-up; 985 986 out-ports { 987 port { 988 etm4_out: endpoint { 989 remote-endpoint = <&apss_funnel_in4>; 990 }; 991 }; 992 }; 993 }; 994 995 etm@7540000 { 996 compatible = "arm,coresight-etm4x", "arm,primecell"; 997 reg = <0 0x07540000 0 0x1000>; 998 999 cpu = <&CPU5>; 1000 1001 clocks = <&aoss_qmp>; 1002 clock-names = "apb_pclk"; 1003 arm,coresight-loses-context-with-cpu; 1004 qcom,skip-power-up; 1005 1006 out-ports { 1007 port { 1008 etm5_out: endpoint { 1009 remote-endpoint = <&apss_funnel_in5>; 1010 }; 1011 }; 1012 }; 1013 }; 1014 1015 etm@7640000 { 1016 compatible = "arm,coresight-etm4x", "arm,primecell"; 1017 reg = <0 0x07640000 0 0x1000>; 1018 1019 cpu = <&CPU6>; 1020 1021 clocks = <&aoss_qmp>; 1022 clock-names = "apb_pclk"; 1023 arm,coresight-loses-context-with-cpu; 1024 qcom,skip-power-up; 1025 1026 out-ports { 1027 port { 1028 etm6_out: endpoint { 1029 remote-endpoint = <&apss_funnel_in6>; 1030 }; 1031 }; 1032 }; 1033 }; 1034 1035 etm@7740000 { 1036 compatible = "arm,coresight-etm4x", "arm,primecell"; 1037 reg = <0 0x07740000 0 0x1000>; 1038 1039 cpu = <&CPU7>; 1040 1041 clocks = <&aoss_qmp>; 1042 clock-names = "apb_pclk"; 1043 arm,coresight-loses-context-with-cpu; 1044 qcom,skip-power-up; 1045 1046 out-ports { 1047 port { 1048 etm7_out: endpoint { 1049 remote-endpoint = <&apss_funnel_in7>; 1050 }; 1051 }; 1052 }; 1053 }; 1054 1055 funnel@7800000 { /* APSS Funnel */ 1056 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1057 reg = <0 0x07800000 0 0x1000>; 1058 1059 clocks = <&aoss_qmp>; 1060 clock-names = "apb_pclk"; 1061 1062 out-ports { 1063 port { 1064 apss_funnel_out: endpoint { 1065 remote-endpoint = <&apss_merge_funnel_in>; 1066 }; 1067 }; 1068 }; 1069 1070 in-ports { 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 1074 port@0 { 1075 reg = <0>; 1076 apss_funnel_in0: endpoint { 1077 remote-endpoint = <&etm0_out>; 1078 }; 1079 }; 1080 1081 port@1 { 1082 reg = <1>; 1083 apss_funnel_in1: endpoint { 1084 remote-endpoint = <&etm1_out>; 1085 }; 1086 }; 1087 1088 port@2 { 1089 reg = <2>; 1090 apss_funnel_in2: endpoint { 1091 remote-endpoint = <&etm2_out>; 1092 }; 1093 }; 1094 1095 port@3 { 1096 reg = <3>; 1097 apss_funnel_in3: endpoint { 1098 remote-endpoint = <&etm3_out>; 1099 }; 1100 }; 1101 1102 port@4 { 1103 reg = <4>; 1104 apss_funnel_in4: endpoint { 1105 remote-endpoint = <&etm4_out>; 1106 }; 1107 }; 1108 1109 port@5 { 1110 reg = <5>; 1111 apss_funnel_in5: endpoint { 1112 remote-endpoint = <&etm5_out>; 1113 }; 1114 }; 1115 1116 port@6 { 1117 reg = <6>; 1118 apss_funnel_in6: endpoint { 1119 remote-endpoint = <&etm6_out>; 1120 }; 1121 }; 1122 1123 port@7 { 1124 reg = <7>; 1125 apss_funnel_in7: endpoint { 1126 remote-endpoint = <&etm7_out>; 1127 }; 1128 }; 1129 }; 1130 }; 1131 1132 funnel@7810000 { 1133 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1134 reg = <0 0x07810000 0 0x1000>; 1135 1136 clocks = <&aoss_qmp>; 1137 clock-names = "apb_pclk"; 1138 1139 out-ports { 1140 port { 1141 apss_merge_funnel_out: endpoint { 1142 remote-endpoint = <&funnel1_in4>; 1143 }; 1144 }; 1145 }; 1146 1147 in-ports { 1148 port { 1149 apss_merge_funnel_in: endpoint { 1150 remote-endpoint = <&apss_funnel_out>; 1151 }; 1152 }; 1153 }; 1154 }; 1155 1156 sdhc_2: sdhci@8804000 { 1157 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1158 status = "disabled"; 1159 1160 reg = <0 0x08804000 0 0x1000>; 1161 1162 iommus = <&apps_smmu 0x100 0x0>; 1163 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1165 interrupt-names = "hc_irq", "pwr_irq"; 1166 1167 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1168 <&gcc GCC_SDCC2_AHB_CLK>, 1169 <&rpmhcc RPMH_CXO_CLK>; 1170 clock-names = "core", "iface", "xo"; 1171 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 1172 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 1173 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1174 power-domains = <&rpmhpd SC7280_CX>; 1175 operating-points-v2 = <&sdhc2_opp_table>; 1176 1177 bus-width = <4>; 1178 dma-coherent; 1179 1180 qcom,dll-config = <0x0007642c>; 1181 1182 sdhc2_opp_table: opp-table { 1183 compatible = "operating-points-v2"; 1184 1185 opp-100000000 { 1186 opp-hz = /bits/ 64 <100000000>; 1187 required-opps = <&rpmhpd_opp_low_svs>; 1188 opp-peak-kBps = <1800000 400000>; 1189 opp-avg-kBps = <100000 0>; 1190 }; 1191 1192 opp-202000000 { 1193 opp-hz = /bits/ 64 <202000000>; 1194 required-opps = <&rpmhpd_opp_nom>; 1195 opp-peak-kBps = <5400000 1600000>; 1196 opp-avg-kBps = <200000 0>; 1197 }; 1198 }; 1199 1200 }; 1201 1202 usb_1_hsphy: phy@88e3000 { 1203 compatible = "qcom,sc7280-usb-hs-phy", 1204 "qcom,usb-snps-hs-7nm-phy"; 1205 reg = <0 0x088e3000 0 0x400>; 1206 status = "disabled"; 1207 #phy-cells = <0>; 1208 1209 clocks = <&rpmhcc RPMH_CXO_CLK>; 1210 clock-names = "ref"; 1211 1212 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1213 }; 1214 1215 usb_2_hsphy: phy@88e4000 { 1216 compatible = "qcom,sc7280-usb-hs-phy", 1217 "qcom,usb-snps-hs-7nm-phy"; 1218 reg = <0 0x088e4000 0 0x400>; 1219 status = "disabled"; 1220 #phy-cells = <0>; 1221 1222 clocks = <&rpmhcc RPMH_CXO_CLK>; 1223 clock-names = "ref"; 1224 1225 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1226 }; 1227 1228 usb_1_qmpphy: phy-wrapper@88e9000 { 1229 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 1230 "qcom,sm8250-qmp-usb3-dp-phy"; 1231 reg = <0 0x088e9000 0 0x200>, 1232 <0 0x088e8000 0 0x40>, 1233 <0 0x088ea000 0 0x200>; 1234 status = "disabled"; 1235 #address-cells = <2>; 1236 #size-cells = <2>; 1237 ranges; 1238 1239 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1240 <&rpmhcc RPMH_CXO_CLK>, 1241 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1242 clock-names = "aux", "ref_clk_src", "com_aux"; 1243 1244 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1245 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1246 reset-names = "phy", "common"; 1247 1248 usb_1_ssphy: usb3-phy@88e9200 { 1249 reg = <0 0x088e9200 0 0x200>, 1250 <0 0x088e9400 0 0x200>, 1251 <0 0x088e9c00 0 0x400>, 1252 <0 0x088e9600 0 0x200>, 1253 <0 0x088e9800 0 0x200>, 1254 <0 0x088e9a00 0 0x100>; 1255 #clock-cells = <0>; 1256 #phy-cells = <0>; 1257 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1258 clock-names = "pipe0"; 1259 clock-output-names = "usb3_phy_pipe_clk_src"; 1260 }; 1261 1262 dp_phy: dp-phy@88ea200 { 1263 reg = <0 0x088ea200 0 0x200>, 1264 <0 0x088ea400 0 0x200>, 1265 <0 0x088eaa00 0 0x200>, 1266 <0 0x088ea600 0 0x200>, 1267 <0 0x088ea800 0 0x200>; 1268 #phy-cells = <0>; 1269 #clock-cells = <1>; 1270 }; 1271 }; 1272 1273 usb_2: usb@8cf8800 { 1274 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1275 reg = <0 0x08cf8800 0 0x400>; 1276 status = "disabled"; 1277 #address-cells = <2>; 1278 #size-cells = <2>; 1279 ranges; 1280 dma-ranges; 1281 1282 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1283 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1284 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1285 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1286 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 1287 clock-names = "cfg_noc", "core", "iface","mock_utmi", 1288 "sleep"; 1289 1290 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1291 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1292 assigned-clock-rates = <19200000>, <200000000>; 1293 1294 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1295 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 1296 <&pdc 13 IRQ_TYPE_EDGE_BOTH>; 1297 interrupt-names = "hs_phy_irq", 1298 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1299 1300 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 1301 1302 resets = <&gcc GCC_USB30_SEC_BCR>; 1303 1304 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 1305 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 1306 interconnect-names = "usb-ddr", "apps-usb"; 1307 1308 usb_2_dwc3: usb@8c00000 { 1309 compatible = "snps,dwc3"; 1310 reg = <0 0x08c00000 0 0xe000>; 1311 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1312 iommus = <&apps_smmu 0xa0 0x0>; 1313 snps,dis_u2_susphy_quirk; 1314 snps,dis_enblslpm_quirk; 1315 phys = <&usb_2_hsphy>; 1316 phy-names = "usb2-phy"; 1317 maximum-speed = "high-speed"; 1318 }; 1319 }; 1320 1321 dc_noc: interconnect@90e0000 { 1322 reg = <0 0x090e0000 0 0x5080>; 1323 compatible = "qcom,sc7280-dc-noc"; 1324 #interconnect-cells = <2>; 1325 qcom,bcm-voters = <&apps_bcm_voter>; 1326 }; 1327 1328 gem_noc: interconnect@9100000 { 1329 reg = <0 0x9100000 0 0xe2200>; 1330 compatible = "qcom,sc7280-gem-noc"; 1331 #interconnect-cells = <2>; 1332 qcom,bcm-voters = <&apps_bcm_voter>; 1333 }; 1334 1335 system-cache-controller@9200000 { 1336 compatible = "qcom,sc7280-llcc"; 1337 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 1338 reg-names = "llcc_base", "llcc_broadcast_base"; 1339 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1340 }; 1341 1342 nsp_noc: interconnect@a0c0000 { 1343 reg = <0 0x0a0c0000 0 0x10000>; 1344 compatible = "qcom,sc7280-nsp-noc"; 1345 #interconnect-cells = <2>; 1346 qcom,bcm-voters = <&apps_bcm_voter>; 1347 }; 1348 1349 usb_1: usb@a6f8800 { 1350 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 1351 reg = <0 0x0a6f8800 0 0x400>; 1352 status = "disabled"; 1353 #address-cells = <2>; 1354 #size-cells = <2>; 1355 ranges; 1356 dma-ranges; 1357 1358 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1359 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1360 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1361 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1362 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1363 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1364 "sleep"; 1365 1366 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1367 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1368 assigned-clock-rates = <19200000>, <200000000>; 1369 1370 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1371 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1372 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1373 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1374 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1375 "dm_hs_phy_irq", "ss_phy_irq"; 1376 1377 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1378 1379 resets = <&gcc GCC_USB30_PRIM_BCR>; 1380 1381 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 1382 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 1383 interconnect-names = "usb-ddr", "apps-usb"; 1384 1385 usb_1_dwc3: usb@a600000 { 1386 compatible = "snps,dwc3"; 1387 reg = <0 0x0a600000 0 0xe000>; 1388 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1389 iommus = <&apps_smmu 0xe0 0x0>; 1390 snps,dis_u2_susphy_quirk; 1391 snps,dis_enblslpm_quirk; 1392 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1393 phy-names = "usb2-phy", "usb3-phy"; 1394 maximum-speed = "super-speed"; 1395 }; 1396 }; 1397 1398 videocc: clock-controller@aaf0000 { 1399 compatible = "qcom,sc7280-videocc"; 1400 reg = <0 0xaaf0000 0 0x10000>; 1401 clocks = <&rpmhcc RPMH_CXO_CLK>, 1402 <&rpmhcc RPMH_CXO_CLK_A>; 1403 clock-names = "bi_tcxo", "bi_tcxo_ao"; 1404 #clock-cells = <1>; 1405 #reset-cells = <1>; 1406 #power-domain-cells = <1>; 1407 }; 1408 1409 dispcc: clock-controller@af00000 { 1410 compatible = "qcom,sc7280-dispcc"; 1411 reg = <0 0xaf00000 0 0x20000>; 1412 clocks = <&rpmhcc RPMH_CXO_CLK>, 1413 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1414 <0>, <0>, <0>, <0>, <0>, <0>; 1415 clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", 1416 "dsi0_phy_pll_out_byteclk", 1417 "dsi0_phy_pll_out_dsiclk", 1418 "dp_phy_pll_link_clk", 1419 "dp_phy_pll_vco_div_clk", 1420 "edp_phy_pll_link_clk", 1421 "edp_phy_pll_vco_div_clk"; 1422 #clock-cells = <1>; 1423 #reset-cells = <1>; 1424 #power-domain-cells = <1>; 1425 }; 1426 1427 pdc: interrupt-controller@b220000 { 1428 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 1429 reg = <0 0x0b220000 0 0x30000>; 1430 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 1431 <55 306 4>, <59 312 3>, <62 374 2>, 1432 <64 434 2>, <66 438 3>, <69 86 1>, 1433 <70 520 54>, <124 609 31>, <155 63 1>, 1434 <156 716 12>; 1435 #interrupt-cells = <2>; 1436 interrupt-parent = <&intc>; 1437 interrupt-controller; 1438 }; 1439 1440 pdc_reset: reset-controller@b5e0000 { 1441 compatible = "qcom,sc7280-pdc-global"; 1442 reg = <0 0x0b5e0000 0 0x20000>; 1443 #reset-cells = <1>; 1444 }; 1445 1446 tsens0: thermal-sensor@c263000 { 1447 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1448 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1449 <0 0x0c222000 0 0x1ff>; /* SROT */ 1450 #qcom,sensors = <15>; 1451 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1453 interrupt-names = "uplow","critical"; 1454 #thermal-sensor-cells = <1>; 1455 }; 1456 1457 tsens1: thermal-sensor@c265000 { 1458 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 1459 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1460 <0 0x0c223000 0 0x1ff>; /* SROT */ 1461 #qcom,sensors = <12>; 1462 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1464 interrupt-names = "uplow","critical"; 1465 #thermal-sensor-cells = <1>; 1466 }; 1467 1468 aoss_reset: reset-controller@c2a0000 { 1469 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 1470 reg = <0 0x0c2a0000 0 0x31000>; 1471 #reset-cells = <1>; 1472 }; 1473 1474 aoss_qmp: power-controller@c300000 { 1475 compatible = "qcom,sc7280-aoss-qmp"; 1476 reg = <0 0x0c300000 0 0x100000>; 1477 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 1478 IPCC_MPROC_SIGNAL_GLINK_QMP 1479 IRQ_TYPE_EDGE_RISING>; 1480 mboxes = <&ipcc IPCC_CLIENT_AOP 1481 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1482 1483 #clock-cells = <0>; 1484 #power-domain-cells = <1>; 1485 }; 1486 1487 spmi_bus: spmi@c440000 { 1488 compatible = "qcom,spmi-pmic-arb"; 1489 reg = <0 0x0c440000 0 0x1100>, 1490 <0 0x0c600000 0 0x2000000>, 1491 <0 0x0e600000 0 0x100000>, 1492 <0 0x0e700000 0 0xa0000>, 1493 <0 0x0c40a000 0 0x26000>; 1494 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1495 interrupt-names = "periph_irq"; 1496 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1497 qcom,ee = <0>; 1498 qcom,channel = <0>; 1499 #address-cells = <2>; 1500 #size-cells = <0>; 1501 interrupt-controller; 1502 #interrupt-cells = <4>; 1503 }; 1504 1505 tlmm: pinctrl@f100000 { 1506 compatible = "qcom,sc7280-pinctrl"; 1507 reg = <0 0x0f100000 0 0x300000>; 1508 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1509 gpio-controller; 1510 #gpio-cells = <2>; 1511 interrupt-controller; 1512 #interrupt-cells = <2>; 1513 gpio-ranges = <&tlmm 0 0 175>; 1514 wakeup-parent = <&pdc>; 1515 1516 qup_uart5_default: qup-uart5-default { 1517 pins = "gpio46", "gpio47"; 1518 function = "qup13"; 1519 }; 1520 1521 sdc1_on: sdc1-on { 1522 clk { 1523 pins = "sdc1_clk"; 1524 }; 1525 1526 cmd { 1527 pins = "sdc1_cmd"; 1528 }; 1529 1530 data { 1531 pins = "sdc1_data"; 1532 }; 1533 1534 rclk { 1535 pins = "sdc1_rclk"; 1536 }; 1537 }; 1538 1539 sdc1_off: sdc1-off { 1540 clk { 1541 pins = "sdc1_clk"; 1542 drive-strength = <2>; 1543 bias-bus-hold; 1544 }; 1545 1546 cmd { 1547 pins = "sdc1_cmd"; 1548 drive-strength = <2>; 1549 bias-bus-hold; 1550 }; 1551 1552 data { 1553 pins = "sdc1_data"; 1554 drive-strength = <2>; 1555 bias-bus-hold; 1556 }; 1557 1558 rclk { 1559 pins = "sdc1_rclk"; 1560 bias-bus-hold; 1561 }; 1562 }; 1563 1564 sdc2_on: sdc2-on { 1565 clk { 1566 pins = "sdc2_clk"; 1567 }; 1568 1569 cmd { 1570 pins = "sdc2_cmd"; 1571 }; 1572 1573 data { 1574 pins = "sdc2_data"; 1575 }; 1576 1577 sd-cd { 1578 pins = "gpio91"; 1579 }; 1580 }; 1581 1582 sdc2_off: sdc2-off { 1583 clk { 1584 pins = "sdc2_clk"; 1585 drive-strength = <2>; 1586 bias-bus-hold; 1587 }; 1588 1589 cmd { 1590 pins ="sdc2_cmd"; 1591 drive-strength = <2>; 1592 bias-bus-hold; 1593 }; 1594 1595 data { 1596 pins ="sdc2_data"; 1597 drive-strength = <2>; 1598 bias-bus-hold; 1599 }; 1600 }; 1601 }; 1602 1603 apps_smmu: iommu@15000000 { 1604 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 1605 reg = <0 0x15000000 0 0x100000>; 1606 #iommu-cells = <2>; 1607 #global-interrupts = <1>; 1608 dma-coherent; 1609 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1617 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1619 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1690 }; 1691 1692 intc: interrupt-controller@17a00000 { 1693 compatible = "arm,gic-v3"; 1694 #address-cells = <2>; 1695 #size-cells = <2>; 1696 ranges; 1697 #interrupt-cells = <3>; 1698 interrupt-controller; 1699 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1700 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1701 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1702 1703 gic-its@17a40000 { 1704 compatible = "arm,gic-v3-its"; 1705 msi-controller; 1706 #msi-cells = <1>; 1707 reg = <0 0x17a40000 0 0x20000>; 1708 status = "disabled"; 1709 }; 1710 }; 1711 1712 watchdog@17c10000 { 1713 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 1714 reg = <0 0x17c10000 0 0x1000>; 1715 clocks = <&sleep_clk>; 1716 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 1717 }; 1718 1719 timer@17c20000 { 1720 #address-cells = <2>; 1721 #size-cells = <2>; 1722 ranges; 1723 compatible = "arm,armv7-timer-mem"; 1724 reg = <0 0x17c20000 0 0x1000>; 1725 1726 frame@17c21000 { 1727 frame-number = <0>; 1728 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1730 reg = <0 0x17c21000 0 0x1000>, 1731 <0 0x17c22000 0 0x1000>; 1732 }; 1733 1734 frame@17c23000 { 1735 frame-number = <1>; 1736 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1737 reg = <0 0x17c23000 0 0x1000>; 1738 status = "disabled"; 1739 }; 1740 1741 frame@17c25000 { 1742 frame-number = <2>; 1743 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1744 reg = <0 0x17c25000 0 0x1000>; 1745 status = "disabled"; 1746 }; 1747 1748 frame@17c27000 { 1749 frame-number = <3>; 1750 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1751 reg = <0 0x17c27000 0 0x1000>; 1752 status = "disabled"; 1753 }; 1754 1755 frame@17c29000 { 1756 frame-number = <4>; 1757 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1758 reg = <0 0x17c29000 0 0x1000>; 1759 status = "disabled"; 1760 }; 1761 1762 frame@17c2b000 { 1763 frame-number = <5>; 1764 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1765 reg = <0 0x17c2b000 0 0x1000>; 1766 status = "disabled"; 1767 }; 1768 1769 frame@17c2d000 { 1770 frame-number = <6>; 1771 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1772 reg = <0 0x17c2d000 0 0x1000>; 1773 status = "disabled"; 1774 }; 1775 }; 1776 1777 apps_rsc: rsc@18200000 { 1778 compatible = "qcom,rpmh-rsc"; 1779 reg = <0 0x18200000 0 0x10000>, 1780 <0 0x18210000 0 0x10000>, 1781 <0 0x18220000 0 0x10000>; 1782 reg-names = "drv-0", "drv-1", "drv-2"; 1783 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1786 qcom,tcs-offset = <0xd00>; 1787 qcom,drv-id = <2>; 1788 qcom,tcs-config = <ACTIVE_TCS 2>, 1789 <SLEEP_TCS 3>, 1790 <WAKE_TCS 3>, 1791 <CONTROL_TCS 1>; 1792 1793 apps_bcm_voter: bcm-voter { 1794 compatible = "qcom,bcm-voter"; 1795 }; 1796 1797 rpmhpd: power-controller { 1798 compatible = "qcom,sc7280-rpmhpd"; 1799 #power-domain-cells = <1>; 1800 operating-points-v2 = <&rpmhpd_opp_table>; 1801 1802 rpmhpd_opp_table: opp-table { 1803 compatible = "operating-points-v2"; 1804 1805 rpmhpd_opp_ret: opp1 { 1806 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1807 }; 1808 1809 rpmhpd_opp_low_svs: opp2 { 1810 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1811 }; 1812 1813 rpmhpd_opp_svs: opp3 { 1814 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1815 }; 1816 1817 rpmhpd_opp_svs_l1: opp4 { 1818 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1819 }; 1820 1821 rpmhpd_opp_svs_l2: opp5 { 1822 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1823 }; 1824 1825 rpmhpd_opp_nom: opp6 { 1826 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1827 }; 1828 1829 rpmhpd_opp_nom_l1: opp7 { 1830 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1831 }; 1832 1833 rpmhpd_opp_turbo: opp8 { 1834 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1835 }; 1836 1837 rpmhpd_opp_turbo_l1: opp9 { 1838 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1839 }; 1840 }; 1841 }; 1842 1843 rpmhcc: clock-controller { 1844 compatible = "qcom,sc7280-rpmh-clk"; 1845 clocks = <&xo_board>; 1846 clock-names = "xo"; 1847 #clock-cells = <1>; 1848 }; 1849 }; 1850 1851 cpufreq_hw: cpufreq@18591000 { 1852 compatible = "qcom,cpufreq-epss"; 1853 reg = <0 0x18591000 0 0x1000>, 1854 <0 0x18592000 0 0x1000>, 1855 <0 0x18593000 0 0x1000>; 1856 1857 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1860 interrupt-names = "dcvsh-irq-0", 1861 "dcvsh-irq-1", 1862 "dcvsh-irq-2"; 1863 1864 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1865 clock-names = "xo", "alternate"; 1866 #freq-domain-cells = <1>; 1867 }; 1868 }; 1869 1870 thermal_zones: thermal-zones { 1871 cpu0-thermal { 1872 polling-delay-passive = <250>; 1873 polling-delay = <0>; 1874 1875 thermal-sensors = <&tsens0 1>; 1876 1877 trips { 1878 cpu0_alert0: trip-point0 { 1879 temperature = <90000>; 1880 hysteresis = <2000>; 1881 type = "passive"; 1882 }; 1883 1884 cpu0_alert1: trip-point1 { 1885 temperature = <95000>; 1886 hysteresis = <2000>; 1887 type = "passive"; 1888 }; 1889 1890 cpu0_crit: cpu-crit { 1891 temperature = <110000>; 1892 hysteresis = <0>; 1893 type = "critical"; 1894 }; 1895 }; 1896 1897 cooling-maps { 1898 map0 { 1899 trip = <&cpu0_alert0>; 1900 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1901 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1902 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1903 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1904 }; 1905 map1 { 1906 trip = <&cpu0_alert1>; 1907 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1908 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1909 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1910 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1911 }; 1912 }; 1913 }; 1914 1915 cpu1-thermal { 1916 polling-delay-passive = <250>; 1917 polling-delay = <0>; 1918 1919 thermal-sensors = <&tsens0 2>; 1920 1921 trips { 1922 cpu1_alert0: trip-point0 { 1923 temperature = <90000>; 1924 hysteresis = <2000>; 1925 type = "passive"; 1926 }; 1927 1928 cpu1_alert1: trip-point1 { 1929 temperature = <95000>; 1930 hysteresis = <2000>; 1931 type = "passive"; 1932 }; 1933 1934 cpu1_crit: cpu-crit { 1935 temperature = <110000>; 1936 hysteresis = <0>; 1937 type = "critical"; 1938 }; 1939 }; 1940 1941 cooling-maps { 1942 map0 { 1943 trip = <&cpu1_alert0>; 1944 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1945 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1946 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1947 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1948 }; 1949 map1 { 1950 trip = <&cpu1_alert1>; 1951 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1952 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1953 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1954 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1955 }; 1956 }; 1957 }; 1958 1959 cpu2-thermal { 1960 polling-delay-passive = <250>; 1961 polling-delay = <0>; 1962 1963 thermal-sensors = <&tsens0 3>; 1964 1965 trips { 1966 cpu2_alert0: trip-point0 { 1967 temperature = <90000>; 1968 hysteresis = <2000>; 1969 type = "passive"; 1970 }; 1971 1972 cpu2_alert1: trip-point1 { 1973 temperature = <95000>; 1974 hysteresis = <2000>; 1975 type = "passive"; 1976 }; 1977 1978 cpu2_crit: cpu-crit { 1979 temperature = <110000>; 1980 hysteresis = <0>; 1981 type = "critical"; 1982 }; 1983 }; 1984 1985 cooling-maps { 1986 map0 { 1987 trip = <&cpu2_alert0>; 1988 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1989 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1990 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1991 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1992 }; 1993 map1 { 1994 trip = <&cpu2_alert1>; 1995 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1996 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1997 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1998 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1999 }; 2000 }; 2001 }; 2002 2003 cpu3-thermal { 2004 polling-delay-passive = <250>; 2005 polling-delay = <0>; 2006 2007 thermal-sensors = <&tsens0 4>; 2008 2009 trips { 2010 cpu3_alert0: trip-point0 { 2011 temperature = <90000>; 2012 hysteresis = <2000>; 2013 type = "passive"; 2014 }; 2015 2016 cpu3_alert1: trip-point1 { 2017 temperature = <95000>; 2018 hysteresis = <2000>; 2019 type = "passive"; 2020 }; 2021 2022 cpu3_crit: cpu-crit { 2023 temperature = <110000>; 2024 hysteresis = <0>; 2025 type = "critical"; 2026 }; 2027 }; 2028 2029 cooling-maps { 2030 map0 { 2031 trip = <&cpu3_alert0>; 2032 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2033 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2034 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2035 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2036 }; 2037 map1 { 2038 trip = <&cpu3_alert1>; 2039 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2040 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2041 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2042 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2043 }; 2044 }; 2045 }; 2046 2047 cpu4-thermal { 2048 polling-delay-passive = <250>; 2049 polling-delay = <0>; 2050 2051 thermal-sensors = <&tsens0 7>; 2052 2053 trips { 2054 cpu4_alert0: trip-point0 { 2055 temperature = <90000>; 2056 hysteresis = <2000>; 2057 type = "passive"; 2058 }; 2059 2060 cpu4_alert1: trip-point1 { 2061 temperature = <95000>; 2062 hysteresis = <2000>; 2063 type = "passive"; 2064 }; 2065 2066 cpu4_crit: cpu-crit { 2067 temperature = <110000>; 2068 hysteresis = <0>; 2069 type = "critical"; 2070 }; 2071 }; 2072 2073 cooling-maps { 2074 map0 { 2075 trip = <&cpu4_alert0>; 2076 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2077 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2078 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2079 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2080 }; 2081 map1 { 2082 trip = <&cpu4_alert1>; 2083 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2084 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2085 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2086 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2087 }; 2088 }; 2089 }; 2090 2091 cpu5-thermal { 2092 polling-delay-passive = <250>; 2093 polling-delay = <0>; 2094 2095 thermal-sensors = <&tsens0 8>; 2096 2097 trips { 2098 cpu5_alert0: trip-point0 { 2099 temperature = <90000>; 2100 hysteresis = <2000>; 2101 type = "passive"; 2102 }; 2103 2104 cpu5_alert1: trip-point1 { 2105 temperature = <95000>; 2106 hysteresis = <2000>; 2107 type = "passive"; 2108 }; 2109 2110 cpu5_crit: cpu-crit { 2111 temperature = <110000>; 2112 hysteresis = <0>; 2113 type = "critical"; 2114 }; 2115 }; 2116 2117 cooling-maps { 2118 map0 { 2119 trip = <&cpu5_alert0>; 2120 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2121 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2122 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2123 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2124 }; 2125 map1 { 2126 trip = <&cpu5_alert1>; 2127 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2128 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2129 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2130 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2131 }; 2132 }; 2133 }; 2134 2135 cpu6-thermal { 2136 polling-delay-passive = <250>; 2137 polling-delay = <0>; 2138 2139 thermal-sensors = <&tsens0 9>; 2140 2141 trips { 2142 cpu6_alert0: trip-point0 { 2143 temperature = <90000>; 2144 hysteresis = <2000>; 2145 type = "passive"; 2146 }; 2147 2148 cpu6_alert1: trip-point1 { 2149 temperature = <95000>; 2150 hysteresis = <2000>; 2151 type = "passive"; 2152 }; 2153 2154 cpu6_crit: cpu-crit { 2155 temperature = <110000>; 2156 hysteresis = <0>; 2157 type = "critical"; 2158 }; 2159 }; 2160 2161 cooling-maps { 2162 map0 { 2163 trip = <&cpu6_alert0>; 2164 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2165 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2166 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2167 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2168 }; 2169 map1 { 2170 trip = <&cpu6_alert1>; 2171 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2172 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2173 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2174 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2175 }; 2176 }; 2177 }; 2178 2179 cpu7-thermal { 2180 polling-delay-passive = <250>; 2181 polling-delay = <0>; 2182 2183 thermal-sensors = <&tsens0 10>; 2184 2185 trips { 2186 cpu7_alert0: trip-point0 { 2187 temperature = <90000>; 2188 hysteresis = <2000>; 2189 type = "passive"; 2190 }; 2191 2192 cpu7_alert1: trip-point1 { 2193 temperature = <95000>; 2194 hysteresis = <2000>; 2195 type = "passive"; 2196 }; 2197 2198 cpu7_crit: cpu-crit { 2199 temperature = <110000>; 2200 hysteresis = <0>; 2201 type = "critical"; 2202 }; 2203 }; 2204 2205 cooling-maps { 2206 map0 { 2207 trip = <&cpu7_alert0>; 2208 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2209 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2210 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2211 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2212 }; 2213 map1 { 2214 trip = <&cpu7_alert1>; 2215 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2216 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2217 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2218 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2219 }; 2220 }; 2221 }; 2222 2223 cpu8-thermal { 2224 polling-delay-passive = <250>; 2225 polling-delay = <0>; 2226 2227 thermal-sensors = <&tsens0 11>; 2228 2229 trips { 2230 cpu8_alert0: trip-point0 { 2231 temperature = <90000>; 2232 hysteresis = <2000>; 2233 type = "passive"; 2234 }; 2235 2236 cpu8_alert1: trip-point1 { 2237 temperature = <95000>; 2238 hysteresis = <2000>; 2239 type = "passive"; 2240 }; 2241 2242 cpu8_crit: cpu-crit { 2243 temperature = <110000>; 2244 hysteresis = <0>; 2245 type = "critical"; 2246 }; 2247 }; 2248 2249 cooling-maps { 2250 map0 { 2251 trip = <&cpu8_alert0>; 2252 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2253 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2254 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2255 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2256 }; 2257 map1 { 2258 trip = <&cpu8_alert1>; 2259 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2260 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2261 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2262 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2263 }; 2264 }; 2265 }; 2266 2267 cpu9-thermal { 2268 polling-delay-passive = <250>; 2269 polling-delay = <0>; 2270 2271 thermal-sensors = <&tsens0 12>; 2272 2273 trips { 2274 cpu9_alert0: trip-point0 { 2275 temperature = <90000>; 2276 hysteresis = <2000>; 2277 type = "passive"; 2278 }; 2279 2280 cpu9_alert1: trip-point1 { 2281 temperature = <95000>; 2282 hysteresis = <2000>; 2283 type = "passive"; 2284 }; 2285 2286 cpu9_crit: cpu-crit { 2287 temperature = <110000>; 2288 hysteresis = <0>; 2289 type = "critical"; 2290 }; 2291 }; 2292 2293 cooling-maps { 2294 map0 { 2295 trip = <&cpu9_alert0>; 2296 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2297 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2298 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2299 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2300 }; 2301 map1 { 2302 trip = <&cpu9_alert1>; 2303 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2304 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2305 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2306 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2307 }; 2308 }; 2309 }; 2310 2311 cpu10-thermal { 2312 polling-delay-passive = <250>; 2313 polling-delay = <0>; 2314 2315 thermal-sensors = <&tsens0 13>; 2316 2317 trips { 2318 cpu10_alert0: trip-point0 { 2319 temperature = <90000>; 2320 hysteresis = <2000>; 2321 type = "passive"; 2322 }; 2323 2324 cpu10_alert1: trip-point1 { 2325 temperature = <95000>; 2326 hysteresis = <2000>; 2327 type = "passive"; 2328 }; 2329 2330 cpu10_crit: cpu-crit { 2331 temperature = <110000>; 2332 hysteresis = <0>; 2333 type = "critical"; 2334 }; 2335 }; 2336 2337 cooling-maps { 2338 map0 { 2339 trip = <&cpu10_alert0>; 2340 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2341 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2342 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2343 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2344 }; 2345 map1 { 2346 trip = <&cpu10_alert1>; 2347 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2348 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2349 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2350 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2351 }; 2352 }; 2353 }; 2354 2355 cpu11-thermal { 2356 polling-delay-passive = <250>; 2357 polling-delay = <0>; 2358 2359 thermal-sensors = <&tsens0 14>; 2360 2361 trips { 2362 cpu11_alert0: trip-point0 { 2363 temperature = <90000>; 2364 hysteresis = <2000>; 2365 type = "passive"; 2366 }; 2367 2368 cpu11_alert1: trip-point1 { 2369 temperature = <95000>; 2370 hysteresis = <2000>; 2371 type = "passive"; 2372 }; 2373 2374 cpu11_crit: cpu-crit { 2375 temperature = <110000>; 2376 hysteresis = <0>; 2377 type = "critical"; 2378 }; 2379 }; 2380 2381 cooling-maps { 2382 map0 { 2383 trip = <&cpu11_alert0>; 2384 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2385 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2386 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2387 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2388 }; 2389 map1 { 2390 trip = <&cpu11_alert1>; 2391 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2392 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2393 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2394 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2395 }; 2396 }; 2397 }; 2398 2399 aoss0-thermal { 2400 polling-delay-passive = <0>; 2401 polling-delay = <0>; 2402 2403 thermal-sensors = <&tsens0 0>; 2404 2405 trips { 2406 aoss0_alert0: trip-point0 { 2407 temperature = <90000>; 2408 hysteresis = <2000>; 2409 type = "hot"; 2410 }; 2411 2412 aoss0_crit: aoss0-crit { 2413 temperature = <110000>; 2414 hysteresis = <0>; 2415 type = "critical"; 2416 }; 2417 }; 2418 }; 2419 2420 aoss1-thermal { 2421 polling-delay-passive = <0>; 2422 polling-delay = <0>; 2423 2424 thermal-sensors = <&tsens1 0>; 2425 2426 trips { 2427 aoss1_alert0: trip-point0 { 2428 temperature = <90000>; 2429 hysteresis = <2000>; 2430 type = "hot"; 2431 }; 2432 2433 aoss1_crit: aoss1-crit { 2434 temperature = <110000>; 2435 hysteresis = <0>; 2436 type = "critical"; 2437 }; 2438 }; 2439 }; 2440 2441 cpuss0-thermal { 2442 polling-delay-passive = <0>; 2443 polling-delay = <0>; 2444 2445 thermal-sensors = <&tsens0 5>; 2446 2447 trips { 2448 cpuss0_alert0: trip-point0 { 2449 temperature = <90000>; 2450 hysteresis = <2000>; 2451 type = "hot"; 2452 }; 2453 cpuss0_crit: cluster0-crit { 2454 temperature = <110000>; 2455 hysteresis = <0>; 2456 type = "critical"; 2457 }; 2458 }; 2459 }; 2460 2461 cpuss1-thermal { 2462 polling-delay-passive = <0>; 2463 polling-delay = <0>; 2464 2465 thermal-sensors = <&tsens0 6>; 2466 2467 trips { 2468 cpuss1_alert0: trip-point0 { 2469 temperature = <90000>; 2470 hysteresis = <2000>; 2471 type = "hot"; 2472 }; 2473 cpuss1_crit: cluster0-crit { 2474 temperature = <110000>; 2475 hysteresis = <0>; 2476 type = "critical"; 2477 }; 2478 }; 2479 }; 2480 2481 gpuss0-thermal { 2482 polling-delay-passive = <0>; 2483 polling-delay = <0>; 2484 2485 thermal-sensors = <&tsens1 1>; 2486 2487 trips { 2488 gpuss0_alert0: trip-point0 { 2489 temperature = <90000>; 2490 hysteresis = <2000>; 2491 type = "hot"; 2492 }; 2493 2494 gpuss0_crit: gpuss0-crit { 2495 temperature = <110000>; 2496 hysteresis = <0>; 2497 type = "critical"; 2498 }; 2499 }; 2500 }; 2501 2502 gpuss1-thermal { 2503 polling-delay-passive = <0>; 2504 polling-delay = <0>; 2505 2506 thermal-sensors = <&tsens1 2>; 2507 2508 trips { 2509 gpuss1_alert0: trip-point0 { 2510 temperature = <90000>; 2511 hysteresis = <2000>; 2512 type = "hot"; 2513 }; 2514 2515 gpuss1_crit: gpuss1-crit { 2516 temperature = <110000>; 2517 hysteresis = <0>; 2518 type = "critical"; 2519 }; 2520 }; 2521 }; 2522 2523 nspss0-thermal { 2524 polling-delay-passive = <0>; 2525 polling-delay = <0>; 2526 2527 thermal-sensors = <&tsens1 3>; 2528 2529 trips { 2530 nspss0_alert0: trip-point0 { 2531 temperature = <90000>; 2532 hysteresis = <2000>; 2533 type = "hot"; 2534 }; 2535 2536 nspss0_crit: nspss0-crit { 2537 temperature = <110000>; 2538 hysteresis = <0>; 2539 type = "critical"; 2540 }; 2541 }; 2542 }; 2543 2544 nspss1-thermal { 2545 polling-delay-passive = <0>; 2546 polling-delay = <0>; 2547 2548 thermal-sensors = <&tsens1 4>; 2549 2550 trips { 2551 nspss1_alert0: trip-point0 { 2552 temperature = <90000>; 2553 hysteresis = <2000>; 2554 type = "hot"; 2555 }; 2556 2557 nspss1_crit: nspss1-crit { 2558 temperature = <110000>; 2559 hysteresis = <0>; 2560 type = "critical"; 2561 }; 2562 }; 2563 }; 2564 2565 video-thermal { 2566 polling-delay-passive = <0>; 2567 polling-delay = <0>; 2568 2569 thermal-sensors = <&tsens1 5>; 2570 2571 trips { 2572 video_alert0: trip-point0 { 2573 temperature = <90000>; 2574 hysteresis = <2000>; 2575 type = "hot"; 2576 }; 2577 2578 video_crit: video-crit { 2579 temperature = <110000>; 2580 hysteresis = <0>; 2581 type = "critical"; 2582 }; 2583 }; 2584 }; 2585 2586 ddr-thermal { 2587 polling-delay-passive = <0>; 2588 polling-delay = <0>; 2589 2590 thermal-sensors = <&tsens1 6>; 2591 2592 trips { 2593 ddr_alert0: trip-point0 { 2594 temperature = <90000>; 2595 hysteresis = <2000>; 2596 type = "hot"; 2597 }; 2598 2599 ddr_crit: ddr-crit { 2600 temperature = <110000>; 2601 hysteresis = <0>; 2602 type = "critical"; 2603 }; 2604 }; 2605 }; 2606 2607 mdmss0-thermal { 2608 polling-delay-passive = <0>; 2609 polling-delay = <0>; 2610 2611 thermal-sensors = <&tsens1 7>; 2612 2613 trips { 2614 mdmss0_alert0: trip-point0 { 2615 temperature = <90000>; 2616 hysteresis = <2000>; 2617 type = "hot"; 2618 }; 2619 2620 mdmss0_crit: mdmss0-crit { 2621 temperature = <110000>; 2622 hysteresis = <0>; 2623 type = "critical"; 2624 }; 2625 }; 2626 }; 2627 2628 mdmss1-thermal { 2629 polling-delay-passive = <0>; 2630 polling-delay = <0>; 2631 2632 thermal-sensors = <&tsens1 8>; 2633 2634 trips { 2635 mdmss1_alert0: trip-point0 { 2636 temperature = <90000>; 2637 hysteresis = <2000>; 2638 type = "hot"; 2639 }; 2640 2641 mdmss1_crit: mdmss1-crit { 2642 temperature = <110000>; 2643 hysteresis = <0>; 2644 type = "critical"; 2645 }; 2646 }; 2647 }; 2648 2649 mdmss2-thermal { 2650 polling-delay-passive = <0>; 2651 polling-delay = <0>; 2652 2653 thermal-sensors = <&tsens1 9>; 2654 2655 trips { 2656 mdmss2_alert0: trip-point0 { 2657 temperature = <90000>; 2658 hysteresis = <2000>; 2659 type = "hot"; 2660 }; 2661 2662 mdmss2_crit: mdmss2-crit { 2663 temperature = <110000>; 2664 hysteresis = <0>; 2665 type = "critical"; 2666 }; 2667 }; 2668 }; 2669 2670 mdmss3-thermal { 2671 polling-delay-passive = <0>; 2672 polling-delay = <0>; 2673 2674 thermal-sensors = <&tsens1 10>; 2675 2676 trips { 2677 mdmss3_alert0: trip-point0 { 2678 temperature = <90000>; 2679 hysteresis = <2000>; 2680 type = "hot"; 2681 }; 2682 2683 mdmss3_crit: mdmss3-crit { 2684 temperature = <110000>; 2685 hysteresis = <0>; 2686 type = "critical"; 2687 }; 2688 }; 2689 }; 2690 2691 camera0-thermal { 2692 polling-delay-passive = <0>; 2693 polling-delay = <0>; 2694 2695 thermal-sensors = <&tsens1 11>; 2696 2697 trips { 2698 camera0_alert0: trip-point0 { 2699 temperature = <90000>; 2700 hysteresis = <2000>; 2701 type = "hot"; 2702 }; 2703 2704 camera0_crit: camera0-crit { 2705 temperature = <110000>; 2706 hysteresis = <0>; 2707 type = "critical"; 2708 }; 2709 }; 2710 }; 2711 }; 2712 2713 timer { 2714 compatible = "arm,armv8-timer"; 2715 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2716 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2717 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2718 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2719 }; 2720}; 2721