1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,camcc-sdm845.h> 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gcc-sdm845.h> 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12#include <dt-bindings/clock/qcom,lpass-sdm845.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sdm845.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sdm845.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/phy/phy-qcom-qusb2.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/reset/qcom,sdm845-aoss.h> 21#include <dt-bindings/reset/qcom,sdm845-pdc.h> 22#include <dt-bindings/soc/qcom,apr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/clock/qcom,gcc-sdm845.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 aliases { 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 i2c8 = &i2c8; 43 i2c9 = &i2c9; 44 i2c10 = &i2c10; 45 i2c11 = &i2c11; 46 i2c12 = &i2c12; 47 i2c13 = &i2c13; 48 i2c14 = &i2c14; 49 i2c15 = &i2c15; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &spi2; 53 spi3 = &spi3; 54 spi4 = &spi4; 55 spi5 = &spi5; 56 spi6 = &spi6; 57 spi7 = &spi7; 58 spi8 = &spi8; 59 spi9 = &spi9; 60 spi10 = &spi10; 61 spi11 = &spi11; 62 spi12 = &spi12; 63 spi13 = &spi13; 64 spi14 = &spi14; 65 spi15 = &spi15; 66 }; 67 68 chosen { }; 69 70 memory@80000000 { 71 device_type = "memory"; 72 /* We expect the bootloader to fill in the size */ 73 reg = <0 0x80000000 0 0>; 74 }; 75 76 reserved-memory { 77 #address-cells = <2>; 78 #size-cells = <2>; 79 ranges; 80 81 hyp_mem: memory@85700000 { 82 reg = <0 0x85700000 0 0x600000>; 83 no-map; 84 }; 85 86 xbl_mem: memory@85e00000 { 87 reg = <0 0x85e00000 0 0x100000>; 88 no-map; 89 }; 90 91 aop_mem: memory@85fc0000 { 92 reg = <0 0x85fc0000 0 0x20000>; 93 no-map; 94 }; 95 96 aop_cmd_db_mem: memory@85fe0000 { 97 compatible = "qcom,cmd-db"; 98 reg = <0x0 0x85fe0000 0 0x20000>; 99 no-map; 100 }; 101 102 smem_mem: memory@86000000 { 103 reg = <0x0 0x86000000 0 0x200000>; 104 no-map; 105 }; 106 107 tz_mem: memory@86200000 { 108 reg = <0 0x86200000 0 0x2d00000>; 109 no-map; 110 }; 111 112 rmtfs_mem: memory@88f00000 { 113 compatible = "qcom,rmtfs-mem"; 114 reg = <0 0x88f00000 0 0x200000>; 115 no-map; 116 117 qcom,client-id = <1>; 118 qcom,vmid = <15>; 119 }; 120 121 qseecom_mem: memory@8ab00000 { 122 reg = <0 0x8ab00000 0 0x1400000>; 123 no-map; 124 }; 125 126 camera_mem: memory@8bf00000 { 127 reg = <0 0x8bf00000 0 0x500000>; 128 no-map; 129 }; 130 131 ipa_fw_mem: memory@8c400000 { 132 reg = <0 0x8c400000 0 0x10000>; 133 no-map; 134 }; 135 136 ipa_gsi_mem: memory@8c410000 { 137 reg = <0 0x8c410000 0 0x5000>; 138 no-map; 139 }; 140 141 gpu_mem: memory@8c415000 { 142 reg = <0 0x8c415000 0 0x2000>; 143 no-map; 144 }; 145 146 adsp_mem: memory@8c500000 { 147 reg = <0 0x8c500000 0 0x1a00000>; 148 no-map; 149 }; 150 151 wlan_msa_mem: memory@8df00000 { 152 reg = <0 0x8df00000 0 0x100000>; 153 no-map; 154 }; 155 156 mpss_region: memory@8e000000 { 157 reg = <0 0x8e000000 0 0x7800000>; 158 no-map; 159 }; 160 161 venus_mem: memory@95800000 { 162 reg = <0 0x95800000 0 0x500000>; 163 no-map; 164 }; 165 166 cdsp_mem: memory@95d00000 { 167 reg = <0 0x95d00000 0 0x800000>; 168 no-map; 169 }; 170 171 mba_region: memory@96500000 { 172 reg = <0 0x96500000 0 0x200000>; 173 no-map; 174 }; 175 176 slpi_mem: memory@96700000 { 177 reg = <0 0x96700000 0 0x1400000>; 178 no-map; 179 }; 180 181 spss_mem: memory@97b00000 { 182 reg = <0 0x97b00000 0 0x100000>; 183 no-map; 184 }; 185 }; 186 187 cpus { 188 #address-cells = <2>; 189 #size-cells = <0>; 190 191 CPU0: cpu@0 { 192 device_type = "cpu"; 193 compatible = "qcom,kryo385"; 194 reg = <0x0 0x0>; 195 enable-method = "psci"; 196 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 197 &LITTLE_CPU_SLEEP_1 198 &CLUSTER_SLEEP_0>; 199 capacity-dmips-mhz = <611>; 200 dynamic-power-coefficient = <154>; 201 qcom,freq-domain = <&cpufreq_hw 0>; 202 operating-points-v2 = <&cpu0_opp_table>; 203 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 205 #cooling-cells = <2>; 206 next-level-cache = <&L2_0>; 207 L2_0: l2-cache { 208 compatible = "cache"; 209 next-level-cache = <&L3_0>; 210 L3_0: l3-cache { 211 compatible = "cache"; 212 }; 213 }; 214 }; 215 216 CPU1: cpu@100 { 217 device_type = "cpu"; 218 compatible = "qcom,kryo385"; 219 reg = <0x0 0x100>; 220 enable-method = "psci"; 221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 222 &LITTLE_CPU_SLEEP_1 223 &CLUSTER_SLEEP_0>; 224 capacity-dmips-mhz = <611>; 225 dynamic-power-coefficient = <154>; 226 qcom,freq-domain = <&cpufreq_hw 0>; 227 operating-points-v2 = <&cpu0_opp_table>; 228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 230 #cooling-cells = <2>; 231 next-level-cache = <&L2_100>; 232 L2_100: l2-cache { 233 compatible = "cache"; 234 next-level-cache = <&L3_0>; 235 }; 236 }; 237 238 CPU2: cpu@200 { 239 device_type = "cpu"; 240 compatible = "qcom,kryo385"; 241 reg = <0x0 0x200>; 242 enable-method = "psci"; 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 244 &LITTLE_CPU_SLEEP_1 245 &CLUSTER_SLEEP_0>; 246 capacity-dmips-mhz = <611>; 247 dynamic-power-coefficient = <154>; 248 qcom,freq-domain = <&cpufreq_hw 0>; 249 operating-points-v2 = <&cpu0_opp_table>; 250 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 251 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 252 #cooling-cells = <2>; 253 next-level-cache = <&L2_200>; 254 L2_200: l2-cache { 255 compatible = "cache"; 256 next-level-cache = <&L3_0>; 257 }; 258 }; 259 260 CPU3: cpu@300 { 261 device_type = "cpu"; 262 compatible = "qcom,kryo385"; 263 reg = <0x0 0x300>; 264 enable-method = "psci"; 265 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 266 &LITTLE_CPU_SLEEP_1 267 &CLUSTER_SLEEP_0>; 268 capacity-dmips-mhz = <611>; 269 dynamic-power-coefficient = <154>; 270 qcom,freq-domain = <&cpufreq_hw 0>; 271 operating-points-v2 = <&cpu0_opp_table>; 272 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 273 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 274 #cooling-cells = <2>; 275 next-level-cache = <&L2_300>; 276 L2_300: l2-cache { 277 compatible = "cache"; 278 next-level-cache = <&L3_0>; 279 }; 280 }; 281 282 CPU4: cpu@400 { 283 device_type = "cpu"; 284 compatible = "qcom,kryo385"; 285 reg = <0x0 0x400>; 286 enable-method = "psci"; 287 capacity-dmips-mhz = <1024>; 288 cpu-idle-states = <&BIG_CPU_SLEEP_0 289 &BIG_CPU_SLEEP_1 290 &CLUSTER_SLEEP_0>; 291 dynamic-power-coefficient = <442>; 292 qcom,freq-domain = <&cpufreq_hw 1>; 293 operating-points-v2 = <&cpu4_opp_table>; 294 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 295 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 296 #cooling-cells = <2>; 297 next-level-cache = <&L2_400>; 298 L2_400: l2-cache { 299 compatible = "cache"; 300 next-level-cache = <&L3_0>; 301 }; 302 }; 303 304 CPU5: cpu@500 { 305 device_type = "cpu"; 306 compatible = "qcom,kryo385"; 307 reg = <0x0 0x500>; 308 enable-method = "psci"; 309 capacity-dmips-mhz = <1024>; 310 cpu-idle-states = <&BIG_CPU_SLEEP_0 311 &BIG_CPU_SLEEP_1 312 &CLUSTER_SLEEP_0>; 313 dynamic-power-coefficient = <442>; 314 qcom,freq-domain = <&cpufreq_hw 1>; 315 operating-points-v2 = <&cpu4_opp_table>; 316 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 317 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 318 #cooling-cells = <2>; 319 next-level-cache = <&L2_500>; 320 L2_500: l2-cache { 321 compatible = "cache"; 322 next-level-cache = <&L3_0>; 323 }; 324 }; 325 326 CPU6: cpu@600 { 327 device_type = "cpu"; 328 compatible = "qcom,kryo385"; 329 reg = <0x0 0x600>; 330 enable-method = "psci"; 331 capacity-dmips-mhz = <1024>; 332 cpu-idle-states = <&BIG_CPU_SLEEP_0 333 &BIG_CPU_SLEEP_1 334 &CLUSTER_SLEEP_0>; 335 dynamic-power-coefficient = <442>; 336 qcom,freq-domain = <&cpufreq_hw 1>; 337 operating-points-v2 = <&cpu4_opp_table>; 338 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 339 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 340 #cooling-cells = <2>; 341 next-level-cache = <&L2_600>; 342 L2_600: l2-cache { 343 compatible = "cache"; 344 next-level-cache = <&L3_0>; 345 }; 346 }; 347 348 CPU7: cpu@700 { 349 device_type = "cpu"; 350 compatible = "qcom,kryo385"; 351 reg = <0x0 0x700>; 352 enable-method = "psci"; 353 capacity-dmips-mhz = <1024>; 354 cpu-idle-states = <&BIG_CPU_SLEEP_0 355 &BIG_CPU_SLEEP_1 356 &CLUSTER_SLEEP_0>; 357 dynamic-power-coefficient = <442>; 358 qcom,freq-domain = <&cpufreq_hw 1>; 359 operating-points-v2 = <&cpu4_opp_table>; 360 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, 361 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 362 #cooling-cells = <2>; 363 next-level-cache = <&L2_700>; 364 L2_700: l2-cache { 365 compatible = "cache"; 366 next-level-cache = <&L3_0>; 367 }; 368 }; 369 370 cpu-map { 371 cluster0 { 372 core0 { 373 cpu = <&CPU0>; 374 }; 375 376 core1 { 377 cpu = <&CPU1>; 378 }; 379 380 core2 { 381 cpu = <&CPU2>; 382 }; 383 384 core3 { 385 cpu = <&CPU3>; 386 }; 387 388 core4 { 389 cpu = <&CPU4>; 390 }; 391 392 core5 { 393 cpu = <&CPU5>; 394 }; 395 396 core6 { 397 cpu = <&CPU6>; 398 }; 399 400 core7 { 401 cpu = <&CPU7>; 402 }; 403 }; 404 }; 405 406 idle-states { 407 entry-method = "psci"; 408 409 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "little-power-down"; 412 arm,psci-suspend-param = <0x40000003>; 413 entry-latency-us = <350>; 414 exit-latency-us = <461>; 415 min-residency-us = <1890>; 416 local-timer-stop; 417 }; 418 419 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 420 compatible = "arm,idle-state"; 421 idle-state-name = "little-rail-power-down"; 422 arm,psci-suspend-param = <0x40000004>; 423 entry-latency-us = <360>; 424 exit-latency-us = <531>; 425 min-residency-us = <3934>; 426 local-timer-stop; 427 }; 428 429 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 430 compatible = "arm,idle-state"; 431 idle-state-name = "big-power-down"; 432 arm,psci-suspend-param = <0x40000003>; 433 entry-latency-us = <264>; 434 exit-latency-us = <621>; 435 min-residency-us = <952>; 436 local-timer-stop; 437 }; 438 439 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 440 compatible = "arm,idle-state"; 441 idle-state-name = "big-rail-power-down"; 442 arm,psci-suspend-param = <0x40000004>; 443 entry-latency-us = <702>; 444 exit-latency-us = <1061>; 445 min-residency-us = <4488>; 446 local-timer-stop; 447 }; 448 449 CLUSTER_SLEEP_0: cluster-sleep-0 { 450 compatible = "arm,idle-state"; 451 idle-state-name = "cluster-power-down"; 452 arm,psci-suspend-param = <0x400000F4>; 453 entry-latency-us = <3263>; 454 exit-latency-us = <6562>; 455 min-residency-us = <9987>; 456 local-timer-stop; 457 }; 458 }; 459 }; 460 461 cpu0_opp_table: cpu0_opp_table { 462 compatible = "operating-points-v2"; 463 opp-shared; 464 465 cpu0_opp1: opp-300000000 { 466 opp-hz = /bits/ 64 <300000000>; 467 opp-peak-kBps = <800000 4800000>; 468 }; 469 470 cpu0_opp2: opp-403200000 { 471 opp-hz = /bits/ 64 <403200000>; 472 opp-peak-kBps = <800000 4800000>; 473 }; 474 475 cpu0_opp3: opp-480000000 { 476 opp-hz = /bits/ 64 <480000000>; 477 opp-peak-kBps = <800000 6451200>; 478 }; 479 480 cpu0_opp4: opp-576000000 { 481 opp-hz = /bits/ 64 <576000000>; 482 opp-peak-kBps = <800000 6451200>; 483 }; 484 485 cpu0_opp5: opp-652800000 { 486 opp-hz = /bits/ 64 <652800000>; 487 opp-peak-kBps = <800000 7680000>; 488 }; 489 490 cpu0_opp6: opp-748800000 { 491 opp-hz = /bits/ 64 <748800000>; 492 opp-peak-kBps = <1804000 9216000>; 493 }; 494 495 cpu0_opp7: opp-825600000 { 496 opp-hz = /bits/ 64 <825600000>; 497 opp-peak-kBps = <1804000 9216000>; 498 }; 499 500 cpu0_opp8: opp-902400000 { 501 opp-hz = /bits/ 64 <902400000>; 502 opp-peak-kBps = <1804000 10444800>; 503 }; 504 505 cpu0_opp9: opp-979200000 { 506 opp-hz = /bits/ 64 <979200000>; 507 opp-peak-kBps = <1804000 11980800>; 508 }; 509 510 cpu0_opp10: opp-1056000000 { 511 opp-hz = /bits/ 64 <1056000000>; 512 opp-peak-kBps = <1804000 11980800>; 513 }; 514 515 cpu0_opp11: opp-1132800000 { 516 opp-hz = /bits/ 64 <1132800000>; 517 opp-peak-kBps = <2188000 13516800>; 518 }; 519 520 cpu0_opp12: opp-1228800000 { 521 opp-hz = /bits/ 64 <1228800000>; 522 opp-peak-kBps = <2188000 15052800>; 523 }; 524 525 cpu0_opp13: opp-1324800000 { 526 opp-hz = /bits/ 64 <1324800000>; 527 opp-peak-kBps = <2188000 16588800>; 528 }; 529 530 cpu0_opp14: opp-1420800000 { 531 opp-hz = /bits/ 64 <1420800000>; 532 opp-peak-kBps = <3072000 18124800>; 533 }; 534 535 cpu0_opp15: opp-1516800000 { 536 opp-hz = /bits/ 64 <1516800000>; 537 opp-peak-kBps = <3072000 19353600>; 538 }; 539 540 cpu0_opp16: opp-1612800000 { 541 opp-hz = /bits/ 64 <1612800000>; 542 opp-peak-kBps = <4068000 19353600>; 543 }; 544 545 cpu0_opp17: opp-1689600000 { 546 opp-hz = /bits/ 64 <1689600000>; 547 opp-peak-kBps = <4068000 20889600>; 548 }; 549 550 cpu0_opp18: opp-1766400000 { 551 opp-hz = /bits/ 64 <1766400000>; 552 opp-peak-kBps = <4068000 22425600>; 553 }; 554 }; 555 556 cpu4_opp_table: cpu4_opp_table { 557 compatible = "operating-points-v2"; 558 opp-shared; 559 560 cpu4_opp1: opp-300000000 { 561 opp-hz = /bits/ 64 <300000000>; 562 opp-peak-kBps = <800000 4800000>; 563 }; 564 565 cpu4_opp2: opp-403200000 { 566 opp-hz = /bits/ 64 <403200000>; 567 opp-peak-kBps = <800000 4800000>; 568 }; 569 570 cpu4_opp3: opp-480000000 { 571 opp-hz = /bits/ 64 <480000000>; 572 opp-peak-kBps = <1804000 4800000>; 573 }; 574 575 cpu4_opp4: opp-576000000 { 576 opp-hz = /bits/ 64 <576000000>; 577 opp-peak-kBps = <1804000 4800000>; 578 }; 579 580 cpu4_opp5: opp-652800000 { 581 opp-hz = /bits/ 64 <652800000>; 582 opp-peak-kBps = <1804000 4800000>; 583 }; 584 585 cpu4_opp6: opp-748800000 { 586 opp-hz = /bits/ 64 <748800000>; 587 opp-peak-kBps = <1804000 4800000>; 588 }; 589 590 cpu4_opp7: opp-825600000 { 591 opp-hz = /bits/ 64 <825600000>; 592 opp-peak-kBps = <2188000 9216000>; 593 }; 594 595 cpu4_opp8: opp-902400000 { 596 opp-hz = /bits/ 64 <902400000>; 597 opp-peak-kBps = <2188000 9216000>; 598 }; 599 600 cpu4_opp9: opp-979200000 { 601 opp-hz = /bits/ 64 <979200000>; 602 opp-peak-kBps = <2188000 9216000>; 603 }; 604 605 cpu4_opp10: opp-1056000000 { 606 opp-hz = /bits/ 64 <1056000000>; 607 opp-peak-kBps = <3072000 9216000>; 608 }; 609 610 cpu4_opp11: opp-1132800000 { 611 opp-hz = /bits/ 64 <1132800000>; 612 opp-peak-kBps = <3072000 11980800>; 613 }; 614 615 cpu4_opp12: opp-1209600000 { 616 opp-hz = /bits/ 64 <1209600000>; 617 opp-peak-kBps = <4068000 11980800>; 618 }; 619 620 cpu4_opp13: opp-1286400000 { 621 opp-hz = /bits/ 64 <1286400000>; 622 opp-peak-kBps = <4068000 11980800>; 623 }; 624 625 cpu4_opp14: opp-1363200000 { 626 opp-hz = /bits/ 64 <1363200000>; 627 opp-peak-kBps = <4068000 15052800>; 628 }; 629 630 cpu4_opp15: opp-1459200000 { 631 opp-hz = /bits/ 64 <1459200000>; 632 opp-peak-kBps = <4068000 15052800>; 633 }; 634 635 cpu4_opp16: opp-1536000000 { 636 opp-hz = /bits/ 64 <1536000000>; 637 opp-peak-kBps = <5412000 15052800>; 638 }; 639 640 cpu4_opp17: opp-1612800000 { 641 opp-hz = /bits/ 64 <1612800000>; 642 opp-peak-kBps = <5412000 15052800>; 643 }; 644 645 cpu4_opp18: opp-1689600000 { 646 opp-hz = /bits/ 64 <1689600000>; 647 opp-peak-kBps = <5412000 19353600>; 648 }; 649 650 cpu4_opp19: opp-1766400000 { 651 opp-hz = /bits/ 64 <1766400000>; 652 opp-peak-kBps = <6220000 19353600>; 653 }; 654 655 cpu4_opp20: opp-1843200000 { 656 opp-hz = /bits/ 64 <1843200000>; 657 opp-peak-kBps = <6220000 19353600>; 658 }; 659 660 cpu4_opp21: opp-1920000000 { 661 opp-hz = /bits/ 64 <1920000000>; 662 opp-peak-kBps = <7216000 19353600>; 663 }; 664 665 cpu4_opp22: opp-1996800000 { 666 opp-hz = /bits/ 64 <1996800000>; 667 opp-peak-kBps = <7216000 20889600>; 668 }; 669 670 cpu4_opp23: opp-2092800000 { 671 opp-hz = /bits/ 64 <2092800000>; 672 opp-peak-kBps = <7216000 20889600>; 673 }; 674 675 cpu4_opp24: opp-2169600000 { 676 opp-hz = /bits/ 64 <2169600000>; 677 opp-peak-kBps = <7216000 20889600>; 678 }; 679 680 cpu4_opp25: opp-2246400000 { 681 opp-hz = /bits/ 64 <2246400000>; 682 opp-peak-kBps = <7216000 20889600>; 683 }; 684 685 cpu4_opp26: opp-2323200000 { 686 opp-hz = /bits/ 64 <2323200000>; 687 opp-peak-kBps = <7216000 20889600>; 688 }; 689 690 cpu4_opp27: opp-2400000000 { 691 opp-hz = /bits/ 64 <2400000000>; 692 opp-peak-kBps = <7216000 22425600>; 693 }; 694 695 cpu4_opp28: opp-2476800000 { 696 opp-hz = /bits/ 64 <2476800000>; 697 opp-peak-kBps = <7216000 22425600>; 698 }; 699 700 cpu4_opp29: opp-2553600000 { 701 opp-hz = /bits/ 64 <2553600000>; 702 opp-peak-kBps = <7216000 22425600>; 703 }; 704 705 cpu4_opp30: opp-2649600000 { 706 opp-hz = /bits/ 64 <2649600000>; 707 opp-peak-kBps = <7216000 22425600>; 708 }; 709 710 cpu4_opp31: opp-2745600000 { 711 opp-hz = /bits/ 64 <2745600000>; 712 opp-peak-kBps = <7216000 25497600>; 713 }; 714 715 cpu4_opp32: opp-2803200000 { 716 opp-hz = /bits/ 64 <2803200000>; 717 opp-peak-kBps = <7216000 25497600>; 718 }; 719 }; 720 721 pmu { 722 compatible = "arm,armv8-pmuv3"; 723 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 724 }; 725 726 timer { 727 compatible = "arm,armv8-timer"; 728 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 729 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 730 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 731 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 732 }; 733 734 clocks { 735 xo_board: xo-board { 736 compatible = "fixed-clock"; 737 #clock-cells = <0>; 738 clock-frequency = <38400000>; 739 clock-output-names = "xo_board"; 740 }; 741 742 sleep_clk: sleep-clk { 743 compatible = "fixed-clock"; 744 #clock-cells = <0>; 745 clock-frequency = <32764>; 746 }; 747 }; 748 749 firmware { 750 scm { 751 compatible = "qcom,scm-sdm845", "qcom,scm"; 752 }; 753 }; 754 755 adsp_pas: remoteproc-adsp { 756 compatible = "qcom,sdm845-adsp-pas"; 757 758 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 759 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 760 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 761 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 762 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 763 interrupt-names = "wdog", "fatal", "ready", 764 "handover", "stop-ack"; 765 766 clocks = <&rpmhcc RPMH_CXO_CLK>; 767 clock-names = "xo"; 768 769 memory-region = <&adsp_mem>; 770 771 qcom,smem-states = <&adsp_smp2p_out 0>; 772 qcom,smem-state-names = "stop"; 773 774 status = "disabled"; 775 776 glink-edge { 777 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 778 label = "lpass"; 779 qcom,remote-pid = <2>; 780 mboxes = <&apss_shared 8>; 781 782 apr { 783 compatible = "qcom,apr-v2"; 784 qcom,glink-channels = "apr_audio_svc"; 785 qcom,apr-domain = <APR_DOMAIN_ADSP>; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 qcom,intents = <512 20>; 789 790 apr-service@3 { 791 reg = <APR_SVC_ADSP_CORE>; 792 compatible = "qcom,q6core"; 793 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 794 }; 795 796 q6afe: apr-service@4 { 797 compatible = "qcom,q6afe"; 798 reg = <APR_SVC_AFE>; 799 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 800 q6afedai: dais { 801 compatible = "qcom,q6afe-dais"; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 #sound-dai-cells = <1>; 805 }; 806 }; 807 808 q6asm: apr-service@7 { 809 compatible = "qcom,q6asm"; 810 reg = <APR_SVC_ASM>; 811 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 812 q6asmdai: dais { 813 compatible = "qcom,q6asm-dais"; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 #sound-dai-cells = <1>; 817 iommus = <&apps_smmu 0x1821 0x0>; 818 }; 819 }; 820 821 q6adm: apr-service@8 { 822 compatible = "qcom,q6adm"; 823 reg = <APR_SVC_ADM>; 824 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 825 q6routing: routing { 826 compatible = "qcom,q6adm-routing"; 827 #sound-dai-cells = <0>; 828 }; 829 }; 830 }; 831 832 fastrpc { 833 compatible = "qcom,fastrpc"; 834 qcom,glink-channels = "fastrpcglink-apps-dsp"; 835 label = "adsp"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 839 compute-cb@3 { 840 compatible = "qcom,fastrpc-compute-cb"; 841 reg = <3>; 842 iommus = <&apps_smmu 0x1823 0x0>; 843 }; 844 845 compute-cb@4 { 846 compatible = "qcom,fastrpc-compute-cb"; 847 reg = <4>; 848 iommus = <&apps_smmu 0x1824 0x0>; 849 }; 850 }; 851 }; 852 }; 853 854 cdsp_pas: remoteproc-cdsp { 855 compatible = "qcom,sdm845-cdsp-pas"; 856 857 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 858 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 859 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 860 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 861 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 862 interrupt-names = "wdog", "fatal", "ready", 863 "handover", "stop-ack"; 864 865 clocks = <&rpmhcc RPMH_CXO_CLK>; 866 clock-names = "xo"; 867 868 memory-region = <&cdsp_mem>; 869 870 qcom,smem-states = <&cdsp_smp2p_out 0>; 871 qcom,smem-state-names = "stop"; 872 873 status = "disabled"; 874 875 glink-edge { 876 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 877 label = "turing"; 878 qcom,remote-pid = <5>; 879 mboxes = <&apss_shared 4>; 880 fastrpc { 881 compatible = "qcom,fastrpc"; 882 qcom,glink-channels = "fastrpcglink-apps-dsp"; 883 label = "cdsp"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 887 compute-cb@1 { 888 compatible = "qcom,fastrpc-compute-cb"; 889 reg = <1>; 890 iommus = <&apps_smmu 0x1401 0x30>; 891 }; 892 893 compute-cb@2 { 894 compatible = "qcom,fastrpc-compute-cb"; 895 reg = <2>; 896 iommus = <&apps_smmu 0x1402 0x30>; 897 }; 898 899 compute-cb@3 { 900 compatible = "qcom,fastrpc-compute-cb"; 901 reg = <3>; 902 iommus = <&apps_smmu 0x1403 0x30>; 903 }; 904 905 compute-cb@4 { 906 compatible = "qcom,fastrpc-compute-cb"; 907 reg = <4>; 908 iommus = <&apps_smmu 0x1404 0x30>; 909 }; 910 911 compute-cb@5 { 912 compatible = "qcom,fastrpc-compute-cb"; 913 reg = <5>; 914 iommus = <&apps_smmu 0x1405 0x30>; 915 }; 916 917 compute-cb@6 { 918 compatible = "qcom,fastrpc-compute-cb"; 919 reg = <6>; 920 iommus = <&apps_smmu 0x1406 0x30>; 921 }; 922 923 compute-cb@7 { 924 compatible = "qcom,fastrpc-compute-cb"; 925 reg = <7>; 926 iommus = <&apps_smmu 0x1407 0x30>; 927 }; 928 929 compute-cb@8 { 930 compatible = "qcom,fastrpc-compute-cb"; 931 reg = <8>; 932 iommus = <&apps_smmu 0x1408 0x30>; 933 }; 934 }; 935 }; 936 }; 937 938 tcsr_mutex: hwlock { 939 compatible = "qcom,tcsr-mutex"; 940 syscon = <&tcsr_mutex_regs 0 0x1000>; 941 #hwlock-cells = <1>; 942 }; 943 944 smem { 945 compatible = "qcom,smem"; 946 memory-region = <&smem_mem>; 947 hwlocks = <&tcsr_mutex 3>; 948 }; 949 950 smp2p-cdsp { 951 compatible = "qcom,smp2p"; 952 qcom,smem = <94>, <432>; 953 954 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 955 956 mboxes = <&apss_shared 6>; 957 958 qcom,local-pid = <0>; 959 qcom,remote-pid = <5>; 960 961 cdsp_smp2p_out: master-kernel { 962 qcom,entry-name = "master-kernel"; 963 #qcom,smem-state-cells = <1>; 964 }; 965 966 cdsp_smp2p_in: slave-kernel { 967 qcom,entry-name = "slave-kernel"; 968 969 interrupt-controller; 970 #interrupt-cells = <2>; 971 }; 972 }; 973 974 smp2p-lpass { 975 compatible = "qcom,smp2p"; 976 qcom,smem = <443>, <429>; 977 978 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 979 980 mboxes = <&apss_shared 10>; 981 982 qcom,local-pid = <0>; 983 qcom,remote-pid = <2>; 984 985 adsp_smp2p_out: master-kernel { 986 qcom,entry-name = "master-kernel"; 987 #qcom,smem-state-cells = <1>; 988 }; 989 990 adsp_smp2p_in: slave-kernel { 991 qcom,entry-name = "slave-kernel"; 992 993 interrupt-controller; 994 #interrupt-cells = <2>; 995 }; 996 }; 997 998 smp2p-mpss { 999 compatible = "qcom,smp2p"; 1000 qcom,smem = <435>, <428>; 1001 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 1002 mboxes = <&apss_shared 14>; 1003 qcom,local-pid = <0>; 1004 qcom,remote-pid = <1>; 1005 1006 modem_smp2p_out: master-kernel { 1007 qcom,entry-name = "master-kernel"; 1008 #qcom,smem-state-cells = <1>; 1009 }; 1010 1011 modem_smp2p_in: slave-kernel { 1012 qcom,entry-name = "slave-kernel"; 1013 interrupt-controller; 1014 #interrupt-cells = <2>; 1015 }; 1016 1017 ipa_smp2p_out: ipa-ap-to-modem { 1018 qcom,entry-name = "ipa"; 1019 #qcom,smem-state-cells = <1>; 1020 }; 1021 1022 ipa_smp2p_in: ipa-modem-to-ap { 1023 qcom,entry-name = "ipa"; 1024 interrupt-controller; 1025 #interrupt-cells = <2>; 1026 }; 1027 }; 1028 1029 smp2p-slpi { 1030 compatible = "qcom,smp2p"; 1031 qcom,smem = <481>, <430>; 1032 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 1033 mboxes = <&apss_shared 26>; 1034 qcom,local-pid = <0>; 1035 qcom,remote-pid = <3>; 1036 1037 slpi_smp2p_out: master-kernel { 1038 qcom,entry-name = "master-kernel"; 1039 #qcom,smem-state-cells = <1>; 1040 }; 1041 1042 slpi_smp2p_in: slave-kernel { 1043 qcom,entry-name = "slave-kernel"; 1044 interrupt-controller; 1045 #interrupt-cells = <2>; 1046 }; 1047 }; 1048 1049 psci { 1050 compatible = "arm,psci-1.0"; 1051 method = "smc"; 1052 }; 1053 1054 soc: soc@0 { 1055 #address-cells = <2>; 1056 #size-cells = <2>; 1057 ranges = <0 0 0 0 0x10 0>; 1058 dma-ranges = <0 0 0 0 0x10 0>; 1059 compatible = "simple-bus"; 1060 1061 gcc: clock-controller@100000 { 1062 compatible = "qcom,gcc-sdm845"; 1063 reg = <0 0x00100000 0 0x1f0000>; 1064 clocks = <&rpmhcc RPMH_CXO_CLK>, 1065 <&rpmhcc RPMH_CXO_CLK_A>, 1066 <&sleep_clk>, 1067 <&pcie0_lane>, 1068 <&pcie1_lane>; 1069 clock-names = "bi_tcxo", 1070 "bi_tcxo_ao", 1071 "sleep_clk", 1072 "pcie_0_pipe_clk", 1073 "pcie_1_pipe_clk"; 1074 #clock-cells = <1>; 1075 #reset-cells = <1>; 1076 #power-domain-cells = <1>; 1077 power-domains = <&rpmhpd SDM845_CX>; 1078 }; 1079 1080 qfprom@784000 { 1081 compatible = "qcom,qfprom"; 1082 reg = <0 0x00784000 0 0x8ff>; 1083 #address-cells = <1>; 1084 #size-cells = <1>; 1085 1086 qusb2p_hstx_trim: hstx-trim-primary@1eb { 1087 reg = <0x1eb 0x1>; 1088 bits = <1 4>; 1089 }; 1090 1091 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 1092 reg = <0x1eb 0x2>; 1093 bits = <6 4>; 1094 }; 1095 }; 1096 1097 rng: rng@793000 { 1098 compatible = "qcom,prng-ee"; 1099 reg = <0 0x00793000 0 0x1000>; 1100 clocks = <&gcc GCC_PRNG_AHB_CLK>; 1101 clock-names = "core"; 1102 }; 1103 1104 qup_opp_table: qup-opp-table { 1105 compatible = "operating-points-v2"; 1106 1107 opp-50000000 { 1108 opp-hz = /bits/ 64 <50000000>; 1109 required-opps = <&rpmhpd_opp_min_svs>; 1110 }; 1111 1112 opp-75000000 { 1113 opp-hz = /bits/ 64 <75000000>; 1114 required-opps = <&rpmhpd_opp_low_svs>; 1115 }; 1116 1117 opp-100000000 { 1118 opp-hz = /bits/ 64 <100000000>; 1119 required-opps = <&rpmhpd_opp_svs>; 1120 }; 1121 1122 opp-128000000 { 1123 opp-hz = /bits/ 64 <128000000>; 1124 required-opps = <&rpmhpd_opp_nom>; 1125 }; 1126 }; 1127 1128 qupv3_id_0: geniqup@8c0000 { 1129 compatible = "qcom,geni-se-qup"; 1130 reg = <0 0x008c0000 0 0x6000>; 1131 clock-names = "m-ahb", "s-ahb"; 1132 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1133 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1134 iommus = <&apps_smmu 0x3 0x0>; 1135 #address-cells = <2>; 1136 #size-cells = <2>; 1137 ranges; 1138 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; 1139 interconnect-names = "qup-core"; 1140 status = "disabled"; 1141 1142 i2c0: i2c@880000 { 1143 compatible = "qcom,geni-i2c"; 1144 reg = <0 0x00880000 0 0x4000>; 1145 clock-names = "se"; 1146 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&qup_i2c0_default>; 1149 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 power-domains = <&rpmhpd SDM845_CX>; 1153 operating-points-v2 = <&qup_opp_table>; 1154 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1155 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1156 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1157 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1158 status = "disabled"; 1159 }; 1160 1161 spi0: spi@880000 { 1162 compatible = "qcom,geni-spi"; 1163 reg = <0 0x00880000 0 0x4000>; 1164 clock-names = "se"; 1165 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&qup_spi0_default>; 1168 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1172 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1173 interconnect-names = "qup-core", "qup-config"; 1174 status = "disabled"; 1175 }; 1176 1177 uart0: serial@880000 { 1178 compatible = "qcom,geni-uart"; 1179 reg = <0 0x00880000 0 0x4000>; 1180 clock-names = "se"; 1181 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1182 pinctrl-names = "default"; 1183 pinctrl-0 = <&qup_uart0_default>; 1184 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1185 power-domains = <&rpmhpd SDM845_CX>; 1186 operating-points-v2 = <&qup_opp_table>; 1187 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1188 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1189 interconnect-names = "qup-core", "qup-config"; 1190 status = "disabled"; 1191 }; 1192 1193 i2c1: i2c@884000 { 1194 compatible = "qcom,geni-i2c"; 1195 reg = <0 0x00884000 0 0x4000>; 1196 clock-names = "se"; 1197 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&qup_i2c1_default>; 1200 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 power-domains = <&rpmhpd SDM845_CX>; 1204 operating-points-v2 = <&qup_opp_table>; 1205 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1206 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1207 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1208 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1209 status = "disabled"; 1210 }; 1211 1212 spi1: spi@884000 { 1213 compatible = "qcom,geni-spi"; 1214 reg = <0 0x00884000 0 0x4000>; 1215 clock-names = "se"; 1216 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1217 pinctrl-names = "default"; 1218 pinctrl-0 = <&qup_spi1_default>; 1219 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1223 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1224 interconnect-names = "qup-core", "qup-config"; 1225 status = "disabled"; 1226 }; 1227 1228 uart1: serial@884000 { 1229 compatible = "qcom,geni-uart"; 1230 reg = <0 0x00884000 0 0x4000>; 1231 clock-names = "se"; 1232 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1233 pinctrl-names = "default"; 1234 pinctrl-0 = <&qup_uart1_default>; 1235 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1236 power-domains = <&rpmhpd SDM845_CX>; 1237 operating-points-v2 = <&qup_opp_table>; 1238 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1239 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1240 interconnect-names = "qup-core", "qup-config"; 1241 status = "disabled"; 1242 }; 1243 1244 i2c2: i2c@888000 { 1245 compatible = "qcom,geni-i2c"; 1246 reg = <0 0x00888000 0 0x4000>; 1247 clock-names = "se"; 1248 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&qup_i2c2_default>; 1251 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 power-domains = <&rpmhpd SDM845_CX>; 1255 operating-points-v2 = <&qup_opp_table>; 1256 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1257 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1258 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1259 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1260 status = "disabled"; 1261 }; 1262 1263 spi2: spi@888000 { 1264 compatible = "qcom,geni-spi"; 1265 reg = <0 0x00888000 0 0x4000>; 1266 clock-names = "se"; 1267 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1268 pinctrl-names = "default"; 1269 pinctrl-0 = <&qup_spi2_default>; 1270 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1274 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1275 interconnect-names = "qup-core", "qup-config"; 1276 status = "disabled"; 1277 }; 1278 1279 uart2: serial@888000 { 1280 compatible = "qcom,geni-uart"; 1281 reg = <0 0x00888000 0 0x4000>; 1282 clock-names = "se"; 1283 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&qup_uart2_default>; 1286 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1287 power-domains = <&rpmhpd SDM845_CX>; 1288 operating-points-v2 = <&qup_opp_table>; 1289 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1290 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1291 interconnect-names = "qup-core", "qup-config"; 1292 status = "disabled"; 1293 }; 1294 1295 i2c3: i2c@88c000 { 1296 compatible = "qcom,geni-i2c"; 1297 reg = <0 0x0088c000 0 0x4000>; 1298 clock-names = "se"; 1299 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1300 pinctrl-names = "default"; 1301 pinctrl-0 = <&qup_i2c3_default>; 1302 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 power-domains = <&rpmhpd SDM845_CX>; 1306 operating-points-v2 = <&qup_opp_table>; 1307 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1308 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1309 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1310 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1311 status = "disabled"; 1312 }; 1313 1314 spi3: spi@88c000 { 1315 compatible = "qcom,geni-spi"; 1316 reg = <0 0x0088c000 0 0x4000>; 1317 clock-names = "se"; 1318 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1319 pinctrl-names = "default"; 1320 pinctrl-0 = <&qup_spi3_default>; 1321 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1325 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1326 interconnect-names = "qup-core", "qup-config"; 1327 status = "disabled"; 1328 }; 1329 1330 uart3: serial@88c000 { 1331 compatible = "qcom,geni-uart"; 1332 reg = <0 0x0088c000 0 0x4000>; 1333 clock-names = "se"; 1334 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1335 pinctrl-names = "default"; 1336 pinctrl-0 = <&qup_uart3_default>; 1337 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1338 power-domains = <&rpmhpd SDM845_CX>; 1339 operating-points-v2 = <&qup_opp_table>; 1340 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1341 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1342 interconnect-names = "qup-core", "qup-config"; 1343 status = "disabled"; 1344 }; 1345 1346 i2c4: i2c@890000 { 1347 compatible = "qcom,geni-i2c"; 1348 reg = <0 0x00890000 0 0x4000>; 1349 clock-names = "se"; 1350 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1351 pinctrl-names = "default"; 1352 pinctrl-0 = <&qup_i2c4_default>; 1353 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 power-domains = <&rpmhpd SDM845_CX>; 1357 operating-points-v2 = <&qup_opp_table>; 1358 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1359 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1360 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1361 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1362 status = "disabled"; 1363 }; 1364 1365 spi4: spi@890000 { 1366 compatible = "qcom,geni-spi"; 1367 reg = <0 0x00890000 0 0x4000>; 1368 clock-names = "se"; 1369 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1370 pinctrl-names = "default"; 1371 pinctrl-0 = <&qup_spi4_default>; 1372 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1376 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1377 interconnect-names = "qup-core", "qup-config"; 1378 status = "disabled"; 1379 }; 1380 1381 uart4: serial@890000 { 1382 compatible = "qcom,geni-uart"; 1383 reg = <0 0x00890000 0 0x4000>; 1384 clock-names = "se"; 1385 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1386 pinctrl-names = "default"; 1387 pinctrl-0 = <&qup_uart4_default>; 1388 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1389 power-domains = <&rpmhpd SDM845_CX>; 1390 operating-points-v2 = <&qup_opp_table>; 1391 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1392 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1393 interconnect-names = "qup-core", "qup-config"; 1394 status = "disabled"; 1395 }; 1396 1397 i2c5: i2c@894000 { 1398 compatible = "qcom,geni-i2c"; 1399 reg = <0 0x00894000 0 0x4000>; 1400 clock-names = "se"; 1401 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1402 pinctrl-names = "default"; 1403 pinctrl-0 = <&qup_i2c5_default>; 1404 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 power-domains = <&rpmhpd SDM845_CX>; 1408 operating-points-v2 = <&qup_opp_table>; 1409 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1410 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1411 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1412 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1413 status = "disabled"; 1414 }; 1415 1416 spi5: spi@894000 { 1417 compatible = "qcom,geni-spi"; 1418 reg = <0 0x00894000 0 0x4000>; 1419 clock-names = "se"; 1420 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1421 pinctrl-names = "default"; 1422 pinctrl-0 = <&qup_spi5_default>; 1423 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1424 #address-cells = <1>; 1425 #size-cells = <0>; 1426 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1427 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1428 interconnect-names = "qup-core", "qup-config"; 1429 status = "disabled"; 1430 }; 1431 1432 uart5: serial@894000 { 1433 compatible = "qcom,geni-uart"; 1434 reg = <0 0x00894000 0 0x4000>; 1435 clock-names = "se"; 1436 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&qup_uart5_default>; 1439 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1440 power-domains = <&rpmhpd SDM845_CX>; 1441 operating-points-v2 = <&qup_opp_table>; 1442 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1443 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1444 interconnect-names = "qup-core", "qup-config"; 1445 status = "disabled"; 1446 }; 1447 1448 i2c6: i2c@898000 { 1449 compatible = "qcom,geni-i2c"; 1450 reg = <0 0x00898000 0 0x4000>; 1451 clock-names = "se"; 1452 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1453 pinctrl-names = "default"; 1454 pinctrl-0 = <&qup_i2c6_default>; 1455 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1456 #address-cells = <1>; 1457 #size-cells = <0>; 1458 power-domains = <&rpmhpd SDM845_CX>; 1459 operating-points-v2 = <&qup_opp_table>; 1460 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1461 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, 1462 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; 1463 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1464 status = "disabled"; 1465 }; 1466 1467 spi6: spi@898000 { 1468 compatible = "qcom,geni-spi"; 1469 reg = <0 0x00898000 0 0x4000>; 1470 clock-names = "se"; 1471 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1472 pinctrl-names = "default"; 1473 pinctrl-0 = <&qup_spi6_default>; 1474 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1475 #address-cells = <1>; 1476 #size-cells = <0>; 1477 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1478 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1479 interconnect-names = "qup-core", "qup-config"; 1480 status = "disabled"; 1481 }; 1482 1483 uart6: serial@898000 { 1484 compatible = "qcom,geni-uart"; 1485 reg = <0 0x00898000 0 0x4000>; 1486 clock-names = "se"; 1487 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1488 pinctrl-names = "default"; 1489 pinctrl-0 = <&qup_uart6_default>; 1490 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1491 power-domains = <&rpmhpd SDM845_CX>; 1492 operating-points-v2 = <&qup_opp_table>; 1493 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1494 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1495 interconnect-names = "qup-core", "qup-config"; 1496 status = "disabled"; 1497 }; 1498 1499 i2c7: i2c@89c000 { 1500 compatible = "qcom,geni-i2c"; 1501 reg = <0 0x0089c000 0 0x4000>; 1502 clock-names = "se"; 1503 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1504 pinctrl-names = "default"; 1505 pinctrl-0 = <&qup_i2c7_default>; 1506 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 power-domains = <&rpmhpd SDM845_CX>; 1510 operating-points-v2 = <&qup_opp_table>; 1511 status = "disabled"; 1512 }; 1513 1514 spi7: spi@89c000 { 1515 compatible = "qcom,geni-spi"; 1516 reg = <0 0x0089c000 0 0x4000>; 1517 clock-names = "se"; 1518 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1519 pinctrl-names = "default"; 1520 pinctrl-0 = <&qup_spi7_default>; 1521 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1522 #address-cells = <1>; 1523 #size-cells = <0>; 1524 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1525 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1526 interconnect-names = "qup-core", "qup-config"; 1527 status = "disabled"; 1528 }; 1529 1530 uart7: serial@89c000 { 1531 compatible = "qcom,geni-uart"; 1532 reg = <0 0x0089c000 0 0x4000>; 1533 clock-names = "se"; 1534 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1535 pinctrl-names = "default"; 1536 pinctrl-0 = <&qup_uart7_default>; 1537 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1538 power-domains = <&rpmhpd SDM845_CX>; 1539 operating-points-v2 = <&qup_opp_table>; 1540 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, 1541 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; 1542 interconnect-names = "qup-core", "qup-config"; 1543 status = "disabled"; 1544 }; 1545 }; 1546 1547 qupv3_id_1: geniqup@ac0000 { 1548 compatible = "qcom,geni-se-qup"; 1549 reg = <0 0x00ac0000 0 0x6000>; 1550 clock-names = "m-ahb", "s-ahb"; 1551 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1552 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1553 iommus = <&apps_smmu 0x6c3 0x0>; 1554 #address-cells = <2>; 1555 #size-cells = <2>; 1556 ranges; 1557 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; 1558 interconnect-names = "qup-core"; 1559 status = "disabled"; 1560 1561 i2c8: i2c@a80000 { 1562 compatible = "qcom,geni-i2c"; 1563 reg = <0 0x00a80000 0 0x4000>; 1564 clock-names = "se"; 1565 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1566 pinctrl-names = "default"; 1567 pinctrl-0 = <&qup_i2c8_default>; 1568 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1569 #address-cells = <1>; 1570 #size-cells = <0>; 1571 power-domains = <&rpmhpd SDM845_CX>; 1572 operating-points-v2 = <&qup_opp_table>; 1573 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1574 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1575 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1576 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1577 status = "disabled"; 1578 }; 1579 1580 spi8: spi@a80000 { 1581 compatible = "qcom,geni-spi"; 1582 reg = <0 0x00a80000 0 0x4000>; 1583 clock-names = "se"; 1584 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1585 pinctrl-names = "default"; 1586 pinctrl-0 = <&qup_spi8_default>; 1587 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1588 #address-cells = <1>; 1589 #size-cells = <0>; 1590 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1591 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1592 interconnect-names = "qup-core", "qup-config"; 1593 status = "disabled"; 1594 }; 1595 1596 uart8: serial@a80000 { 1597 compatible = "qcom,geni-uart"; 1598 reg = <0 0x00a80000 0 0x4000>; 1599 clock-names = "se"; 1600 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1601 pinctrl-names = "default"; 1602 pinctrl-0 = <&qup_uart8_default>; 1603 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1604 power-domains = <&rpmhpd SDM845_CX>; 1605 operating-points-v2 = <&qup_opp_table>; 1606 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1607 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1608 interconnect-names = "qup-core", "qup-config"; 1609 status = "disabled"; 1610 }; 1611 1612 i2c9: i2c@a84000 { 1613 compatible = "qcom,geni-i2c"; 1614 reg = <0 0x00a84000 0 0x4000>; 1615 clock-names = "se"; 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1617 pinctrl-names = "default"; 1618 pinctrl-0 = <&qup_i2c9_default>; 1619 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 power-domains = <&rpmhpd SDM845_CX>; 1623 operating-points-v2 = <&qup_opp_table>; 1624 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1625 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1626 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1627 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1628 status = "disabled"; 1629 }; 1630 1631 spi9: spi@a84000 { 1632 compatible = "qcom,geni-spi"; 1633 reg = <0 0x00a84000 0 0x4000>; 1634 clock-names = "se"; 1635 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1636 pinctrl-names = "default"; 1637 pinctrl-0 = <&qup_spi9_default>; 1638 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1642 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1643 interconnect-names = "qup-core", "qup-config"; 1644 status = "disabled"; 1645 }; 1646 1647 uart9: serial@a84000 { 1648 compatible = "qcom,geni-debug-uart"; 1649 reg = <0 0x00a84000 0 0x4000>; 1650 clock-names = "se"; 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1652 pinctrl-names = "default"; 1653 pinctrl-0 = <&qup_uart9_default>; 1654 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1655 power-domains = <&rpmhpd SDM845_CX>; 1656 operating-points-v2 = <&qup_opp_table>; 1657 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1658 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1659 interconnect-names = "qup-core", "qup-config"; 1660 status = "disabled"; 1661 }; 1662 1663 i2c10: i2c@a88000 { 1664 compatible = "qcom,geni-i2c"; 1665 reg = <0 0x00a88000 0 0x4000>; 1666 clock-names = "se"; 1667 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1668 pinctrl-names = "default"; 1669 pinctrl-0 = <&qup_i2c10_default>; 1670 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 power-domains = <&rpmhpd SDM845_CX>; 1674 operating-points-v2 = <&qup_opp_table>; 1675 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1676 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1677 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1678 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1679 status = "disabled"; 1680 }; 1681 1682 spi10: spi@a88000 { 1683 compatible = "qcom,geni-spi"; 1684 reg = <0 0x00a88000 0 0x4000>; 1685 clock-names = "se"; 1686 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&qup_spi10_default>; 1689 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1693 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1694 interconnect-names = "qup-core", "qup-config"; 1695 status = "disabled"; 1696 }; 1697 1698 uart10: serial@a88000 { 1699 compatible = "qcom,geni-uart"; 1700 reg = <0 0x00a88000 0 0x4000>; 1701 clock-names = "se"; 1702 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1703 pinctrl-names = "default"; 1704 pinctrl-0 = <&qup_uart10_default>; 1705 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1706 power-domains = <&rpmhpd SDM845_CX>; 1707 operating-points-v2 = <&qup_opp_table>; 1708 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1709 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1710 interconnect-names = "qup-core", "qup-config"; 1711 status = "disabled"; 1712 }; 1713 1714 i2c11: i2c@a8c000 { 1715 compatible = "qcom,geni-i2c"; 1716 reg = <0 0x00a8c000 0 0x4000>; 1717 clock-names = "se"; 1718 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1719 pinctrl-names = "default"; 1720 pinctrl-0 = <&qup_i2c11_default>; 1721 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1722 #address-cells = <1>; 1723 #size-cells = <0>; 1724 power-domains = <&rpmhpd SDM845_CX>; 1725 operating-points-v2 = <&qup_opp_table>; 1726 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1727 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1728 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1729 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1730 status = "disabled"; 1731 }; 1732 1733 spi11: spi@a8c000 { 1734 compatible = "qcom,geni-spi"; 1735 reg = <0 0x00a8c000 0 0x4000>; 1736 clock-names = "se"; 1737 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1738 pinctrl-names = "default"; 1739 pinctrl-0 = <&qup_spi11_default>; 1740 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1741 #address-cells = <1>; 1742 #size-cells = <0>; 1743 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1744 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1745 interconnect-names = "qup-core", "qup-config"; 1746 status = "disabled"; 1747 }; 1748 1749 uart11: serial@a8c000 { 1750 compatible = "qcom,geni-uart"; 1751 reg = <0 0x00a8c000 0 0x4000>; 1752 clock-names = "se"; 1753 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1754 pinctrl-names = "default"; 1755 pinctrl-0 = <&qup_uart11_default>; 1756 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1757 power-domains = <&rpmhpd SDM845_CX>; 1758 operating-points-v2 = <&qup_opp_table>; 1759 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1760 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1761 interconnect-names = "qup-core", "qup-config"; 1762 status = "disabled"; 1763 }; 1764 1765 i2c12: i2c@a90000 { 1766 compatible = "qcom,geni-i2c"; 1767 reg = <0 0x00a90000 0 0x4000>; 1768 clock-names = "se"; 1769 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1770 pinctrl-names = "default"; 1771 pinctrl-0 = <&qup_i2c12_default>; 1772 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1773 #address-cells = <1>; 1774 #size-cells = <0>; 1775 power-domains = <&rpmhpd SDM845_CX>; 1776 operating-points-v2 = <&qup_opp_table>; 1777 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1778 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1779 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1780 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1781 status = "disabled"; 1782 }; 1783 1784 spi12: spi@a90000 { 1785 compatible = "qcom,geni-spi"; 1786 reg = <0 0x00a90000 0 0x4000>; 1787 clock-names = "se"; 1788 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1789 pinctrl-names = "default"; 1790 pinctrl-0 = <&qup_spi12_default>; 1791 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1792 #address-cells = <1>; 1793 #size-cells = <0>; 1794 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1795 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1796 interconnect-names = "qup-core", "qup-config"; 1797 status = "disabled"; 1798 }; 1799 1800 uart12: serial@a90000 { 1801 compatible = "qcom,geni-uart"; 1802 reg = <0 0x00a90000 0 0x4000>; 1803 clock-names = "se"; 1804 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1805 pinctrl-names = "default"; 1806 pinctrl-0 = <&qup_uart12_default>; 1807 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1808 power-domains = <&rpmhpd SDM845_CX>; 1809 operating-points-v2 = <&qup_opp_table>; 1810 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1811 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1812 interconnect-names = "qup-core", "qup-config"; 1813 status = "disabled"; 1814 }; 1815 1816 i2c13: i2c@a94000 { 1817 compatible = "qcom,geni-i2c"; 1818 reg = <0 0x00a94000 0 0x4000>; 1819 clock-names = "se"; 1820 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1821 pinctrl-names = "default"; 1822 pinctrl-0 = <&qup_i2c13_default>; 1823 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1824 #address-cells = <1>; 1825 #size-cells = <0>; 1826 power-domains = <&rpmhpd SDM845_CX>; 1827 operating-points-v2 = <&qup_opp_table>; 1828 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1829 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1830 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1831 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1832 status = "disabled"; 1833 }; 1834 1835 spi13: spi@a94000 { 1836 compatible = "qcom,geni-spi"; 1837 reg = <0 0x00a94000 0 0x4000>; 1838 clock-names = "se"; 1839 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1840 pinctrl-names = "default"; 1841 pinctrl-0 = <&qup_spi13_default>; 1842 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1843 #address-cells = <1>; 1844 #size-cells = <0>; 1845 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1846 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1847 interconnect-names = "qup-core", "qup-config"; 1848 status = "disabled"; 1849 }; 1850 1851 uart13: serial@a94000 { 1852 compatible = "qcom,geni-uart"; 1853 reg = <0 0x00a94000 0 0x4000>; 1854 clock-names = "se"; 1855 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1856 pinctrl-names = "default"; 1857 pinctrl-0 = <&qup_uart13_default>; 1858 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1859 power-domains = <&rpmhpd SDM845_CX>; 1860 operating-points-v2 = <&qup_opp_table>; 1861 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1862 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1863 interconnect-names = "qup-core", "qup-config"; 1864 status = "disabled"; 1865 }; 1866 1867 i2c14: i2c@a98000 { 1868 compatible = "qcom,geni-i2c"; 1869 reg = <0 0x00a98000 0 0x4000>; 1870 clock-names = "se"; 1871 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1872 pinctrl-names = "default"; 1873 pinctrl-0 = <&qup_i2c14_default>; 1874 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1875 #address-cells = <1>; 1876 #size-cells = <0>; 1877 power-domains = <&rpmhpd SDM845_CX>; 1878 operating-points-v2 = <&qup_opp_table>; 1879 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1880 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1881 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1882 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1883 status = "disabled"; 1884 }; 1885 1886 spi14: spi@a98000 { 1887 compatible = "qcom,geni-spi"; 1888 reg = <0 0x00a98000 0 0x4000>; 1889 clock-names = "se"; 1890 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1891 pinctrl-names = "default"; 1892 pinctrl-0 = <&qup_spi14_default>; 1893 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1894 #address-cells = <1>; 1895 #size-cells = <0>; 1896 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1897 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1898 interconnect-names = "qup-core", "qup-config"; 1899 status = "disabled"; 1900 }; 1901 1902 uart14: serial@a98000 { 1903 compatible = "qcom,geni-uart"; 1904 reg = <0 0x00a98000 0 0x4000>; 1905 clock-names = "se"; 1906 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1907 pinctrl-names = "default"; 1908 pinctrl-0 = <&qup_uart14_default>; 1909 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1910 power-domains = <&rpmhpd SDM845_CX>; 1911 operating-points-v2 = <&qup_opp_table>; 1912 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1913 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1914 interconnect-names = "qup-core", "qup-config"; 1915 status = "disabled"; 1916 }; 1917 1918 i2c15: i2c@a9c000 { 1919 compatible = "qcom,geni-i2c"; 1920 reg = <0 0x00a9c000 0 0x4000>; 1921 clock-names = "se"; 1922 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1923 pinctrl-names = "default"; 1924 pinctrl-0 = <&qup_i2c15_default>; 1925 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1926 #address-cells = <1>; 1927 #size-cells = <0>; 1928 power-domains = <&rpmhpd SDM845_CX>; 1929 operating-points-v2 = <&qup_opp_table>; 1930 status = "disabled"; 1931 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1932 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, 1933 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; 1934 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1935 }; 1936 1937 spi15: spi@a9c000 { 1938 compatible = "qcom,geni-spi"; 1939 reg = <0 0x00a9c000 0 0x4000>; 1940 clock-names = "se"; 1941 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1942 pinctrl-names = "default"; 1943 pinctrl-0 = <&qup_spi15_default>; 1944 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1945 #address-cells = <1>; 1946 #size-cells = <0>; 1947 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1948 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1949 interconnect-names = "qup-core", "qup-config"; 1950 status = "disabled"; 1951 }; 1952 1953 uart15: serial@a9c000 { 1954 compatible = "qcom,geni-uart"; 1955 reg = <0 0x00a9c000 0 0x4000>; 1956 clock-names = "se"; 1957 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1958 pinctrl-names = "default"; 1959 pinctrl-0 = <&qup_uart15_default>; 1960 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1961 power-domains = <&rpmhpd SDM845_CX>; 1962 operating-points-v2 = <&qup_opp_table>; 1963 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, 1964 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; 1965 interconnect-names = "qup-core", "qup-config"; 1966 status = "disabled"; 1967 }; 1968 }; 1969 1970 system-cache-controller@1100000 { 1971 compatible = "qcom,sdm845-llcc"; 1972 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; 1973 reg-names = "llcc_base", "llcc_broadcast_base"; 1974 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1975 }; 1976 1977 pcie0: pci@1c00000 { 1978 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1979 reg = <0 0x01c00000 0 0x2000>, 1980 <0 0x60000000 0 0xf1d>, 1981 <0 0x60000f20 0 0xa8>, 1982 <0 0x60100000 0 0x100000>; 1983 reg-names = "parf", "dbi", "elbi", "config"; 1984 device_type = "pci"; 1985 linux,pci-domain = <0>; 1986 bus-range = <0x00 0xff>; 1987 num-lanes = <1>; 1988 1989 #address-cells = <3>; 1990 #size-cells = <2>; 1991 1992 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1993 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; 1994 1995 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1996 interrupt-names = "msi"; 1997 #interrupt-cells = <1>; 1998 interrupt-map-mask = <0 0 0 0x7>; 1999 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2000 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2001 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2002 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2003 2004 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2005 <&gcc GCC_PCIE_0_AUX_CLK>, 2006 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2007 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2008 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2009 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2010 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2011 clock-names = "pipe", 2012 "aux", 2013 "cfg", 2014 "bus_master", 2015 "bus_slave", 2016 "slave_q2a", 2017 "tbu"; 2018 2019 iommus = <&apps_smmu 0x1c10 0xf>; 2020 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 2021 <0x100 &apps_smmu 0x1c11 0x1>, 2022 <0x200 &apps_smmu 0x1c12 0x1>, 2023 <0x300 &apps_smmu 0x1c13 0x1>, 2024 <0x400 &apps_smmu 0x1c14 0x1>, 2025 <0x500 &apps_smmu 0x1c15 0x1>, 2026 <0x600 &apps_smmu 0x1c16 0x1>, 2027 <0x700 &apps_smmu 0x1c17 0x1>, 2028 <0x800 &apps_smmu 0x1c18 0x1>, 2029 <0x900 &apps_smmu 0x1c19 0x1>, 2030 <0xa00 &apps_smmu 0x1c1a 0x1>, 2031 <0xb00 &apps_smmu 0x1c1b 0x1>, 2032 <0xc00 &apps_smmu 0x1c1c 0x1>, 2033 <0xd00 &apps_smmu 0x1c1d 0x1>, 2034 <0xe00 &apps_smmu 0x1c1e 0x1>, 2035 <0xf00 &apps_smmu 0x1c1f 0x1>; 2036 2037 resets = <&gcc GCC_PCIE_0_BCR>; 2038 reset-names = "pci"; 2039 2040 power-domains = <&gcc PCIE_0_GDSC>; 2041 2042 phys = <&pcie0_lane>; 2043 phy-names = "pciephy"; 2044 2045 status = "disabled"; 2046 }; 2047 2048 pcie0_phy: phy@1c06000 { 2049 compatible = "qcom,sdm845-qmp-pcie-phy"; 2050 reg = <0 0x01c06000 0 0x18c>; 2051 #address-cells = <2>; 2052 #size-cells = <2>; 2053 ranges; 2054 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2055 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2056 <&gcc GCC_PCIE_0_CLKREF_CLK>, 2057 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2058 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2059 2060 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2061 reset-names = "phy"; 2062 2063 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2064 assigned-clock-rates = <100000000>; 2065 2066 status = "disabled"; 2067 2068 pcie0_lane: phy@1c06200 { 2069 reg = <0 0x01c06200 0 0x128>, 2070 <0 0x01c06400 0 0x1fc>, 2071 <0 0x01c06800 0 0x218>, 2072 <0 0x01c06600 0 0x70>; 2073 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 2074 clock-names = "pipe0"; 2075 2076 #clock-cells = <0>; 2077 #phy-cells = <0>; 2078 clock-output-names = "pcie_0_pipe_clk"; 2079 }; 2080 }; 2081 2082 pcie1: pci@1c08000 { 2083 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 2084 reg = <0 0x01c08000 0 0x2000>, 2085 <0 0x40000000 0 0xf1d>, 2086 <0 0x40000f20 0 0xa8>, 2087 <0 0x40100000 0 0x100000>; 2088 reg-names = "parf", "dbi", "elbi", "config"; 2089 device_type = "pci"; 2090 linux,pci-domain = <1>; 2091 bus-range = <0x00 0xff>; 2092 num-lanes = <1>; 2093 2094 #address-cells = <3>; 2095 #size-cells = <2>; 2096 2097 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2098 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2099 2100 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 2101 interrupt-names = "msi"; 2102 #interrupt-cells = <1>; 2103 interrupt-map-mask = <0 0 0 0x7>; 2104 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2105 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2106 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2107 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2108 2109 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2110 <&gcc GCC_PCIE_1_AUX_CLK>, 2111 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2112 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2113 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2114 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2115 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2116 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2117 clock-names = "pipe", 2118 "aux", 2119 "cfg", 2120 "bus_master", 2121 "bus_slave", 2122 "slave_q2a", 2123 "ref", 2124 "tbu"; 2125 2126 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2127 assigned-clock-rates = <19200000>; 2128 2129 iommus = <&apps_smmu 0x1c00 0xf>; 2130 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2131 <0x100 &apps_smmu 0x1c01 0x1>, 2132 <0x200 &apps_smmu 0x1c02 0x1>, 2133 <0x300 &apps_smmu 0x1c03 0x1>, 2134 <0x400 &apps_smmu 0x1c04 0x1>, 2135 <0x500 &apps_smmu 0x1c05 0x1>, 2136 <0x600 &apps_smmu 0x1c06 0x1>, 2137 <0x700 &apps_smmu 0x1c07 0x1>, 2138 <0x800 &apps_smmu 0x1c08 0x1>, 2139 <0x900 &apps_smmu 0x1c09 0x1>, 2140 <0xa00 &apps_smmu 0x1c0a 0x1>, 2141 <0xb00 &apps_smmu 0x1c0b 0x1>, 2142 <0xc00 &apps_smmu 0x1c0c 0x1>, 2143 <0xd00 &apps_smmu 0x1c0d 0x1>, 2144 <0xe00 &apps_smmu 0x1c0e 0x1>, 2145 <0xf00 &apps_smmu 0x1c0f 0x1>; 2146 2147 resets = <&gcc GCC_PCIE_1_BCR>; 2148 reset-names = "pci"; 2149 2150 power-domains = <&gcc PCIE_1_GDSC>; 2151 2152 phys = <&pcie1_lane>; 2153 phy-names = "pciephy"; 2154 2155 status = "disabled"; 2156 }; 2157 2158 pcie1_phy: phy@1c0a000 { 2159 compatible = "qcom,sdm845-qhp-pcie-phy"; 2160 reg = <0 0x01c0a000 0 0x800>; 2161 #address-cells = <2>; 2162 #size-cells = <2>; 2163 ranges; 2164 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2165 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2166 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2167 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2168 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2169 2170 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2171 reset-names = "phy"; 2172 2173 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 2174 assigned-clock-rates = <100000000>; 2175 2176 status = "disabled"; 2177 2178 pcie1_lane: phy@1c06200 { 2179 reg = <0 0x01c0a800 0 0x800>, 2180 <0 0x01c0a800 0 0x800>, 2181 <0 0x01c0b800 0 0x400>; 2182 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2183 clock-names = "pipe0"; 2184 2185 #clock-cells = <0>; 2186 #phy-cells = <0>; 2187 clock-output-names = "pcie_1_pipe_clk"; 2188 }; 2189 }; 2190 2191 mem_noc: interconnect@1380000 { 2192 compatible = "qcom,sdm845-mem-noc"; 2193 reg = <0 0x01380000 0 0x27200>; 2194 #interconnect-cells = <2>; 2195 qcom,bcm-voters = <&apps_bcm_voter>; 2196 }; 2197 2198 dc_noc: interconnect@14e0000 { 2199 compatible = "qcom,sdm845-dc-noc"; 2200 reg = <0 0x014e0000 0 0x400>; 2201 #interconnect-cells = <2>; 2202 qcom,bcm-voters = <&apps_bcm_voter>; 2203 }; 2204 2205 config_noc: interconnect@1500000 { 2206 compatible = "qcom,sdm845-config-noc"; 2207 reg = <0 0x01500000 0 0x5080>; 2208 #interconnect-cells = <2>; 2209 qcom,bcm-voters = <&apps_bcm_voter>; 2210 }; 2211 2212 system_noc: interconnect@1620000 { 2213 compatible = "qcom,sdm845-system-noc"; 2214 reg = <0 0x01620000 0 0x18080>; 2215 #interconnect-cells = <2>; 2216 qcom,bcm-voters = <&apps_bcm_voter>; 2217 }; 2218 2219 aggre1_noc: interconnect@16e0000 { 2220 compatible = "qcom,sdm845-aggre1-noc"; 2221 reg = <0 0x016e0000 0 0x15080>; 2222 #interconnect-cells = <2>; 2223 qcom,bcm-voters = <&apps_bcm_voter>; 2224 }; 2225 2226 aggre2_noc: interconnect@1700000 { 2227 compatible = "qcom,sdm845-aggre2-noc"; 2228 reg = <0 0x01700000 0 0x1f300>; 2229 #interconnect-cells = <2>; 2230 qcom,bcm-voters = <&apps_bcm_voter>; 2231 }; 2232 2233 mmss_noc: interconnect@1740000 { 2234 compatible = "qcom,sdm845-mmss-noc"; 2235 reg = <0 0x01740000 0 0x1c100>; 2236 #interconnect-cells = <2>; 2237 qcom,bcm-voters = <&apps_bcm_voter>; 2238 }; 2239 2240 ufs_mem_hc: ufshc@1d84000 { 2241 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 2242 "jedec,ufs-2.0"; 2243 reg = <0 0x01d84000 0 0x2500>, 2244 <0 0x01d90000 0 0x8000>; 2245 reg-names = "std", "ice"; 2246 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2247 phys = <&ufs_mem_phy_lanes>; 2248 phy-names = "ufsphy"; 2249 lanes-per-direction = <2>; 2250 power-domains = <&gcc UFS_PHY_GDSC>; 2251 #reset-cells = <1>; 2252 resets = <&gcc GCC_UFS_PHY_BCR>; 2253 reset-names = "rst"; 2254 2255 iommus = <&apps_smmu 0x100 0xf>; 2256 2257 clock-names = 2258 "core_clk", 2259 "bus_aggr_clk", 2260 "iface_clk", 2261 "core_clk_unipro", 2262 "ref_clk", 2263 "tx_lane0_sync_clk", 2264 "rx_lane0_sync_clk", 2265 "rx_lane1_sync_clk", 2266 "ice_core_clk"; 2267 clocks = 2268 <&gcc GCC_UFS_PHY_AXI_CLK>, 2269 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2270 <&gcc GCC_UFS_PHY_AHB_CLK>, 2271 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2272 <&rpmhcc RPMH_CXO_CLK>, 2273 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2274 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2275 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2276 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2277 freq-table-hz = 2278 <50000000 200000000>, 2279 <0 0>, 2280 <0 0>, 2281 <37500000 150000000>, 2282 <0 0>, 2283 <0 0>, 2284 <0 0>, 2285 <0 0>, 2286 <75000000 300000000>; 2287 2288 status = "disabled"; 2289 }; 2290 2291 ufs_mem_phy: phy@1d87000 { 2292 compatible = "qcom,sdm845-qmp-ufs-phy"; 2293 reg = <0 0x01d87000 0 0x18c>; 2294 #address-cells = <2>; 2295 #size-cells = <2>; 2296 ranges; 2297 clock-names = "ref", 2298 "ref_aux"; 2299 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2300 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2301 2302 resets = <&ufs_mem_hc 0>; 2303 reset-names = "ufsphy"; 2304 status = "disabled"; 2305 2306 ufs_mem_phy_lanes: phy@1d87400 { 2307 reg = <0 0x01d87400 0 0x108>, 2308 <0 0x01d87600 0 0x1e0>, 2309 <0 0x01d87c00 0 0x1dc>, 2310 <0 0x01d87800 0 0x108>, 2311 <0 0x01d87a00 0 0x1e0>; 2312 #phy-cells = <0>; 2313 }; 2314 }; 2315 2316 cryptobam: dma@1dc4000 { 2317 compatible = "qcom,bam-v1.7.0"; 2318 reg = <0 0x01dc4000 0 0x24000>; 2319 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2320 clocks = <&rpmhcc RPMH_CE_CLK>; 2321 clock-names = "bam_clk"; 2322 #dma-cells = <1>; 2323 qcom,ee = <0>; 2324 qcom,controlled-remotely; 2325 iommus = <&apps_smmu 0x704 0x1>, 2326 <&apps_smmu 0x706 0x1>, 2327 <&apps_smmu 0x714 0x1>, 2328 <&apps_smmu 0x716 0x1>; 2329 }; 2330 2331 crypto: crypto@1dfa000 { 2332 compatible = "qcom,crypto-v5.4"; 2333 reg = <0 0x01dfa000 0 0x6000>; 2334 clocks = <&gcc GCC_CE1_AHB_CLK>, 2335 <&gcc GCC_CE1_AXI_CLK>, 2336 <&rpmhcc RPMH_CE_CLK>; 2337 clock-names = "iface", "bus", "core"; 2338 dmas = <&cryptobam 6>, <&cryptobam 7>; 2339 dma-names = "rx", "tx"; 2340 iommus = <&apps_smmu 0x704 0x1>, 2341 <&apps_smmu 0x706 0x1>, 2342 <&apps_smmu 0x714 0x1>, 2343 <&apps_smmu 0x716 0x1>; 2344 }; 2345 2346 ipa: ipa@1e40000 { 2347 compatible = "qcom,sdm845-ipa"; 2348 2349 iommus = <&apps_smmu 0x720 0x0>, 2350 <&apps_smmu 0x722 0x0>; 2351 reg = <0 0x1e40000 0 0x7000>, 2352 <0 0x1e47000 0 0x2000>, 2353 <0 0x1e04000 0 0x2c000>; 2354 reg-names = "ipa-reg", 2355 "ipa-shared", 2356 "gsi"; 2357 2358 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 2359 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2360 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2361 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2362 interrupt-names = "ipa", 2363 "gsi", 2364 "ipa-clock-query", 2365 "ipa-setup-ready"; 2366 2367 clocks = <&rpmhcc RPMH_IPA_CLK>; 2368 clock-names = "core"; 2369 2370 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, 2371 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 2372 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2373 interconnect-names = "memory", 2374 "imem", 2375 "config"; 2376 2377 qcom,smem-states = <&ipa_smp2p_out 0>, 2378 <&ipa_smp2p_out 1>; 2379 qcom,smem-state-names = "ipa-clock-enabled-valid", 2380 "ipa-clock-enabled"; 2381 2382 status = "disabled"; 2383 }; 2384 2385 tcsr_mutex_regs: syscon@1f40000 { 2386 compatible = "syscon"; 2387 reg = <0 0x01f40000 0 0x40000>; 2388 }; 2389 2390 tlmm: pinctrl@3400000 { 2391 compatible = "qcom,sdm845-pinctrl"; 2392 reg = <0 0x03400000 0 0xc00000>; 2393 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2394 gpio-controller; 2395 #gpio-cells = <2>; 2396 interrupt-controller; 2397 #interrupt-cells = <2>; 2398 gpio-ranges = <&tlmm 0 0 151>; 2399 wakeup-parent = <&pdc_intc>; 2400 2401 cci0_default: cci0-default { 2402 /* SDA, SCL */ 2403 pins = "gpio17", "gpio18"; 2404 function = "cci_i2c"; 2405 2406 bias-pull-up; 2407 drive-strength = <2>; /* 2 mA */ 2408 }; 2409 2410 cci0_sleep: cci0-sleep { 2411 /* SDA, SCL */ 2412 pins = "gpio17", "gpio18"; 2413 function = "cci_i2c"; 2414 2415 drive-strength = <2>; /* 2 mA */ 2416 bias-pull-down; 2417 }; 2418 2419 cci1_default: cci1-default { 2420 /* SDA, SCL */ 2421 pins = "gpio19", "gpio20"; 2422 function = "cci_i2c"; 2423 2424 bias-pull-up; 2425 drive-strength = <2>; /* 2 mA */ 2426 }; 2427 2428 cci1_sleep: cci1-sleep { 2429 /* SDA, SCL */ 2430 pins = "gpio19", "gpio20"; 2431 function = "cci_i2c"; 2432 2433 drive-strength = <2>; /* 2 mA */ 2434 bias-pull-down; 2435 }; 2436 2437 qspi_clk: qspi-clk { 2438 pinmux { 2439 pins = "gpio95"; 2440 function = "qspi_clk"; 2441 }; 2442 }; 2443 2444 qspi_cs0: qspi-cs0 { 2445 pinmux { 2446 pins = "gpio90"; 2447 function = "qspi_cs"; 2448 }; 2449 }; 2450 2451 qspi_cs1: qspi-cs1 { 2452 pinmux { 2453 pins = "gpio89"; 2454 function = "qspi_cs"; 2455 }; 2456 }; 2457 2458 qspi_data01: qspi-data01 { 2459 pinmux-data { 2460 pins = "gpio91", "gpio92"; 2461 function = "qspi_data"; 2462 }; 2463 }; 2464 2465 qspi_data12: qspi-data12 { 2466 pinmux-data { 2467 pins = "gpio93", "gpio94"; 2468 function = "qspi_data"; 2469 }; 2470 }; 2471 2472 qup_i2c0_default: qup-i2c0-default { 2473 pinmux { 2474 pins = "gpio0", "gpio1"; 2475 function = "qup0"; 2476 }; 2477 }; 2478 2479 qup_i2c1_default: qup-i2c1-default { 2480 pinmux { 2481 pins = "gpio17", "gpio18"; 2482 function = "qup1"; 2483 }; 2484 }; 2485 2486 qup_i2c2_default: qup-i2c2-default { 2487 pinmux { 2488 pins = "gpio27", "gpio28"; 2489 function = "qup2"; 2490 }; 2491 }; 2492 2493 qup_i2c3_default: qup-i2c3-default { 2494 pinmux { 2495 pins = "gpio41", "gpio42"; 2496 function = "qup3"; 2497 }; 2498 }; 2499 2500 qup_i2c4_default: qup-i2c4-default { 2501 pinmux { 2502 pins = "gpio89", "gpio90"; 2503 function = "qup4"; 2504 }; 2505 }; 2506 2507 qup_i2c5_default: qup-i2c5-default { 2508 pinmux { 2509 pins = "gpio85", "gpio86"; 2510 function = "qup5"; 2511 }; 2512 }; 2513 2514 qup_i2c6_default: qup-i2c6-default { 2515 pinmux { 2516 pins = "gpio45", "gpio46"; 2517 function = "qup6"; 2518 }; 2519 }; 2520 2521 qup_i2c7_default: qup-i2c7-default { 2522 pinmux { 2523 pins = "gpio93", "gpio94"; 2524 function = "qup7"; 2525 }; 2526 }; 2527 2528 qup_i2c8_default: qup-i2c8-default { 2529 pinmux { 2530 pins = "gpio65", "gpio66"; 2531 function = "qup8"; 2532 }; 2533 }; 2534 2535 qup_i2c9_default: qup-i2c9-default { 2536 pinmux { 2537 pins = "gpio6", "gpio7"; 2538 function = "qup9"; 2539 }; 2540 }; 2541 2542 qup_i2c10_default: qup-i2c10-default { 2543 pinmux { 2544 pins = "gpio55", "gpio56"; 2545 function = "qup10"; 2546 }; 2547 }; 2548 2549 qup_i2c11_default: qup-i2c11-default { 2550 pinmux { 2551 pins = "gpio31", "gpio32"; 2552 function = "qup11"; 2553 }; 2554 }; 2555 2556 qup_i2c12_default: qup-i2c12-default { 2557 pinmux { 2558 pins = "gpio49", "gpio50"; 2559 function = "qup12"; 2560 }; 2561 }; 2562 2563 qup_i2c13_default: qup-i2c13-default { 2564 pinmux { 2565 pins = "gpio105", "gpio106"; 2566 function = "qup13"; 2567 }; 2568 }; 2569 2570 qup_i2c14_default: qup-i2c14-default { 2571 pinmux { 2572 pins = "gpio33", "gpio34"; 2573 function = "qup14"; 2574 }; 2575 }; 2576 2577 qup_i2c15_default: qup-i2c15-default { 2578 pinmux { 2579 pins = "gpio81", "gpio82"; 2580 function = "qup15"; 2581 }; 2582 }; 2583 2584 qup_spi0_default: qup-spi0-default { 2585 pinmux { 2586 pins = "gpio0", "gpio1", 2587 "gpio2", "gpio3"; 2588 function = "qup0"; 2589 }; 2590 }; 2591 2592 qup_spi1_default: qup-spi1-default { 2593 pinmux { 2594 pins = "gpio17", "gpio18", 2595 "gpio19", "gpio20"; 2596 function = "qup1"; 2597 }; 2598 }; 2599 2600 qup_spi2_default: qup-spi2-default { 2601 pinmux { 2602 pins = "gpio27", "gpio28", 2603 "gpio29", "gpio30"; 2604 function = "qup2"; 2605 }; 2606 }; 2607 2608 qup_spi3_default: qup-spi3-default { 2609 pinmux { 2610 pins = "gpio41", "gpio42", 2611 "gpio43", "gpio44"; 2612 function = "qup3"; 2613 }; 2614 }; 2615 2616 qup_spi4_default: qup-spi4-default { 2617 pinmux { 2618 pins = "gpio89", "gpio90", 2619 "gpio91", "gpio92"; 2620 function = "qup4"; 2621 }; 2622 }; 2623 2624 qup_spi5_default: qup-spi5-default { 2625 pinmux { 2626 pins = "gpio85", "gpio86", 2627 "gpio87", "gpio88"; 2628 function = "qup5"; 2629 }; 2630 }; 2631 2632 qup_spi6_default: qup-spi6-default { 2633 pinmux { 2634 pins = "gpio45", "gpio46", 2635 "gpio47", "gpio48"; 2636 function = "qup6"; 2637 }; 2638 }; 2639 2640 qup_spi7_default: qup-spi7-default { 2641 pinmux { 2642 pins = "gpio93", "gpio94", 2643 "gpio95", "gpio96"; 2644 function = "qup7"; 2645 }; 2646 }; 2647 2648 qup_spi8_default: qup-spi8-default { 2649 pinmux { 2650 pins = "gpio65", "gpio66", 2651 "gpio67", "gpio68"; 2652 function = "qup8"; 2653 }; 2654 }; 2655 2656 qup_spi9_default: qup-spi9-default { 2657 pinmux { 2658 pins = "gpio6", "gpio7", 2659 "gpio4", "gpio5"; 2660 function = "qup9"; 2661 }; 2662 }; 2663 2664 qup_spi10_default: qup-spi10-default { 2665 pinmux { 2666 pins = "gpio55", "gpio56", 2667 "gpio53", "gpio54"; 2668 function = "qup10"; 2669 }; 2670 }; 2671 2672 qup_spi11_default: qup-spi11-default { 2673 pinmux { 2674 pins = "gpio31", "gpio32", 2675 "gpio33", "gpio34"; 2676 function = "qup11"; 2677 }; 2678 }; 2679 2680 qup_spi12_default: qup-spi12-default { 2681 pinmux { 2682 pins = "gpio49", "gpio50", 2683 "gpio51", "gpio52"; 2684 function = "qup12"; 2685 }; 2686 }; 2687 2688 qup_spi13_default: qup-spi13-default { 2689 pinmux { 2690 pins = "gpio105", "gpio106", 2691 "gpio107", "gpio108"; 2692 function = "qup13"; 2693 }; 2694 }; 2695 2696 qup_spi14_default: qup-spi14-default { 2697 pinmux { 2698 pins = "gpio33", "gpio34", 2699 "gpio31", "gpio32"; 2700 function = "qup14"; 2701 }; 2702 }; 2703 2704 qup_spi15_default: qup-spi15-default { 2705 pinmux { 2706 pins = "gpio81", "gpio82", 2707 "gpio83", "gpio84"; 2708 function = "qup15"; 2709 }; 2710 }; 2711 2712 qup_uart0_default: qup-uart0-default { 2713 pinmux { 2714 pins = "gpio2", "gpio3"; 2715 function = "qup0"; 2716 }; 2717 }; 2718 2719 qup_uart1_default: qup-uart1-default { 2720 pinmux { 2721 pins = "gpio19", "gpio20"; 2722 function = "qup1"; 2723 }; 2724 }; 2725 2726 qup_uart2_default: qup-uart2-default { 2727 pinmux { 2728 pins = "gpio29", "gpio30"; 2729 function = "qup2"; 2730 }; 2731 }; 2732 2733 qup_uart3_default: qup-uart3-default { 2734 pinmux { 2735 pins = "gpio43", "gpio44"; 2736 function = "qup3"; 2737 }; 2738 }; 2739 2740 qup_uart4_default: qup-uart4-default { 2741 pinmux { 2742 pins = "gpio91", "gpio92"; 2743 function = "qup4"; 2744 }; 2745 }; 2746 2747 qup_uart5_default: qup-uart5-default { 2748 pinmux { 2749 pins = "gpio87", "gpio88"; 2750 function = "qup5"; 2751 }; 2752 }; 2753 2754 qup_uart6_default: qup-uart6-default { 2755 pinmux { 2756 pins = "gpio47", "gpio48"; 2757 function = "qup6"; 2758 }; 2759 }; 2760 2761 qup_uart7_default: qup-uart7-default { 2762 pinmux { 2763 pins = "gpio95", "gpio96"; 2764 function = "qup7"; 2765 }; 2766 }; 2767 2768 qup_uart8_default: qup-uart8-default { 2769 pinmux { 2770 pins = "gpio67", "gpio68"; 2771 function = "qup8"; 2772 }; 2773 }; 2774 2775 qup_uart9_default: qup-uart9-default { 2776 pinmux { 2777 pins = "gpio4", "gpio5"; 2778 function = "qup9"; 2779 }; 2780 }; 2781 2782 qup_uart10_default: qup-uart10-default { 2783 pinmux { 2784 pins = "gpio53", "gpio54"; 2785 function = "qup10"; 2786 }; 2787 }; 2788 2789 qup_uart11_default: qup-uart11-default { 2790 pinmux { 2791 pins = "gpio33", "gpio34"; 2792 function = "qup11"; 2793 }; 2794 }; 2795 2796 qup_uart12_default: qup-uart12-default { 2797 pinmux { 2798 pins = "gpio51", "gpio52"; 2799 function = "qup12"; 2800 }; 2801 }; 2802 2803 qup_uart13_default: qup-uart13-default { 2804 pinmux { 2805 pins = "gpio107", "gpio108"; 2806 function = "qup13"; 2807 }; 2808 }; 2809 2810 qup_uart14_default: qup-uart14-default { 2811 pinmux { 2812 pins = "gpio31", "gpio32"; 2813 function = "qup14"; 2814 }; 2815 }; 2816 2817 qup_uart15_default: qup-uart15-default { 2818 pinmux { 2819 pins = "gpio83", "gpio84"; 2820 function = "qup15"; 2821 }; 2822 }; 2823 2824 quat_mi2s_sleep: quat_mi2s_sleep { 2825 mux { 2826 pins = "gpio58", "gpio59"; 2827 function = "gpio"; 2828 }; 2829 2830 config { 2831 pins = "gpio58", "gpio59"; 2832 drive-strength = <2>; 2833 bias-pull-down; 2834 input-enable; 2835 }; 2836 }; 2837 2838 quat_mi2s_active: quat_mi2s_active { 2839 mux { 2840 pins = "gpio58", "gpio59"; 2841 function = "qua_mi2s"; 2842 }; 2843 2844 config { 2845 pins = "gpio58", "gpio59"; 2846 drive-strength = <8>; 2847 bias-disable; 2848 output-high; 2849 }; 2850 }; 2851 2852 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { 2853 mux { 2854 pins = "gpio60"; 2855 function = "gpio"; 2856 }; 2857 2858 config { 2859 pins = "gpio60"; 2860 drive-strength = <2>; 2861 bias-pull-down; 2862 input-enable; 2863 }; 2864 }; 2865 2866 quat_mi2s_sd0_active: quat_mi2s_sd0_active { 2867 mux { 2868 pins = "gpio60"; 2869 function = "qua_mi2s"; 2870 }; 2871 2872 config { 2873 pins = "gpio60"; 2874 drive-strength = <8>; 2875 bias-disable; 2876 }; 2877 }; 2878 2879 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { 2880 mux { 2881 pins = "gpio61"; 2882 function = "gpio"; 2883 }; 2884 2885 config { 2886 pins = "gpio61"; 2887 drive-strength = <2>; 2888 bias-pull-down; 2889 input-enable; 2890 }; 2891 }; 2892 2893 quat_mi2s_sd1_active: quat_mi2s_sd1_active { 2894 mux { 2895 pins = "gpio61"; 2896 function = "qua_mi2s"; 2897 }; 2898 2899 config { 2900 pins = "gpio61"; 2901 drive-strength = <8>; 2902 bias-disable; 2903 }; 2904 }; 2905 2906 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { 2907 mux { 2908 pins = "gpio62"; 2909 function = "gpio"; 2910 }; 2911 2912 config { 2913 pins = "gpio62"; 2914 drive-strength = <2>; 2915 bias-pull-down; 2916 input-enable; 2917 }; 2918 }; 2919 2920 quat_mi2s_sd2_active: quat_mi2s_sd2_active { 2921 mux { 2922 pins = "gpio62"; 2923 function = "qua_mi2s"; 2924 }; 2925 2926 config { 2927 pins = "gpio62"; 2928 drive-strength = <8>; 2929 bias-disable; 2930 }; 2931 }; 2932 2933 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { 2934 mux { 2935 pins = "gpio63"; 2936 function = "gpio"; 2937 }; 2938 2939 config { 2940 pins = "gpio63"; 2941 drive-strength = <2>; 2942 bias-pull-down; 2943 input-enable; 2944 }; 2945 }; 2946 2947 quat_mi2s_sd3_active: quat_mi2s_sd3_active { 2948 mux { 2949 pins = "gpio63"; 2950 function = "qua_mi2s"; 2951 }; 2952 2953 config { 2954 pins = "gpio63"; 2955 drive-strength = <8>; 2956 bias-disable; 2957 }; 2958 }; 2959 }; 2960 2961 mss_pil: remoteproc@4080000 { 2962 compatible = "qcom,sdm845-mss-pil"; 2963 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 2964 reg-names = "qdsp6", "rmb"; 2965 2966 interrupts-extended = 2967 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2968 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2969 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2970 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2971 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2972 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2973 interrupt-names = "wdog", "fatal", "ready", 2974 "handover", "stop-ack", 2975 "shutdown-ack"; 2976 2977 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2978 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 2979 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2980 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 2981 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2982 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 2983 <&gcc GCC_PRNG_AHB_CLK>, 2984 <&rpmhcc RPMH_CXO_CLK>; 2985 clock-names = "iface", "bus", "mem", "gpll0_mss", 2986 "snoc_axi", "mnoc_axi", "prng", "xo"; 2987 2988 qcom,smem-states = <&modem_smp2p_out 0>; 2989 qcom,smem-state-names = "stop"; 2990 2991 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2992 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2993 reset-names = "mss_restart", "pdc_reset"; 2994 2995 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2996 2997 power-domains = <&aoss_qmp 2>, 2998 <&rpmhpd SDM845_CX>, 2999 <&rpmhpd SDM845_MX>, 3000 <&rpmhpd SDM845_MSS>; 3001 power-domain-names = "load_state", "cx", "mx", "mss"; 3002 3003 mba { 3004 memory-region = <&mba_region>; 3005 }; 3006 3007 mpss { 3008 memory-region = <&mpss_region>; 3009 }; 3010 3011 glink-edge { 3012 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 3013 label = "modem"; 3014 qcom,remote-pid = <1>; 3015 mboxes = <&apss_shared 12>; 3016 }; 3017 }; 3018 3019 gpucc: clock-controller@5090000 { 3020 compatible = "qcom,sdm845-gpucc"; 3021 reg = <0 0x05090000 0 0x9000>; 3022 #clock-cells = <1>; 3023 #reset-cells = <1>; 3024 #power-domain-cells = <1>; 3025 clocks = <&rpmhcc RPMH_CXO_CLK>, 3026 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3027 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3028 clock-names = "bi_tcxo", 3029 "gcc_gpu_gpll0_clk_src", 3030 "gcc_gpu_gpll0_div_clk_src"; 3031 }; 3032 3033 stm@6002000 { 3034 compatible = "arm,coresight-stm", "arm,primecell"; 3035 reg = <0 0x06002000 0 0x1000>, 3036 <0 0x16280000 0 0x180000>; 3037 reg-names = "stm-base", "stm-stimulus-base"; 3038 3039 clocks = <&aoss_qmp>; 3040 clock-names = "apb_pclk"; 3041 3042 out-ports { 3043 port { 3044 stm_out: endpoint { 3045 remote-endpoint = 3046 <&funnel0_in7>; 3047 }; 3048 }; 3049 }; 3050 }; 3051 3052 funnel@6041000 { 3053 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3054 reg = <0 0x06041000 0 0x1000>; 3055 3056 clocks = <&aoss_qmp>; 3057 clock-names = "apb_pclk"; 3058 3059 out-ports { 3060 port { 3061 funnel0_out: endpoint { 3062 remote-endpoint = 3063 <&merge_funnel_in0>; 3064 }; 3065 }; 3066 }; 3067 3068 in-ports { 3069 #address-cells = <1>; 3070 #size-cells = <0>; 3071 3072 port@7 { 3073 reg = <7>; 3074 funnel0_in7: endpoint { 3075 remote-endpoint = <&stm_out>; 3076 }; 3077 }; 3078 }; 3079 }; 3080 3081 funnel@6043000 { 3082 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3083 reg = <0 0x06043000 0 0x1000>; 3084 3085 clocks = <&aoss_qmp>; 3086 clock-names = "apb_pclk"; 3087 3088 out-ports { 3089 port { 3090 funnel2_out: endpoint { 3091 remote-endpoint = 3092 <&merge_funnel_in2>; 3093 }; 3094 }; 3095 }; 3096 3097 in-ports { 3098 #address-cells = <1>; 3099 #size-cells = <0>; 3100 3101 port@5 { 3102 reg = <5>; 3103 funnel2_in5: endpoint { 3104 remote-endpoint = 3105 <&apss_merge_funnel_out>; 3106 }; 3107 }; 3108 }; 3109 }; 3110 3111 funnel@6045000 { 3112 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3113 reg = <0 0x06045000 0 0x1000>; 3114 3115 clocks = <&aoss_qmp>; 3116 clock-names = "apb_pclk"; 3117 3118 out-ports { 3119 port { 3120 merge_funnel_out: endpoint { 3121 remote-endpoint = <&etf_in>; 3122 }; 3123 }; 3124 }; 3125 3126 in-ports { 3127 #address-cells = <1>; 3128 #size-cells = <0>; 3129 3130 port@0 { 3131 reg = <0>; 3132 merge_funnel_in0: endpoint { 3133 remote-endpoint = 3134 <&funnel0_out>; 3135 }; 3136 }; 3137 3138 port@2 { 3139 reg = <2>; 3140 merge_funnel_in2: endpoint { 3141 remote-endpoint = 3142 <&funnel2_out>; 3143 }; 3144 }; 3145 }; 3146 }; 3147 3148 replicator@6046000 { 3149 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3150 reg = <0 0x06046000 0 0x1000>; 3151 3152 clocks = <&aoss_qmp>; 3153 clock-names = "apb_pclk"; 3154 3155 out-ports { 3156 port { 3157 replicator_out: endpoint { 3158 remote-endpoint = <&etr_in>; 3159 }; 3160 }; 3161 }; 3162 3163 in-ports { 3164 port { 3165 replicator_in: endpoint { 3166 remote-endpoint = <&etf_out>; 3167 }; 3168 }; 3169 }; 3170 }; 3171 3172 etf@6047000 { 3173 compatible = "arm,coresight-tmc", "arm,primecell"; 3174 reg = <0 0x06047000 0 0x1000>; 3175 3176 clocks = <&aoss_qmp>; 3177 clock-names = "apb_pclk"; 3178 3179 out-ports { 3180 port { 3181 etf_out: endpoint { 3182 remote-endpoint = 3183 <&replicator_in>; 3184 }; 3185 }; 3186 }; 3187 3188 in-ports { 3189 #address-cells = <1>; 3190 #size-cells = <0>; 3191 3192 port@1 { 3193 reg = <1>; 3194 etf_in: endpoint { 3195 remote-endpoint = 3196 <&merge_funnel_out>; 3197 }; 3198 }; 3199 }; 3200 }; 3201 3202 etr@6048000 { 3203 compatible = "arm,coresight-tmc", "arm,primecell"; 3204 reg = <0 0x06048000 0 0x1000>; 3205 3206 clocks = <&aoss_qmp>; 3207 clock-names = "apb_pclk"; 3208 arm,scatter-gather; 3209 3210 in-ports { 3211 port { 3212 etr_in: endpoint { 3213 remote-endpoint = 3214 <&replicator_out>; 3215 }; 3216 }; 3217 }; 3218 }; 3219 3220 etm@7040000 { 3221 compatible = "arm,coresight-etm4x", "arm,primecell"; 3222 reg = <0 0x07040000 0 0x1000>; 3223 3224 cpu = <&CPU0>; 3225 3226 clocks = <&aoss_qmp>; 3227 clock-names = "apb_pclk"; 3228 arm,coresight-loses-context-with-cpu; 3229 3230 out-ports { 3231 port { 3232 etm0_out: endpoint { 3233 remote-endpoint = 3234 <&apss_funnel_in0>; 3235 }; 3236 }; 3237 }; 3238 }; 3239 3240 etm@7140000 { 3241 compatible = "arm,coresight-etm4x", "arm,primecell"; 3242 reg = <0 0x07140000 0 0x1000>; 3243 3244 cpu = <&CPU1>; 3245 3246 clocks = <&aoss_qmp>; 3247 clock-names = "apb_pclk"; 3248 arm,coresight-loses-context-with-cpu; 3249 3250 out-ports { 3251 port { 3252 etm1_out: endpoint { 3253 remote-endpoint = 3254 <&apss_funnel_in1>; 3255 }; 3256 }; 3257 }; 3258 }; 3259 3260 etm@7240000 { 3261 compatible = "arm,coresight-etm4x", "arm,primecell"; 3262 reg = <0 0x07240000 0 0x1000>; 3263 3264 cpu = <&CPU2>; 3265 3266 clocks = <&aoss_qmp>; 3267 clock-names = "apb_pclk"; 3268 arm,coresight-loses-context-with-cpu; 3269 3270 out-ports { 3271 port { 3272 etm2_out: endpoint { 3273 remote-endpoint = 3274 <&apss_funnel_in2>; 3275 }; 3276 }; 3277 }; 3278 }; 3279 3280 etm@7340000 { 3281 compatible = "arm,coresight-etm4x", "arm,primecell"; 3282 reg = <0 0x07340000 0 0x1000>; 3283 3284 cpu = <&CPU3>; 3285 3286 clocks = <&aoss_qmp>; 3287 clock-names = "apb_pclk"; 3288 arm,coresight-loses-context-with-cpu; 3289 3290 out-ports { 3291 port { 3292 etm3_out: endpoint { 3293 remote-endpoint = 3294 <&apss_funnel_in3>; 3295 }; 3296 }; 3297 }; 3298 }; 3299 3300 etm@7440000 { 3301 compatible = "arm,coresight-etm4x", "arm,primecell"; 3302 reg = <0 0x07440000 0 0x1000>; 3303 3304 cpu = <&CPU4>; 3305 3306 clocks = <&aoss_qmp>; 3307 clock-names = "apb_pclk"; 3308 arm,coresight-loses-context-with-cpu; 3309 3310 out-ports { 3311 port { 3312 etm4_out: endpoint { 3313 remote-endpoint = 3314 <&apss_funnel_in4>; 3315 }; 3316 }; 3317 }; 3318 }; 3319 3320 etm@7540000 { 3321 compatible = "arm,coresight-etm4x", "arm,primecell"; 3322 reg = <0 0x07540000 0 0x1000>; 3323 3324 cpu = <&CPU5>; 3325 3326 clocks = <&aoss_qmp>; 3327 clock-names = "apb_pclk"; 3328 arm,coresight-loses-context-with-cpu; 3329 3330 out-ports { 3331 port { 3332 etm5_out: endpoint { 3333 remote-endpoint = 3334 <&apss_funnel_in5>; 3335 }; 3336 }; 3337 }; 3338 }; 3339 3340 etm@7640000 { 3341 compatible = "arm,coresight-etm4x", "arm,primecell"; 3342 reg = <0 0x07640000 0 0x1000>; 3343 3344 cpu = <&CPU6>; 3345 3346 clocks = <&aoss_qmp>; 3347 clock-names = "apb_pclk"; 3348 arm,coresight-loses-context-with-cpu; 3349 3350 out-ports { 3351 port { 3352 etm6_out: endpoint { 3353 remote-endpoint = 3354 <&apss_funnel_in6>; 3355 }; 3356 }; 3357 }; 3358 }; 3359 3360 etm@7740000 { 3361 compatible = "arm,coresight-etm4x", "arm,primecell"; 3362 reg = <0 0x07740000 0 0x1000>; 3363 3364 cpu = <&CPU7>; 3365 3366 clocks = <&aoss_qmp>; 3367 clock-names = "apb_pclk"; 3368 arm,coresight-loses-context-with-cpu; 3369 3370 out-ports { 3371 port { 3372 etm7_out: endpoint { 3373 remote-endpoint = 3374 <&apss_funnel_in7>; 3375 }; 3376 }; 3377 }; 3378 }; 3379 3380 funnel@7800000 { /* APSS Funnel */ 3381 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3382 reg = <0 0x07800000 0 0x1000>; 3383 3384 clocks = <&aoss_qmp>; 3385 clock-names = "apb_pclk"; 3386 3387 out-ports { 3388 port { 3389 apss_funnel_out: endpoint { 3390 remote-endpoint = 3391 <&apss_merge_funnel_in>; 3392 }; 3393 }; 3394 }; 3395 3396 in-ports { 3397 #address-cells = <1>; 3398 #size-cells = <0>; 3399 3400 port@0 { 3401 reg = <0>; 3402 apss_funnel_in0: endpoint { 3403 remote-endpoint = 3404 <&etm0_out>; 3405 }; 3406 }; 3407 3408 port@1 { 3409 reg = <1>; 3410 apss_funnel_in1: endpoint { 3411 remote-endpoint = 3412 <&etm1_out>; 3413 }; 3414 }; 3415 3416 port@2 { 3417 reg = <2>; 3418 apss_funnel_in2: endpoint { 3419 remote-endpoint = 3420 <&etm2_out>; 3421 }; 3422 }; 3423 3424 port@3 { 3425 reg = <3>; 3426 apss_funnel_in3: endpoint { 3427 remote-endpoint = 3428 <&etm3_out>; 3429 }; 3430 }; 3431 3432 port@4 { 3433 reg = <4>; 3434 apss_funnel_in4: endpoint { 3435 remote-endpoint = 3436 <&etm4_out>; 3437 }; 3438 }; 3439 3440 port@5 { 3441 reg = <5>; 3442 apss_funnel_in5: endpoint { 3443 remote-endpoint = 3444 <&etm5_out>; 3445 }; 3446 }; 3447 3448 port@6 { 3449 reg = <6>; 3450 apss_funnel_in6: endpoint { 3451 remote-endpoint = 3452 <&etm6_out>; 3453 }; 3454 }; 3455 3456 port@7 { 3457 reg = <7>; 3458 apss_funnel_in7: endpoint { 3459 remote-endpoint = 3460 <&etm7_out>; 3461 }; 3462 }; 3463 }; 3464 }; 3465 3466 funnel@7810000 { 3467 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3468 reg = <0 0x07810000 0 0x1000>; 3469 3470 clocks = <&aoss_qmp>; 3471 clock-names = "apb_pclk"; 3472 3473 out-ports { 3474 port { 3475 apss_merge_funnel_out: endpoint { 3476 remote-endpoint = 3477 <&funnel2_in5>; 3478 }; 3479 }; 3480 }; 3481 3482 in-ports { 3483 port { 3484 apss_merge_funnel_in: endpoint { 3485 remote-endpoint = 3486 <&apss_funnel_out>; 3487 }; 3488 }; 3489 }; 3490 }; 3491 3492 sdhc_2: sdhci@8804000 { 3493 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 3494 reg = <0 0x08804000 0 0x1000>; 3495 3496 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3498 interrupt-names = "hc_irq", "pwr_irq"; 3499 3500 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3501 <&gcc GCC_SDCC2_APPS_CLK>; 3502 clock-names = "iface", "core"; 3503 iommus = <&apps_smmu 0xa0 0xf>; 3504 power-domains = <&rpmhpd SDM845_CX>; 3505 operating-points-v2 = <&sdhc2_opp_table>; 3506 3507 status = "disabled"; 3508 3509 sdhc2_opp_table: sdhc2-opp-table { 3510 compatible = "operating-points-v2"; 3511 3512 opp-9600000 { 3513 opp-hz = /bits/ 64 <9600000>; 3514 required-opps = <&rpmhpd_opp_min_svs>; 3515 }; 3516 3517 opp-19200000 { 3518 opp-hz = /bits/ 64 <19200000>; 3519 required-opps = <&rpmhpd_opp_low_svs>; 3520 }; 3521 3522 opp-100000000 { 3523 opp-hz = /bits/ 64 <100000000>; 3524 required-opps = <&rpmhpd_opp_svs>; 3525 }; 3526 3527 opp-201500000 { 3528 opp-hz = /bits/ 64 <201500000>; 3529 required-opps = <&rpmhpd_opp_svs_l1>; 3530 }; 3531 }; 3532 }; 3533 3534 qspi_opp_table: qspi-opp-table { 3535 compatible = "operating-points-v2"; 3536 3537 opp-19200000 { 3538 opp-hz = /bits/ 64 <19200000>; 3539 required-opps = <&rpmhpd_opp_min_svs>; 3540 }; 3541 3542 opp-100000000 { 3543 opp-hz = /bits/ 64 <100000000>; 3544 required-opps = <&rpmhpd_opp_low_svs>; 3545 }; 3546 3547 opp-150000000 { 3548 opp-hz = /bits/ 64 <150000000>; 3549 required-opps = <&rpmhpd_opp_svs>; 3550 }; 3551 3552 opp-300000000 { 3553 opp-hz = /bits/ 64 <300000000>; 3554 required-opps = <&rpmhpd_opp_nom>; 3555 }; 3556 }; 3557 3558 qspi: spi@88df000 { 3559 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 3560 reg = <0 0x088df000 0 0x600>; 3561 #address-cells = <1>; 3562 #size-cells = <0>; 3563 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3564 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3565 <&gcc GCC_QSPI_CORE_CLK>; 3566 clock-names = "iface", "core"; 3567 power-domains = <&rpmhpd SDM845_CX>; 3568 operating-points-v2 = <&qspi_opp_table>; 3569 status = "disabled"; 3570 }; 3571 3572 slim: slim@171c0000 { 3573 compatible = "qcom,slim-ngd-v2.1.0"; 3574 reg = <0 0x171c0000 0 0x2c000>; 3575 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3576 3577 qcom,apps-ch-pipes = <0x780000>; 3578 qcom,ea-pc = <0x270>; 3579 status = "okay"; 3580 dmas = <&slimbam 3>, <&slimbam 4>, 3581 <&slimbam 5>, <&slimbam 6>; 3582 dma-names = "rx", "tx", "tx2", "rx2"; 3583 3584 iommus = <&apps_smmu 0x1806 0x0>; 3585 #address-cells = <1>; 3586 #size-cells = <0>; 3587 3588 ngd@1 { 3589 reg = <1>; 3590 #address-cells = <2>; 3591 #size-cells = <0>; 3592 3593 wcd9340_ifd: ifd@0{ 3594 compatible = "slim217,250"; 3595 reg = <0 0>; 3596 }; 3597 3598 wcd9340: codec@1{ 3599 compatible = "slim217,250"; 3600 reg = <1 0>; 3601 slim-ifc-dev = <&wcd9340_ifd>; 3602 3603 #sound-dai-cells = <1>; 3604 3605 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; 3606 interrupt-controller; 3607 #interrupt-cells = <1>; 3608 3609 #clock-cells = <0>; 3610 clock-frequency = <9600000>; 3611 clock-output-names = "mclk"; 3612 qcom,micbias1-microvolt = <1800000>; 3613 qcom,micbias2-microvolt = <1800000>; 3614 qcom,micbias3-microvolt = <1800000>; 3615 qcom,micbias4-microvolt = <1800000>; 3616 3617 #address-cells = <1>; 3618 #size-cells = <1>; 3619 3620 wcdgpio: gpio-controller@42 { 3621 compatible = "qcom,wcd9340-gpio"; 3622 gpio-controller; 3623 #gpio-cells = <2>; 3624 reg = <0x42 0x2>; 3625 }; 3626 3627 swm: swm@c85 { 3628 compatible = "qcom,soundwire-v1.3.0"; 3629 reg = <0xc85 0x40>; 3630 interrupts-extended = <&wcd9340 20>; 3631 3632 qcom,dout-ports = <6>; 3633 qcom,din-ports = <2>; 3634 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; 3635 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; 3636 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; 3637 3638 #sound-dai-cells = <1>; 3639 clocks = <&wcd9340>; 3640 clock-names = "iface"; 3641 #address-cells = <2>; 3642 #size-cells = <0>; 3643 3644 3645 }; 3646 }; 3647 }; 3648 }; 3649 3650 sound: sound { 3651 }; 3652 3653 usb_1_hsphy: phy@88e2000 { 3654 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3655 reg = <0 0x088e2000 0 0x400>; 3656 status = "disabled"; 3657 #phy-cells = <0>; 3658 3659 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3660 <&rpmhcc RPMH_CXO_CLK>; 3661 clock-names = "cfg_ahb", "ref"; 3662 3663 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3664 3665 nvmem-cells = <&qusb2p_hstx_trim>; 3666 }; 3667 3668 usb_2_hsphy: phy@88e3000 { 3669 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; 3670 reg = <0 0x088e3000 0 0x400>; 3671 status = "disabled"; 3672 #phy-cells = <0>; 3673 3674 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3675 <&rpmhcc RPMH_CXO_CLK>; 3676 clock-names = "cfg_ahb", "ref"; 3677 3678 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3679 3680 nvmem-cells = <&qusb2s_hstx_trim>; 3681 }; 3682 3683 usb_1_qmpphy: phy@88e9000 { 3684 compatible = "qcom,sdm845-qmp-usb3-phy"; 3685 reg = <0 0x088e9000 0 0x18c>, 3686 <0 0x088e8000 0 0x10>; 3687 reg-names = "reg-base", "dp_com"; 3688 status = "disabled"; 3689 #address-cells = <2>; 3690 #size-cells = <2>; 3691 ranges; 3692 3693 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3694 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3695 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3696 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3697 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3698 3699 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3700 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3701 reset-names = "phy", "common"; 3702 3703 usb_1_ssphy: phy@88e9200 { 3704 reg = <0 0x088e9200 0 0x128>, 3705 <0 0x088e9400 0 0x200>, 3706 <0 0x088e9c00 0 0x218>, 3707 <0 0x088e9600 0 0x128>, 3708 <0 0x088e9800 0 0x200>, 3709 <0 0x088e9a00 0 0x100>; 3710 #clock-cells = <0>; 3711 #phy-cells = <0>; 3712 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3713 clock-names = "pipe0"; 3714 clock-output-names = "usb3_phy_pipe_clk_src"; 3715 }; 3716 }; 3717 3718 usb_2_qmpphy: phy@88eb000 { 3719 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 3720 reg = <0 0x088eb000 0 0x18c>; 3721 status = "disabled"; 3722 #address-cells = <2>; 3723 #size-cells = <2>; 3724 ranges; 3725 3726 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3727 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3728 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3729 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3730 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 3731 3732 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3733 <&gcc GCC_USB3_PHY_SEC_BCR>; 3734 reset-names = "phy", "common"; 3735 3736 usb_2_ssphy: phy@88eb200 { 3737 reg = <0 0x088eb200 0 0x128>, 3738 <0 0x088eb400 0 0x1fc>, 3739 <0 0x088eb800 0 0x218>, 3740 <0 0x088eb600 0 0x70>; 3741 #clock-cells = <0>; 3742 #phy-cells = <0>; 3743 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3744 clock-names = "pipe0"; 3745 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3746 }; 3747 }; 3748 3749 usb_1: usb@a6f8800 { 3750 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3751 reg = <0 0x0a6f8800 0 0x400>; 3752 status = "disabled"; 3753 #address-cells = <2>; 3754 #size-cells = <2>; 3755 ranges; 3756 dma-ranges; 3757 3758 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3759 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3760 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3761 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3762 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 3763 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3764 "sleep"; 3765 3766 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3767 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3768 assigned-clock-rates = <19200000>, <150000000>; 3769 3770 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3771 <&intc GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 3772 <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>, 3773 <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>; 3774 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3775 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3776 3777 power-domains = <&gcc USB30_PRIM_GDSC>; 3778 3779 resets = <&gcc GCC_USB30_PRIM_BCR>; 3780 3781 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, 3782 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3783 interconnect-names = "usb-ddr", "apps-usb"; 3784 3785 usb_1_dwc3: dwc3@a600000 { 3786 compatible = "snps,dwc3"; 3787 reg = <0 0x0a600000 0 0xcd00>; 3788 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3789 iommus = <&apps_smmu 0x740 0>; 3790 snps,dis_u2_susphy_quirk; 3791 snps,dis_enblslpm_quirk; 3792 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3793 phy-names = "usb2-phy", "usb3-phy"; 3794 }; 3795 }; 3796 3797 usb_2: usb@a8f8800 { 3798 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 3799 reg = <0 0x0a8f8800 0 0x400>; 3800 status = "disabled"; 3801 #address-cells = <2>; 3802 #size-cells = <2>; 3803 ranges; 3804 dma-ranges; 3805 3806 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3807 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3808 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3809 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3810 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 3811 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 3812 "sleep"; 3813 3814 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3815 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3816 assigned-clock-rates = <19200000>, <150000000>; 3817 3818 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3819 <&intc GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 3820 <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>, 3821 <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>; 3822 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3823 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3824 3825 power-domains = <&gcc USB30_SEC_GDSC>; 3826 3827 resets = <&gcc GCC_USB30_SEC_BCR>; 3828 3829 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, 3830 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3831 interconnect-names = "usb-ddr", "apps-usb"; 3832 3833 usb_2_dwc3: dwc3@a800000 { 3834 compatible = "snps,dwc3"; 3835 reg = <0 0x0a800000 0 0xcd00>; 3836 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3837 iommus = <&apps_smmu 0x760 0>; 3838 snps,dis_u2_susphy_quirk; 3839 snps,dis_enblslpm_quirk; 3840 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3841 phy-names = "usb2-phy", "usb3-phy"; 3842 }; 3843 }; 3844 3845 venus: video-codec@aa00000 { 3846 compatible = "qcom,sdm845-venus-v2"; 3847 reg = <0 0x0aa00000 0 0xff000>; 3848 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3849 power-domains = <&videocc VENUS_GDSC>, 3850 <&videocc VCODEC0_GDSC>, 3851 <&videocc VCODEC1_GDSC>, 3852 <&rpmhpd SDM845_CX>; 3853 power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; 3854 operating-points-v2 = <&venus_opp_table>; 3855 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3856 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3857 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3858 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3859 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>, 3860 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 3861 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 3862 clock-names = "core", "iface", "bus", 3863 "vcodec0_core", "vcodec0_bus", 3864 "vcodec1_core", "vcodec1_bus"; 3865 iommus = <&apps_smmu 0x10a0 0x8>, 3866 <&apps_smmu 0x10b0 0x0>; 3867 memory-region = <&venus_mem>; 3868 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, 3869 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 3870 interconnect-names = "video-mem", "cpu-cfg"; 3871 3872 video-core0 { 3873 compatible = "venus-decoder"; 3874 }; 3875 3876 video-core1 { 3877 compatible = "venus-encoder"; 3878 }; 3879 3880 venus_opp_table: venus-opp-table { 3881 compatible = "operating-points-v2"; 3882 3883 opp-100000000 { 3884 opp-hz = /bits/ 64 <100000000>; 3885 required-opps = <&rpmhpd_opp_min_svs>; 3886 }; 3887 3888 opp-200000000 { 3889 opp-hz = /bits/ 64 <200000000>; 3890 required-opps = <&rpmhpd_opp_low_svs>; 3891 }; 3892 3893 opp-320000000 { 3894 opp-hz = /bits/ 64 <320000000>; 3895 required-opps = <&rpmhpd_opp_svs>; 3896 }; 3897 3898 opp-380000000 { 3899 opp-hz = /bits/ 64 <380000000>; 3900 required-opps = <&rpmhpd_opp_svs_l1>; 3901 }; 3902 3903 opp-444000000 { 3904 opp-hz = /bits/ 64 <444000000>; 3905 required-opps = <&rpmhpd_opp_nom>; 3906 }; 3907 3908 opp-533000097 { 3909 opp-hz = /bits/ 64 <533000097>; 3910 required-opps = <&rpmhpd_opp_turbo>; 3911 }; 3912 }; 3913 }; 3914 3915 videocc: clock-controller@ab00000 { 3916 compatible = "qcom,sdm845-videocc"; 3917 reg = <0 0x0ab00000 0 0x10000>; 3918 clocks = <&rpmhcc RPMH_CXO_CLK>; 3919 clock-names = "bi_tcxo"; 3920 #clock-cells = <1>; 3921 #power-domain-cells = <1>; 3922 #reset-cells = <1>; 3923 }; 3924 3925 camss: camss@acb3000 { 3926 compatible = "qcom,sdm845-camss"; 3927 3928 reg = <0 0xacb3000 0 0x1000>, 3929 <0 0xacba000 0 0x1000>, 3930 <0 0xacc8000 0 0x1000>, 3931 <0 0xac65000 0 0x1000>, 3932 <0 0xac66000 0 0x1000>, 3933 <0 0xac67000 0 0x1000>, 3934 <0 0xac68000 0 0x1000>, 3935 <0 0xacaf000 0 0x4000>, 3936 <0 0xacb6000 0 0x4000>, 3937 <0 0xacc4000 0 0x4000>; 3938 reg-names = "csid0", 3939 "csid1", 3940 "csid2", 3941 "csiphy0", 3942 "csiphy1", 3943 "csiphy2", 3944 "csiphy3", 3945 "vfe0", 3946 "vfe1", 3947 "vfe_lite"; 3948 3949 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3950 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3951 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3952 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 3953 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 3954 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 3955 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 3956 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3957 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3958 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 3959 interrupt-names = "csid0", 3960 "csid1", 3961 "csid2", 3962 "csiphy0", 3963 "csiphy1", 3964 "csiphy2", 3965 "csiphy3", 3966 "vfe0", 3967 "vfe1", 3968 "vfe_lite"; 3969 3970 power-domains = <&clock_camcc IFE_0_GDSC>, 3971 <&clock_camcc IFE_1_GDSC>, 3972 <&clock_camcc TITAN_TOP_GDSC>; 3973 3974 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 3975 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 3976 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, 3977 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, 3978 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, 3979 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, 3980 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, 3981 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, 3982 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, 3983 <&clock_camcc CAM_CC_CSIPHY0_CLK>, 3984 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, 3985 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, 3986 <&clock_camcc CAM_CC_CSIPHY1_CLK>, 3987 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, 3988 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, 3989 <&clock_camcc CAM_CC_CSIPHY2_CLK>, 3990 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, 3991 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, 3992 <&clock_camcc CAM_CC_CSIPHY3_CLK>, 3993 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, 3994 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, 3995 <&gcc GCC_CAMERA_AHB_CLK>, 3996 <&gcc GCC_CAMERA_AXI_CLK>, 3997 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3998 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 3999 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, 4000 <&clock_camcc CAM_CC_IFE_0_CLK>, 4001 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4002 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, 4003 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, 4004 <&clock_camcc CAM_CC_IFE_1_CLK>, 4005 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4006 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, 4007 <&clock_camcc CAM_CC_IFE_LITE_CLK>, 4008 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4009 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>; 4010 clock-names = "camnoc_axi", 4011 "cpas_ahb", 4012 "cphy_rx_src", 4013 "csi0", 4014 "csi0_src", 4015 "csi1", 4016 "csi1_src", 4017 "csi2", 4018 "csi2_src", 4019 "csiphy0", 4020 "csiphy0_timer", 4021 "csiphy0_timer_src", 4022 "csiphy1", 4023 "csiphy1_timer", 4024 "csiphy1_timer_src", 4025 "csiphy2", 4026 "csiphy2_timer", 4027 "csiphy2_timer_src", 4028 "csiphy3", 4029 "csiphy3_timer", 4030 "csiphy3_timer_src", 4031 "gcc_camera_ahb", 4032 "gcc_camera_axi", 4033 "slow_ahb_src", 4034 "soc_ahb", 4035 "vfe0_axi", 4036 "vfe0", 4037 "vfe0_cphy_rx", 4038 "vfe0_src", 4039 "vfe1_axi", 4040 "vfe1", 4041 "vfe1_cphy_rx", 4042 "vfe1_src", 4043 "vfe_lite", 4044 "vfe_lite_cphy_rx", 4045 "vfe_lite_src"; 4046 4047 iommus = <&apps_smmu 0x0808 0x0>, 4048 <&apps_smmu 0x0810 0x8>, 4049 <&apps_smmu 0x0c08 0x0>, 4050 <&apps_smmu 0x0c10 0x8>; 4051 4052 status = "disabled"; 4053 4054 ports { 4055 #address-cells = <1>; 4056 #size-cells = <0>; 4057 }; 4058 }; 4059 4060 cci: cci@ac4a000 { 4061 compatible = "qcom,sdm845-cci"; 4062 #address-cells = <1>; 4063 #size-cells = <0>; 4064 4065 reg = <0 0x0ac4a000 0 0x4000>; 4066 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4067 power-domains = <&clock_camcc TITAN_TOP_GDSC>; 4068 4069 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4070 <&clock_camcc CAM_CC_SOC_AHB_CLK>, 4071 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4072 <&clock_camcc CAM_CC_CPAS_AHB_CLK>, 4073 <&clock_camcc CAM_CC_CCI_CLK>, 4074 <&clock_camcc CAM_CC_CCI_CLK_SRC>; 4075 clock-names = "camnoc_axi", 4076 "soc_ahb", 4077 "slow_ahb_src", 4078 "cpas_ahb", 4079 "cci", 4080 "cci_src"; 4081 4082 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, 4083 <&clock_camcc CAM_CC_CCI_CLK>; 4084 assigned-clock-rates = <80000000>, <37500000>; 4085 4086 pinctrl-names = "default", "sleep"; 4087 pinctrl-0 = <&cci0_default &cci1_default>; 4088 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4089 4090 status = "disabled"; 4091 4092 cci_i2c0: i2c-bus@0 { 4093 reg = <0>; 4094 clock-frequency = <1000000>; 4095 #address-cells = <1>; 4096 #size-cells = <0>; 4097 }; 4098 4099 cci_i2c1: i2c-bus@1 { 4100 reg = <1>; 4101 clock-frequency = <1000000>; 4102 #address-cells = <1>; 4103 #size-cells = <0>; 4104 }; 4105 }; 4106 4107 clock_camcc: clock-controller@ad00000 { 4108 compatible = "qcom,sdm845-camcc"; 4109 reg = <0 0x0ad00000 0 0x10000>; 4110 #clock-cells = <1>; 4111 #reset-cells = <1>; 4112 #power-domain-cells = <1>; 4113 }; 4114 4115 dsi_opp_table: dsi-opp-table { 4116 compatible = "operating-points-v2"; 4117 4118 opp-19200000 { 4119 opp-hz = /bits/ 64 <19200000>; 4120 required-opps = <&rpmhpd_opp_min_svs>; 4121 }; 4122 4123 opp-180000000 { 4124 opp-hz = /bits/ 64 <180000000>; 4125 required-opps = <&rpmhpd_opp_low_svs>; 4126 }; 4127 4128 opp-275000000 { 4129 opp-hz = /bits/ 64 <275000000>; 4130 required-opps = <&rpmhpd_opp_svs>; 4131 }; 4132 4133 opp-328580000 { 4134 opp-hz = /bits/ 64 <328580000>; 4135 required-opps = <&rpmhpd_opp_svs_l1>; 4136 }; 4137 4138 opp-358000000 { 4139 opp-hz = /bits/ 64 <358000000>; 4140 required-opps = <&rpmhpd_opp_nom>; 4141 }; 4142 }; 4143 4144 mdss: mdss@ae00000 { 4145 compatible = "qcom,sdm845-mdss"; 4146 reg = <0 0x0ae00000 0 0x1000>; 4147 reg-names = "mdss"; 4148 4149 power-domains = <&dispcc MDSS_GDSC>; 4150 4151 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4152 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4153 clock-names = "iface", "core"; 4154 4155 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 4156 assigned-clock-rates = <300000000>; 4157 4158 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4159 interrupt-controller; 4160 #interrupt-cells = <1>; 4161 4162 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, 4163 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; 4164 interconnect-names = "mdp0-mem", "mdp1-mem"; 4165 4166 iommus = <&apps_smmu 0x880 0x8>, 4167 <&apps_smmu 0xc80 0x8>; 4168 4169 status = "disabled"; 4170 4171 #address-cells = <2>; 4172 #size-cells = <2>; 4173 ranges; 4174 4175 mdss_mdp: mdp@ae01000 { 4176 compatible = "qcom,sdm845-dpu"; 4177 reg = <0 0x0ae01000 0 0x8f000>, 4178 <0 0x0aeb0000 0 0x2008>; 4179 reg-names = "mdp", "vbif"; 4180 4181 clocks = <&gcc GCC_DISP_AXI_CLK>, 4182 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4183 <&dispcc DISP_CC_MDSS_AXI_CLK>, 4184 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4185 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4186 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 4187 4188 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 4189 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4190 assigned-clock-rates = <300000000>, 4191 <19200000>; 4192 operating-points-v2 = <&mdp_opp_table>; 4193 power-domains = <&rpmhpd SDM845_CX>; 4194 4195 interrupt-parent = <&mdss>; 4196 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 4197 4198 status = "disabled"; 4199 4200 ports { 4201 #address-cells = <1>; 4202 #size-cells = <0>; 4203 4204 port@0 { 4205 reg = <0>; 4206 dpu_intf1_out: endpoint { 4207 remote-endpoint = <&dsi0_in>; 4208 }; 4209 }; 4210 4211 port@1 { 4212 reg = <1>; 4213 dpu_intf2_out: endpoint { 4214 remote-endpoint = <&dsi1_in>; 4215 }; 4216 }; 4217 }; 4218 4219 mdp_opp_table: mdp-opp-table { 4220 compatible = "operating-points-v2"; 4221 4222 opp-19200000 { 4223 opp-hz = /bits/ 64 <19200000>; 4224 required-opps = <&rpmhpd_opp_min_svs>; 4225 }; 4226 4227 opp-171428571 { 4228 opp-hz = /bits/ 64 <171428571>; 4229 required-opps = <&rpmhpd_opp_low_svs>; 4230 }; 4231 4232 opp-344000000 { 4233 opp-hz = /bits/ 64 <344000000>; 4234 required-opps = <&rpmhpd_opp_svs_l1>; 4235 }; 4236 4237 opp-430000000 { 4238 opp-hz = /bits/ 64 <430000000>; 4239 required-opps = <&rpmhpd_opp_nom>; 4240 }; 4241 }; 4242 }; 4243 4244 dsi0: dsi@ae94000 { 4245 compatible = "qcom,mdss-dsi-ctrl"; 4246 reg = <0 0x0ae94000 0 0x400>; 4247 reg-names = "dsi_ctrl"; 4248 4249 interrupt-parent = <&mdss>; 4250 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 4251 4252 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4253 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4254 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4255 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4256 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4257 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4258 clock-names = "byte", 4259 "byte_intf", 4260 "pixel", 4261 "core", 4262 "iface", 4263 "bus"; 4264 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4265 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 4266 4267 operating-points-v2 = <&dsi_opp_table>; 4268 power-domains = <&rpmhpd SDM845_CX>; 4269 4270 phys = <&dsi0_phy>; 4271 phy-names = "dsi"; 4272 4273 status = "disabled"; 4274 4275 ports { 4276 #address-cells = <1>; 4277 #size-cells = <0>; 4278 4279 port@0 { 4280 reg = <0>; 4281 dsi0_in: endpoint { 4282 remote-endpoint = <&dpu_intf1_out>; 4283 }; 4284 }; 4285 4286 port@1 { 4287 reg = <1>; 4288 dsi0_out: endpoint { 4289 }; 4290 }; 4291 }; 4292 }; 4293 4294 dsi0_phy: dsi-phy@ae94400 { 4295 compatible = "qcom,dsi-phy-10nm"; 4296 reg = <0 0x0ae94400 0 0x200>, 4297 <0 0x0ae94600 0 0x280>, 4298 <0 0x0ae94a00 0 0x1e0>; 4299 reg-names = "dsi_phy", 4300 "dsi_phy_lane", 4301 "dsi_pll"; 4302 4303 #clock-cells = <1>; 4304 #phy-cells = <0>; 4305 4306 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4307 <&rpmhcc RPMH_CXO_CLK>; 4308 clock-names = "iface", "ref"; 4309 4310 status = "disabled"; 4311 }; 4312 4313 dsi1: dsi@ae96000 { 4314 compatible = "qcom,mdss-dsi-ctrl"; 4315 reg = <0 0x0ae96000 0 0x400>; 4316 reg-names = "dsi_ctrl"; 4317 4318 interrupt-parent = <&mdss>; 4319 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 4320 4321 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4322 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4323 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4324 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4325 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4326 <&dispcc DISP_CC_MDSS_AXI_CLK>; 4327 clock-names = "byte", 4328 "byte_intf", 4329 "pixel", 4330 "core", 4331 "iface", 4332 "bus"; 4333 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4334 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 4335 4336 operating-points-v2 = <&dsi_opp_table>; 4337 power-domains = <&rpmhpd SDM845_CX>; 4338 4339 phys = <&dsi1_phy>; 4340 phy-names = "dsi"; 4341 4342 status = "disabled"; 4343 4344 ports { 4345 #address-cells = <1>; 4346 #size-cells = <0>; 4347 4348 port@0 { 4349 reg = <0>; 4350 dsi1_in: endpoint { 4351 remote-endpoint = <&dpu_intf2_out>; 4352 }; 4353 }; 4354 4355 port@1 { 4356 reg = <1>; 4357 dsi1_out: endpoint { 4358 }; 4359 }; 4360 }; 4361 }; 4362 4363 dsi1_phy: dsi-phy@ae96400 { 4364 compatible = "qcom,dsi-phy-10nm"; 4365 reg = <0 0x0ae96400 0 0x200>, 4366 <0 0x0ae96600 0 0x280>, 4367 <0 0x0ae96a00 0 0x10e>; 4368 reg-names = "dsi_phy", 4369 "dsi_phy_lane", 4370 "dsi_pll"; 4371 4372 #clock-cells = <1>; 4373 #phy-cells = <0>; 4374 4375 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4376 <&rpmhcc RPMH_CXO_CLK>; 4377 clock-names = "iface", "ref"; 4378 4379 status = "disabled"; 4380 }; 4381 }; 4382 4383 gpu: gpu@5000000 { 4384 compatible = "qcom,adreno-630.2", "qcom,adreno"; 4385 #stream-id-cells = <16>; 4386 4387 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; 4388 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 4389 4390 /* 4391 * Look ma, no clocks! The GPU clocks and power are 4392 * controlled entirely by the GMU 4393 */ 4394 4395 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4396 4397 iommus = <&adreno_smmu 0>; 4398 4399 operating-points-v2 = <&gpu_opp_table>; 4400 4401 qcom,gmu = <&gmu>; 4402 4403 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; 4404 interconnect-names = "gfx-mem"; 4405 4406 gpu_opp_table: opp-table { 4407 compatible = "operating-points-v2"; 4408 4409 opp-710000000 { 4410 opp-hz = /bits/ 64 <710000000>; 4411 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4412 opp-peak-kBps = <7216000>; 4413 }; 4414 4415 opp-675000000 { 4416 opp-hz = /bits/ 64 <675000000>; 4417 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4418 opp-peak-kBps = <7216000>; 4419 }; 4420 4421 opp-596000000 { 4422 opp-hz = /bits/ 64 <596000000>; 4423 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4424 opp-peak-kBps = <6220000>; 4425 }; 4426 4427 opp-520000000 { 4428 opp-hz = /bits/ 64 <520000000>; 4429 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4430 opp-peak-kBps = <6220000>; 4431 }; 4432 4433 opp-414000000 { 4434 opp-hz = /bits/ 64 <414000000>; 4435 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4436 opp-peak-kBps = <4068000>; 4437 }; 4438 4439 opp-342000000 { 4440 opp-hz = /bits/ 64 <342000000>; 4441 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4442 opp-peak-kBps = <2724000>; 4443 }; 4444 4445 opp-257000000 { 4446 opp-hz = /bits/ 64 <257000000>; 4447 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4448 opp-peak-kBps = <1648000>; 4449 }; 4450 }; 4451 }; 4452 4453 adreno_smmu: iommu@5040000 { 4454 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 4455 reg = <0 0x5040000 0 0x10000>; 4456 #iommu-cells = <1>; 4457 #global-interrupts = <2>; 4458 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 4459 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 4460 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 4461 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 4462 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 4463 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 4464 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 4465 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 4466 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 4467 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 4468 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4469 <&gcc GCC_GPU_CFG_AHB_CLK>; 4470 clock-names = "bus", "iface"; 4471 4472 power-domains = <&gpucc GPU_CX_GDSC>; 4473 }; 4474 4475 gmu: gmu@506a000 { 4476 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 4477 4478 reg = <0 0x506a000 0 0x30000>, 4479 <0 0xb280000 0 0x10000>, 4480 <0 0xb480000 0 0x10000>; 4481 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 4482 4483 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4484 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4485 interrupt-names = "hfi", "gmu"; 4486 4487 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4488 <&gpucc GPU_CC_CXO_CLK>, 4489 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4490 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 4491 clock-names = "gmu", "cxo", "axi", "memnoc"; 4492 4493 power-domains = <&gpucc GPU_CX_GDSC>, 4494 <&gpucc GPU_GX_GDSC>; 4495 power-domain-names = "cx", "gx"; 4496 4497 iommus = <&adreno_smmu 5>; 4498 4499 operating-points-v2 = <&gmu_opp_table>; 4500 4501 gmu_opp_table: opp-table { 4502 compatible = "operating-points-v2"; 4503 4504 opp-400000000 { 4505 opp-hz = /bits/ 64 <400000000>; 4506 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4507 }; 4508 4509 opp-200000000 { 4510 opp-hz = /bits/ 64 <200000000>; 4511 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4512 }; 4513 }; 4514 }; 4515 4516 dispcc: clock-controller@af00000 { 4517 compatible = "qcom,sdm845-dispcc"; 4518 reg = <0 0x0af00000 0 0x10000>; 4519 clocks = <&rpmhcc RPMH_CXO_CLK>, 4520 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4521 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4522 <&dsi0_phy 0>, 4523 <&dsi0_phy 1>, 4524 <&dsi1_phy 0>, 4525 <&dsi1_phy 1>, 4526 <0>, 4527 <0>; 4528 clock-names = "bi_tcxo", 4529 "gcc_disp_gpll0_clk_src", 4530 "gcc_disp_gpll0_div_clk_src", 4531 "dsi0_phy_pll_out_byteclk", 4532 "dsi0_phy_pll_out_dsiclk", 4533 "dsi1_phy_pll_out_byteclk", 4534 "dsi1_phy_pll_out_dsiclk", 4535 "dp_link_clk_divsel_ten", 4536 "dp_vco_divided_clk_src_mux"; 4537 #clock-cells = <1>; 4538 #reset-cells = <1>; 4539 #power-domain-cells = <1>; 4540 }; 4541 4542 pdc_intc: interrupt-controller@b220000 { 4543 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 4544 reg = <0 0x0b220000 0 0x30000>; 4545 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 4546 #interrupt-cells = <2>; 4547 interrupt-parent = <&intc>; 4548 interrupt-controller; 4549 }; 4550 4551 pdc_reset: reset-controller@b2e0000 { 4552 compatible = "qcom,sdm845-pdc-global"; 4553 reg = <0 0x0b2e0000 0 0x20000>; 4554 #reset-cells = <1>; 4555 }; 4556 4557 tsens0: thermal-sensor@c263000 { 4558 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4559 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4560 <0 0x0c222000 0 0x1ff>; /* SROT */ 4561 #qcom,sensors = <13>; 4562 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4563 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4564 interrupt-names = "uplow", "critical"; 4565 #thermal-sensor-cells = <1>; 4566 }; 4567 4568 tsens1: thermal-sensor@c265000 { 4569 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 4570 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4571 <0 0x0c223000 0 0x1ff>; /* SROT */ 4572 #qcom,sensors = <8>; 4573 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4574 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4575 interrupt-names = "uplow", "critical"; 4576 #thermal-sensor-cells = <1>; 4577 }; 4578 4579 aoss_reset: reset-controller@c2a0000 { 4580 compatible = "qcom,sdm845-aoss-cc"; 4581 reg = <0 0x0c2a0000 0 0x31000>; 4582 #reset-cells = <1>; 4583 }; 4584 4585 aoss_qmp: power-controller@c300000 { 4586 compatible = "qcom,sdm845-aoss-qmp"; 4587 reg = <0 0x0c300000 0 0x100000>; 4588 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4589 mboxes = <&apss_shared 0>; 4590 4591 #clock-cells = <0>; 4592 #power-domain-cells = <1>; 4593 4594 cx_cdev: cx { 4595 #cooling-cells = <2>; 4596 }; 4597 4598 ebi_cdev: ebi { 4599 #cooling-cells = <2>; 4600 }; 4601 }; 4602 4603 spmi_bus: spmi@c440000 { 4604 compatible = "qcom,spmi-pmic-arb"; 4605 reg = <0 0x0c440000 0 0x1100>, 4606 <0 0x0c600000 0 0x2000000>, 4607 <0 0x0e600000 0 0x100000>, 4608 <0 0x0e700000 0 0xa0000>, 4609 <0 0x0c40a000 0 0x26000>; 4610 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4611 interrupt-names = "periph_irq"; 4612 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4613 qcom,ee = <0>; 4614 qcom,channel = <0>; 4615 #address-cells = <2>; 4616 #size-cells = <0>; 4617 interrupt-controller; 4618 #interrupt-cells = <4>; 4619 cell-index = <0>; 4620 }; 4621 4622 imem@146bf000 { 4623 compatible = "simple-mfd"; 4624 reg = <0 0x146bf000 0 0x1000>; 4625 4626 #address-cells = <1>; 4627 #size-cells = <1>; 4628 4629 ranges = <0 0 0x146bf000 0x1000>; 4630 4631 pil-reloc@94c { 4632 compatible = "qcom,pil-reloc-info"; 4633 reg = <0x94c 0xc8>; 4634 }; 4635 }; 4636 4637 apps_smmu: iommu@15000000 { 4638 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 4639 reg = <0 0x15000000 0 0x80000>; 4640 #iommu-cells = <2>; 4641 #global-interrupts = <1>; 4642 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4643 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4644 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4645 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4646 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4647 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4648 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4649 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4650 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4651 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4652 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4653 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4654 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4655 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4656 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4657 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4658 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4659 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4660 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4661 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4662 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4663 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4664 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4665 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4666 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4667 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4668 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4669 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4670 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4671 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4672 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4673 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4674 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4675 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4676 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4677 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4678 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4679 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4680 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4681 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4682 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4683 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4684 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4685 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4686 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4687 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4688 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4689 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4690 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4691 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4692 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4693 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4694 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4695 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4696 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4697 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4698 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4699 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4700 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4701 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4702 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4703 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4704 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4705 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4706 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 4707 }; 4708 4709 lpasscc: clock-controller@17014000 { 4710 compatible = "qcom,sdm845-lpasscc"; 4711 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 4712 reg-names = "cc", "qdsp6ss"; 4713 #clock-cells = <1>; 4714 status = "disabled"; 4715 }; 4716 4717 gladiator_noc: interconnect@17900000 { 4718 compatible = "qcom,sdm845-gladiator-noc"; 4719 reg = <0 0x17900000 0 0xd080>; 4720 #interconnect-cells = <2>; 4721 qcom,bcm-voters = <&apps_bcm_voter>; 4722 }; 4723 4724 watchdog@17980000 { 4725 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 4726 reg = <0 0x17980000 0 0x1000>; 4727 clocks = <&sleep_clk>; 4728 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4729 }; 4730 4731 apss_shared: mailbox@17990000 { 4732 compatible = "qcom,sdm845-apss-shared"; 4733 reg = <0 0x17990000 0 0x1000>; 4734 #mbox-cells = <1>; 4735 }; 4736 4737 apps_rsc: rsc@179c0000 { 4738 label = "apps_rsc"; 4739 compatible = "qcom,rpmh-rsc"; 4740 reg = <0 0x179c0000 0 0x10000>, 4741 <0 0x179d0000 0 0x10000>, 4742 <0 0x179e0000 0 0x10000>; 4743 reg-names = "drv-0", "drv-1", "drv-2"; 4744 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4745 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4746 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4747 qcom,tcs-offset = <0xd00>; 4748 qcom,drv-id = <2>; 4749 qcom,tcs-config = <ACTIVE_TCS 2>, 4750 <SLEEP_TCS 3>, 4751 <WAKE_TCS 3>, 4752 <CONTROL_TCS 1>; 4753 4754 apps_bcm_voter: bcm-voter { 4755 compatible = "qcom,bcm-voter"; 4756 }; 4757 4758 rpmhcc: clock-controller { 4759 compatible = "qcom,sdm845-rpmh-clk"; 4760 #clock-cells = <1>; 4761 clock-names = "xo"; 4762 clocks = <&xo_board>; 4763 }; 4764 4765 rpmhpd: power-controller { 4766 compatible = "qcom,sdm845-rpmhpd"; 4767 #power-domain-cells = <1>; 4768 operating-points-v2 = <&rpmhpd_opp_table>; 4769 4770 rpmhpd_opp_table: opp-table { 4771 compatible = "operating-points-v2"; 4772 4773 rpmhpd_opp_ret: opp1 { 4774 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4775 }; 4776 4777 rpmhpd_opp_min_svs: opp2 { 4778 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4779 }; 4780 4781 rpmhpd_opp_low_svs: opp3 { 4782 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4783 }; 4784 4785 rpmhpd_opp_svs: opp4 { 4786 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4787 }; 4788 4789 rpmhpd_opp_svs_l1: opp5 { 4790 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4791 }; 4792 4793 rpmhpd_opp_nom: opp6 { 4794 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4795 }; 4796 4797 rpmhpd_opp_nom_l1: opp7 { 4798 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4799 }; 4800 4801 rpmhpd_opp_nom_l2: opp8 { 4802 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4803 }; 4804 4805 rpmhpd_opp_turbo: opp9 { 4806 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4807 }; 4808 4809 rpmhpd_opp_turbo_l1: opp10 { 4810 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4811 }; 4812 }; 4813 }; 4814 }; 4815 4816 intc: interrupt-controller@17a00000 { 4817 compatible = "arm,gic-v3"; 4818 #address-cells = <2>; 4819 #size-cells = <2>; 4820 ranges; 4821 #interrupt-cells = <3>; 4822 interrupt-controller; 4823 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 4824 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 4825 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4826 4827 msi-controller@17a40000 { 4828 compatible = "arm,gic-v3-its"; 4829 msi-controller; 4830 #msi-cells = <1>; 4831 reg = <0 0x17a40000 0 0x20000>; 4832 status = "disabled"; 4833 }; 4834 }; 4835 4836 slimbam: dma-controller@17184000 { 4837 compatible = "qcom,bam-v1.7.0"; 4838 qcom,controlled-remotely; 4839 reg = <0 0x17184000 0 0x2a000>; 4840 num-channels = <31>; 4841 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 4842 #dma-cells = <1>; 4843 qcom,ee = <1>; 4844 qcom,num-ees = <2>; 4845 iommus = <&apps_smmu 0x1806 0x0>; 4846 }; 4847 4848 timer@17c90000 { 4849 #address-cells = <2>; 4850 #size-cells = <2>; 4851 ranges; 4852 compatible = "arm,armv7-timer-mem"; 4853 reg = <0 0x17c90000 0 0x1000>; 4854 4855 frame@17ca0000 { 4856 frame-number = <0>; 4857 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 4858 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4859 reg = <0 0x17ca0000 0 0x1000>, 4860 <0 0x17cb0000 0 0x1000>; 4861 }; 4862 4863 frame@17cc0000 { 4864 frame-number = <1>; 4865 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 4866 reg = <0 0x17cc0000 0 0x1000>; 4867 status = "disabled"; 4868 }; 4869 4870 frame@17cd0000 { 4871 frame-number = <2>; 4872 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4873 reg = <0 0x17cd0000 0 0x1000>; 4874 status = "disabled"; 4875 }; 4876 4877 frame@17ce0000 { 4878 frame-number = <3>; 4879 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4880 reg = <0 0x17ce0000 0 0x1000>; 4881 status = "disabled"; 4882 }; 4883 4884 frame@17cf0000 { 4885 frame-number = <4>; 4886 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4887 reg = <0 0x17cf0000 0 0x1000>; 4888 status = "disabled"; 4889 }; 4890 4891 frame@17d00000 { 4892 frame-number = <5>; 4893 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4894 reg = <0 0x17d00000 0 0x1000>; 4895 status = "disabled"; 4896 }; 4897 4898 frame@17d10000 { 4899 frame-number = <6>; 4900 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4901 reg = <0 0x17d10000 0 0x1000>; 4902 status = "disabled"; 4903 }; 4904 }; 4905 4906 osm_l3: interconnect@17d41000 { 4907 compatible = "qcom,sdm845-osm-l3"; 4908 reg = <0 0x17d41000 0 0x1400>; 4909 4910 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4911 clock-names = "xo", "alternate"; 4912 4913 #interconnect-cells = <1>; 4914 }; 4915 4916 cpufreq_hw: cpufreq@17d43000 { 4917 compatible = "qcom,cpufreq-hw"; 4918 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 4919 reg-names = "freq-domain0", "freq-domain1"; 4920 4921 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4922 clock-names = "xo", "alternate"; 4923 4924 #freq-domain-cells = <1>; 4925 }; 4926 4927 wifi: wifi@18800000 { 4928 compatible = "qcom,wcn3990-wifi"; 4929 status = "disabled"; 4930 reg = <0 0x18800000 0 0x800000>; 4931 reg-names = "membase"; 4932 memory-region = <&wlan_msa_mem>; 4933 clock-names = "cxo_ref_clk_pin"; 4934 clocks = <&rpmhcc RPMH_RF_CLK2>; 4935 interrupts = 4936 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4937 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4938 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4939 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4940 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4941 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4942 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4943 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4944 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4945 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4946 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4947 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4948 iommus = <&apps_smmu 0x0040 0x1>; 4949 }; 4950 }; 4951 4952 thermal-zones { 4953 cpu0-thermal { 4954 polling-delay-passive = <250>; 4955 polling-delay = <1000>; 4956 4957 thermal-sensors = <&tsens0 1>; 4958 4959 trips { 4960 cpu0_alert0: trip-point0 { 4961 temperature = <90000>; 4962 hysteresis = <2000>; 4963 type = "passive"; 4964 }; 4965 4966 cpu0_alert1: trip-point1 { 4967 temperature = <95000>; 4968 hysteresis = <2000>; 4969 type = "passive"; 4970 }; 4971 4972 cpu0_crit: cpu_crit { 4973 temperature = <110000>; 4974 hysteresis = <1000>; 4975 type = "critical"; 4976 }; 4977 }; 4978 4979 cooling-maps { 4980 map0 { 4981 trip = <&cpu0_alert0>; 4982 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4983 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4984 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4985 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4986 }; 4987 map1 { 4988 trip = <&cpu0_alert1>; 4989 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4990 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4991 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4992 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4993 }; 4994 }; 4995 }; 4996 4997 cpu1-thermal { 4998 polling-delay-passive = <250>; 4999 polling-delay = <1000>; 5000 5001 thermal-sensors = <&tsens0 2>; 5002 5003 trips { 5004 cpu1_alert0: trip-point0 { 5005 temperature = <90000>; 5006 hysteresis = <2000>; 5007 type = "passive"; 5008 }; 5009 5010 cpu1_alert1: trip-point1 { 5011 temperature = <95000>; 5012 hysteresis = <2000>; 5013 type = "passive"; 5014 }; 5015 5016 cpu1_crit: cpu_crit { 5017 temperature = <110000>; 5018 hysteresis = <1000>; 5019 type = "critical"; 5020 }; 5021 }; 5022 5023 cooling-maps { 5024 map0 { 5025 trip = <&cpu1_alert0>; 5026 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5027 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5028 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5029 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5030 }; 5031 map1 { 5032 trip = <&cpu1_alert1>; 5033 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5034 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5035 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5036 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5037 }; 5038 }; 5039 }; 5040 5041 cpu2-thermal { 5042 polling-delay-passive = <250>; 5043 polling-delay = <1000>; 5044 5045 thermal-sensors = <&tsens0 3>; 5046 5047 trips { 5048 cpu2_alert0: trip-point0 { 5049 temperature = <90000>; 5050 hysteresis = <2000>; 5051 type = "passive"; 5052 }; 5053 5054 cpu2_alert1: trip-point1 { 5055 temperature = <95000>; 5056 hysteresis = <2000>; 5057 type = "passive"; 5058 }; 5059 5060 cpu2_crit: cpu_crit { 5061 temperature = <110000>; 5062 hysteresis = <1000>; 5063 type = "critical"; 5064 }; 5065 }; 5066 5067 cooling-maps { 5068 map0 { 5069 trip = <&cpu2_alert0>; 5070 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5071 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5072 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5073 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5074 }; 5075 map1 { 5076 trip = <&cpu2_alert1>; 5077 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5078 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5079 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5080 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5081 }; 5082 }; 5083 }; 5084 5085 cpu3-thermal { 5086 polling-delay-passive = <250>; 5087 polling-delay = <1000>; 5088 5089 thermal-sensors = <&tsens0 4>; 5090 5091 trips { 5092 cpu3_alert0: trip-point0 { 5093 temperature = <90000>; 5094 hysteresis = <2000>; 5095 type = "passive"; 5096 }; 5097 5098 cpu3_alert1: trip-point1 { 5099 temperature = <95000>; 5100 hysteresis = <2000>; 5101 type = "passive"; 5102 }; 5103 5104 cpu3_crit: cpu_crit { 5105 temperature = <110000>; 5106 hysteresis = <1000>; 5107 type = "critical"; 5108 }; 5109 }; 5110 5111 cooling-maps { 5112 map0 { 5113 trip = <&cpu3_alert0>; 5114 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5115 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5116 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5117 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5118 }; 5119 map1 { 5120 trip = <&cpu3_alert1>; 5121 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5122 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5123 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5124 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5125 }; 5126 }; 5127 }; 5128 5129 cpu4-thermal { 5130 polling-delay-passive = <250>; 5131 polling-delay = <1000>; 5132 5133 thermal-sensors = <&tsens0 7>; 5134 5135 trips { 5136 cpu4_alert0: trip-point0 { 5137 temperature = <90000>; 5138 hysteresis = <2000>; 5139 type = "passive"; 5140 }; 5141 5142 cpu4_alert1: trip-point1 { 5143 temperature = <95000>; 5144 hysteresis = <2000>; 5145 type = "passive"; 5146 }; 5147 5148 cpu4_crit: cpu_crit { 5149 temperature = <110000>; 5150 hysteresis = <1000>; 5151 type = "critical"; 5152 }; 5153 }; 5154 5155 cooling-maps { 5156 map0 { 5157 trip = <&cpu4_alert0>; 5158 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5159 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5160 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5161 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5162 }; 5163 map1 { 5164 trip = <&cpu4_alert1>; 5165 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5166 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5167 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5168 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5169 }; 5170 }; 5171 }; 5172 5173 cpu5-thermal { 5174 polling-delay-passive = <250>; 5175 polling-delay = <1000>; 5176 5177 thermal-sensors = <&tsens0 8>; 5178 5179 trips { 5180 cpu5_alert0: trip-point0 { 5181 temperature = <90000>; 5182 hysteresis = <2000>; 5183 type = "passive"; 5184 }; 5185 5186 cpu5_alert1: trip-point1 { 5187 temperature = <95000>; 5188 hysteresis = <2000>; 5189 type = "passive"; 5190 }; 5191 5192 cpu5_crit: cpu_crit { 5193 temperature = <110000>; 5194 hysteresis = <1000>; 5195 type = "critical"; 5196 }; 5197 }; 5198 5199 cooling-maps { 5200 map0 { 5201 trip = <&cpu5_alert0>; 5202 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5203 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5204 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5205 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5206 }; 5207 map1 { 5208 trip = <&cpu5_alert1>; 5209 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5210 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5211 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5212 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5213 }; 5214 }; 5215 }; 5216 5217 cpu6-thermal { 5218 polling-delay-passive = <250>; 5219 polling-delay = <1000>; 5220 5221 thermal-sensors = <&tsens0 9>; 5222 5223 trips { 5224 cpu6_alert0: trip-point0 { 5225 temperature = <90000>; 5226 hysteresis = <2000>; 5227 type = "passive"; 5228 }; 5229 5230 cpu6_alert1: trip-point1 { 5231 temperature = <95000>; 5232 hysteresis = <2000>; 5233 type = "passive"; 5234 }; 5235 5236 cpu6_crit: cpu_crit { 5237 temperature = <110000>; 5238 hysteresis = <1000>; 5239 type = "critical"; 5240 }; 5241 }; 5242 5243 cooling-maps { 5244 map0 { 5245 trip = <&cpu6_alert0>; 5246 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5247 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5248 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5249 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5250 }; 5251 map1 { 5252 trip = <&cpu6_alert1>; 5253 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5254 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5255 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5256 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5257 }; 5258 }; 5259 }; 5260 5261 cpu7-thermal { 5262 polling-delay-passive = <250>; 5263 polling-delay = <1000>; 5264 5265 thermal-sensors = <&tsens0 10>; 5266 5267 trips { 5268 cpu7_alert0: trip-point0 { 5269 temperature = <90000>; 5270 hysteresis = <2000>; 5271 type = "passive"; 5272 }; 5273 5274 cpu7_alert1: trip-point1 { 5275 temperature = <95000>; 5276 hysteresis = <2000>; 5277 type = "passive"; 5278 }; 5279 5280 cpu7_crit: cpu_crit { 5281 temperature = <110000>; 5282 hysteresis = <1000>; 5283 type = "critical"; 5284 }; 5285 }; 5286 5287 cooling-maps { 5288 map0 { 5289 trip = <&cpu7_alert0>; 5290 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5291 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5292 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5293 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5294 }; 5295 map1 { 5296 trip = <&cpu7_alert1>; 5297 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5298 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5299 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5300 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5301 }; 5302 }; 5303 }; 5304 5305 aoss0-thermal { 5306 polling-delay-passive = <250>; 5307 polling-delay = <1000>; 5308 5309 thermal-sensors = <&tsens0 0>; 5310 5311 trips { 5312 aoss0_alert0: trip-point0 { 5313 temperature = <90000>; 5314 hysteresis = <2000>; 5315 type = "hot"; 5316 }; 5317 }; 5318 }; 5319 5320 cluster0-thermal { 5321 polling-delay-passive = <250>; 5322 polling-delay = <1000>; 5323 5324 thermal-sensors = <&tsens0 5>; 5325 5326 trips { 5327 cluster0_alert0: trip-point0 { 5328 temperature = <90000>; 5329 hysteresis = <2000>; 5330 type = "hot"; 5331 }; 5332 cluster0_crit: cluster0_crit { 5333 temperature = <110000>; 5334 hysteresis = <2000>; 5335 type = "critical"; 5336 }; 5337 }; 5338 }; 5339 5340 cluster1-thermal { 5341 polling-delay-passive = <250>; 5342 polling-delay = <1000>; 5343 5344 thermal-sensors = <&tsens0 6>; 5345 5346 trips { 5347 cluster1_alert0: trip-point0 { 5348 temperature = <90000>; 5349 hysteresis = <2000>; 5350 type = "hot"; 5351 }; 5352 cluster1_crit: cluster1_crit { 5353 temperature = <110000>; 5354 hysteresis = <2000>; 5355 type = "critical"; 5356 }; 5357 }; 5358 }; 5359 5360 gpu-thermal-top { 5361 polling-delay-passive = <250>; 5362 polling-delay = <1000>; 5363 5364 thermal-sensors = <&tsens0 11>; 5365 5366 trips { 5367 gpu1_alert0: trip-point0 { 5368 temperature = <90000>; 5369 hysteresis = <2000>; 5370 type = "hot"; 5371 }; 5372 }; 5373 }; 5374 5375 gpu-thermal-bottom { 5376 polling-delay-passive = <250>; 5377 polling-delay = <1000>; 5378 5379 thermal-sensors = <&tsens0 12>; 5380 5381 trips { 5382 gpu2_alert0: trip-point0 { 5383 temperature = <90000>; 5384 hysteresis = <2000>; 5385 type = "hot"; 5386 }; 5387 }; 5388 }; 5389 5390 aoss1-thermal { 5391 polling-delay-passive = <250>; 5392 polling-delay = <1000>; 5393 5394 thermal-sensors = <&tsens1 0>; 5395 5396 trips { 5397 aoss1_alert0: trip-point0 { 5398 temperature = <90000>; 5399 hysteresis = <2000>; 5400 type = "hot"; 5401 }; 5402 }; 5403 }; 5404 5405 q6-modem-thermal { 5406 polling-delay-passive = <250>; 5407 polling-delay = <1000>; 5408 5409 thermal-sensors = <&tsens1 1>; 5410 5411 trips { 5412 q6_modem_alert0: trip-point0 { 5413 temperature = <90000>; 5414 hysteresis = <2000>; 5415 type = "hot"; 5416 }; 5417 }; 5418 }; 5419 5420 mem-thermal { 5421 polling-delay-passive = <250>; 5422 polling-delay = <1000>; 5423 5424 thermal-sensors = <&tsens1 2>; 5425 5426 trips { 5427 mem_alert0: trip-point0 { 5428 temperature = <90000>; 5429 hysteresis = <2000>; 5430 type = "hot"; 5431 }; 5432 }; 5433 }; 5434 5435 wlan-thermal { 5436 polling-delay-passive = <250>; 5437 polling-delay = <1000>; 5438 5439 thermal-sensors = <&tsens1 3>; 5440 5441 trips { 5442 wlan_alert0: trip-point0 { 5443 temperature = <90000>; 5444 hysteresis = <2000>; 5445 type = "hot"; 5446 }; 5447 }; 5448 }; 5449 5450 q6-hvx-thermal { 5451 polling-delay-passive = <250>; 5452 polling-delay = <1000>; 5453 5454 thermal-sensors = <&tsens1 4>; 5455 5456 trips { 5457 q6_hvx_alert0: trip-point0 { 5458 temperature = <90000>; 5459 hysteresis = <2000>; 5460 type = "hot"; 5461 }; 5462 }; 5463 }; 5464 5465 camera-thermal { 5466 polling-delay-passive = <250>; 5467 polling-delay = <1000>; 5468 5469 thermal-sensors = <&tsens1 5>; 5470 5471 trips { 5472 camera_alert0: trip-point0 { 5473 temperature = <90000>; 5474 hysteresis = <2000>; 5475 type = "hot"; 5476 }; 5477 }; 5478 }; 5479 5480 video-thermal { 5481 polling-delay-passive = <250>; 5482 polling-delay = <1000>; 5483 5484 thermal-sensors = <&tsens1 6>; 5485 5486 trips { 5487 video_alert0: trip-point0 { 5488 temperature = <90000>; 5489 hysteresis = <2000>; 5490 type = "hot"; 5491 }; 5492 }; 5493 }; 5494 5495 modem-thermal { 5496 polling-delay-passive = <250>; 5497 polling-delay = <1000>; 5498 5499 thermal-sensors = <&tsens1 7>; 5500 5501 trips { 5502 modem_alert0: trip-point0 { 5503 temperature = <90000>; 5504 hysteresis = <2000>; 5505 type = "hot"; 5506 }; 5507 }; 5508 }; 5509 }; 5510}; 5511