1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8350.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/interconnect/qcom,sm8350.h> 10#include <dt-bindings/mailbox/qcom-ipcc.h> 11#include <dt-bindings/power/qcom-aoss-qmp.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/soc/qcom,rpmh-rsc.h> 14#include <dt-bindings/thermal/thermal.h> 15#include <dt-bindings/interconnect/qcom,sm8350.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 chosen { }; 24 25 clocks { 26 xo_board: xo-board { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <38400000>; 30 clock-output-names = "xo_board"; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 clock-frequency = <32000>; 36 #clock-cells = <0>; 37 }; 38 39 ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 { 40 compatible = "fixed-clock"; 41 clock-frequency = <1000>; 42 #clock-cells = <0>; 43 }; 44 45 ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 { 46 compatible = "fixed-clock"; 47 clock-frequency = <1000>; 48 #clock-cells = <0>; 49 }; 50 51 ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 { 52 compatible = "fixed-clock"; 53 clock-frequency = <1000>; 54 #clock-cells = <0>; 55 }; 56 }; 57 58 cpus { 59 #address-cells = <2>; 60 #size-cells = <0>; 61 62 CPU0: cpu@0 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a55"; 65 reg = <0x0 0x0>; 66 enable-method = "psci"; 67 next-level-cache = <&L2_0>; 68 qcom,freq-domain = <&cpufreq_hw 0>; 69 #cooling-cells = <2>; 70 L2_0: l2-cache { 71 compatible = "cache"; 72 next-level-cache = <&L3_0>; 73 L3_0: l3-cache { 74 compatible = "cache"; 75 }; 76 }; 77 }; 78 79 CPU1: cpu@100 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a55"; 82 reg = <0x0 0x100>; 83 enable-method = "psci"; 84 next-level-cache = <&L2_100>; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 #cooling-cells = <2>; 87 L2_100: l2-cache { 88 compatible = "cache"; 89 next-level-cache = <&L3_0>; 90 }; 91 }; 92 93 CPU2: cpu@200 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a55"; 96 reg = <0x0 0x200>; 97 enable-method = "psci"; 98 next-level-cache = <&L2_200>; 99 qcom,freq-domain = <&cpufreq_hw 0>; 100 #cooling-cells = <2>; 101 L2_200: l2-cache { 102 compatible = "cache"; 103 next-level-cache = <&L3_0>; 104 }; 105 }; 106 107 CPU3: cpu@300 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a55"; 110 reg = <0x0 0x300>; 111 enable-method = "psci"; 112 next-level-cache = <&L2_300>; 113 qcom,freq-domain = <&cpufreq_hw 0>; 114 #cooling-cells = <2>; 115 L2_300: l2-cache { 116 compatible = "cache"; 117 next-level-cache = <&L3_0>; 118 }; 119 }; 120 121 CPU4: cpu@400 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a78"; 124 reg = <0x0 0x400>; 125 enable-method = "psci"; 126 next-level-cache = <&L2_400>; 127 qcom,freq-domain = <&cpufreq_hw 1>; 128 #cooling-cells = <2>; 129 L2_400: l2-cache { 130 compatible = "cache"; 131 next-level-cache = <&L3_0>; 132 }; 133 }; 134 135 CPU5: cpu@500 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a78"; 138 reg = <0x0 0x500>; 139 enable-method = "psci"; 140 next-level-cache = <&L2_500>; 141 qcom,freq-domain = <&cpufreq_hw 1>; 142 #cooling-cells = <2>; 143 L2_500: l2-cache { 144 compatible = "cache"; 145 next-level-cache = <&L3_0>; 146 }; 147 148 }; 149 150 CPU6: cpu@600 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a78"; 153 reg = <0x0 0x600>; 154 enable-method = "psci"; 155 next-level-cache = <&L2_600>; 156 qcom,freq-domain = <&cpufreq_hw 1>; 157 #cooling-cells = <2>; 158 L2_600: l2-cache { 159 compatible = "cache"; 160 next-level-cache = <&L3_0>; 161 }; 162 }; 163 164 CPU7: cpu@700 { 165 device_type = "cpu"; 166 compatible = "arm,cortex-x1"; 167 reg = <0x0 0x700>; 168 enable-method = "psci"; 169 next-level-cache = <&L2_700>; 170 qcom,freq-domain = <&cpufreq_hw 2>; 171 #cooling-cells = <2>; 172 L2_700: l2-cache { 173 compatible = "cache"; 174 next-level-cache = <&L3_0>; 175 }; 176 }; 177 }; 178 179 firmware { 180 scm: scm { 181 compatible = "qcom,scm-sm8350", "qcom,scm"; 182 #reset-cells = <1>; 183 }; 184 }; 185 186 memory@80000000 { 187 device_type = "memory"; 188 /* We expect the bootloader to fill in the size */ 189 reg = <0x0 0x80000000 0x0 0x0>; 190 }; 191 192 pmu { 193 compatible = "arm,armv8-pmuv3"; 194 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 195 }; 196 197 psci { 198 compatible = "arm,psci-1.0"; 199 method = "smc"; 200 }; 201 202 reserved_memory: reserved-memory { 203 #address-cells = <2>; 204 #size-cells = <2>; 205 ranges; 206 207 hyp_mem: memory@80000000 { 208 reg = <0x0 0x80000000 0x0 0x600000>; 209 no-map; 210 }; 211 212 xbl_aop_mem: memory@80700000 { 213 no-map; 214 reg = <0x0 0x80700000 0x0 0x160000>; 215 }; 216 217 cmd_db: memory@80860000 { 218 compatible = "qcom,cmd-db"; 219 reg = <0x0 0x80860000 0x0 0x20000>; 220 no-map; 221 }; 222 223 reserved_xbl_uefi_log: memory@80880000 { 224 reg = <0x0 0x80880000 0x0 0x14000>; 225 no-map; 226 }; 227 228 smem_mem: memory@80900000 { 229 reg = <0x0 0x80900000 0x0 0x200000>; 230 no-map; 231 }; 232 233 cpucp_fw_mem: memory@80b00000 { 234 reg = <0x0 0x80b00000 0x0 0x100000>; 235 no-map; 236 }; 237 238 cdsp_secure_heap: memory@80c00000 { 239 reg = <0x0 0x80c00000 0x0 0x4600000>; 240 no-map; 241 }; 242 243 pil_camera_mem: mmeory@85200000 { 244 reg = <0x0 0x85200000 0x0 0x500000>; 245 no-map; 246 }; 247 248 pil_video_mem: memory@85700000 { 249 reg = <0x0 0x85700000 0x0 0x500000>; 250 no-map; 251 }; 252 253 pil_cvp_mem: memory@85c00000 { 254 reg = <0x0 0x85c00000 0x0 0x500000>; 255 no-map; 256 }; 257 258 pil_adsp_mem: memory@86100000 { 259 reg = <0x0 0x86100000 0x0 0x2100000>; 260 no-map; 261 }; 262 263 pil_slpi_mem: memory@88200000 { 264 reg = <0x0 0x88200000 0x0 0x1500000>; 265 no-map; 266 }; 267 268 pil_cdsp_mem: memory@89700000 { 269 reg = <0x0 0x89700000 0x0 0x1e00000>; 270 no-map; 271 }; 272 273 pil_ipa_fw_mem: memory@8b500000 { 274 reg = <0x0 0x8b500000 0x0 0x10000>; 275 no-map; 276 }; 277 278 pil_ipa_gsi_mem: memory@8b510000 { 279 reg = <0x0 0x8b510000 0x0 0xa000>; 280 no-map; 281 }; 282 283 pil_gpu_mem: memory@8b51a000 { 284 reg = <0x0 0x8b51a000 0x0 0x2000>; 285 no-map; 286 }; 287 288 pil_spss_mem: memory@8b600000 { 289 reg = <0x0 0x8b600000 0x0 0x100000>; 290 no-map; 291 }; 292 293 pil_modem_mem: memory@8b800000 { 294 reg = <0x0 0x8b800000 0x0 0x10000000>; 295 no-map; 296 }; 297 298 rmtfs_mem: memory@9b800000 { 299 compatible = "qcom,rmtfs-mem"; 300 reg = <0x0 0x9b800000 0x0 0x280000>; 301 no-map; 302 303 qcom,client-id = <1>; 304 qcom,vmid = <15>; 305 }; 306 307 hyp_reserved_mem: memory@d0000000 { 308 reg = <0x0 0xd0000000 0x0 0x800000>; 309 no-map; 310 }; 311 312 pil_trustedvm_mem: memory@d0800000 { 313 reg = <0x0 0xd0800000 0x0 0x76f7000>; 314 no-map; 315 }; 316 317 qrtr_shbuf: memory@d7ef7000 { 318 reg = <0x0 0xd7ef7000 0x0 0x9000>; 319 no-map; 320 }; 321 322 chan0_shbuf: memory@d7f00000 { 323 reg = <0x0 0xd7f00000 0x0 0x80000>; 324 no-map; 325 }; 326 327 chan1_shbuf: memory@d7f80000 { 328 reg = <0x0 0xd7f80000 0x0 0x80000>; 329 no-map; 330 }; 331 332 removed_mem: memory@d8800000 { 333 reg = <0x0 0xd8800000 0x0 0x6800000>; 334 no-map; 335 }; 336 }; 337 338 smem: qcom,smem { 339 compatible = "qcom,smem"; 340 memory-region = <&smem_mem>; 341 hwlocks = <&tcsr_mutex 3>; 342 }; 343 344 smp2p-adsp { 345 compatible = "qcom,smp2p"; 346 qcom,smem = <443>, <429>; 347 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 348 IPCC_MPROC_SIGNAL_SMP2P 349 IRQ_TYPE_EDGE_RISING>; 350 mboxes = <&ipcc IPCC_CLIENT_LPASS 351 IPCC_MPROC_SIGNAL_SMP2P>; 352 353 qcom,local-pid = <0>; 354 qcom,remote-pid = <2>; 355 356 smp2p_adsp_out: master-kernel { 357 qcom,entry-name = "master-kernel"; 358 #qcom,smem-state-cells = <1>; 359 }; 360 361 smp2p_adsp_in: slave-kernel { 362 qcom,entry-name = "slave-kernel"; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 }; 366 }; 367 368 smp2p-cdsp { 369 compatible = "qcom,smp2p"; 370 qcom,smem = <94>, <432>; 371 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 372 IPCC_MPROC_SIGNAL_SMP2P 373 IRQ_TYPE_EDGE_RISING>; 374 mboxes = <&ipcc IPCC_CLIENT_CDSP 375 IPCC_MPROC_SIGNAL_SMP2P>; 376 377 qcom,local-pid = <0>; 378 qcom,remote-pid = <5>; 379 380 smp2p_cdsp_out: master-kernel { 381 qcom,entry-name = "master-kernel"; 382 #qcom,smem-state-cells = <1>; 383 }; 384 385 smp2p_cdsp_in: slave-kernel { 386 qcom,entry-name = "slave-kernel"; 387 interrupt-controller; 388 #interrupt-cells = <2>; 389 }; 390 }; 391 392 smp2p-modem { 393 compatible = "qcom,smp2p"; 394 qcom,smem = <435>, <428>; 395 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 396 IPCC_MPROC_SIGNAL_SMP2P 397 IRQ_TYPE_EDGE_RISING>; 398 mboxes = <&ipcc IPCC_CLIENT_MPSS 399 IPCC_MPROC_SIGNAL_SMP2P>; 400 401 qcom,local-pid = <0>; 402 qcom,remote-pid = <1>; 403 404 smp2p_modem_out: master-kernel { 405 qcom,entry-name = "master-kernel"; 406 #qcom,smem-state-cells = <1>; 407 }; 408 409 smp2p_modem_in: slave-kernel { 410 qcom,entry-name = "slave-kernel"; 411 interrupt-controller; 412 #interrupt-cells = <2>; 413 }; 414 415 ipa_smp2p_out: ipa-ap-to-modem { 416 qcom,entry-name = "ipa"; 417 #qcom,smem-state-cells = <1>; 418 }; 419 420 ipa_smp2p_in: ipa-modem-to-ap { 421 qcom,entry-name = "ipa"; 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 }; 425 }; 426 427 smp2p-slpi { 428 compatible = "qcom,smp2p"; 429 qcom,smem = <481>, <430>; 430 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 431 IPCC_MPROC_SIGNAL_SMP2P 432 IRQ_TYPE_EDGE_RISING>; 433 mboxes = <&ipcc IPCC_CLIENT_SLPI 434 IPCC_MPROC_SIGNAL_SMP2P>; 435 436 qcom,local-pid = <0>; 437 qcom,remote-pid = <3>; 438 439 smp2p_slpi_out: master-kernel { 440 qcom,entry-name = "master-kernel"; 441 #qcom,smem-state-cells = <1>; 442 }; 443 444 smp2p_slpi_in: slave-kernel { 445 qcom,entry-name = "slave-kernel"; 446 interrupt-controller; 447 #interrupt-cells = <2>; 448 }; 449 }; 450 451 soc: soc@0 { 452 #address-cells = <2>; 453 #size-cells = <2>; 454 ranges = <0 0 0 0 0x10 0>; 455 dma-ranges = <0 0 0 0 0x10 0>; 456 compatible = "simple-bus"; 457 458 gcc: clock-controller@100000 { 459 compatible = "qcom,gcc-sm8350"; 460 reg = <0x0 0x00100000 0x0 0x1f0000>; 461 #clock-cells = <1>; 462 #reset-cells = <1>; 463 #power-domain-cells = <1>; 464 clock-names = "bi_tcxo", 465 "sleep_clk", 466 "pcie_0_pipe_clk", 467 "pcie_1_pipe_clk", 468 "ufs_card_rx_symbol_0_clk", 469 "ufs_card_rx_symbol_1_clk", 470 "ufs_card_tx_symbol_0_clk", 471 "ufs_phy_rx_symbol_0_clk", 472 "ufs_phy_rx_symbol_1_clk", 473 "ufs_phy_tx_symbol_0_clk", 474 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 475 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 476 clocks = <&rpmhcc RPMH_CXO_CLK>, 477 <&sleep_clk>, 478 <0>, 479 <0>, 480 <0>, 481 <0>, 482 <0>, 483 <&ufs_phy_rx_symbol_0_clk>, 484 <&ufs_phy_rx_symbol_1_clk>, 485 <&ufs_phy_tx_symbol_0_clk>, 486 <0>, 487 <0>; 488 }; 489 490 ipcc: mailbox@408000 { 491 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 492 reg = <0 0x00408000 0 0x1000>; 493 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 494 interrupt-controller; 495 #interrupt-cells = <3>; 496 #mbox-cells = <2>; 497 }; 498 499 qupv3_id_0: geniqup@9c0000 { 500 compatible = "qcom,geni-se-qup"; 501 reg = <0x0 0x009c0000 0x0 0x6000>; 502 clock-names = "m-ahb", "s-ahb"; 503 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 504 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 505 #address-cells = <2>; 506 #size-cells = <2>; 507 ranges; 508 status = "disabled"; 509 510 uart2: serial@98c000 { 511 compatible = "qcom,geni-debug-uart"; 512 reg = <0 0x0098c000 0 0x4000>; 513 clock-names = "se"; 514 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&qup_uart3_default_state>; 517 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 status = "disabled"; 521 }; 522 }; 523 524 qupv3_id_1: geniqup@ac0000 { 525 compatible = "qcom,geni-se-qup"; 526 reg = <0x0 0x00ac0000 0x0 0x6000>; 527 clock-names = "m-ahb", "s-ahb"; 528 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 529 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 530 #address-cells = <2>; 531 #size-cells = <2>; 532 ranges; 533 status = "disabled"; 534 535 i2c13: i2c@a94000 { 536 compatible = "qcom,geni-i2c"; 537 reg = <0 0x00a94000 0 0x4000>; 538 clock-names = "se"; 539 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&qup_i2c13_default_state>; 542 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 status = "disabled"; 546 }; 547 }; 548 549 apps_smmu: iommu@15000000 { 550 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 551 reg = <0 0x15000000 0 0x100000>; 552 #iommu-cells = <2>; 553 #global-interrupts = <2>; 554 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 652 }; 653 654 config_noc: interconnect@1500000 { 655 compatible = "qcom,sm8350-config-noc"; 656 reg = <0 0x01500000 0 0xa580>; 657 #interconnect-cells = <1>; 658 qcom,bcm-voters = <&apps_bcm_voter>; 659 }; 660 661 mc_virt: interconnect@1580000 { 662 compatible = "qcom,sm8350-mc-virt"; 663 reg = <0 0x01580000 0 0x1000>; 664 #interconnect-cells = <1>; 665 qcom,bcm-voters = <&apps_bcm_voter>; 666 }; 667 668 system_noc: interconnect@1680000 { 669 compatible = "qcom,sm8350-system-noc"; 670 reg = <0 0x01680000 0 0x1c200>; 671 #interconnect-cells = <1>; 672 qcom,bcm-voters = <&apps_bcm_voter>; 673 }; 674 675 aggre1_noc: interconnect@16e0000 { 676 compatible = "qcom,sm8350-aggre1-noc"; 677 reg = <0 0x016e0000 0 0x1f180>; 678 #interconnect-cells = <1>; 679 qcom,bcm-voters = <&apps_bcm_voter>; 680 }; 681 682 aggre2_noc: interconnect@1700000 { 683 compatible = "qcom,sm8350-aggre2-noc"; 684 reg = <0 0x01700000 0 0x33000>; 685 #interconnect-cells = <1>; 686 qcom,bcm-voters = <&apps_bcm_voter>; 687 }; 688 689 mmss_noc: interconnect@1740000 { 690 compatible = "qcom,sm8350-mmss-noc"; 691 reg = <0 0x01740000 0 0x1f080>; 692 #interconnect-cells = <1>; 693 qcom,bcm-voters = <&apps_bcm_voter>; 694 }; 695 696 lpass_ag_noc: interconnect@3c40000 { 697 compatible = "qcom,sm8350-lpass-ag-noc"; 698 reg = <0 0x03c40000 0 0xf080>; 699 #interconnect-cells = <1>; 700 qcom,bcm-voters = <&apps_bcm_voter>; 701 }; 702 703 compute_noc: interconnect@a0c0000{ 704 compatible = "qcom,sm8350-compute-noc"; 705 reg = <0 0x0a0c0000 0 0xa180>; 706 #interconnect-cells = <1>; 707 qcom,bcm-voters = <&apps_bcm_voter>; 708 }; 709 710 ipa: ipa@1e40000 { 711 compatible = "qcom,sm8350-ipa"; 712 713 iommus = <&apps_smmu 0x5c0 0x0>, 714 <&apps_smmu 0x5c2 0x0>; 715 reg = <0 0x1e40000 0 0x8000>, 716 <0 0x1e50000 0 0x4b20>, 717 <0 0x1e04000 0 0x23000>; 718 reg-names = "ipa-reg", 719 "ipa-shared", 720 "gsi"; 721 722 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 723 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 724 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 725 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 726 interrupt-names = "ipa", 727 "gsi", 728 "ipa-clock-query", 729 "ipa-setup-ready"; 730 731 clocks = <&rpmhcc RPMH_IPA_CLK>; 732 clock-names = "core"; 733 734 interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, 735 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; 736 interconnect-names = "memory", 737 "config"; 738 739 qcom,qmp = <&aoss_qmp>; 740 741 qcom,smem-states = <&ipa_smp2p_out 0>, 742 <&ipa_smp2p_out 1>; 743 qcom,smem-state-names = "ipa-clock-enabled-valid", 744 "ipa-clock-enabled"; 745 746 status = "disabled"; 747 }; 748 749 tcsr_mutex: hwlock@1f40000 { 750 compatible = "qcom,tcsr-mutex"; 751 reg = <0x0 0x01f40000 0x0 0x40000>; 752 #hwlock-cells = <1>; 753 }; 754 755 mpss: remoteproc@4080000 { 756 compatible = "qcom,sm8350-mpss-pas"; 757 reg = <0x0 0x04080000 0x0 0x4040>; 758 759 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 760 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 761 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 762 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 763 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 764 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 765 interrupt-names = "wdog", "fatal", "ready", "handover", 766 "stop-ack", "shutdown-ack"; 767 768 clocks = <&rpmhcc RPMH_CXO_CLK>; 769 clock-names = "xo"; 770 771 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 772 <&rpmhpd 0>, 773 <&rpmhpd 12>; 774 power-domain-names = "load_state", "cx", "mss"; 775 776 interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; 777 778 memory-region = <&pil_modem_mem>; 779 780 qcom,smem-states = <&smp2p_modem_out 0>; 781 qcom,smem-state-names = "stop"; 782 783 status = "disabled"; 784 785 glink-edge { 786 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 787 IPCC_MPROC_SIGNAL_GLINK_QMP 788 IRQ_TYPE_EDGE_RISING>; 789 mboxes = <&ipcc IPCC_CLIENT_MPSS 790 IPCC_MPROC_SIGNAL_GLINK_QMP>; 791 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 792 label = "modem"; 793 qcom,remote-pid = <1>; 794 }; 795 }; 796 797 pdc: interrupt-controller@b220000 { 798 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 799 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 800 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 801 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 802 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 803 <156 716 12>; 804 #interrupt-cells = <2>; 805 interrupt-parent = <&intc>; 806 interrupt-controller; 807 }; 808 809 tsens0: thermal-sensor@c263000 { 810 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 811 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 812 <0 0x0c222000 0 0x8>; /* SROT */ 813 #qcom,sensors = <15>; 814 interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 815 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 816 interrupt-names = "uplow", "critical"; 817 #thermal-sensor-cells = <1>; 818 }; 819 820 tsens1: thermal-sensor@c265000 { 821 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 822 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 823 <0 0x0c223000 0 0x8>; /* SROT */ 824 #qcom,sensors = <14>; 825 interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 826 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 827 interrupt-names = "uplow", "critical"; 828 #thermal-sensor-cells = <1>; 829 }; 830 831 aoss_qmp: power-controller@c300000 { 832 compatible = "qcom,sm8350-aoss-qmp"; 833 reg = <0 0x0c300000 0 0x100000>; 834 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 835 IRQ_TYPE_EDGE_RISING>; 836 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 837 838 #clock-cells = <0>; 839 #power-domain-cells = <1>; 840 }; 841 842 spmi_bus: spmi@c440000 { 843 compatible = "qcom,spmi-pmic-arb"; 844 reg = <0x0 0xc440000 0x0 0x1100>, 845 <0x0 0xc600000 0x0 0x2000000>, 846 <0x0 0xe600000 0x0 0x100000>, 847 <0x0 0xe700000 0x0 0xa0000>, 848 <0x0 0xc40a000 0x0 0x26000>; 849 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 850 interrupt-names = "periph_irq"; 851 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 852 qcom,ee = <0>; 853 qcom,channel = <0>; 854 #address-cells = <2>; 855 #size-cells = <0>; 856 interrupt-controller; 857 #interrupt-cells = <4>; 858 }; 859 860 tlmm: pinctrl@f100000 { 861 compatible = "qcom,sm8350-tlmm"; 862 reg = <0 0x0f100000 0 0x300000>; 863 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 864 gpio-controller; 865 #gpio-cells = <2>; 866 interrupt-controller; 867 #interrupt-cells = <2>; 868 gpio-ranges = <&tlmm 0 0 204>; 869 wakeup-parent = <&pdc>; 870 871 qup_uart3_default_state: qup-uart3-default-state { 872 rx { 873 pins = "gpio18"; 874 function = "qup3"; 875 }; 876 tx { 877 pins = "gpio19"; 878 function = "qup3"; 879 }; 880 }; 881 882 qup_i2c13_default_state: qup-i2c13-default-state { 883 mux { 884 pins = "gpio0", "gpio1"; 885 function = "qup13"; 886 }; 887 888 config { 889 pins = "gpio0", "gpio1"; 890 drive-strength = <2>; 891 bias-pull-up; 892 }; 893 }; 894 }; 895 896 rng: rng@10d3000 { 897 compatible = "qcom,prng-ee"; 898 reg = <0 0x010d3000 0 0x1000>; 899 clocks = <&rpmhcc RPMH_HWKM_CLK>; 900 clock-names = "core"; 901 }; 902 903 intc: interrupt-controller@17a00000 { 904 compatible = "arm,gic-v3"; 905 #interrupt-cells = <3>; 906 interrupt-controller; 907 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 908 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 909 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 910 }; 911 912 timer@17c20000 { 913 compatible = "arm,armv7-timer-mem"; 914 #address-cells = <2>; 915 #size-cells = <2>; 916 ranges; 917 reg = <0x0 0x17c20000 0x0 0x1000>; 918 clock-frequency = <19200000>; 919 920 frame@17c21000 { 921 frame-number = <0>; 922 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 924 reg = <0x0 0x17c21000 0x0 0x1000>, 925 <0x0 0x17c22000 0x0 0x1000>; 926 }; 927 928 frame@17c23000 { 929 frame-number = <1>; 930 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 931 reg = <0x0 0x17c23000 0x0 0x1000>; 932 status = "disabled"; 933 }; 934 935 frame@17c25000 { 936 frame-number = <2>; 937 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 938 reg = <0x0 0x17c25000 0x0 0x1000>; 939 status = "disabled"; 940 }; 941 942 frame@17c27000 { 943 frame-number = <3>; 944 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 945 reg = <0x0 0x17c27000 0x0 0x1000>; 946 status = "disabled"; 947 }; 948 949 frame@17c29000 { 950 frame-number = <4>; 951 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 952 reg = <0x0 0x17c29000 0x0 0x1000>; 953 status = "disabled"; 954 }; 955 956 frame@17c2b000 { 957 frame-number = <5>; 958 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 959 reg = <0x0 0x17c2b000 0x0 0x1000>; 960 status = "disabled"; 961 }; 962 963 frame@17c2d000 { 964 frame-number = <6>; 965 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 966 reg = <0x0 0x17c2d000 0x0 0x1000>; 967 status = "disabled"; 968 }; 969 }; 970 971 apps_rsc: rsc@18200000 { 972 label = "apps_rsc"; 973 compatible = "qcom,rpmh-rsc"; 974 reg = <0x0 0x18200000 0x0 0x10000>, 975 <0x0 0x18210000 0x0 0x10000>, 976 <0x0 0x18220000 0x0 0x10000>; 977 reg-names = "drv-0", "drv-1", "drv-2"; 978 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 981 qcom,tcs-offset = <0xd00>; 982 qcom,drv-id = <2>; 983 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 984 <WAKE_TCS 3>, <CONTROL_TCS 0>; 985 986 rpmhcc: clock-controller { 987 compatible = "qcom,sm8350-rpmh-clk"; 988 #clock-cells = <1>; 989 clock-names = "xo"; 990 clocks = <&xo_board>; 991 }; 992 993 rpmhpd: power-controller { 994 compatible = "qcom,sm8350-rpmhpd"; 995 #power-domain-cells = <1>; 996 operating-points-v2 = <&rpmhpd_opp_table>; 997 998 rpmhpd_opp_table: opp-table { 999 compatible = "operating-points-v2"; 1000 1001 rpmhpd_opp_ret: opp1 { 1002 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1003 }; 1004 1005 rpmhpd_opp_min_svs: opp2 { 1006 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1007 }; 1008 1009 rpmhpd_opp_low_svs: opp3 { 1010 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1011 }; 1012 1013 rpmhpd_opp_svs: opp4 { 1014 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1015 }; 1016 1017 rpmhpd_opp_svs_l1: opp5 { 1018 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1019 }; 1020 1021 rpmhpd_opp_nom: opp6 { 1022 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1023 }; 1024 1025 rpmhpd_opp_nom_l1: opp7 { 1026 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1027 }; 1028 1029 rpmhpd_opp_nom_l2: opp8 { 1030 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1031 }; 1032 1033 rpmhpd_opp_turbo: opp9 { 1034 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1035 }; 1036 1037 rpmhpd_opp_turbo_l1: opp10 { 1038 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1039 }; 1040 }; 1041 }; 1042 1043 apps_bcm_voter: bcm_voter { 1044 compatible = "qcom,bcm-voter"; 1045 }; 1046 }; 1047 1048 cpufreq_hw: cpufreq@18591000 { 1049 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 1050 reg = <0 0x18591000 0 0x1000>, 1051 <0 0x18592000 0 0x1000>, 1052 <0 0x18593000 0 0x1000>; 1053 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 1054 1055 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1058 interrupt-names = "dcvsh-irq-0", 1059 "dcvsh-irq-1", 1060 "dcvsh-irq-2"; 1061 1062 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1063 clock-names = "xo", "alternate"; 1064 1065 #freq-domain-cells = <1>; 1066 }; 1067 1068 ufs_mem_hc: ufshc@1d84000 { 1069 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1070 "jedec,ufs-2.0"; 1071 reg = <0 0x01d84000 0 0x3000>; 1072 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1073 phys = <&ufs_mem_phy_lanes>; 1074 phy-names = "ufsphy"; 1075 lanes-per-direction = <2>; 1076 #reset-cells = <1>; 1077 resets = <&gcc GCC_UFS_PHY_BCR>; 1078 reset-names = "rst"; 1079 1080 power-domains = <&gcc UFS_PHY_GDSC>; 1081 1082 iommus = <&apps_smmu 0xe0 0x0>; 1083 1084 clock-names = 1085 "ref_clk", 1086 "core_clk", 1087 "bus_aggr_clk", 1088 "iface_clk", 1089 "core_clk_unipro", 1090 "ref_clk", 1091 "tx_lane0_sync_clk", 1092 "rx_lane0_sync_clk", 1093 "rx_lane1_sync_clk"; 1094 clocks = 1095 <&rpmhcc RPMH_CXO_CLK>, 1096 <&gcc GCC_UFS_PHY_AXI_CLK>, 1097 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1098 <&gcc GCC_UFS_PHY_AHB_CLK>, 1099 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1100 <&rpmhcc RPMH_CXO_CLK>, 1101 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1102 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1103 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1104 freq-table-hz = 1105 <75000000 300000000>, 1106 <75000000 300000000>, 1107 <0 0>, 1108 <0 0>, 1109 <75000000 300000000>, 1110 <0 0>, 1111 <0 0>, 1112 <0 0>, 1113 <0 0>; 1114 status = "disabled"; 1115 }; 1116 1117 ufs_mem_phy: phy@1d87000 { 1118 compatible = "qcom,sm8350-qmp-ufs-phy"; 1119 reg = <0 0x01d87000 0 0x1c4>; 1120 #address-cells = <2>; 1121 #size-cells = <2>; 1122 #clock-cells = <1>; 1123 ranges; 1124 clock-names = "ref", 1125 "ref_aux"; 1126 clocks = <&rpmhcc RPMH_CXO_CLK>, 1127 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1128 1129 resets = <&ufs_mem_hc 0>; 1130 reset-names = "ufsphy"; 1131 status = "disabled"; 1132 1133 ufs_mem_phy_lanes: phy@1d87400 { 1134 reg = <0 0x01d87400 0 0x188>, 1135 <0 0x01d87600 0 0x200>, 1136 <0 0x01d87c00 0 0x200>, 1137 <0 0x01d87800 0 0x188>, 1138 <0 0x01d87a00 0 0x200>; 1139 #phy-cells = <0>; 1140 #clock-cells = <0>; 1141 }; 1142 }; 1143 1144 slpi: remoteproc@5c00000 { 1145 compatible = "qcom,sm8350-slpi-pas"; 1146 reg = <0 0x05c00000 0 0x4000>; 1147 1148 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 1149 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 1150 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 1151 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 1152 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 1153 interrupt-names = "wdog", "fatal", "ready", 1154 "handover", "stop-ack"; 1155 1156 clocks = <&rpmhcc RPMH_CXO_CLK>; 1157 clock-names = "xo"; 1158 1159 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, 1160 <&rpmhpd 4>, 1161 <&rpmhpd 5>; 1162 power-domain-names = "load_state", "lcx", "lmx"; 1163 1164 memory-region = <&pil_slpi_mem>; 1165 1166 qcom,smem-states = <&smp2p_slpi_out 0>; 1167 qcom,smem-state-names = "stop"; 1168 1169 status = "disabled"; 1170 1171 glink-edge { 1172 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 1173 IPCC_MPROC_SIGNAL_GLINK_QMP 1174 IRQ_TYPE_EDGE_RISING>; 1175 mboxes = <&ipcc IPCC_CLIENT_SLPI 1176 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1177 1178 label = "slpi"; 1179 qcom,remote-pid = <3>; 1180 1181 }; 1182 }; 1183 1184 cdsp: remoteproc@98900000 { 1185 compatible = "qcom,sm8350-cdsp-pas"; 1186 reg = <0 0x098900000 0 0x1400000>; 1187 1188 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1189 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1190 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1191 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1192 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1193 interrupt-names = "wdog", "fatal", "ready", 1194 "handover", "stop-ack"; 1195 1196 clocks = <&rpmhcc RPMH_CXO_CLK>; 1197 clock-names = "xo"; 1198 1199 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, 1200 <&rpmhpd 0>, 1201 <&rpmhpd 10>; 1202 power-domain-names = "load_state", "cx", "mxc"; 1203 1204 interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; 1205 1206 memory-region = <&pil_cdsp_mem>; 1207 1208 qcom,smem-states = <&smp2p_cdsp_out 0>; 1209 qcom,smem-state-names = "stop"; 1210 1211 status = "disabled"; 1212 1213 glink-edge { 1214 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1215 IPCC_MPROC_SIGNAL_GLINK_QMP 1216 IRQ_TYPE_EDGE_RISING>; 1217 mboxes = <&ipcc IPCC_CLIENT_CDSP 1218 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1219 1220 label = "cdsp"; 1221 qcom,remote-pid = <5>; 1222 }; 1223 }; 1224 1225 usb_1_hsphy: phy@88e3000 { 1226 compatible = "qcom,sm8350-usb-hs-phy", 1227 "qcom,usb-snps-hs-7nm-phy"; 1228 reg = <0 0x088e3000 0 0x400>; 1229 status = "disabled"; 1230 #phy-cells = <0>; 1231 1232 clocks = <&rpmhcc RPMH_CXO_CLK>; 1233 clock-names = "ref"; 1234 1235 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1236 }; 1237 1238 usb_2_hsphy: phy@88e4000 { 1239 compatible = "qcom,sm8250-usb-hs-phy", 1240 "qcom,usb-snps-hs-7nm-phy"; 1241 reg = <0 0x088e4000 0 0x400>; 1242 status = "disabled"; 1243 #phy-cells = <0>; 1244 1245 clocks = <&rpmhcc RPMH_CXO_CLK>; 1246 clock-names = "ref"; 1247 1248 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1249 }; 1250 1251 usb_1_qmpphy: phy-wrapper@88e9000 { 1252 compatible = "qcom,sm8350-qmp-usb3-phy"; 1253 reg = <0 0x088e9000 0 0x200>, 1254 <0 0x088e8000 0 0x20>; 1255 reg-names = "reg-base", "dp_com"; 1256 status = "disabled"; 1257 #clock-cells = <1>; 1258 #address-cells = <2>; 1259 #size-cells = <2>; 1260 ranges; 1261 1262 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1263 <&rpmhcc RPMH_CXO_CLK>, 1264 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1265 clock-names = "aux", "ref_clk_src", "com_aux"; 1266 1267 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1268 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1269 reset-names = "phy", "common"; 1270 1271 usb_1_ssphy: phy@88e9200 { 1272 reg = <0 0x088e9200 0 0x200>, 1273 <0 0x088e9400 0 0x200>, 1274 <0 0x088e9c00 0 0x400>, 1275 <0 0x088e9600 0 0x200>, 1276 <0 0x088e9800 0 0x200>, 1277 <0 0x088e9a00 0 0x100>; 1278 #phy-cells = <0>; 1279 #clock-cells = <1>; 1280 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1281 clock-names = "pipe0"; 1282 clock-output-names = "usb3_phy_pipe_clk_src"; 1283 }; 1284 }; 1285 1286 usb_2_qmpphy: phy-wrapper@88eb000 { 1287 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 1288 reg = <0 0x088eb000 0 0x200>; 1289 status = "disabled"; 1290 #clock-cells = <1>; 1291 #address-cells = <2>; 1292 #size-cells = <2>; 1293 ranges; 1294 1295 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 1296 <&rpmhcc RPMH_CXO_CLK>, 1297 <&gcc GCC_USB3_SEC_CLKREF_EN>, 1298 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 1299 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 1300 1301 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 1302 <&gcc GCC_USB3_PHY_SEC_BCR>; 1303 reset-names = "phy", "common"; 1304 1305 usb_2_ssphy: phy@88ebe00 { 1306 reg = <0 0x088ebe00 0 0x200>, 1307 <0 0x088ec000 0 0x200>, 1308 <0 0x088eb200 0 0x1100>; 1309 #phy-cells = <0>; 1310 #clock-cells = <1>; 1311 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 1312 clock-names = "pipe0"; 1313 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 1314 }; 1315 }; 1316 1317 dc_noc: interconnect@90c0000 { 1318 compatible = "qcom,sm8350-dc-noc"; 1319 reg = <0 0x090c0000 0 0x4200>; 1320 #interconnect-cells = <1>; 1321 qcom,bcm-voters = <&apps_bcm_voter>; 1322 }; 1323 1324 gem_noc: interconnect@9100000 { 1325 compatible = "qcom,sm8350-gem-noc"; 1326 reg = <0 0x09100000 0 0xb4000>; 1327 #interconnect-cells = <1>; 1328 qcom,bcm-voters = <&apps_bcm_voter>; 1329 }; 1330 1331 usb_1: usb@a6f8800 { 1332 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 1333 reg = <0 0x0a6f8800 0 0x400>; 1334 status = "disabled"; 1335 #address-cells = <2>; 1336 #size-cells = <2>; 1337 ranges; 1338 1339 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1340 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1341 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1342 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1343 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1344 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1345 "sleep"; 1346 1347 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1348 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1349 assigned-clock-rates = <19200000>, <200000000>; 1350 1351 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1352 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1353 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1354 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1355 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1356 "dm_hs_phy_irq", "ss_phy_irq"; 1357 1358 power-domains = <&gcc USB30_PRIM_GDSC>; 1359 1360 resets = <&gcc GCC_USB30_PRIM_BCR>; 1361 1362 usb_1_dwc3: usb@a600000 { 1363 compatible = "snps,dwc3"; 1364 reg = <0 0x0a600000 0 0xcd00>; 1365 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1366 iommus = <&apps_smmu 0x0 0x0>; 1367 snps,dis_u2_susphy_quirk; 1368 snps,dis_enblslpm_quirk; 1369 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1370 phy-names = "usb2-phy", "usb3-phy"; 1371 }; 1372 }; 1373 1374 usb_2: usb@a8f8800 { 1375 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 1376 reg = <0 0x0a8f8800 0 0x400>; 1377 status = "disabled"; 1378 #address-cells = <2>; 1379 #size-cells = <2>; 1380 ranges; 1381 1382 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1383 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1384 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1385 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1386 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 1387 <&gcc GCC_USB3_SEC_CLKREF_EN>; 1388 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1389 "sleep", "xo"; 1390 1391 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1392 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1393 assigned-clock-rates = <19200000>, <200000000>; 1394 1395 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1396 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 1397 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 1398 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 1399 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 1400 "dm_hs_phy_irq", "ss_phy_irq"; 1401 1402 power-domains = <&gcc USB30_SEC_GDSC>; 1403 1404 resets = <&gcc GCC_USB30_SEC_BCR>; 1405 1406 usb_2_dwc3: usb@a800000 { 1407 compatible = "snps,dwc3"; 1408 reg = <0 0x0a800000 0 0xcd00>; 1409 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1410 iommus = <&apps_smmu 0x20 0x0>; 1411 snps,dis_u2_susphy_quirk; 1412 snps,dis_enblslpm_quirk; 1413 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 1414 phy-names = "usb2-phy", "usb3-phy"; 1415 }; 1416 }; 1417 1418 adsp: remoteproc@17300000 { 1419 compatible = "qcom,sm8350-adsp-pas"; 1420 reg = <0 0x17300000 0 0x100>; 1421 1422 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 1423 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1424 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1425 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1426 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1427 interrupt-names = "wdog", "fatal", "ready", 1428 "handover", "stop-ack"; 1429 1430 clocks = <&rpmhcc RPMH_CXO_CLK>; 1431 clock-names = "xo"; 1432 1433 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, 1434 <&rpmhpd 4>, 1435 <&rpmhpd 5>; 1436 power-domain-names = "load_state", "lcx", "lmx"; 1437 1438 memory-region = <&pil_adsp_mem>; 1439 1440 qcom,smem-states = <&smp2p_adsp_out 0>; 1441 qcom,smem-state-names = "stop"; 1442 1443 status = "disabled"; 1444 1445 glink-edge { 1446 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1447 IPCC_MPROC_SIGNAL_GLINK_QMP 1448 IRQ_TYPE_EDGE_RISING>; 1449 mboxes = <&ipcc IPCC_CLIENT_LPASS 1450 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1451 1452 label = "lpass"; 1453 qcom,remote-pid = <2>; 1454 }; 1455 }; 1456 }; 1457 1458 thermal_zones: thermal-zones { 1459 cpu0-thermal { 1460 polling-delay-passive = <250>; 1461 polling-delay = <1000>; 1462 1463 thermal-sensors = <&tsens0 1>; 1464 1465 trips { 1466 cpu0_alert0: trip-point0 { 1467 temperature = <90000>; 1468 hysteresis = <2000>; 1469 type = "passive"; 1470 }; 1471 1472 cpu0_alert1: trip-point1 { 1473 temperature = <95000>; 1474 hysteresis = <2000>; 1475 type = "passive"; 1476 }; 1477 1478 cpu0_crit: cpu_crit { 1479 temperature = <110000>; 1480 hysteresis = <1000>; 1481 type = "critical"; 1482 }; 1483 }; 1484 1485 cooling-maps { 1486 map0 { 1487 trip = <&cpu0_alert0>; 1488 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1489 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1490 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1491 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1492 }; 1493 map1 { 1494 trip = <&cpu0_alert1>; 1495 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1496 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1497 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1498 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1499 }; 1500 }; 1501 }; 1502 1503 cpu1-thermal { 1504 polling-delay-passive = <250>; 1505 polling-delay = <1000>; 1506 1507 thermal-sensors = <&tsens0 2>; 1508 1509 trips { 1510 cpu1_alert0: trip-point0 { 1511 temperature = <90000>; 1512 hysteresis = <2000>; 1513 type = "passive"; 1514 }; 1515 1516 cpu1_alert1: trip-point1 { 1517 temperature = <95000>; 1518 hysteresis = <2000>; 1519 type = "passive"; 1520 }; 1521 1522 cpu1_crit: cpu_crit { 1523 temperature = <110000>; 1524 hysteresis = <1000>; 1525 type = "critical"; 1526 }; 1527 }; 1528 1529 cooling-maps { 1530 map0 { 1531 trip = <&cpu1_alert0>; 1532 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1533 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1534 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1535 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1536 }; 1537 map1 { 1538 trip = <&cpu1_alert1>; 1539 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1540 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1541 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1542 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1543 }; 1544 }; 1545 }; 1546 1547 cpu2-thermal { 1548 polling-delay-passive = <250>; 1549 polling-delay = <1000>; 1550 1551 thermal-sensors = <&tsens0 3>; 1552 1553 trips { 1554 cpu2_alert0: trip-point0 { 1555 temperature = <90000>; 1556 hysteresis = <2000>; 1557 type = "passive"; 1558 }; 1559 1560 cpu2_alert1: trip-point1 { 1561 temperature = <95000>; 1562 hysteresis = <2000>; 1563 type = "passive"; 1564 }; 1565 1566 cpu2_crit: cpu_crit { 1567 temperature = <110000>; 1568 hysteresis = <1000>; 1569 type = "critical"; 1570 }; 1571 }; 1572 1573 cooling-maps { 1574 map0 { 1575 trip = <&cpu2_alert0>; 1576 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1577 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1578 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1579 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1580 }; 1581 map1 { 1582 trip = <&cpu2_alert1>; 1583 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1584 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1585 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1586 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1587 }; 1588 }; 1589 }; 1590 1591 cpu3-thermal { 1592 polling-delay-passive = <250>; 1593 polling-delay = <1000>; 1594 1595 thermal-sensors = <&tsens0 4>; 1596 1597 trips { 1598 cpu3_alert0: trip-point0 { 1599 temperature = <90000>; 1600 hysteresis = <2000>; 1601 type = "passive"; 1602 }; 1603 1604 cpu3_alert1: trip-point1 { 1605 temperature = <95000>; 1606 hysteresis = <2000>; 1607 type = "passive"; 1608 }; 1609 1610 cpu3_crit: cpu_crit { 1611 temperature = <110000>; 1612 hysteresis = <1000>; 1613 type = "critical"; 1614 }; 1615 }; 1616 1617 cooling-maps { 1618 map0 { 1619 trip = <&cpu3_alert0>; 1620 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1621 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1622 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1623 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1624 }; 1625 map1 { 1626 trip = <&cpu3_alert1>; 1627 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1628 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1629 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1630 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1631 }; 1632 }; 1633 }; 1634 1635 cpu4-top-thermal { 1636 polling-delay-passive = <250>; 1637 polling-delay = <1000>; 1638 1639 thermal-sensors = <&tsens0 7>; 1640 1641 trips { 1642 cpu4_top_alert0: trip-point0 { 1643 temperature = <90000>; 1644 hysteresis = <2000>; 1645 type = "passive"; 1646 }; 1647 1648 cpu4_top_alert1: trip-point1 { 1649 temperature = <95000>; 1650 hysteresis = <2000>; 1651 type = "passive"; 1652 }; 1653 1654 cpu4_top_crit: cpu_crit { 1655 temperature = <110000>; 1656 hysteresis = <1000>; 1657 type = "critical"; 1658 }; 1659 }; 1660 1661 cooling-maps { 1662 map0 { 1663 trip = <&cpu4_top_alert0>; 1664 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1665 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1666 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1667 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1668 }; 1669 map1 { 1670 trip = <&cpu4_top_alert1>; 1671 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1672 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1673 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1674 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1675 }; 1676 }; 1677 }; 1678 1679 cpu5-top-thermal { 1680 polling-delay-passive = <250>; 1681 polling-delay = <1000>; 1682 1683 thermal-sensors = <&tsens0 8>; 1684 1685 trips { 1686 cpu5_top_alert0: trip-point0 { 1687 temperature = <90000>; 1688 hysteresis = <2000>; 1689 type = "passive"; 1690 }; 1691 1692 cpu5_top_alert1: trip-point1 { 1693 temperature = <95000>; 1694 hysteresis = <2000>; 1695 type = "passive"; 1696 }; 1697 1698 cpu5_top_crit: cpu_crit { 1699 temperature = <110000>; 1700 hysteresis = <1000>; 1701 type = "critical"; 1702 }; 1703 }; 1704 1705 cooling-maps { 1706 map0 { 1707 trip = <&cpu5_top_alert0>; 1708 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1709 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1710 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1711 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1712 }; 1713 map1 { 1714 trip = <&cpu5_top_alert1>; 1715 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1716 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1717 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1718 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1719 }; 1720 }; 1721 }; 1722 1723 cpu6-top-thermal { 1724 polling-delay-passive = <250>; 1725 polling-delay = <1000>; 1726 1727 thermal-sensors = <&tsens0 9>; 1728 1729 trips { 1730 cpu6_top_alert0: trip-point0 { 1731 temperature = <90000>; 1732 hysteresis = <2000>; 1733 type = "passive"; 1734 }; 1735 1736 cpu6_top_alert1: trip-point1 { 1737 temperature = <95000>; 1738 hysteresis = <2000>; 1739 type = "passive"; 1740 }; 1741 1742 cpu6_top_crit: cpu_crit { 1743 temperature = <110000>; 1744 hysteresis = <1000>; 1745 type = "critical"; 1746 }; 1747 }; 1748 1749 cooling-maps { 1750 map0 { 1751 trip = <&cpu6_top_alert0>; 1752 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1753 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1754 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1755 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1756 }; 1757 map1 { 1758 trip = <&cpu6_top_alert1>; 1759 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1760 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1761 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1762 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1763 }; 1764 }; 1765 }; 1766 1767 cpu7-top-thermal { 1768 polling-delay-passive = <250>; 1769 polling-delay = <1000>; 1770 1771 thermal-sensors = <&tsens0 10>; 1772 1773 trips { 1774 cpu7_top_alert0: trip-point0 { 1775 temperature = <90000>; 1776 hysteresis = <2000>; 1777 type = "passive"; 1778 }; 1779 1780 cpu7_top_alert1: trip-point1 { 1781 temperature = <95000>; 1782 hysteresis = <2000>; 1783 type = "passive"; 1784 }; 1785 1786 cpu7_top_crit: cpu_crit { 1787 temperature = <110000>; 1788 hysteresis = <1000>; 1789 type = "critical"; 1790 }; 1791 }; 1792 1793 cooling-maps { 1794 map0 { 1795 trip = <&cpu7_top_alert0>; 1796 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1797 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1798 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1799 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1800 }; 1801 map1 { 1802 trip = <&cpu7_top_alert1>; 1803 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1804 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1805 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1806 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1807 }; 1808 }; 1809 }; 1810 1811 cpu4-bottom-thermal { 1812 polling-delay-passive = <250>; 1813 polling-delay = <1000>; 1814 1815 thermal-sensors = <&tsens0 11>; 1816 1817 trips { 1818 cpu4_bottom_alert0: trip-point0 { 1819 temperature = <90000>; 1820 hysteresis = <2000>; 1821 type = "passive"; 1822 }; 1823 1824 cpu4_bottom_alert1: trip-point1 { 1825 temperature = <95000>; 1826 hysteresis = <2000>; 1827 type = "passive"; 1828 }; 1829 1830 cpu4_bottom_crit: cpu_crit { 1831 temperature = <110000>; 1832 hysteresis = <1000>; 1833 type = "critical"; 1834 }; 1835 }; 1836 1837 cooling-maps { 1838 map0 { 1839 trip = <&cpu4_bottom_alert0>; 1840 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1841 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1842 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1843 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1844 }; 1845 map1 { 1846 trip = <&cpu4_bottom_alert1>; 1847 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1848 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1849 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1850 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1851 }; 1852 }; 1853 }; 1854 1855 cpu5-bottom-thermal { 1856 polling-delay-passive = <250>; 1857 polling-delay = <1000>; 1858 1859 thermal-sensors = <&tsens0 12>; 1860 1861 trips { 1862 cpu5_bottom_alert0: trip-point0 { 1863 temperature = <90000>; 1864 hysteresis = <2000>; 1865 type = "passive"; 1866 }; 1867 1868 cpu5_bottom_alert1: trip-point1 { 1869 temperature = <95000>; 1870 hysteresis = <2000>; 1871 type = "passive"; 1872 }; 1873 1874 cpu5_bottom_crit: cpu_crit { 1875 temperature = <110000>; 1876 hysteresis = <1000>; 1877 type = "critical"; 1878 }; 1879 }; 1880 1881 cooling-maps { 1882 map0 { 1883 trip = <&cpu5_bottom_alert0>; 1884 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1885 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1886 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1887 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1888 }; 1889 map1 { 1890 trip = <&cpu5_bottom_alert1>; 1891 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1892 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1893 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1894 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1895 }; 1896 }; 1897 }; 1898 1899 cpu6-bottom-thermal { 1900 polling-delay-passive = <250>; 1901 polling-delay = <1000>; 1902 1903 thermal-sensors = <&tsens0 13>; 1904 1905 trips { 1906 cpu6_bottom_alert0: trip-point0 { 1907 temperature = <90000>; 1908 hysteresis = <2000>; 1909 type = "passive"; 1910 }; 1911 1912 cpu6_bottom_alert1: trip-point1 { 1913 temperature = <95000>; 1914 hysteresis = <2000>; 1915 type = "passive"; 1916 }; 1917 1918 cpu6_bottom_crit: cpu_crit { 1919 temperature = <110000>; 1920 hysteresis = <1000>; 1921 type = "critical"; 1922 }; 1923 }; 1924 1925 cooling-maps { 1926 map0 { 1927 trip = <&cpu6_bottom_alert0>; 1928 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1929 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1930 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1931 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1932 }; 1933 map1 { 1934 trip = <&cpu6_bottom_alert1>; 1935 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1936 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1937 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1938 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1939 }; 1940 }; 1941 }; 1942 1943 cpu7-bottom-thermal { 1944 polling-delay-passive = <250>; 1945 polling-delay = <1000>; 1946 1947 thermal-sensors = <&tsens0 14>; 1948 1949 trips { 1950 cpu7_bottom_alert0: trip-point0 { 1951 temperature = <90000>; 1952 hysteresis = <2000>; 1953 type = "passive"; 1954 }; 1955 1956 cpu7_bottom_alert1: trip-point1 { 1957 temperature = <95000>; 1958 hysteresis = <2000>; 1959 type = "passive"; 1960 }; 1961 1962 cpu7_bottom_crit: cpu_crit { 1963 temperature = <110000>; 1964 hysteresis = <1000>; 1965 type = "critical"; 1966 }; 1967 }; 1968 1969 cooling-maps { 1970 map0 { 1971 trip = <&cpu7_bottom_alert0>; 1972 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1973 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1974 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1975 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1976 }; 1977 map1 { 1978 trip = <&cpu7_bottom_alert1>; 1979 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1980 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1981 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1982 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1983 }; 1984 }; 1985 }; 1986 1987 aoss0-thermal { 1988 polling-delay-passive = <250>; 1989 polling-delay = <1000>; 1990 1991 thermal-sensors = <&tsens0 0>; 1992 1993 trips { 1994 aoss0_alert0: trip-point0 { 1995 temperature = <90000>; 1996 hysteresis = <2000>; 1997 type = "hot"; 1998 }; 1999 }; 2000 }; 2001 2002 cluster0-thermal { 2003 polling-delay-passive = <250>; 2004 polling-delay = <1000>; 2005 2006 thermal-sensors = <&tsens0 5>; 2007 2008 trips { 2009 cluster0_alert0: trip-point0 { 2010 temperature = <90000>; 2011 hysteresis = <2000>; 2012 type = "hot"; 2013 }; 2014 cluster0_crit: cluster0_crit { 2015 temperature = <110000>; 2016 hysteresis = <2000>; 2017 type = "critical"; 2018 }; 2019 }; 2020 }; 2021 2022 cluster1-thermal { 2023 polling-delay-passive = <250>; 2024 polling-delay = <1000>; 2025 2026 thermal-sensors = <&tsens0 6>; 2027 2028 trips { 2029 cluster1_alert0: trip-point0 { 2030 temperature = <90000>; 2031 hysteresis = <2000>; 2032 type = "hot"; 2033 }; 2034 cluster1_crit: cluster1_crit { 2035 temperature = <110000>; 2036 hysteresis = <2000>; 2037 type = "critical"; 2038 }; 2039 }; 2040 }; 2041 2042 aoss1-thermal { 2043 polling-delay-passive = <250>; 2044 polling-delay = <1000>; 2045 2046 thermal-sensors = <&tsens1 0>; 2047 2048 trips { 2049 aoss1_alert0: trip-point0 { 2050 temperature = <90000>; 2051 hysteresis = <2000>; 2052 type = "hot"; 2053 }; 2054 }; 2055 }; 2056 2057 gpu-thermal-top { 2058 polling-delay-passive = <250>; 2059 polling-delay = <1000>; 2060 2061 thermal-sensors = <&tsens1 1>; 2062 2063 trips { 2064 gpu1_alert0: trip-point0 { 2065 temperature = <90000>; 2066 hysteresis = <1000>; 2067 type = "hot"; 2068 }; 2069 }; 2070 }; 2071 2072 gpu-thermal-bottom { 2073 polling-delay-passive = <250>; 2074 polling-delay = <1000>; 2075 2076 thermal-sensors = <&tsens1 2>; 2077 2078 trips { 2079 gpu2_alert0: trip-point0 { 2080 temperature = <90000>; 2081 hysteresis = <1000>; 2082 type = "hot"; 2083 }; 2084 }; 2085 }; 2086 2087 nspss1-thermal { 2088 polling-delay-passive = <250>; 2089 polling-delay = <1000>; 2090 2091 thermal-sensors = <&tsens1 3>; 2092 2093 trips { 2094 nspss1_alert0: trip-point0 { 2095 temperature = <90000>; 2096 hysteresis = <1000>; 2097 type = "hot"; 2098 }; 2099 }; 2100 }; 2101 2102 nspss2-thermal { 2103 polling-delay-passive = <250>; 2104 polling-delay = <1000>; 2105 2106 thermal-sensors = <&tsens1 4>; 2107 2108 trips { 2109 nspss2_alert0: trip-point0 { 2110 temperature = <90000>; 2111 hysteresis = <1000>; 2112 type = "hot"; 2113 }; 2114 }; 2115 }; 2116 2117 nspss3-thermal { 2118 polling-delay-passive = <250>; 2119 polling-delay = <1000>; 2120 2121 thermal-sensors = <&tsens1 5>; 2122 2123 trips { 2124 nspss3_alert0: trip-point0 { 2125 temperature = <90000>; 2126 hysteresis = <1000>; 2127 type = "hot"; 2128 }; 2129 }; 2130 }; 2131 2132 video-thermal { 2133 polling-delay-passive = <250>; 2134 polling-delay = <1000>; 2135 2136 thermal-sensors = <&tsens1 6>; 2137 2138 trips { 2139 video_alert0: trip-point0 { 2140 temperature = <90000>; 2141 hysteresis = <2000>; 2142 type = "hot"; 2143 }; 2144 }; 2145 }; 2146 2147 mem-thermal { 2148 polling-delay-passive = <250>; 2149 polling-delay = <1000>; 2150 2151 thermal-sensors = <&tsens1 7>; 2152 2153 trips { 2154 mem_alert0: trip-point0 { 2155 temperature = <90000>; 2156 hysteresis = <2000>; 2157 type = "hot"; 2158 }; 2159 }; 2160 }; 2161 2162 modem1-thermal-top { 2163 polling-delay-passive = <250>; 2164 polling-delay = <1000>; 2165 2166 thermal-sensors = <&tsens1 8>; 2167 2168 trips { 2169 modem1_alert0: trip-point0 { 2170 temperature = <90000>; 2171 hysteresis = <2000>; 2172 type = "hot"; 2173 }; 2174 }; 2175 }; 2176 2177 modem2-thermal-top { 2178 polling-delay-passive = <250>; 2179 polling-delay = <1000>; 2180 2181 thermal-sensors = <&tsens1 9>; 2182 2183 trips { 2184 modem2_alert0: trip-point0 { 2185 temperature = <90000>; 2186 hysteresis = <2000>; 2187 type = "hot"; 2188 }; 2189 }; 2190 }; 2191 2192 modem3-thermal-top { 2193 polling-delay-passive = <250>; 2194 polling-delay = <1000>; 2195 2196 thermal-sensors = <&tsens1 10>; 2197 2198 trips { 2199 modem3_alert0: trip-point0 { 2200 temperature = <90000>; 2201 hysteresis = <2000>; 2202 type = "hot"; 2203 }; 2204 }; 2205 }; 2206 2207 modem4-thermal-top { 2208 polling-delay-passive = <250>; 2209 polling-delay = <1000>; 2210 2211 thermal-sensors = <&tsens1 11>; 2212 2213 trips { 2214 modem4_alert0: trip-point0 { 2215 temperature = <90000>; 2216 hysteresis = <2000>; 2217 type = "hot"; 2218 }; 2219 }; 2220 }; 2221 2222 camera-thermal-top { 2223 polling-delay-passive = <250>; 2224 polling-delay = <1000>; 2225 2226 thermal-sensors = <&tsens1 12>; 2227 2228 trips { 2229 camera1_alert0: trip-point0 { 2230 temperature = <90000>; 2231 hysteresis = <2000>; 2232 type = "hot"; 2233 }; 2234 }; 2235 }; 2236 2237 cam-thermal-bottom { 2238 polling-delay-passive = <250>; 2239 polling-delay = <1000>; 2240 2241 thermal-sensors = <&tsens1 13>; 2242 2243 trips { 2244 camera2_alert0: trip-point0 { 2245 temperature = <90000>; 2246 hysteresis = <2000>; 2247 type = "hot"; 2248 }; 2249 }; 2250 }; 2251 }; 2252 2253 timer { 2254 compatible = "arm,armv8-timer"; 2255 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2256 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2257 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2258 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2259 }; 2260}; 2261