1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/mux/ti-serdes.h> 10 11/ { 12 cmn_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17 18 cmn_refclk1: clock-cmnrefclk1 { 19 #clock-cells = <0>; 20 compatible = "fixed-clock"; 21 clock-frequency = <0>; 22 }; 23}; 24 25&cbass_main { 26 msmc_ram: sram@70000000 { 27 compatible = "mmio-sram"; 28 reg = <0x0 0x70000000 0x0 0x800000>; 29 #address-cells = <1>; 30 #size-cells = <1>; 31 ranges = <0x0 0x0 0x70000000 0x800000>; 32 33 atf-sram@0 { 34 reg = <0x0 0x20000>; 35 }; 36 }; 37 38 scm_conf: scm-conf@100000 { 39 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 40 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 41 #address-cells = <1>; 42 #size-cells = <1>; 43 ranges = <0x0 0x0 0x00100000 0x1c000>; 44 45 serdes_ln_ctrl: mux-controller@4080 { 46 compatible = "mmio-mux"; 47 reg = <0x00004080 0x50>; 48 #mux-control-cells = <1>; 49 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 50 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 51 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 52 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 53 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 54 /* SERDES4 lane0/1/2/3 select */ 55 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 56 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 57 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 58 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 59 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 60 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 61 }; 62 63 usb_serdes_mux: mux-controller@4000 { 64 compatible = "mmio-mux"; 65 #mux-control-cells = <1>; 66 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 67 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 68 }; 69 }; 70 71 gic500: interrupt-controller@1800000 { 72 compatible = "arm,gic-v3"; 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 #interrupt-cells = <3>; 77 interrupt-controller; 78 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 79 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 80 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 81 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 82 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 83 84 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 85 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 86 87 gic_its: msi-controller@1820000 { 88 compatible = "arm,gic-v3-its"; 89 reg = <0x00 0x01820000 0x00 0x10000>; 90 socionext,synquacer-pre-its = <0x1000000 0x400000>; 91 msi-controller; 92 #msi-cells = <1>; 93 }; 94 }; 95 96 main_gpio_intr: interrupt-controller@a00000 { 97 compatible = "ti,sci-intr"; 98 reg = <0x00 0x00a00000 0x00 0x800>; 99 ti,intr-trigger-type = <1>; 100 interrupt-controller; 101 interrupt-parent = <&gic500>; 102 #interrupt-cells = <1>; 103 ti,sci = <&dmsc>; 104 ti,sci-dev-id = <131>; 105 ti,interrupt-ranges = <8 392 56>; 106 }; 107 108 main_navss: bus@30000000 { 109 compatible = "simple-mfd"; 110 #address-cells = <2>; 111 #size-cells = <2>; 112 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 113 dma-coherent; 114 dma-ranges; 115 116 ti,sci-dev-id = <199>; 117 118 main_navss_intr: interrupt-controller@310e0000 { 119 compatible = "ti,sci-intr"; 120 reg = <0x0 0x310e0000 0x0 0x4000>; 121 ti,intr-trigger-type = <4>; 122 interrupt-controller; 123 interrupt-parent = <&gic500>; 124 #interrupt-cells = <1>; 125 ti,sci = <&dmsc>; 126 ti,sci-dev-id = <213>; 127 ti,interrupt-ranges = <0 64 64>, 128 <64 448 64>, 129 <128 672 64>; 130 }; 131 132 main_udmass_inta: interrupt-controller@33d00000 { 133 compatible = "ti,sci-inta"; 134 reg = <0x0 0x33d00000 0x0 0x100000>; 135 interrupt-controller; 136 interrupt-parent = <&main_navss_intr>; 137 msi-controller; 138 #interrupt-cells = <0>; 139 ti,sci = <&dmsc>; 140 ti,sci-dev-id = <209>; 141 ti,interrupt-ranges = <0 0 256>; 142 }; 143 144 secure_proxy_main: mailbox@32c00000 { 145 compatible = "ti,am654-secure-proxy"; 146 #mbox-cells = <1>; 147 reg-names = "target_data", "rt", "scfg"; 148 reg = <0x00 0x32c00000 0x00 0x100000>, 149 <0x00 0x32400000 0x00 0x100000>, 150 <0x00 0x32800000 0x00 0x100000>; 151 interrupt-names = "rx_011"; 152 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 153 }; 154 155 smmu0: iommu@36600000 { 156 compatible = "arm,smmu-v3"; 157 reg = <0x0 0x36600000 0x0 0x100000>; 158 interrupt-parent = <&gic500>; 159 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 160 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 161 interrupt-names = "eventq", "gerror"; 162 #iommu-cells = <1>; 163 }; 164 165 hwspinlock: spinlock@30e00000 { 166 compatible = "ti,am654-hwspinlock"; 167 reg = <0x00 0x30e00000 0x00 0x1000>; 168 #hwlock-cells = <1>; 169 }; 170 171 mailbox0_cluster0: mailbox@31f80000 { 172 compatible = "ti,am654-mailbox"; 173 reg = <0x00 0x31f80000 0x00 0x200>; 174 #mbox-cells = <1>; 175 ti,mbox-num-users = <4>; 176 ti,mbox-num-fifos = <16>; 177 interrupt-parent = <&main_navss_intr>; 178 }; 179 180 mailbox0_cluster1: mailbox@31f81000 { 181 compatible = "ti,am654-mailbox"; 182 reg = <0x00 0x31f81000 0x00 0x200>; 183 #mbox-cells = <1>; 184 ti,mbox-num-users = <4>; 185 ti,mbox-num-fifos = <16>; 186 interrupt-parent = <&main_navss_intr>; 187 }; 188 189 mailbox0_cluster2: mailbox@31f82000 { 190 compatible = "ti,am654-mailbox"; 191 reg = <0x00 0x31f82000 0x00 0x200>; 192 #mbox-cells = <1>; 193 ti,mbox-num-users = <4>; 194 ti,mbox-num-fifos = <16>; 195 interrupt-parent = <&main_navss_intr>; 196 }; 197 198 mailbox0_cluster3: mailbox@31f83000 { 199 compatible = "ti,am654-mailbox"; 200 reg = <0x00 0x31f83000 0x00 0x200>; 201 #mbox-cells = <1>; 202 ti,mbox-num-users = <4>; 203 ti,mbox-num-fifos = <16>; 204 interrupt-parent = <&main_navss_intr>; 205 }; 206 207 mailbox0_cluster4: mailbox@31f84000 { 208 compatible = "ti,am654-mailbox"; 209 reg = <0x00 0x31f84000 0x00 0x200>; 210 #mbox-cells = <1>; 211 ti,mbox-num-users = <4>; 212 ti,mbox-num-fifos = <16>; 213 interrupt-parent = <&main_navss_intr>; 214 }; 215 216 mailbox0_cluster5: mailbox@31f85000 { 217 compatible = "ti,am654-mailbox"; 218 reg = <0x00 0x31f85000 0x00 0x200>; 219 #mbox-cells = <1>; 220 ti,mbox-num-users = <4>; 221 ti,mbox-num-fifos = <16>; 222 interrupt-parent = <&main_navss_intr>; 223 }; 224 225 mailbox0_cluster6: mailbox@31f86000 { 226 compatible = "ti,am654-mailbox"; 227 reg = <0x00 0x31f86000 0x00 0x200>; 228 #mbox-cells = <1>; 229 ti,mbox-num-users = <4>; 230 ti,mbox-num-fifos = <16>; 231 interrupt-parent = <&main_navss_intr>; 232 }; 233 234 mailbox0_cluster7: mailbox@31f87000 { 235 compatible = "ti,am654-mailbox"; 236 reg = <0x00 0x31f87000 0x00 0x200>; 237 #mbox-cells = <1>; 238 ti,mbox-num-users = <4>; 239 ti,mbox-num-fifos = <16>; 240 interrupt-parent = <&main_navss_intr>; 241 }; 242 243 mailbox0_cluster8: mailbox@31f88000 { 244 compatible = "ti,am654-mailbox"; 245 reg = <0x00 0x31f88000 0x00 0x200>; 246 #mbox-cells = <1>; 247 ti,mbox-num-users = <4>; 248 ti,mbox-num-fifos = <16>; 249 interrupt-parent = <&main_navss_intr>; 250 }; 251 252 mailbox0_cluster9: mailbox@31f89000 { 253 compatible = "ti,am654-mailbox"; 254 reg = <0x00 0x31f89000 0x00 0x200>; 255 #mbox-cells = <1>; 256 ti,mbox-num-users = <4>; 257 ti,mbox-num-fifos = <16>; 258 interrupt-parent = <&main_navss_intr>; 259 }; 260 261 mailbox0_cluster10: mailbox@31f8a000 { 262 compatible = "ti,am654-mailbox"; 263 reg = <0x00 0x31f8a000 0x00 0x200>; 264 #mbox-cells = <1>; 265 ti,mbox-num-users = <4>; 266 ti,mbox-num-fifos = <16>; 267 interrupt-parent = <&main_navss_intr>; 268 }; 269 270 mailbox0_cluster11: mailbox@31f8b000 { 271 compatible = "ti,am654-mailbox"; 272 reg = <0x00 0x31f8b000 0x00 0x200>; 273 #mbox-cells = <1>; 274 ti,mbox-num-users = <4>; 275 ti,mbox-num-fifos = <16>; 276 interrupt-parent = <&main_navss_intr>; 277 }; 278 279 main_ringacc: ringacc@3c000000 { 280 compatible = "ti,am654-navss-ringacc"; 281 reg = <0x0 0x3c000000 0x0 0x400000>, 282 <0x0 0x38000000 0x0 0x400000>, 283 <0x0 0x31120000 0x0 0x100>, 284 <0x0 0x33000000 0x0 0x40000>; 285 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 286 ti,num-rings = <1024>; 287 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 288 ti,sci = <&dmsc>; 289 ti,sci-dev-id = <211>; 290 msi-parent = <&main_udmass_inta>; 291 }; 292 293 main_udmap: dma-controller@31150000 { 294 compatible = "ti,j721e-navss-main-udmap"; 295 reg = <0x0 0x31150000 0x0 0x100>, 296 <0x0 0x34000000 0x0 0x100000>, 297 <0x0 0x35000000 0x0 0x100000>; 298 reg-names = "gcfg", "rchanrt", "tchanrt"; 299 msi-parent = <&main_udmass_inta>; 300 #dma-cells = <1>; 301 302 ti,sci = <&dmsc>; 303 ti,sci-dev-id = <212>; 304 ti,ringacc = <&main_ringacc>; 305 306 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 307 <0x0f>, /* TX_HCHAN */ 308 <0x10>; /* TX_UHCHAN */ 309 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 310 <0x0b>, /* RX_HCHAN */ 311 <0x0c>; /* RX_UHCHAN */ 312 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 313 }; 314 315 cpts@310d0000 { 316 compatible = "ti,j721e-cpts"; 317 reg = <0x0 0x310d0000 0x0 0x400>; 318 reg-names = "cpts"; 319 clocks = <&k3_clks 201 1>; 320 clock-names = "cpts"; 321 interrupts-extended = <&main_navss_intr 391>; 322 interrupt-names = "cpts"; 323 ti,cpts-periodic-outputs = <6>; 324 ti,cpts-ext-ts-inputs = <8>; 325 }; 326 }; 327 328 main_crypto: crypto@4e00000 { 329 compatible = "ti,j721e-sa2ul"; 330 reg = <0x0 0x4e00000 0x0 0x1200>; 331 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 332 #address-cells = <2>; 333 #size-cells = <2>; 334 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 335 336 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 337 <&main_udmap 0x4001>; 338 dma-names = "tx", "rx1", "rx2"; 339 340 rng: rng@4e10000 { 341 compatible = "inside-secure,safexcel-eip76"; 342 reg = <0x0 0x4e10000 0x0 0x7d>; 343 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&k3_clks 264 1>; 345 }; 346 }; 347 348 main_pmx0: pinctrl@11c000 { 349 compatible = "pinctrl-single"; 350 /* Proxy 0 addressing */ 351 reg = <0x0 0x11c000 0x0 0x2b4>; 352 #pinctrl-cells = <1>; 353 pinctrl-single,register-width = <32>; 354 pinctrl-single,function-mask = <0xffffffff>; 355 }; 356 357 serdes_wiz0: wiz@5000000 { 358 compatible = "ti,j721e-wiz-16g"; 359 #address-cells = <1>; 360 #size-cells = <1>; 361 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 362 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; 363 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 364 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 365 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 366 num-lanes = <2>; 367 #reset-cells = <1>; 368 ranges = <0x5000000 0x0 0x5000000 0x10000>; 369 370 wiz0_pll0_refclk: pll0-refclk { 371 clocks = <&k3_clks 292 11>, <&cmn_refclk>; 372 #clock-cells = <0>; 373 assigned-clocks = <&wiz0_pll0_refclk>; 374 assigned-clock-parents = <&k3_clks 292 11>; 375 }; 376 377 wiz0_pll1_refclk: pll1-refclk { 378 clocks = <&k3_clks 292 0>, <&cmn_refclk1>; 379 #clock-cells = <0>; 380 assigned-clocks = <&wiz0_pll1_refclk>; 381 assigned-clock-parents = <&k3_clks 292 0>; 382 }; 383 384 wiz0_refclk_dig: refclk-dig { 385 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; 386 #clock-cells = <0>; 387 assigned-clocks = <&wiz0_refclk_dig>; 388 assigned-clock-parents = <&k3_clks 292 11>; 389 }; 390 391 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 392 clocks = <&wiz0_refclk_dig>; 393 #clock-cells = <0>; 394 }; 395 396 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 397 clocks = <&wiz0_pll1_refclk>; 398 #clock-cells = <0>; 399 }; 400 401 serdes0: serdes@5000000 { 402 compatible = "ti,sierra-phy-t0"; 403 reg-names = "serdes"; 404 reg = <0x5000000 0x10000>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 #clock-cells = <1>; 408 resets = <&serdes_wiz0 0>; 409 reset-names = "sierra_reset"; 410 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, 411 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; 412 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 413 "pll0_refclk", "pll1_refclk"; 414 }; 415 }; 416 417 serdes_wiz1: wiz@5010000 { 418 compatible = "ti,j721e-wiz-16g"; 419 #address-cells = <1>; 420 #size-cells = <1>; 421 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 422 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; 423 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 424 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 425 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 426 num-lanes = <2>; 427 #reset-cells = <1>; 428 ranges = <0x5010000 0x0 0x5010000 0x10000>; 429 430 wiz1_pll0_refclk: pll0-refclk { 431 clocks = <&k3_clks 293 13>, <&cmn_refclk>; 432 #clock-cells = <0>; 433 assigned-clocks = <&wiz1_pll0_refclk>; 434 assigned-clock-parents = <&k3_clks 293 13>; 435 }; 436 437 wiz1_pll1_refclk: pll1-refclk { 438 clocks = <&k3_clks 293 0>, <&cmn_refclk1>; 439 #clock-cells = <0>; 440 assigned-clocks = <&wiz1_pll1_refclk>; 441 assigned-clock-parents = <&k3_clks 293 0>; 442 }; 443 444 wiz1_refclk_dig: refclk-dig { 445 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; 446 #clock-cells = <0>; 447 assigned-clocks = <&wiz1_refclk_dig>; 448 assigned-clock-parents = <&k3_clks 293 13>; 449 }; 450 451 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 452 clocks = <&wiz1_refclk_dig>; 453 #clock-cells = <0>; 454 }; 455 456 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 457 clocks = <&wiz1_pll1_refclk>; 458 #clock-cells = <0>; 459 }; 460 461 serdes1: serdes@5010000 { 462 compatible = "ti,sierra-phy-t0"; 463 reg-names = "serdes"; 464 reg = <0x5010000 0x10000>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 #clock-cells = <1>; 468 resets = <&serdes_wiz1 0>; 469 reset-names = "sierra_reset"; 470 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, 471 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; 472 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 473 "pll0_refclk", "pll1_refclk"; 474 }; 475 }; 476 477 serdes_wiz2: wiz@5020000 { 478 compatible = "ti,j721e-wiz-16g"; 479 #address-cells = <1>; 480 #size-cells = <1>; 481 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 482 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; 483 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 484 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 485 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 486 num-lanes = <2>; 487 #reset-cells = <1>; 488 ranges = <0x5020000 0x0 0x5020000 0x10000>; 489 490 wiz2_pll0_refclk: pll0-refclk { 491 clocks = <&k3_clks 294 11>, <&cmn_refclk>; 492 #clock-cells = <0>; 493 assigned-clocks = <&wiz2_pll0_refclk>; 494 assigned-clock-parents = <&k3_clks 294 11>; 495 }; 496 497 wiz2_pll1_refclk: pll1-refclk { 498 clocks = <&k3_clks 294 0>, <&cmn_refclk1>; 499 #clock-cells = <0>; 500 assigned-clocks = <&wiz2_pll1_refclk>; 501 assigned-clock-parents = <&k3_clks 294 0>; 502 }; 503 504 wiz2_refclk_dig: refclk-dig { 505 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; 506 #clock-cells = <0>; 507 assigned-clocks = <&wiz2_refclk_dig>; 508 assigned-clock-parents = <&k3_clks 294 11>; 509 }; 510 511 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 512 clocks = <&wiz2_refclk_dig>; 513 #clock-cells = <0>; 514 }; 515 516 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 517 clocks = <&wiz2_pll1_refclk>; 518 #clock-cells = <0>; 519 }; 520 521 serdes2: serdes@5020000 { 522 compatible = "ti,sierra-phy-t0"; 523 reg-names = "serdes"; 524 reg = <0x5020000 0x10000>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 #clock-cells = <1>; 528 resets = <&serdes_wiz2 0>; 529 reset-names = "sierra_reset"; 530 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, 531 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; 532 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 533 "pll0_refclk", "pll1_refclk"; 534 }; 535 }; 536 537 serdes_wiz3: wiz@5030000 { 538 compatible = "ti,j721e-wiz-16g"; 539 #address-cells = <1>; 540 #size-cells = <1>; 541 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 542 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; 543 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 544 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 545 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 546 num-lanes = <2>; 547 #reset-cells = <1>; 548 ranges = <0x5030000 0x0 0x5030000 0x10000>; 549 550 wiz3_pll0_refclk: pll0-refclk { 551 clocks = <&k3_clks 295 9>, <&cmn_refclk>; 552 #clock-cells = <0>; 553 assigned-clocks = <&wiz3_pll0_refclk>; 554 assigned-clock-parents = <&k3_clks 295 9>; 555 }; 556 557 wiz3_pll1_refclk: pll1-refclk { 558 clocks = <&k3_clks 295 0>, <&cmn_refclk1>; 559 #clock-cells = <0>; 560 assigned-clocks = <&wiz3_pll1_refclk>; 561 assigned-clock-parents = <&k3_clks 295 0>; 562 }; 563 564 wiz3_refclk_dig: refclk-dig { 565 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; 566 #clock-cells = <0>; 567 assigned-clocks = <&wiz3_refclk_dig>; 568 assigned-clock-parents = <&k3_clks 295 9>; 569 }; 570 571 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 572 clocks = <&wiz3_refclk_dig>; 573 #clock-cells = <0>; 574 }; 575 576 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 577 clocks = <&wiz3_pll1_refclk>; 578 #clock-cells = <0>; 579 }; 580 581 serdes3: serdes@5030000 { 582 compatible = "ti,sierra-phy-t0"; 583 reg-names = "serdes"; 584 reg = <0x5030000 0x10000>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 #clock-cells = <1>; 588 resets = <&serdes_wiz3 0>; 589 reset-names = "sierra_reset"; 590 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, 591 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; 592 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 593 "pll0_refclk", "pll1_refclk"; 594 }; 595 }; 596 597 pcie0_rc: pcie@2900000 { 598 compatible = "ti,j721e-pcie-host"; 599 reg = <0x00 0x02900000 0x00 0x1000>, 600 <0x00 0x02907000 0x00 0x400>, 601 <0x00 0x0d000000 0x00 0x00800000>, 602 <0x00 0x10000000 0x00 0x00001000>; 603 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 604 interrupt-names = "link_state"; 605 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 606 device_type = "pci"; 607 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 608 max-link-speed = <3>; 609 num-lanes = <2>; 610 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 611 clocks = <&k3_clks 239 1>; 612 clock-names = "fck"; 613 #address-cells = <3>; 614 #size-cells = <2>; 615 bus-range = <0x0 0xff>; 616 vendor-id = <0x104c>; 617 device-id = <0xb00d>; 618 msi-map = <0x0 &gic_its 0x0 0x10000>; 619 dma-coherent; 620 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 621 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 622 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 623 }; 624 625 pcie0_ep: pcie-ep@2900000 { 626 compatible = "ti,j721e-pcie-ep"; 627 reg = <0x00 0x02900000 0x00 0x1000>, 628 <0x00 0x02907000 0x00 0x400>, 629 <0x00 0x0d000000 0x00 0x00800000>, 630 <0x00 0x10000000 0x00 0x08000000>; 631 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 632 interrupt-names = "link_state"; 633 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 634 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 635 max-link-speed = <3>; 636 num-lanes = <2>; 637 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 638 clocks = <&k3_clks 239 1>; 639 clock-names = "fck"; 640 max-functions = /bits/ 8 <6>; 641 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 642 dma-coherent; 643 }; 644 645 pcie1_rc: pcie@2910000 { 646 compatible = "ti,j721e-pcie-host"; 647 reg = <0x00 0x02910000 0x00 0x1000>, 648 <0x00 0x02917000 0x00 0x400>, 649 <0x00 0x0d800000 0x00 0x00800000>, 650 <0x00 0x18000000 0x00 0x00001000>; 651 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 652 interrupt-names = "link_state"; 653 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 654 device_type = "pci"; 655 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 656 max-link-speed = <3>; 657 num-lanes = <2>; 658 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 659 clocks = <&k3_clks 240 1>; 660 clock-names = "fck"; 661 #address-cells = <3>; 662 #size-cells = <2>; 663 bus-range = <0x0 0xff>; 664 vendor-id = <0x104c>; 665 device-id = <0xb00d>; 666 msi-map = <0x0 &gic_its 0x10000 0x10000>; 667 dma-coherent; 668 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, 669 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; 670 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 671 }; 672 673 pcie1_ep: pcie-ep@2910000 { 674 compatible = "ti,j721e-pcie-ep"; 675 reg = <0x00 0x02910000 0x00 0x1000>, 676 <0x00 0x02917000 0x00 0x400>, 677 <0x00 0x0d800000 0x00 0x00800000>, 678 <0x00 0x18000000 0x00 0x08000000>; 679 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 680 interrupt-names = "link_state"; 681 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 682 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 683 max-link-speed = <3>; 684 num-lanes = <2>; 685 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 686 clocks = <&k3_clks 240 1>; 687 clock-names = "fck"; 688 max-functions = /bits/ 8 <6>; 689 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 690 dma-coherent; 691 }; 692 693 pcie2_rc: pcie@2920000 { 694 compatible = "ti,j721e-pcie-host"; 695 reg = <0x00 0x02920000 0x00 0x1000>, 696 <0x00 0x02927000 0x00 0x400>, 697 <0x00 0x0e000000 0x00 0x00800000>, 698 <0x44 0x00000000 0x00 0x00001000>; 699 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 700 interrupt-names = "link_state"; 701 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 702 device_type = "pci"; 703 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 704 max-link-speed = <3>; 705 num-lanes = <2>; 706 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 707 clocks = <&k3_clks 241 1>; 708 clock-names = "fck"; 709 #address-cells = <3>; 710 #size-cells = <2>; 711 bus-range = <0x0 0xff>; 712 vendor-id = <0x104c>; 713 device-id = <0xb00d>; 714 msi-map = <0x0 &gic_its 0x20000 0x10000>; 715 dma-coherent; 716 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 717 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 718 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 719 }; 720 721 pcie2_ep: pcie-ep@2920000 { 722 compatible = "ti,j721e-pcie-ep"; 723 reg = <0x00 0x02920000 0x00 0x1000>, 724 <0x00 0x02927000 0x00 0x400>, 725 <0x00 0x0e000000 0x00 0x00800000>, 726 <0x44 0x00000000 0x00 0x08000000>; 727 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 728 interrupt-names = "link_state"; 729 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 730 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 731 max-link-speed = <3>; 732 num-lanes = <2>; 733 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 734 clocks = <&k3_clks 241 1>; 735 clock-names = "fck"; 736 max-functions = /bits/ 8 <6>; 737 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 738 dma-coherent; 739 }; 740 741 pcie3_rc: pcie@2930000 { 742 compatible = "ti,j721e-pcie-host"; 743 reg = <0x00 0x02930000 0x00 0x1000>, 744 <0x00 0x02937000 0x00 0x400>, 745 <0x00 0x0e800000 0x00 0x00800000>, 746 <0x44 0x10000000 0x00 0x00001000>; 747 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 748 interrupt-names = "link_state"; 749 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 750 device_type = "pci"; 751 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 752 max-link-speed = <3>; 753 num-lanes = <2>; 754 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 755 clocks = <&k3_clks 242 1>; 756 clock-names = "fck"; 757 #address-cells = <3>; 758 #size-cells = <2>; 759 bus-range = <0x0 0xff>; 760 vendor-id = <0x104c>; 761 device-id = <0xb00d>; 762 msi-map = <0x0 &gic_its 0x30000 0x10000>; 763 dma-coherent; 764 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 765 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 766 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 767 }; 768 769 pcie3_ep: pcie-ep@2930000 { 770 compatible = "ti,j721e-pcie-ep"; 771 reg = <0x00 0x02930000 0x00 0x1000>, 772 <0x00 0x02937000 0x00 0x400>, 773 <0x00 0x0e800000 0x00 0x00800000>, 774 <0x44 0x10000000 0x00 0x08000000>; 775 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 776 interrupt-names = "link_state"; 777 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 778 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 779 max-link-speed = <3>; 780 num-lanes = <2>; 781 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 782 clocks = <&k3_clks 242 1>; 783 clock-names = "fck"; 784 max-functions = /bits/ 8 <6>; 785 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 786 dma-coherent; 787 #address-cells = <2>; 788 #size-cells = <2>; 789 }; 790 791 main_uart0: serial@2800000 { 792 compatible = "ti,j721e-uart", "ti,am654-uart"; 793 reg = <0x00 0x02800000 0x00 0x100>; 794 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 795 clock-frequency = <48000000>; 796 current-speed = <115200>; 797 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 798 clocks = <&k3_clks 146 0>; 799 clock-names = "fclk"; 800 }; 801 802 main_uart1: serial@2810000 { 803 compatible = "ti,j721e-uart", "ti,am654-uart"; 804 reg = <0x00 0x02810000 0x00 0x100>; 805 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 806 clock-frequency = <48000000>; 807 current-speed = <115200>; 808 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 809 clocks = <&k3_clks 278 0>; 810 clock-names = "fclk"; 811 }; 812 813 main_uart2: serial@2820000 { 814 compatible = "ti,j721e-uart", "ti,am654-uart"; 815 reg = <0x00 0x02820000 0x00 0x100>; 816 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 817 clock-frequency = <48000000>; 818 current-speed = <115200>; 819 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 820 clocks = <&k3_clks 279 0>; 821 clock-names = "fclk"; 822 }; 823 824 main_uart3: serial@2830000 { 825 compatible = "ti,j721e-uart", "ti,am654-uart"; 826 reg = <0x00 0x02830000 0x00 0x100>; 827 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 828 clock-frequency = <48000000>; 829 current-speed = <115200>; 830 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 831 clocks = <&k3_clks 280 0>; 832 clock-names = "fclk"; 833 }; 834 835 main_uart4: serial@2840000 { 836 compatible = "ti,j721e-uart", "ti,am654-uart"; 837 reg = <0x00 0x02840000 0x00 0x100>; 838 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 839 clock-frequency = <48000000>; 840 current-speed = <115200>; 841 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 842 clocks = <&k3_clks 281 0>; 843 clock-names = "fclk"; 844 }; 845 846 main_uart5: serial@2850000 { 847 compatible = "ti,j721e-uart", "ti,am654-uart"; 848 reg = <0x00 0x02850000 0x00 0x100>; 849 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 850 clock-frequency = <48000000>; 851 current-speed = <115200>; 852 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 853 clocks = <&k3_clks 282 0>; 854 clock-names = "fclk"; 855 }; 856 857 main_uart6: serial@2860000 { 858 compatible = "ti,j721e-uart", "ti,am654-uart"; 859 reg = <0x00 0x02860000 0x00 0x100>; 860 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 861 clock-frequency = <48000000>; 862 current-speed = <115200>; 863 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 864 clocks = <&k3_clks 283 0>; 865 clock-names = "fclk"; 866 }; 867 868 main_uart7: serial@2870000 { 869 compatible = "ti,j721e-uart", "ti,am654-uart"; 870 reg = <0x00 0x02870000 0x00 0x100>; 871 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 872 clock-frequency = <48000000>; 873 current-speed = <115200>; 874 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 875 clocks = <&k3_clks 284 0>; 876 clock-names = "fclk"; 877 }; 878 879 main_uart8: serial@2880000 { 880 compatible = "ti,j721e-uart", "ti,am654-uart"; 881 reg = <0x00 0x02880000 0x00 0x100>; 882 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 883 clock-frequency = <48000000>; 884 current-speed = <115200>; 885 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 886 clocks = <&k3_clks 285 0>; 887 clock-names = "fclk"; 888 }; 889 890 main_uart9: serial@2890000 { 891 compatible = "ti,j721e-uart", "ti,am654-uart"; 892 reg = <0x00 0x02890000 0x00 0x100>; 893 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 894 clock-frequency = <48000000>; 895 current-speed = <115200>; 896 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 897 clocks = <&k3_clks 286 0>; 898 clock-names = "fclk"; 899 }; 900 901 main_gpio0: gpio@600000 { 902 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 903 reg = <0x0 0x00600000 0x0 0x100>; 904 gpio-controller; 905 #gpio-cells = <2>; 906 interrupt-parent = <&main_gpio_intr>; 907 interrupts = <256>, <257>, <258>, <259>, 908 <260>, <261>, <262>, <263>; 909 interrupt-controller; 910 #interrupt-cells = <2>; 911 ti,ngpio = <128>; 912 ti,davinci-gpio-unbanked = <0>; 913 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 914 clocks = <&k3_clks 105 0>; 915 clock-names = "gpio"; 916 }; 917 918 main_gpio1: gpio@601000 { 919 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 920 reg = <0x0 0x00601000 0x0 0x100>; 921 gpio-controller; 922 #gpio-cells = <2>; 923 interrupt-parent = <&main_gpio_intr>; 924 interrupts = <288>, <289>, <290>; 925 interrupt-controller; 926 #interrupt-cells = <2>; 927 ti,ngpio = <36>; 928 ti,davinci-gpio-unbanked = <0>; 929 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 930 clocks = <&k3_clks 106 0>; 931 clock-names = "gpio"; 932 }; 933 934 main_gpio2: gpio@610000 { 935 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 936 reg = <0x0 0x00610000 0x0 0x100>; 937 gpio-controller; 938 #gpio-cells = <2>; 939 interrupt-parent = <&main_gpio_intr>; 940 interrupts = <264>, <265>, <266>, <267>, 941 <268>, <269>, <270>, <271>; 942 interrupt-controller; 943 #interrupt-cells = <2>; 944 ti,ngpio = <128>; 945 ti,davinci-gpio-unbanked = <0>; 946 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 947 clocks = <&k3_clks 107 0>; 948 clock-names = "gpio"; 949 }; 950 951 main_gpio3: gpio@611000 { 952 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 953 reg = <0x0 0x00611000 0x0 0x100>; 954 gpio-controller; 955 #gpio-cells = <2>; 956 interrupt-parent = <&main_gpio_intr>; 957 interrupts = <292>, <293>, <294>; 958 interrupt-controller; 959 #interrupt-cells = <2>; 960 ti,ngpio = <36>; 961 ti,davinci-gpio-unbanked = <0>; 962 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 963 clocks = <&k3_clks 108 0>; 964 clock-names = "gpio"; 965 }; 966 967 main_gpio4: gpio@620000 { 968 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 969 reg = <0x0 0x00620000 0x0 0x100>; 970 gpio-controller; 971 #gpio-cells = <2>; 972 interrupt-parent = <&main_gpio_intr>; 973 interrupts = <272>, <273>, <274>, <275>, 974 <276>, <277>, <278>, <279>; 975 interrupt-controller; 976 #interrupt-cells = <2>; 977 ti,ngpio = <128>; 978 ti,davinci-gpio-unbanked = <0>; 979 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 980 clocks = <&k3_clks 109 0>; 981 clock-names = "gpio"; 982 }; 983 984 main_gpio5: gpio@621000 { 985 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 986 reg = <0x0 0x00621000 0x0 0x100>; 987 gpio-controller; 988 #gpio-cells = <2>; 989 interrupt-parent = <&main_gpio_intr>; 990 interrupts = <296>, <297>, <298>; 991 interrupt-controller; 992 #interrupt-cells = <2>; 993 ti,ngpio = <36>; 994 ti,davinci-gpio-unbanked = <0>; 995 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 996 clocks = <&k3_clks 110 0>; 997 clock-names = "gpio"; 998 }; 999 1000 main_gpio6: gpio@630000 { 1001 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1002 reg = <0x0 0x00630000 0x0 0x100>; 1003 gpio-controller; 1004 #gpio-cells = <2>; 1005 interrupt-parent = <&main_gpio_intr>; 1006 interrupts = <280>, <281>, <282>, <283>, 1007 <284>, <285>, <286>, <287>; 1008 interrupt-controller; 1009 #interrupt-cells = <2>; 1010 ti,ngpio = <128>; 1011 ti,davinci-gpio-unbanked = <0>; 1012 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1013 clocks = <&k3_clks 111 0>; 1014 clock-names = "gpio"; 1015 }; 1016 1017 main_gpio7: gpio@631000 { 1018 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1019 reg = <0x0 0x00631000 0x0 0x100>; 1020 gpio-controller; 1021 #gpio-cells = <2>; 1022 interrupt-parent = <&main_gpio_intr>; 1023 interrupts = <300>, <301>, <302>; 1024 interrupt-controller; 1025 #interrupt-cells = <2>; 1026 ti,ngpio = <36>; 1027 ti,davinci-gpio-unbanked = <0>; 1028 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1029 clocks = <&k3_clks 112 0>; 1030 clock-names = "gpio"; 1031 }; 1032 1033 main_sdhci0: mmc@4f80000 { 1034 compatible = "ti,j721e-sdhci-8bit"; 1035 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1036 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1037 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1038 clock-names = "clk_ahb", "clk_xin"; 1039 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; 1040 assigned-clocks = <&k3_clks 91 1>; 1041 assigned-clock-parents = <&k3_clks 91 2>; 1042 bus-width = <8>; 1043 mmc-hs200-1_8v; 1044 mmc-ddr-1_8v; 1045 ti,otap-del-sel-legacy = <0xf>; 1046 ti,otap-del-sel-mmc-hs = <0xf>; 1047 ti,otap-del-sel-ddr52 = <0x5>; 1048 ti,otap-del-sel-hs200 = <0x6>; 1049 ti,otap-del-sel-hs400 = <0x0>; 1050 ti,itap-del-sel-legacy = <0x10>; 1051 ti,itap-del-sel-mmc-hs = <0xa>; 1052 ti,itap-del-sel-ddr52 = <0x3>; 1053 ti,trm-icp = <0x8>; 1054 dma-coherent; 1055 }; 1056 1057 main_sdhci1: mmc@4fb0000 { 1058 compatible = "ti,j721e-sdhci-4bit"; 1059 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1060 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1061 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1062 clock-names = "clk_ahb", "clk_xin"; 1063 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; 1064 assigned-clocks = <&k3_clks 92 0>; 1065 assigned-clock-parents = <&k3_clks 92 1>; 1066 ti,otap-del-sel-legacy = <0x0>; 1067 ti,otap-del-sel-sd-hs = <0xf>; 1068 ti,otap-del-sel-sdr12 = <0xf>; 1069 ti,otap-del-sel-sdr25 = <0xf>; 1070 ti,otap-del-sel-sdr50 = <0xc>; 1071 ti,otap-del-sel-ddr50 = <0xc>; 1072 ti,itap-del-sel-legacy = <0x0>; 1073 ti,itap-del-sel-sd-hs = <0x0>; 1074 ti,itap-del-sel-sdr12 = <0x0>; 1075 ti,itap-del-sel-sdr25 = <0x0>; 1076 ti,itap-del-sel-ddr50 = <0x2>; 1077 ti,trm-icp = <0x8>; 1078 ti,clkbuf-sel = <0x7>; 1079 dma-coherent; 1080 sdhci-caps-mask = <0x2 0x0>; 1081 }; 1082 1083 main_sdhci2: mmc@4f98000 { 1084 compatible = "ti,j721e-sdhci-4bit"; 1085 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1086 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1087 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1088 clock-names = "clk_ahb", "clk_xin"; 1089 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; 1090 assigned-clocks = <&k3_clks 93 0>; 1091 assigned-clock-parents = <&k3_clks 93 1>; 1092 ti,otap-del-sel-legacy = <0x0>; 1093 ti,otap-del-sel-sd-hs = <0xf>; 1094 ti,otap-del-sel-sdr12 = <0xf>; 1095 ti,otap-del-sel-sdr25 = <0xf>; 1096 ti,otap-del-sel-sdr50 = <0xc>; 1097 ti,otap-del-sel-ddr50 = <0xc>; 1098 ti,itap-del-sel-legacy = <0x0>; 1099 ti,itap-del-sel-sd-hs = <0x0>; 1100 ti,itap-del-sel-sdr12 = <0x0>; 1101 ti,itap-del-sel-sdr25 = <0x0>; 1102 ti,itap-del-sel-ddr50 = <0x2>; 1103 ti,trm-icp = <0x8>; 1104 ti,clkbuf-sel = <0x7>; 1105 dma-coherent; 1106 sdhci-caps-mask = <0x2 0x0>; 1107 }; 1108 1109 usbss0: cdns-usb@4104000 { 1110 compatible = "ti,j721e-usb"; 1111 reg = <0x00 0x4104000 0x00 0x100>; 1112 dma-coherent; 1113 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1114 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1115 clock-names = "ref", "lpm"; 1116 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1117 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1118 #address-cells = <2>; 1119 #size-cells = <2>; 1120 ranges; 1121 1122 usb0: usb@6000000 { 1123 compatible = "cdns,usb3"; 1124 reg = <0x00 0x6000000 0x00 0x10000>, 1125 <0x00 0x6010000 0x00 0x10000>, 1126 <0x00 0x6020000 0x00 0x10000>; 1127 reg-names = "otg", "xhci", "dev"; 1128 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1129 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1130 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1131 interrupt-names = "host", 1132 "peripheral", 1133 "otg"; 1134 maximum-speed = "super-speed"; 1135 dr_mode = "otg"; 1136 }; 1137 }; 1138 1139 usbss1: cdns-usb@4114000 { 1140 compatible = "ti,j721e-usb"; 1141 reg = <0x00 0x4114000 0x00 0x100>; 1142 dma-coherent; 1143 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1144 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1145 clock-names = "ref", "lpm"; 1146 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1147 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1148 #address-cells = <2>; 1149 #size-cells = <2>; 1150 ranges; 1151 1152 usb1: usb@6400000 { 1153 compatible = "cdns,usb3"; 1154 reg = <0x00 0x6400000 0x00 0x10000>, 1155 <0x00 0x6410000 0x00 0x10000>, 1156 <0x00 0x6420000 0x00 0x10000>; 1157 reg-names = "otg", "xhci", "dev"; 1158 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1159 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1160 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1161 interrupt-names = "host", 1162 "peripheral", 1163 "otg"; 1164 maximum-speed = "super-speed"; 1165 dr_mode = "otg"; 1166 }; 1167 }; 1168 1169 main_i2c0: i2c@2000000 { 1170 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1171 reg = <0x0 0x2000000 0x0 0x100>; 1172 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 clock-names = "fck"; 1176 clocks = <&k3_clks 187 0>; 1177 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1178 }; 1179 1180 main_i2c1: i2c@2010000 { 1181 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1182 reg = <0x0 0x2010000 0x0 0x100>; 1183 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 clock-names = "fck"; 1187 clocks = <&k3_clks 188 0>; 1188 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1189 }; 1190 1191 main_i2c2: i2c@2020000 { 1192 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1193 reg = <0x0 0x2020000 0x0 0x100>; 1194 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 clock-names = "fck"; 1198 clocks = <&k3_clks 189 0>; 1199 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1200 }; 1201 1202 main_i2c3: i2c@2030000 { 1203 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1204 reg = <0x0 0x2030000 0x0 0x100>; 1205 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 clock-names = "fck"; 1209 clocks = <&k3_clks 190 0>; 1210 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1211 }; 1212 1213 main_i2c4: i2c@2040000 { 1214 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1215 reg = <0x0 0x2040000 0x0 0x100>; 1216 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 clock-names = "fck"; 1220 clocks = <&k3_clks 191 0>; 1221 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1222 }; 1223 1224 main_i2c5: i2c@2050000 { 1225 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1226 reg = <0x0 0x2050000 0x0 0x100>; 1227 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 clock-names = "fck"; 1231 clocks = <&k3_clks 192 0>; 1232 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1233 }; 1234 1235 main_i2c6: i2c@2060000 { 1236 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1237 reg = <0x0 0x2060000 0x0 0x100>; 1238 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1239 #address-cells = <1>; 1240 #size-cells = <0>; 1241 clock-names = "fck"; 1242 clocks = <&k3_clks 193 0>; 1243 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1244 }; 1245 1246 ufs_wrapper: ufs-wrapper@4e80000 { 1247 compatible = "ti,j721e-ufs"; 1248 reg = <0x0 0x4e80000 0x0 0x100>; 1249 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1250 clocks = <&k3_clks 277 1>; 1251 assigned-clocks = <&k3_clks 277 1>; 1252 assigned-clock-parents = <&k3_clks 277 4>; 1253 ranges; 1254 #address-cells = <2>; 1255 #size-cells = <2>; 1256 1257 ufs@4e84000 { 1258 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1259 reg = <0x0 0x4e84000 0x0 0x10000>; 1260 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1261 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1262 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1263 clock-names = "core_clk", "phy_clk", "ref_clk"; 1264 dma-coherent; 1265 }; 1266 }; 1267 1268 dss: dss@4a00000 { 1269 compatible = "ti,j721e-dss"; 1270 reg = 1271 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1272 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1273 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1274 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1275 1276 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1277 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1278 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1279 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1280 1281 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1282 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1283 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1284 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1285 1286 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1287 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1288 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1289 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1290 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1291 1292 reg-names = "common_m", "common_s0", 1293 "common_s1", "common_s2", 1294 "vidl1", "vidl2","vid1","vid2", 1295 "ovr1", "ovr2", "ovr3", "ovr4", 1296 "vp1", "vp2", "vp3", "vp4", 1297 "wb"; 1298 1299 clocks = <&k3_clks 152 0>, 1300 <&k3_clks 152 1>, 1301 <&k3_clks 152 4>, 1302 <&k3_clks 152 9>, 1303 <&k3_clks 152 13>; 1304 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1305 1306 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1307 1308 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1311 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1312 interrupt-names = "common_m", 1313 "common_s0", 1314 "common_s1", 1315 "common_s2"; 1316 1317 dss_ports: ports { 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 }; 1321 }; 1322 1323 mcasp0: mcasp@2b00000 { 1324 compatible = "ti,am33xx-mcasp-audio"; 1325 reg = <0x0 0x02b00000 0x0 0x2000>, 1326 <0x0 0x02b08000 0x0 0x1000>; 1327 reg-names = "mpu","dat"; 1328 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1329 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1330 interrupt-names = "tx", "rx"; 1331 1332 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1333 dma-names = "tx", "rx"; 1334 1335 clocks = <&k3_clks 174 1>; 1336 clock-names = "fck"; 1337 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1338 }; 1339 1340 mcasp1: mcasp@2b10000 { 1341 compatible = "ti,am33xx-mcasp-audio"; 1342 reg = <0x0 0x02b10000 0x0 0x2000>, 1343 <0x0 0x02b18000 0x0 0x1000>; 1344 reg-names = "mpu","dat"; 1345 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1347 interrupt-names = "tx", "rx"; 1348 1349 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1350 dma-names = "tx", "rx"; 1351 1352 clocks = <&k3_clks 175 1>; 1353 clock-names = "fck"; 1354 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1355 }; 1356 1357 mcasp2: mcasp@2b20000 { 1358 compatible = "ti,am33xx-mcasp-audio"; 1359 reg = <0x0 0x02b20000 0x0 0x2000>, 1360 <0x0 0x02b28000 0x0 0x1000>; 1361 reg-names = "mpu","dat"; 1362 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1364 interrupt-names = "tx", "rx"; 1365 1366 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1367 dma-names = "tx", "rx"; 1368 1369 clocks = <&k3_clks 176 1>; 1370 clock-names = "fck"; 1371 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1372 }; 1373 1374 mcasp3: mcasp@2b30000 { 1375 compatible = "ti,am33xx-mcasp-audio"; 1376 reg = <0x0 0x02b30000 0x0 0x2000>, 1377 <0x0 0x02b38000 0x0 0x1000>; 1378 reg-names = "mpu","dat"; 1379 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1381 interrupt-names = "tx", "rx"; 1382 1383 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1384 dma-names = "tx", "rx"; 1385 1386 clocks = <&k3_clks 177 1>; 1387 clock-names = "fck"; 1388 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1389 }; 1390 1391 mcasp4: mcasp@2b40000 { 1392 compatible = "ti,am33xx-mcasp-audio"; 1393 reg = <0x0 0x02b40000 0x0 0x2000>, 1394 <0x0 0x02b48000 0x0 0x1000>; 1395 reg-names = "mpu","dat"; 1396 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1398 interrupt-names = "tx", "rx"; 1399 1400 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1401 dma-names = "tx", "rx"; 1402 1403 clocks = <&k3_clks 178 1>; 1404 clock-names = "fck"; 1405 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1406 }; 1407 1408 mcasp5: mcasp@2b50000 { 1409 compatible = "ti,am33xx-mcasp-audio"; 1410 reg = <0x0 0x02b50000 0x0 0x2000>, 1411 <0x0 0x02b58000 0x0 0x1000>; 1412 reg-names = "mpu","dat"; 1413 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1415 interrupt-names = "tx", "rx"; 1416 1417 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1418 dma-names = "tx", "rx"; 1419 1420 clocks = <&k3_clks 179 1>; 1421 clock-names = "fck"; 1422 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1423 }; 1424 1425 mcasp6: mcasp@2b60000 { 1426 compatible = "ti,am33xx-mcasp-audio"; 1427 reg = <0x0 0x02b60000 0x0 0x2000>, 1428 <0x0 0x02b68000 0x0 0x1000>; 1429 reg-names = "mpu","dat"; 1430 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1432 interrupt-names = "tx", "rx"; 1433 1434 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1435 dma-names = "tx", "rx"; 1436 1437 clocks = <&k3_clks 180 1>; 1438 clock-names = "fck"; 1439 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1440 }; 1441 1442 mcasp7: mcasp@2b70000 { 1443 compatible = "ti,am33xx-mcasp-audio"; 1444 reg = <0x0 0x02b70000 0x0 0x2000>, 1445 <0x0 0x02b78000 0x0 0x1000>; 1446 reg-names = "mpu","dat"; 1447 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1449 interrupt-names = "tx", "rx"; 1450 1451 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1452 dma-names = "tx", "rx"; 1453 1454 clocks = <&k3_clks 181 1>; 1455 clock-names = "fck"; 1456 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1457 }; 1458 1459 mcasp8: mcasp@2b80000 { 1460 compatible = "ti,am33xx-mcasp-audio"; 1461 reg = <0x0 0x02b80000 0x0 0x2000>, 1462 <0x0 0x02b88000 0x0 0x1000>; 1463 reg-names = "mpu","dat"; 1464 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1466 interrupt-names = "tx", "rx"; 1467 1468 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1469 dma-names = "tx", "rx"; 1470 1471 clocks = <&k3_clks 182 1>; 1472 clock-names = "fck"; 1473 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1474 }; 1475 1476 mcasp9: mcasp@2b90000 { 1477 compatible = "ti,am33xx-mcasp-audio"; 1478 reg = <0x0 0x02b90000 0x0 0x2000>, 1479 <0x0 0x02b98000 0x0 0x1000>; 1480 reg-names = "mpu","dat"; 1481 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1483 interrupt-names = "tx", "rx"; 1484 1485 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1486 dma-names = "tx", "rx"; 1487 1488 clocks = <&k3_clks 183 1>; 1489 clock-names = "fck"; 1490 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1491 }; 1492 1493 mcasp10: mcasp@2ba0000 { 1494 compatible = "ti,am33xx-mcasp-audio"; 1495 reg = <0x0 0x02ba0000 0x0 0x2000>, 1496 <0x0 0x02ba8000 0x0 0x1000>; 1497 reg-names = "mpu","dat"; 1498 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1500 interrupt-names = "tx", "rx"; 1501 1502 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1503 dma-names = "tx", "rx"; 1504 1505 clocks = <&k3_clks 184 1>; 1506 clock-names = "fck"; 1507 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1508 }; 1509 1510 mcasp11: mcasp@2bb0000 { 1511 compatible = "ti,am33xx-mcasp-audio"; 1512 reg = <0x0 0x02bb0000 0x0 0x2000>, 1513 <0x0 0x02bb8000 0x0 0x1000>; 1514 reg-names = "mpu","dat"; 1515 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1517 interrupt-names = "tx", "rx"; 1518 1519 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1520 dma-names = "tx", "rx"; 1521 1522 clocks = <&k3_clks 185 1>; 1523 clock-names = "fck"; 1524 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1525 }; 1526 1527 watchdog0: watchdog@2200000 { 1528 compatible = "ti,j7-rti-wdt"; 1529 reg = <0x0 0x2200000 0x0 0x100>; 1530 clocks = <&k3_clks 252 1>; 1531 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1532 assigned-clocks = <&k3_clks 252 1>; 1533 assigned-clock-parents = <&k3_clks 252 5>; 1534 }; 1535 1536 watchdog1: watchdog@2210000 { 1537 compatible = "ti,j7-rti-wdt"; 1538 reg = <0x0 0x2210000 0x0 0x100>; 1539 clocks = <&k3_clks 253 1>; 1540 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1541 assigned-clocks = <&k3_clks 253 1>; 1542 assigned-clock-parents = <&k3_clks 253 5>; 1543 }; 1544 1545 main_r5fss0: r5fss@5c00000 { 1546 compatible = "ti,j721e-r5fss"; 1547 ti,cluster-mode = <1>; 1548 #address-cells = <1>; 1549 #size-cells = <1>; 1550 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1551 <0x5d00000 0x00 0x5d00000 0x20000>; 1552 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 1553 1554 main_r5fss0_core0: r5f@5c00000 { 1555 compatible = "ti,j721e-r5f"; 1556 reg = <0x5c00000 0x00008000>, 1557 <0x5c10000 0x00008000>; 1558 reg-names = "atcm", "btcm"; 1559 ti,sci = <&dmsc>; 1560 ti,sci-dev-id = <245>; 1561 ti,sci-proc-ids = <0x06 0xff>; 1562 resets = <&k3_reset 245 1>; 1563 firmware-name = "j7-main-r5f0_0-fw"; 1564 ti,atcm-enable = <1>; 1565 ti,btcm-enable = <1>; 1566 ti,loczrama = <1>; 1567 }; 1568 1569 main_r5fss0_core1: r5f@5d00000 { 1570 compatible = "ti,j721e-r5f"; 1571 reg = <0x5d00000 0x00008000>, 1572 <0x5d10000 0x00008000>; 1573 reg-names = "atcm", "btcm"; 1574 ti,sci = <&dmsc>; 1575 ti,sci-dev-id = <246>; 1576 ti,sci-proc-ids = <0x07 0xff>; 1577 resets = <&k3_reset 246 1>; 1578 firmware-name = "j7-main-r5f0_1-fw"; 1579 ti,atcm-enable = <1>; 1580 ti,btcm-enable = <1>; 1581 ti,loczrama = <1>; 1582 }; 1583 }; 1584 1585 main_r5fss1: r5fss@5e00000 { 1586 compatible = "ti,j721e-r5fss"; 1587 ti,cluster-mode = <1>; 1588 #address-cells = <1>; 1589 #size-cells = <1>; 1590 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 1591 <0x5f00000 0x00 0x5f00000 0x20000>; 1592 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; 1593 1594 main_r5fss1_core0: r5f@5e00000 { 1595 compatible = "ti,j721e-r5f"; 1596 reg = <0x5e00000 0x00008000>, 1597 <0x5e10000 0x00008000>; 1598 reg-names = "atcm", "btcm"; 1599 ti,sci = <&dmsc>; 1600 ti,sci-dev-id = <247>; 1601 ti,sci-proc-ids = <0x08 0xff>; 1602 resets = <&k3_reset 247 1>; 1603 firmware-name = "j7-main-r5f1_0-fw"; 1604 ti,atcm-enable = <1>; 1605 ti,btcm-enable = <1>; 1606 ti,loczrama = <1>; 1607 }; 1608 1609 main_r5fss1_core1: r5f@5f00000 { 1610 compatible = "ti,j721e-r5f"; 1611 reg = <0x5f00000 0x00008000>, 1612 <0x5f10000 0x00008000>; 1613 reg-names = "atcm", "btcm"; 1614 ti,sci = <&dmsc>; 1615 ti,sci-dev-id = <248>; 1616 ti,sci-proc-ids = <0x09 0xff>; 1617 resets = <&k3_reset 248 1>; 1618 firmware-name = "j7-main-r5f1_1-fw"; 1619 ti,atcm-enable = <1>; 1620 ti,btcm-enable = <1>; 1621 ti,loczrama = <1>; 1622 }; 1623 }; 1624 1625 c66_0: dsp@4d80800000 { 1626 compatible = "ti,j721e-c66-dsp"; 1627 reg = <0x4d 0x80800000 0x00 0x00048000>, 1628 <0x4d 0x80e00000 0x00 0x00008000>, 1629 <0x4d 0x80f00000 0x00 0x00008000>; 1630 reg-names = "l2sram", "l1pram", "l1dram"; 1631 ti,sci = <&dmsc>; 1632 ti,sci-dev-id = <142>; 1633 ti,sci-proc-ids = <0x03 0xff>; 1634 resets = <&k3_reset 142 1>; 1635 firmware-name = "j7-c66_0-fw"; 1636 }; 1637 1638 c66_1: dsp@4d81800000 { 1639 compatible = "ti,j721e-c66-dsp"; 1640 reg = <0x4d 0x81800000 0x00 0x00048000>, 1641 <0x4d 0x81e00000 0x00 0x00008000>, 1642 <0x4d 0x81f00000 0x00 0x00008000>; 1643 reg-names = "l2sram", "l1pram", "l1dram"; 1644 ti,sci = <&dmsc>; 1645 ti,sci-dev-id = <143>; 1646 ti,sci-proc-ids = <0x04 0xff>; 1647 resets = <&k3_reset 143 1>; 1648 firmware-name = "j7-c66_1-fw"; 1649 }; 1650 1651 c71_0: dsp@64800000 { 1652 compatible = "ti,j721e-c71-dsp"; 1653 reg = <0x00 0x64800000 0x00 0x00080000>, 1654 <0x00 0x64e00000 0x00 0x0000c000>; 1655 reg-names = "l2sram", "l1dram"; 1656 ti,sci = <&dmsc>; 1657 ti,sci-dev-id = <15>; 1658 ti,sci-proc-ids = <0x30 0xff>; 1659 resets = <&k3_reset 15 1>; 1660 firmware-name = "j7-c71_0-fw"; 1661 }; 1662 1663 icssg0: icssg@b000000 { 1664 compatible = "ti,j721e-icssg"; 1665 reg = <0x00 0xb000000 0x00 0x80000>; 1666 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 1667 #address-cells = <1>; 1668 #size-cells = <1>; 1669 ranges = <0x0 0x00 0x0b000000 0x100000>; 1670 1671 icssg0_mem: memories@0 { 1672 reg = <0x0 0x2000>, 1673 <0x2000 0x2000>, 1674 <0x10000 0x10000>; 1675 reg-names = "dram0", "dram1", 1676 "shrdram2"; 1677 }; 1678 1679 icssg0_cfg: cfg@26000 { 1680 compatible = "ti,pruss-cfg", "syscon"; 1681 reg = <0x26000 0x200>; 1682 #address-cells = <1>; 1683 #size-cells = <1>; 1684 ranges = <0x0 0x26000 0x2000>; 1685 1686 clocks { 1687 #address-cells = <1>; 1688 #size-cells = <0>; 1689 1690 icssg0_coreclk_mux: coreclk-mux@3c { 1691 reg = <0x3c>; 1692 #clock-cells = <0>; 1693 clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ 1694 <&k3_clks 119 1>; /* icssg0_iclk */ 1695 assigned-clocks = <&icssg0_coreclk_mux>; 1696 assigned-clock-parents = <&k3_clks 119 1>; 1697 }; 1698 1699 icssg0_iepclk_mux: iepclk-mux@30 { 1700 reg = <0x30>; 1701 #clock-cells = <0>; 1702 clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ 1703 <&icssg0_coreclk_mux>; /* core_clk */ 1704 assigned-clocks = <&icssg0_iepclk_mux>; 1705 assigned-clock-parents = <&icssg0_coreclk_mux>; 1706 }; 1707 }; 1708 }; 1709 1710 icssg0_mii_rt: mii-rt@32000 { 1711 compatible = "ti,pruss-mii", "syscon"; 1712 reg = <0x32000 0x100>; 1713 }; 1714 1715 icssg0_mii_g_rt: mii-g-rt@33000 { 1716 compatible = "ti,pruss-mii-g", "syscon"; 1717 reg = <0x33000 0x1000>; 1718 }; 1719 1720 icssg0_intc: interrupt-controller@20000 { 1721 compatible = "ti,icssg-intc"; 1722 reg = <0x20000 0x2000>; 1723 interrupt-controller; 1724 #interrupt-cells = <3>; 1725 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1733 interrupt-names = "host_intr0", "host_intr1", 1734 "host_intr2", "host_intr3", 1735 "host_intr4", "host_intr5", 1736 "host_intr6", "host_intr7"; 1737 }; 1738 1739 pru0_0: pru@34000 { 1740 compatible = "ti,j721e-pru"; 1741 reg = <0x34000 0x3000>, 1742 <0x22000 0x100>, 1743 <0x22400 0x100>; 1744 reg-names = "iram", "control", "debug"; 1745 firmware-name = "j7-pru0_0-fw"; 1746 }; 1747 1748 rtu0_0: rtu@4000 { 1749 compatible = "ti,j721e-rtu"; 1750 reg = <0x4000 0x2000>, 1751 <0x23000 0x100>, 1752 <0x23400 0x100>; 1753 reg-names = "iram", "control", "debug"; 1754 firmware-name = "j7-rtu0_0-fw"; 1755 }; 1756 1757 tx_pru0_0: txpru@a000 { 1758 compatible = "ti,j721e-tx-pru"; 1759 reg = <0xa000 0x1800>, 1760 <0x25000 0x100>, 1761 <0x25400 0x100>; 1762 reg-names = "iram", "control", "debug"; 1763 firmware-name = "j7-txpru0_0-fw"; 1764 }; 1765 1766 pru0_1: pru@38000 { 1767 compatible = "ti,j721e-pru"; 1768 reg = <0x38000 0x3000>, 1769 <0x24000 0x100>, 1770 <0x24400 0x100>; 1771 reg-names = "iram", "control", "debug"; 1772 firmware-name = "j7-pru0_1-fw"; 1773 }; 1774 1775 rtu0_1: rtu@6000 { 1776 compatible = "ti,j721e-rtu"; 1777 reg = <0x6000 0x2000>, 1778 <0x23800 0x100>, 1779 <0x23c00 0x100>; 1780 reg-names = "iram", "control", "debug"; 1781 firmware-name = "j7-rtu0_1-fw"; 1782 }; 1783 1784 tx_pru0_1: txpru@c000 { 1785 compatible = "ti,j721e-tx-pru"; 1786 reg = <0xc000 0x1800>, 1787 <0x25800 0x100>, 1788 <0x25c00 0x100>; 1789 reg-names = "iram", "control", "debug"; 1790 firmware-name = "j7-txpru0_1-fw"; 1791 }; 1792 1793 icssg0_mdio: mdio@32400 { 1794 compatible = "ti,davinci_mdio"; 1795 reg = <0x32400 0x100>; 1796 clocks = <&k3_clks 119 1>; 1797 clock-names = "fck"; 1798 #address-cells = <1>; 1799 #size-cells = <0>; 1800 bus_freq = <1000000>; 1801 }; 1802 }; 1803 1804 icssg1: icssg@b100000 { 1805 compatible = "ti,j721e-icssg"; 1806 reg = <0x00 0xb100000 0x00 0x80000>; 1807 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 1808 #address-cells = <1>; 1809 #size-cells = <1>; 1810 ranges = <0x0 0x00 0x0b100000 0x100000>; 1811 1812 icssg1_mem: memories@b100000 { 1813 reg = <0x0 0x2000>, 1814 <0x2000 0x2000>, 1815 <0x10000 0x10000>; 1816 reg-names = "dram0", "dram1", 1817 "shrdram2"; 1818 }; 1819 1820 icssg1_cfg: cfg@26000 { 1821 compatible = "ti,pruss-cfg", "syscon"; 1822 reg = <0x26000 0x200>; 1823 #address-cells = <1>; 1824 #size-cells = <1>; 1825 ranges = <0x0 0x26000 0x2000>; 1826 1827 clocks { 1828 #address-cells = <1>; 1829 #size-cells = <0>; 1830 1831 icssg1_coreclk_mux: coreclk-mux@3c { 1832 reg = <0x3c>; 1833 #clock-cells = <0>; 1834 clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ 1835 <&k3_clks 120 4>; /* icssg1_iclk */ 1836 assigned-clocks = <&icssg1_coreclk_mux>; 1837 assigned-clock-parents = <&k3_clks 120 4>; 1838 }; 1839 1840 icssg1_iepclk_mux: iepclk-mux@30 { 1841 reg = <0x30>; 1842 #clock-cells = <0>; 1843 clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ 1844 <&icssg1_coreclk_mux>; /* core_clk */ 1845 assigned-clocks = <&icssg1_iepclk_mux>; 1846 assigned-clock-parents = <&icssg1_coreclk_mux>; 1847 }; 1848 }; 1849 }; 1850 1851 icssg1_mii_rt: mii-rt@32000 { 1852 compatible = "ti,pruss-mii", "syscon"; 1853 reg = <0x32000 0x100>; 1854 }; 1855 1856 icssg1_mii_g_rt: mii-g-rt@33000 { 1857 compatible = "ti,pruss-mii-g", "syscon"; 1858 reg = <0x33000 0x1000>; 1859 }; 1860 1861 icssg1_intc: interrupt-controller@20000 { 1862 compatible = "ti,icssg-intc"; 1863 reg = <0x20000 0x2000>; 1864 interrupt-controller; 1865 #interrupt-cells = <3>; 1866 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1874 interrupt-names = "host_intr0", "host_intr1", 1875 "host_intr2", "host_intr3", 1876 "host_intr4", "host_intr5", 1877 "host_intr6", "host_intr7"; 1878 }; 1879 1880 pru1_0: pru@34000 { 1881 compatible = "ti,j721e-pru"; 1882 reg = <0x34000 0x4000>, 1883 <0x22000 0x100>, 1884 <0x22400 0x100>; 1885 reg-names = "iram", "control", "debug"; 1886 firmware-name = "j7-pru1_0-fw"; 1887 }; 1888 1889 rtu1_0: rtu@4000 { 1890 compatible = "ti,j721e-rtu"; 1891 reg = <0x4000 0x2000>, 1892 <0x23000 0x100>, 1893 <0x23400 0x100>; 1894 reg-names = "iram", "control", "debug"; 1895 firmware-name = "j7-rtu1_0-fw"; 1896 }; 1897 1898 tx_pru1_0: txpru@a000 { 1899 compatible = "ti,j721e-tx-pru"; 1900 reg = <0xa000 0x1800>, 1901 <0x25000 0x100>, 1902 <0x25400 0x100>; 1903 reg-names = "iram", "control", "debug"; 1904 firmware-name = "j7-txpru1_0-fw"; 1905 }; 1906 1907 pru1_1: pru@38000 { 1908 compatible = "ti,j721e-pru"; 1909 reg = <0x38000 0x4000>, 1910 <0x24000 0x100>, 1911 <0x24400 0x100>; 1912 reg-names = "iram", "control", "debug"; 1913 firmware-name = "j7-pru1_1-fw"; 1914 }; 1915 1916 rtu1_1: rtu@6000 { 1917 compatible = "ti,j721e-rtu"; 1918 reg = <0x6000 0x2000>, 1919 <0x23800 0x100>, 1920 <0x23c00 0x100>; 1921 reg-names = "iram", "control", "debug"; 1922 firmware-name = "j7-rtu1_1-fw"; 1923 }; 1924 1925 tx_pru1_1: txpru@c000 { 1926 compatible = "ti,j721e-tx-pru"; 1927 reg = <0xc000 0x1800>, 1928 <0x25800 0x100>, 1929 <0x25c00 0x100>; 1930 reg-names = "iram", "control", "debug"; 1931 firmware-name = "j7-txpru1_1-fw"; 1932 }; 1933 1934 icssg1_mdio: mdio@32400 { 1935 compatible = "ti,davinci_mdio"; 1936 reg = <0x32400 0x100>; 1937 clocks = <&k3_clks 120 4>; 1938 clock-names = "fck"; 1939 #address-cells = <1>; 1940 #size-cells = <0>; 1941 bus_freq = <1000000>; 1942 }; 1943 }; 1944}; 1945