1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/clocksource.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/mutex.h>
19 #include <linux/of_device.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/time.h>
23 #include <linux/string.h>
24 #include <linux/pm_runtime.h>
25
26 #include <sound/core.h>
27 #include <sound/initval.h>
28
29 #include <sound/hda_codec.h>
30 #include "hda_controller.h"
31
32 /* Defines for Nvidia Tegra HDA support */
33 #define HDA_BAR0 0x8000
34
35 #define HDA_CFG_CMD 0x1004
36 #define HDA_CFG_BAR0 0x1010
37
38 #define HDA_ENABLE_IO_SPACE (1 << 0)
39 #define HDA_ENABLE_MEM_SPACE (1 << 1)
40 #define HDA_ENABLE_BUS_MASTER (1 << 2)
41 #define HDA_ENABLE_SERR (1 << 8)
42 #define HDA_DISABLE_INTR (1 << 10)
43 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
44 #define HDA_BAR0_FINAL_PROGRAM (1 << 14)
45
46 /* IPFS */
47 #define HDA_IPFS_CONFIG 0x180
48 #define HDA_IPFS_EN_FPCI 0x1
49
50 #define HDA_IPFS_FPCI_BAR0 0x80
51 #define HDA_FPCI_BAR0_START 0x40
52
53 #define HDA_IPFS_INTR_MASK 0x188
54 #define HDA_IPFS_EN_INTR (1 << 16)
55
56 /* FPCI */
57 #define FPCI_DBG_CFG_2 0x10F4
58 #define FPCI_GCAP_NSDO_SHIFT 18
59 #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT)
60
61 /* max number of SDs */
62 #define NUM_CAPTURE_SD 1
63 #define NUM_PLAYBACK_SD 1
64
65 /*
66 * Tegra194 does not reflect correct number of SDO lines. Below macro
67 * is used to update the GCAP register to workaround the issue.
68 */
69 #define TEGRA194_NUM_SDO_LINES 4
70
71 struct hda_tegra_soc {
72 bool has_hda2codec_2x_reset;
73 };
74
75 struct hda_tegra {
76 struct azx chip;
77 struct device *dev;
78 struct reset_control_bulk_data resets[3];
79 struct clk_bulk_data clocks[3];
80 unsigned int nresets;
81 unsigned int nclocks;
82 void __iomem *regs;
83 struct work_struct probe_work;
84 const struct hda_tegra_soc *soc;
85 };
86
87 #ifdef CONFIG_PM
88 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
89 module_param(power_save, bint, 0644);
90 MODULE_PARM_DESC(power_save,
91 "Automatic power-saving timeout (in seconds, 0 = disable).");
92 #else
93 #define power_save 0
94 #endif
95
96 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
97
hda_tegra_init(struct hda_tegra * hda)98 static void hda_tegra_init(struct hda_tegra *hda)
99 {
100 u32 v;
101
102 /* Enable PCI access */
103 v = readl(hda->regs + HDA_IPFS_CONFIG);
104 v |= HDA_IPFS_EN_FPCI;
105 writel(v, hda->regs + HDA_IPFS_CONFIG);
106
107 /* Enable MEM/IO space and bus master */
108 v = readl(hda->regs + HDA_CFG_CMD);
109 v &= ~HDA_DISABLE_INTR;
110 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
111 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
112 writel(v, hda->regs + HDA_CFG_CMD);
113
114 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
115 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
116 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
117
118 v = readl(hda->regs + HDA_IPFS_INTR_MASK);
119 v |= HDA_IPFS_EN_INTR;
120 writel(v, hda->regs + HDA_IPFS_INTR_MASK);
121 }
122
123 /*
124 * power management
125 */
hda_tegra_suspend(struct device * dev)126 static int __maybe_unused hda_tegra_suspend(struct device *dev)
127 {
128 struct snd_card *card = dev_get_drvdata(dev);
129 int rc;
130
131 rc = pm_runtime_force_suspend(dev);
132 if (rc < 0)
133 return rc;
134 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
135
136 return 0;
137 }
138
hda_tegra_resume(struct device * dev)139 static int __maybe_unused hda_tegra_resume(struct device *dev)
140 {
141 struct snd_card *card = dev_get_drvdata(dev);
142 int rc;
143
144 rc = pm_runtime_force_resume(dev);
145 if (rc < 0)
146 return rc;
147 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
148
149 return 0;
150 }
151
hda_tegra_runtime_suspend(struct device * dev)152 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev)
153 {
154 struct snd_card *card = dev_get_drvdata(dev);
155 struct azx *chip = card->private_data;
156 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
157
158 if (chip && chip->running) {
159 /* enable controller wake up event */
160 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
161 STATESTS_INT_MASK);
162
163 azx_stop_chip(chip);
164 azx_enter_link_reset(chip);
165 }
166 clk_bulk_disable_unprepare(hda->nclocks, hda->clocks);
167
168 return 0;
169 }
170
hda_tegra_runtime_resume(struct device * dev)171 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)
172 {
173 struct snd_card *card = dev_get_drvdata(dev);
174 struct azx *chip = card->private_data;
175 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
176 int rc;
177
178 if (!chip->running) {
179 rc = reset_control_bulk_assert(hda->nresets, hda->resets);
180 if (rc)
181 return rc;
182 }
183
184 rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks);
185 if (rc != 0)
186 return rc;
187 if (chip->running) {
188 hda_tegra_init(hda);
189 azx_init_chip(chip, 1);
190 /* disable controller wake up event*/
191 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
192 ~STATESTS_INT_MASK);
193 } else {
194 usleep_range(10, 100);
195
196 rc = reset_control_bulk_deassert(hda->nresets, hda->resets);
197 if (rc)
198 return rc;
199 }
200
201 return 0;
202 }
203
204 static const struct dev_pm_ops hda_tegra_pm = {
205 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
206 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
207 hda_tegra_runtime_resume,
208 NULL)
209 };
210
hda_tegra_dev_disconnect(struct snd_device * device)211 static int hda_tegra_dev_disconnect(struct snd_device *device)
212 {
213 struct azx *chip = device->device_data;
214
215 chip->bus.shutdown = 1;
216 return 0;
217 }
218
219 /*
220 * destructor
221 */
hda_tegra_dev_free(struct snd_device * device)222 static int hda_tegra_dev_free(struct snd_device *device)
223 {
224 struct azx *chip = device->device_data;
225 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
226
227 cancel_work_sync(&hda->probe_work);
228 if (azx_bus(chip)->chip_init) {
229 azx_stop_all_streams(chip);
230 azx_stop_chip(chip);
231 }
232
233 azx_free_stream_pages(chip);
234 azx_free_streams(chip);
235 snd_hdac_bus_exit(azx_bus(chip));
236
237 return 0;
238 }
239
hda_tegra_init_chip(struct azx * chip,struct platform_device * pdev)240 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
241 {
242 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
243 struct hdac_bus *bus = azx_bus(chip);
244 struct resource *res;
245
246 hda->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
247 if (IS_ERR(hda->regs))
248 return PTR_ERR(hda->regs);
249
250 bus->remap_addr = hda->regs + HDA_BAR0;
251 bus->addr = res->start + HDA_BAR0;
252
253 hda_tegra_init(hda);
254
255 return 0;
256 }
257
hda_tegra_first_init(struct azx * chip,struct platform_device * pdev)258 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
259 {
260 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
261 struct hdac_bus *bus = azx_bus(chip);
262 struct snd_card *card = chip->card;
263 int err;
264 unsigned short gcap;
265 int irq_id = platform_get_irq(pdev, 0);
266 const char *sname, *drv_name = "tegra-hda";
267 struct device_node *np = pdev->dev.of_node;
268
269 if (irq_id < 0)
270 return irq_id;
271
272 err = hda_tegra_init_chip(chip, pdev);
273 if (err)
274 return err;
275
276 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
277 IRQF_SHARED, KBUILD_MODNAME, chip);
278 if (err) {
279 dev_err(chip->card->dev,
280 "unable to request IRQ %d, disabling device\n",
281 irq_id);
282 return err;
283 }
284 bus->irq = irq_id;
285 bus->dma_stop_delay = 100;
286 card->sync_irq = bus->irq;
287
288 /*
289 * Tegra194 has 4 SDO lines and the STRIPE can be used to
290 * indicate how many of the SDO lines the stream should be
291 * striped. But GCAP register does not reflect the true
292 * capability of HW. Below workaround helps to fix this.
293 *
294 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2,
295 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines.
296 */
297 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) {
298 u32 val;
299
300 dev_info(card->dev, "Override SDO lines to %u\n",
301 TEGRA194_NUM_SDO_LINES);
302
303 val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK;
304 val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT;
305 writel(val, hda->regs + FPCI_DBG_CFG_2);
306 }
307
308 gcap = azx_readw(chip, GCAP);
309 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
310
311 chip->align_buffer_size = 1;
312
313 /* read number of streams from GCAP register instead of using
314 * hardcoded value
315 */
316 chip->capture_streams = (gcap >> 8) & 0x0f;
317 chip->playback_streams = (gcap >> 12) & 0x0f;
318 if (!chip->playback_streams && !chip->capture_streams) {
319 /* gcap didn't give any info, switching to old method */
320 chip->playback_streams = NUM_PLAYBACK_SD;
321 chip->capture_streams = NUM_CAPTURE_SD;
322 }
323 chip->capture_index_offset = 0;
324 chip->playback_index_offset = chip->capture_streams;
325 chip->num_streams = chip->playback_streams + chip->capture_streams;
326
327 /* initialize streams */
328 err = azx_init_streams(chip);
329 if (err < 0) {
330 dev_err(card->dev, "failed to initialize streams: %d\n", err);
331 return err;
332 }
333
334 err = azx_alloc_stream_pages(chip);
335 if (err < 0) {
336 dev_err(card->dev, "failed to allocate stream pages: %d\n",
337 err);
338 return err;
339 }
340
341 /* initialize chip */
342 azx_init_chip(chip, 1);
343
344 /*
345 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with
346 * 4 SDO lines due to legacy design limitation. Following
347 * is, from HD Audio Specification (Revision 1.0a), used to
348 * control striping of the stream across multiple SDO lines
349 * for sample rates <= 48K.
350 *
351 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
352 *
353 * Due to legacy design issue it is recommended that above
354 * ratio must be greater than 8. Since number of SDO lines is
355 * in powers of 2, next available ratio is 16 which can be
356 * used as a limiting factor here.
357 */
358 if (of_device_is_compatible(np, "nvidia,tegra30-hda"))
359 chip->bus.core.sdo_limit = 16;
360
361 /* codec detection */
362 if (!bus->codec_mask) {
363 dev_err(card->dev, "no codecs found!\n");
364 return -ENODEV;
365 }
366
367 /* driver name */
368 strncpy(card->driver, drv_name, sizeof(card->driver));
369 /* shortname for card */
370 sname = of_get_property(np, "nvidia,model", NULL);
371 if (!sname)
372 sname = drv_name;
373 if (strlen(sname) > sizeof(card->shortname))
374 dev_info(card->dev, "truncating shortname for card\n");
375 strncpy(card->shortname, sname, sizeof(card->shortname));
376
377 /* longname for card */
378 snprintf(card->longname, sizeof(card->longname),
379 "%s at 0x%lx irq %i",
380 card->shortname, bus->addr, bus->irq);
381
382 return 0;
383 }
384
385 /*
386 * constructor
387 */
388
389 static void hda_tegra_probe_work(struct work_struct *work);
390
hda_tegra_create(struct snd_card * card,unsigned int driver_caps,struct hda_tegra * hda)391 static int hda_tegra_create(struct snd_card *card,
392 unsigned int driver_caps,
393 struct hda_tegra *hda)
394 {
395 static const struct snd_device_ops ops = {
396 .dev_disconnect = hda_tegra_dev_disconnect,
397 .dev_free = hda_tegra_dev_free,
398 };
399 struct azx *chip;
400 int err;
401
402 chip = &hda->chip;
403
404 mutex_init(&chip->open_mutex);
405 chip->card = card;
406 chip->ops = &hda_tegra_ops;
407 chip->driver_caps = driver_caps;
408 chip->driver_type = driver_caps & 0xff;
409 chip->dev_index = 0;
410 INIT_LIST_HEAD(&chip->pcm_list);
411
412 chip->codec_probe_mask = -1;
413
414 chip->single_cmd = false;
415 chip->snoop = true;
416
417 INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
418
419 err = azx_bus_init(chip, NULL);
420 if (err < 0)
421 return err;
422
423 chip->bus.core.sync_write = 0;
424 chip->bus.core.needs_damn_long_delay = 1;
425 chip->bus.core.aligned_mmio = 1;
426
427 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
428 if (err < 0) {
429 dev_err(card->dev, "Error creating device\n");
430 return err;
431 }
432
433 return 0;
434 }
435
436 static const struct hda_tegra_soc tegra30_data = {
437 .has_hda2codec_2x_reset = true,
438 };
439
440 static const struct hda_tegra_soc tegra194_data = {
441 .has_hda2codec_2x_reset = false,
442 };
443
444 static const struct of_device_id hda_tegra_match[] = {
445 { .compatible = "nvidia,tegra30-hda", .data = &tegra30_data },
446 { .compatible = "nvidia,tegra194-hda", .data = &tegra194_data },
447 {},
448 };
449 MODULE_DEVICE_TABLE(of, hda_tegra_match);
450
hda_tegra_probe(struct platform_device * pdev)451 static int hda_tegra_probe(struct platform_device *pdev)
452 {
453 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
454 AZX_DCAPS_PM_RUNTIME |
455 AZX_DCAPS_4K_BDLE_BOUNDARY;
456 struct snd_card *card;
457 struct azx *chip;
458 struct hda_tegra *hda;
459 int err;
460
461 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
462 if (!hda)
463 return -ENOMEM;
464 hda->dev = &pdev->dev;
465 chip = &hda->chip;
466
467 hda->soc = of_device_get_match_data(&pdev->dev);
468
469 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
470 THIS_MODULE, 0, &card);
471 if (err < 0) {
472 dev_err(&pdev->dev, "Error creating card!\n");
473 return err;
474 }
475
476 hda->resets[hda->nresets++].id = "hda";
477 hda->resets[hda->nresets++].id = "hda2hdmi";
478 /*
479 * "hda2codec_2x" reset is not present on Tegra194. Though DT would
480 * be updated to reflect this, but to have backward compatibility
481 * below is necessary.
482 */
483 if (hda->soc->has_hda2codec_2x_reset)
484 hda->resets[hda->nresets++].id = "hda2codec_2x";
485
486 err = devm_reset_control_bulk_get_exclusive(&pdev->dev, hda->nresets,
487 hda->resets);
488 if (err)
489 goto out_free;
490
491 hda->clocks[hda->nclocks++].id = "hda";
492 hda->clocks[hda->nclocks++].id = "hda2hdmi";
493 hda->clocks[hda->nclocks++].id = "hda2codec_2x";
494
495 err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks);
496 if (err < 0)
497 goto out_free;
498
499 err = hda_tegra_create(card, driver_flags, hda);
500 if (err < 0)
501 goto out_free;
502 card->private_data = chip;
503
504 dev_set_drvdata(&pdev->dev, card);
505
506 pm_runtime_enable(hda->dev);
507 if (!azx_has_pm_runtime(chip))
508 pm_runtime_forbid(hda->dev);
509
510 schedule_work(&hda->probe_work);
511
512 return 0;
513
514 out_free:
515 snd_card_free(card);
516 return err;
517 }
518
hda_tegra_probe_work(struct work_struct * work)519 static void hda_tegra_probe_work(struct work_struct *work)
520 {
521 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
522 struct azx *chip = &hda->chip;
523 struct platform_device *pdev = to_platform_device(hda->dev);
524 int err;
525
526 pm_runtime_get_sync(hda->dev);
527 err = hda_tegra_first_init(chip, pdev);
528 if (err < 0)
529 goto out_free;
530
531 /* create codec instances */
532 err = azx_probe_codecs(chip, 8);
533 if (err < 0)
534 goto out_free;
535
536 err = azx_codec_configure(chip);
537 if (err < 0)
538 goto out_free;
539
540 err = snd_card_register(chip->card);
541 if (err < 0)
542 goto out_free;
543
544 chip->running = 1;
545 snd_hda_set_power_save(&chip->bus, power_save * 1000);
546
547 out_free:
548 pm_runtime_put(hda->dev);
549 return; /* no error return from async probe */
550 }
551
hda_tegra_remove(struct platform_device * pdev)552 static int hda_tegra_remove(struct platform_device *pdev)
553 {
554 int ret;
555
556 ret = snd_card_free(dev_get_drvdata(&pdev->dev));
557 pm_runtime_disable(&pdev->dev);
558
559 return ret;
560 }
561
hda_tegra_shutdown(struct platform_device * pdev)562 static void hda_tegra_shutdown(struct platform_device *pdev)
563 {
564 struct snd_card *card = dev_get_drvdata(&pdev->dev);
565 struct azx *chip;
566
567 if (!card)
568 return;
569 chip = card->private_data;
570 if (chip && chip->running)
571 azx_stop_chip(chip);
572 }
573
574 static struct platform_driver tegra_platform_hda = {
575 .driver = {
576 .name = "tegra-hda",
577 .pm = &hda_tegra_pm,
578 .of_match_table = hda_tegra_match,
579 },
580 .probe = hda_tegra_probe,
581 .remove = hda_tegra_remove,
582 .shutdown = hda_tegra_shutdown,
583 };
584 module_platform_driver(tegra_platform_hda);
585
586 MODULE_DESCRIPTION("Tegra HDA bus driver");
587 MODULE_LICENSE("GPL v2");
588