1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * HD audio interface patch for Creative CA0132 chip
4 *
5 * Copyright (c) 2011, Creative Technology Ltd.
6 *
7 * Based on patch_ca0110.c
8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
9 */
10
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/mutex.h>
15 #include <linux/module.h>
16 #include <linux/firmware.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/io.h>
20 #include <linux/pci.h>
21 #include <asm/io.h>
22 #include <sound/core.h>
23 #include <sound/hda_codec.h>
24 #include "hda_local.h"
25 #include "hda_auto_parser.h"
26 #include "hda_jack.h"
27
28 #include "ca0132_regs.h"
29
30 /* Enable this to see controls for tuning purpose. */
31 /*#define ENABLE_TUNING_CONTROLS*/
32
33 #ifdef ENABLE_TUNING_CONTROLS
34 #include <sound/tlv.h>
35 #endif
36
37 #define FLOAT_ZERO 0x00000000
38 #define FLOAT_ONE 0x3f800000
39 #define FLOAT_TWO 0x40000000
40 #define FLOAT_THREE 0x40400000
41 #define FLOAT_FIVE 0x40a00000
42 #define FLOAT_SIX 0x40c00000
43 #define FLOAT_EIGHT 0x41000000
44 #define FLOAT_MINUS_5 0xc0a00000
45
46 #define UNSOL_TAG_DSP 0x16
47
48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
50
51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
54
55 #define MASTERCONTROL 0x80
56 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
58
59 #define WIDGET_CHIP_CTRL 0x15
60 #define WIDGET_DSP_CTRL 0x16
61
62 #define MEM_CONNID_MICIN1 3
63 #define MEM_CONNID_MICIN2 5
64 #define MEM_CONNID_MICOUT1 12
65 #define MEM_CONNID_MICOUT2 14
66 #define MEM_CONNID_WUH 10
67 #define MEM_CONNID_DSP 16
68 #define MEM_CONNID_DMIC 100
69
70 #define SCP_SET 0
71 #define SCP_GET 1
72
73 #define EFX_FILE "ctefx.bin"
74 #define DESKTOP_EFX_FILE "ctefx-desktop.bin"
75 #define R3DI_EFX_FILE "ctefx-r3di.bin"
76
77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
78 MODULE_FIRMWARE(EFX_FILE);
79 MODULE_FIRMWARE(DESKTOP_EFX_FILE);
80 MODULE_FIRMWARE(R3DI_EFX_FILE);
81 #endif
82
83 static const char *const dirstr[2] = { "Playback", "Capture" };
84
85 #define NUM_OF_OUTPUTS 2
86 static const char *const out_type_str[2] = { "Speakers", "Headphone" };
87 enum {
88 SPEAKER_OUT,
89 HEADPHONE_OUT,
90 };
91
92 enum {
93 DIGITAL_MIC,
94 LINE_MIC_IN
95 };
96
97 /* Strings for Input Source Enum Control */
98 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" };
99 #define IN_SRC_NUM_OF_INPUTS 3
100 enum {
101 REAR_MIC,
102 REAR_LINE_IN,
103 FRONT_MIC,
104 };
105
106 enum {
107 #define VNODE_START_NID 0x80
108 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
109 VNID_MIC,
110 VNID_HP_SEL,
111 VNID_AMIC1_SEL,
112 VNID_HP_ASEL,
113 VNID_AMIC1_ASEL,
114 VNODE_END_NID,
115 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
116
117 #define EFFECT_START_NID 0x90
118 #define OUT_EFFECT_START_NID EFFECT_START_NID
119 SURROUND = OUT_EFFECT_START_NID,
120 CRYSTALIZER,
121 DIALOG_PLUS,
122 SMART_VOLUME,
123 X_BASS,
124 EQUALIZER,
125 OUT_EFFECT_END_NID,
126 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
127
128 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
129 ECHO_CANCELLATION = IN_EFFECT_START_NID,
130 VOICE_FOCUS,
131 MIC_SVM,
132 NOISE_REDUCTION,
133 IN_EFFECT_END_NID,
134 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
135
136 VOICEFX = IN_EFFECT_END_NID,
137 PLAY_ENHANCEMENT,
138 CRYSTAL_VOICE,
139 EFFECT_END_NID,
140 OUTPUT_SOURCE_ENUM,
141 INPUT_SOURCE_ENUM,
142 XBASS_XOVER,
143 EQ_PRESET_ENUM,
144 SMART_VOLUME_ENUM,
145 MIC_BOOST_ENUM,
146 AE5_HEADPHONE_GAIN_ENUM,
147 AE5_SOUND_FILTER_ENUM,
148 ZXR_HEADPHONE_GAIN,
149 SPEAKER_CHANNEL_CFG_ENUM,
150 SPEAKER_FULL_RANGE_FRONT,
151 SPEAKER_FULL_RANGE_REAR,
152 BASS_REDIRECTION,
153 BASS_REDIRECTION_XOVER,
154 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
155 };
156
157 /* Effects values size*/
158 #define EFFECT_VALS_MAX_COUNT 12
159
160 /*
161 * Default values for the effect slider controls, they are in order of their
162 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
163 * X-bass.
164 */
165 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
166 /* Amount of effect level sliders for ca0132_alt controls. */
167 #define EFFECT_LEVEL_SLIDERS 5
168
169 /* Latency introduced by DSP blocks in milliseconds. */
170 #define DSP_CAPTURE_INIT_LATENCY 0
171 #define DSP_CRYSTAL_VOICE_LATENCY 124
172 #define DSP_PLAYBACK_INIT_LATENCY 13
173 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
174 #define DSP_SPEAKER_OUT_LATENCY 7
175
176 struct ct_effect {
177 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
178 hda_nid_t nid;
179 int mid; /*effect module ID*/
180 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
181 int direct; /* 0:output; 1:input*/
182 int params; /* number of default non-on/off params */
183 /*effect default values, 1st is on/off. */
184 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
185 };
186
187 #define EFX_DIR_OUT 0
188 #define EFX_DIR_IN 1
189
190 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
191 { .name = "Surround",
192 .nid = SURROUND,
193 .mid = 0x96,
194 .reqs = {0, 1},
195 .direct = EFX_DIR_OUT,
196 .params = 1,
197 .def_vals = {0x3F800000, 0x3F2B851F}
198 },
199 { .name = "Crystalizer",
200 .nid = CRYSTALIZER,
201 .mid = 0x96,
202 .reqs = {7, 8},
203 .direct = EFX_DIR_OUT,
204 .params = 1,
205 .def_vals = {0x3F800000, 0x3F266666}
206 },
207 { .name = "Dialog Plus",
208 .nid = DIALOG_PLUS,
209 .mid = 0x96,
210 .reqs = {2, 3},
211 .direct = EFX_DIR_OUT,
212 .params = 1,
213 .def_vals = {0x00000000, 0x3F000000}
214 },
215 { .name = "Smart Volume",
216 .nid = SMART_VOLUME,
217 .mid = 0x96,
218 .reqs = {4, 5, 6},
219 .direct = EFX_DIR_OUT,
220 .params = 2,
221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
222 },
223 { .name = "X-Bass",
224 .nid = X_BASS,
225 .mid = 0x96,
226 .reqs = {24, 23, 25},
227 .direct = EFX_DIR_OUT,
228 .params = 2,
229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
230 },
231 { .name = "Equalizer",
232 .nid = EQUALIZER,
233 .mid = 0x96,
234 .reqs = {9, 10, 11, 12, 13, 14,
235 15, 16, 17, 18, 19, 20},
236 .direct = EFX_DIR_OUT,
237 .params = 11,
238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
239 0x00000000, 0x00000000, 0x00000000, 0x00000000,
240 0x00000000, 0x00000000, 0x00000000, 0x00000000}
241 },
242 { .name = "Echo Cancellation",
243 .nid = ECHO_CANCELLATION,
244 .mid = 0x95,
245 .reqs = {0, 1, 2, 3},
246 .direct = EFX_DIR_IN,
247 .params = 3,
248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
249 },
250 { .name = "Voice Focus",
251 .nid = VOICE_FOCUS,
252 .mid = 0x95,
253 .reqs = {6, 7, 8, 9},
254 .direct = EFX_DIR_IN,
255 .params = 3,
256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
257 },
258 { .name = "Mic SVM",
259 .nid = MIC_SVM,
260 .mid = 0x95,
261 .reqs = {44, 45},
262 .direct = EFX_DIR_IN,
263 .params = 1,
264 .def_vals = {0x00000000, 0x3F3D70A4}
265 },
266 { .name = "Noise Reduction",
267 .nid = NOISE_REDUCTION,
268 .mid = 0x95,
269 .reqs = {4, 5},
270 .direct = EFX_DIR_IN,
271 .params = 1,
272 .def_vals = {0x3F800000, 0x3F000000}
273 },
274 { .name = "VoiceFX",
275 .nid = VOICEFX,
276 .mid = 0x95,
277 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
278 .direct = EFX_DIR_IN,
279 .params = 8,
280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
282 0x00000000}
283 }
284 };
285
286 /* Tuning controls */
287 #ifdef ENABLE_TUNING_CONTROLS
288
289 enum {
290 #define TUNING_CTL_START_NID 0xC0
291 WEDGE_ANGLE = TUNING_CTL_START_NID,
292 SVM_LEVEL,
293 EQUALIZER_BAND_0,
294 EQUALIZER_BAND_1,
295 EQUALIZER_BAND_2,
296 EQUALIZER_BAND_3,
297 EQUALIZER_BAND_4,
298 EQUALIZER_BAND_5,
299 EQUALIZER_BAND_6,
300 EQUALIZER_BAND_7,
301 EQUALIZER_BAND_8,
302 EQUALIZER_BAND_9,
303 TUNING_CTL_END_NID
304 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
305 };
306
307 struct ct_tuning_ctl {
308 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
309 hda_nid_t parent_nid;
310 hda_nid_t nid;
311 int mid; /*effect module ID*/
312 int req; /*effect module request*/
313 int direct; /* 0:output; 1:input*/
314 unsigned int def_val;/*effect default values*/
315 };
316
317 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
318 { .name = "Wedge Angle",
319 .parent_nid = VOICE_FOCUS,
320 .nid = WEDGE_ANGLE,
321 .mid = 0x95,
322 .req = 8,
323 .direct = EFX_DIR_IN,
324 .def_val = 0x41F00000
325 },
326 { .name = "SVM Level",
327 .parent_nid = MIC_SVM,
328 .nid = SVM_LEVEL,
329 .mid = 0x95,
330 .req = 45,
331 .direct = EFX_DIR_IN,
332 .def_val = 0x3F3D70A4
333 },
334 { .name = "EQ Band0",
335 .parent_nid = EQUALIZER,
336 .nid = EQUALIZER_BAND_0,
337 .mid = 0x96,
338 .req = 11,
339 .direct = EFX_DIR_OUT,
340 .def_val = 0x00000000
341 },
342 { .name = "EQ Band1",
343 .parent_nid = EQUALIZER,
344 .nid = EQUALIZER_BAND_1,
345 .mid = 0x96,
346 .req = 12,
347 .direct = EFX_DIR_OUT,
348 .def_val = 0x00000000
349 },
350 { .name = "EQ Band2",
351 .parent_nid = EQUALIZER,
352 .nid = EQUALIZER_BAND_2,
353 .mid = 0x96,
354 .req = 13,
355 .direct = EFX_DIR_OUT,
356 .def_val = 0x00000000
357 },
358 { .name = "EQ Band3",
359 .parent_nid = EQUALIZER,
360 .nid = EQUALIZER_BAND_3,
361 .mid = 0x96,
362 .req = 14,
363 .direct = EFX_DIR_OUT,
364 .def_val = 0x00000000
365 },
366 { .name = "EQ Band4",
367 .parent_nid = EQUALIZER,
368 .nid = EQUALIZER_BAND_4,
369 .mid = 0x96,
370 .req = 15,
371 .direct = EFX_DIR_OUT,
372 .def_val = 0x00000000
373 },
374 { .name = "EQ Band5",
375 .parent_nid = EQUALIZER,
376 .nid = EQUALIZER_BAND_5,
377 .mid = 0x96,
378 .req = 16,
379 .direct = EFX_DIR_OUT,
380 .def_val = 0x00000000
381 },
382 { .name = "EQ Band6",
383 .parent_nid = EQUALIZER,
384 .nid = EQUALIZER_BAND_6,
385 .mid = 0x96,
386 .req = 17,
387 .direct = EFX_DIR_OUT,
388 .def_val = 0x00000000
389 },
390 { .name = "EQ Band7",
391 .parent_nid = EQUALIZER,
392 .nid = EQUALIZER_BAND_7,
393 .mid = 0x96,
394 .req = 18,
395 .direct = EFX_DIR_OUT,
396 .def_val = 0x00000000
397 },
398 { .name = "EQ Band8",
399 .parent_nid = EQUALIZER,
400 .nid = EQUALIZER_BAND_8,
401 .mid = 0x96,
402 .req = 19,
403 .direct = EFX_DIR_OUT,
404 .def_val = 0x00000000
405 },
406 { .name = "EQ Band9",
407 .parent_nid = EQUALIZER,
408 .nid = EQUALIZER_BAND_9,
409 .mid = 0x96,
410 .req = 20,
411 .direct = EFX_DIR_OUT,
412 .def_val = 0x00000000
413 }
414 };
415 #endif
416
417 /* Voice FX Presets */
418 #define VOICEFX_MAX_PARAM_COUNT 9
419
420 struct ct_voicefx {
421 char *name;
422 hda_nid_t nid;
423 int mid;
424 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
425 };
426
427 struct ct_voicefx_preset {
428 char *name; /*preset name*/
429 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
430 };
431
432 static const struct ct_voicefx ca0132_voicefx = {
433 .name = "VoiceFX Capture Switch",
434 .nid = VOICEFX,
435 .mid = 0x95,
436 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
437 };
438
439 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
440 { .name = "Neutral",
441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
442 0x44FA0000, 0x3F800000, 0x3F800000,
443 0x3F800000, 0x00000000, 0x00000000 }
444 },
445 { .name = "Female2Male",
446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
447 0x44FA0000, 0x3F19999A, 0x3F866666,
448 0x3F800000, 0x00000000, 0x00000000 }
449 },
450 { .name = "Male2Female",
451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
452 0x450AC000, 0x4017AE14, 0x3F6B851F,
453 0x3F800000, 0x00000000, 0x00000000 }
454 },
455 { .name = "ScrappyKid",
456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
457 0x44FA0000, 0x40400000, 0x3F28F5C3,
458 0x3F800000, 0x00000000, 0x00000000 }
459 },
460 { .name = "Elderly",
461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
462 0x44E10000, 0x3FB33333, 0x3FB9999A,
463 0x3F800000, 0x3E3A2E43, 0x00000000 }
464 },
465 { .name = "Orc",
466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
467 0x45098000, 0x3F266666, 0x3FC00000,
468 0x3F800000, 0x00000000, 0x00000000 }
469 },
470 { .name = "Elf",
471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
472 0x45193000, 0x3F8E147B, 0x3F75C28F,
473 0x3F800000, 0x00000000, 0x00000000 }
474 },
475 { .name = "Dwarf",
476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
477 0x45007000, 0x3F451EB8, 0x3F7851EC,
478 0x3F800000, 0x00000000, 0x00000000 }
479 },
480 { .name = "AlienBrute",
481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
482 0x451F6000, 0x3F266666, 0x3FA7D945,
483 0x3F800000, 0x3CF5C28F, 0x00000000 }
484 },
485 { .name = "Robot",
486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
487 0x44FA0000, 0x3FB2718B, 0x3F800000,
488 0xBC07010E, 0x00000000, 0x00000000 }
489 },
490 { .name = "Marine",
491 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
493 0x3F0A3D71, 0x00000000, 0x00000000 }
494 },
495 { .name = "Emo",
496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
497 0x44FA0000, 0x3F800000, 0x3F800000,
498 0x3E4CCCCD, 0x00000000, 0x00000000 }
499 },
500 { .name = "DeepVoice",
501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
503 0x3F800000, 0x00000000, 0x00000000 }
504 },
505 { .name = "Munchkin",
506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
507 0x44FA0000, 0x3F800000, 0x3F1A043C,
508 0x3F800000, 0x00000000, 0x00000000 }
509 }
510 };
511
512 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
513
514 #define EQ_PRESET_MAX_PARAM_COUNT 11
515
516 struct ct_eq {
517 char *name;
518 hda_nid_t nid;
519 int mid;
520 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
521 };
522
523 struct ct_eq_preset {
524 char *name; /*preset name*/
525 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
526 };
527
528 static const struct ct_eq ca0132_alt_eq_enum = {
529 .name = "FX: Equalizer Preset Switch",
530 .nid = EQ_PRESET_ENUM,
531 .mid = 0x96,
532 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
533 };
534
535
536 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
537 { .name = "Flat",
538 .vals = { 0x00000000, 0x00000000, 0x00000000,
539 0x00000000, 0x00000000, 0x00000000,
540 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0x00000000 }
542 },
543 { .name = "Acoustic",
544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
545 0x40000000, 0x00000000, 0x00000000,
546 0x00000000, 0x00000000, 0x40000000,
547 0x40000000, 0x40000000 }
548 },
549 { .name = "Classical",
550 .vals = { 0x00000000, 0x00000000, 0x40C00000,
551 0x40C00000, 0x40466666, 0x00000000,
552 0x00000000, 0x00000000, 0x00000000,
553 0x40466666, 0x40466666 }
554 },
555 { .name = "Country",
556 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
558 0x00000000, 0x00000000, 0x40000000,
559 0x40466666, 0x40800000 }
560 },
561 { .name = "Dance",
562 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
563 0x40466666, 0x40866666, 0xBF99999A,
564 0xBF99999A, 0x00000000, 0x00000000,
565 0x40800000, 0x40800000 }
566 },
567 { .name = "Jazz",
568 .vals = { 0x00000000, 0x00000000, 0x00000000,
569 0x3F8CCCCD, 0x40800000, 0x40800000,
570 0x40800000, 0x00000000, 0x3F8CCCCD,
571 0x40466666, 0x40466666 }
572 },
573 { .name = "New Age",
574 .vals = { 0x00000000, 0x00000000, 0x40000000,
575 0x40000000, 0x00000000, 0x00000000,
576 0x00000000, 0x3F8CCCCD, 0x40000000,
577 0x40000000, 0x40000000 }
578 },
579 { .name = "Pop",
580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
581 0x40000000, 0x40000000, 0x00000000,
582 0xBF99999A, 0xBF99999A, 0x00000000,
583 0x40466666, 0x40C00000 }
584 },
585 { .name = "Rock",
586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
587 0x3F8CCCCD, 0x40000000, 0xBF99999A,
588 0xBF99999A, 0x00000000, 0x00000000,
589 0x40800000, 0x40800000 }
590 },
591 { .name = "Vocal",
592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
593 0xBF99999A, 0x00000000, 0x40466666,
594 0x40800000, 0x40466666, 0x00000000,
595 0x00000000, 0x3F8CCCCD }
596 }
597 };
598
599 /*
600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is
601 * set as not being full range, and bass redirection is enabled, all
602 * frequencies below the crossover frequency are redirected to the LFE
603 * channel. If the surround configuration has no LFE channel, this can't be
604 * enabled. X-Bass must be disabled when using these.
605 */
606 enum speaker_range_reqs {
607 SPEAKER_BASS_REDIRECT = 0x15,
608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
609 /* Between 0x16-0x1a are the X-Bass reqs. */
610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a,
611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b,
612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c,
613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d,
614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e,
615 };
616
617 /*
618 * Definitions for the DSP req's to handle speaker tuning. These all belong to
619 * module ID 0x96, the output effects module.
620 */
621 enum speaker_tuning_reqs {
622 /*
623 * Currently, this value is always set to 0.0f. However, on Windows,
624 * when selecting certain headphone profiles on the new Sound Blaster
625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
626 * sent. This gets the speaker EQ address area, which is then used to
627 * send over (presumably) an equalizer profile for the specific
628 * headphone setup. It is sent using the same method the DSP
629 * firmware is uploaded with, which I believe is why the 'ctspeq.bin'
630 * file exists in linux firmware tree but goes unused. It would also
631 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused.
632 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is
633 * set to 1.0f.
634 */
635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f,
636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20,
637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21,
638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22,
639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23,
640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24,
641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25,
642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26,
643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27,
644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
645 /*
646 * Inversion is used when setting headphone virtualization to line
647 * out. Not sure why this is, but it's the only place it's ever used.
648 */
649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29,
650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a,
651 SPEAKER_TUNING_CENTER_INVERT = 0x2b,
652 SPEAKER_TUNING_LFE_INVERT = 0x2c,
653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d,
654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e,
655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f,
656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30,
657 /* Delay is used when setting surround speaker distance in Windows. */
658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31,
659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32,
660 SPEAKER_TUNING_CENTER_DELAY = 0x33,
661 SPEAKER_TUNING_LFE_DELAY = 0x34,
662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35,
663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36,
664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37,
665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38,
666 /* Of these two, only mute seems to ever be used. */
667 SPEAKER_TUNING_MAIN_VOLUME = 0x39,
668 SPEAKER_TUNING_MUTE = 0x3a,
669 };
670
671 /* Surround output channel count configuration structures. */
672 #define SPEAKER_CHANNEL_CFG_COUNT 5
673 enum {
674 SPEAKER_CHANNELS_2_0,
675 SPEAKER_CHANNELS_2_1,
676 SPEAKER_CHANNELS_4_0,
677 SPEAKER_CHANNELS_4_1,
678 SPEAKER_CHANNELS_5_1,
679 };
680
681 struct ca0132_alt_speaker_channel_cfg {
682 char *name;
683 unsigned int val;
684 };
685
686 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = {
687 { .name = "2.0",
688 .val = FLOAT_ONE
689 },
690 { .name = "2.1",
691 .val = FLOAT_TWO
692 },
693 { .name = "4.0",
694 .val = FLOAT_FIVE
695 },
696 { .name = "4.1",
697 .val = FLOAT_SIX
698 },
699 { .name = "5.1",
700 .val = FLOAT_EIGHT
701 }
702 };
703
704 /*
705 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
706 * and I don't know what the third req is, but it's always zero. I assume it's
707 * some sort of update or set command to tell the DSP there's new volume info.
708 */
709 #define DSP_VOL_OUT 0
710 #define DSP_VOL_IN 1
711
712 struct ct_dsp_volume_ctl {
713 hda_nid_t vnid;
714 int mid; /* module ID*/
715 unsigned int reqs[3]; /* scp req ID */
716 };
717
718 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
719 { .vnid = VNID_SPK,
720 .mid = 0x32,
721 .reqs = {3, 4, 2}
722 },
723 { .vnid = VNID_MIC,
724 .mid = 0x37,
725 .reqs = {2, 3, 1}
726 }
727 };
728
729 /* Values for ca0113_mmio_command_set for selecting output. */
730 #define AE_CA0113_OUT_SET_COMMANDS 6
731 struct ae_ca0113_output_set {
732 unsigned int group[AE_CA0113_OUT_SET_COMMANDS];
733 unsigned int target[AE_CA0113_OUT_SET_COMMANDS];
734 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS];
735 };
736
737 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = {
738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
740 /* Speakers. */
741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
742 /* Headphones. */
743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
744 };
745
746 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = {
747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
749 /* Speakers. */
750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
751 /* Headphones. */
752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
753 };
754
755 /* ae5 ca0113 command sequences to set headphone gain levels. */
756 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
757 struct ae5_headphone_gain_set {
758 char *name;
759 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
760 };
761
762 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
763 { .name = "Low (16-31",
764 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
765 },
766 { .name = "Medium (32-149",
767 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
768 },
769 { .name = "High (150-600",
770 .vals = { 0xff, 0xff, 0xff, 0x7f }
771 }
772 };
773
774 struct ae5_filter_set {
775 char *name;
776 unsigned int val;
777 };
778
779 static const struct ae5_filter_set ae5_filter_presets[] = {
780 { .name = "Slow Roll Off",
781 .val = 0xa0
782 },
783 { .name = "Minimum Phase",
784 .val = 0xc0
785 },
786 { .name = "Fast Roll Off",
787 .val = 0x80
788 }
789 };
790
791 /*
792 * Data structures for storing audio router remapping data. These are used to
793 * remap a currently active streams ports.
794 */
795 struct chipio_stream_remap_data {
796 unsigned int stream_id;
797 unsigned int count;
798
799 unsigned int offset[16];
800 unsigned int value[16];
801 };
802
803 static const struct chipio_stream_remap_data stream_remap_data[] = {
804 { .stream_id = 0x14,
805 .count = 0x04,
806 .offset = { 0x00, 0x04, 0x08, 0x0c },
807 .value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 },
808 },
809 { .stream_id = 0x0c,
810 .count = 0x0c,
811 .offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c,
812 0x20, 0x24, 0x28, 0x2c },
813 .value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3,
814 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7,
815 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb },
816 },
817 { .stream_id = 0x0c,
818 .count = 0x08,
819 .offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c },
820 .value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5,
821 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb },
822 }
823 };
824
825 enum hda_cmd_vendor_io {
826 /* for DspIO node */
827 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
828 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
829
830 VENDOR_DSPIO_STATUS = 0xF01,
831 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
832 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
833 VENDOR_DSPIO_DSP_INIT = 0x703,
834 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
835 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
836
837 /* for ChipIO node */
838 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
839 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
840 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
841 VENDOR_CHIPIO_DATA_LOW = 0x300,
842 VENDOR_CHIPIO_DATA_HIGH = 0x400,
843
844 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
845 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
846
847 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
848 VENDOR_CHIPIO_STATUS = 0xF01,
849 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
850 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
851
852 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
853 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
854 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
855 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
856 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
857
858 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
859 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
860
861 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
862 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
863 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
864 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
865 VENDOR_CHIPIO_FLAG_SET = 0x70F,
866 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
867 VENDOR_CHIPIO_PARAM_SET = 0x710,
868 VENDOR_CHIPIO_PARAM_GET = 0xF10,
869
870 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
871 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
872 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
873 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
874
875 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
876 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
877 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
878 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
879
880 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
881 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
882 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
883 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
884 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
885 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
886
887 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
888 };
889
890 /*
891 * Control flag IDs
892 */
893 enum control_flag_id {
894 /* Connection manager stream setup is bypassed/enabled */
895 CONTROL_FLAG_C_MGR = 0,
896 /* DSP DMA is bypassed/enabled */
897 CONTROL_FLAG_DMA = 1,
898 /* 8051 'idle' mode is disabled/enabled */
899 CONTROL_FLAG_IDLE_ENABLE = 2,
900 /* Tracker for the SPDIF-in path is bypassed/enabled */
901 CONTROL_FLAG_TRACKER = 3,
902 /* DigitalOut to Spdif2Out connection is disabled/enabled */
903 CONTROL_FLAG_SPDIF2OUT = 4,
904 /* Digital Microphone is disabled/enabled */
905 CONTROL_FLAG_DMIC = 5,
906 /* ADC_B rate is 48 kHz/96 kHz */
907 CONTROL_FLAG_ADC_B_96KHZ = 6,
908 /* ADC_C rate is 48 kHz/96 kHz */
909 CONTROL_FLAG_ADC_C_96KHZ = 7,
910 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
911 CONTROL_FLAG_DAC_96KHZ = 8,
912 /* DSP rate is 48 kHz/96 kHz */
913 CONTROL_FLAG_DSP_96KHZ = 9,
914 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
915 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
916 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
917 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
918 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
919 CONTROL_FLAG_DECODE_LOOP = 12,
920 /* De-emphasis filter on DAC-1 disabled/enabled */
921 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
922 /* De-emphasis filter on DAC-2 disabled/enabled */
923 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
924 /* De-emphasis filter on DAC-3 disabled/enabled */
925 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
926 /* High-pass filter on ADC_B disabled/enabled */
927 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
928 /* High-pass filter on ADC_C disabled/enabled */
929 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
930 /* Common mode on Port_A disabled/enabled */
931 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
932 /* Common mode on Port_D disabled/enabled */
933 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
934 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
935 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
936 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
937 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
938 /* ASI rate is 48kHz/96kHz */
939 CONTROL_FLAG_ASI_96KHZ = 22,
940 /* DAC power settings able to control attached ports no/yes */
941 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
942 /* Clock Stop OK reporting is disabled/enabled */
943 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
944 /* Number of control flags */
945 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
946 };
947
948 /*
949 * Control parameter IDs
950 */
951 enum control_param_id {
952 /* 0: None, 1: Mic1In*/
953 CONTROL_PARAM_VIP_SOURCE = 1,
954 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
955 CONTROL_PARAM_SPDIF1_SOURCE = 2,
956 /* Port A output stage gain setting to use when 16 Ohm output
957 * impedance is selected*/
958 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
959 /* Port D output stage gain setting to use when 16 Ohm output
960 * impedance is selected*/
961 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
962
963 /*
964 * This control param name was found in the 8051 memory, and makes
965 * sense given the fact the AE-5 uses it and has the ASI flag set.
966 */
967 CONTROL_PARAM_ASI = 23,
968
969 /* Stream Control */
970
971 /* Select stream with the given ID */
972 CONTROL_PARAM_STREAM_ID = 24,
973 /* Source connection point for the selected stream */
974 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
975 /* Destination connection point for the selected stream */
976 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
977 /* Number of audio channels in the selected stream */
978 CONTROL_PARAM_STREAMS_CHANNELS = 27,
979 /*Enable control for the selected stream */
980 CONTROL_PARAM_STREAM_CONTROL = 28,
981
982 /* Connection Point Control */
983
984 /* Select connection point with the given ID */
985 CONTROL_PARAM_CONN_POINT_ID = 29,
986 /* Connection point sample rate */
987 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
988
989 /* Node Control */
990
991 /* Select HDA node with the given ID */
992 CONTROL_PARAM_NODE_ID = 31
993 };
994
995 /*
996 * Dsp Io Status codes
997 */
998 enum hda_vendor_status_dspio {
999 /* Success */
1000 VENDOR_STATUS_DSPIO_OK = 0x00,
1001 /* Busy, unable to accept new command, the host must retry */
1002 VENDOR_STATUS_DSPIO_BUSY = 0x01,
1003 /* SCP command queue is full */
1004 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
1005 /* SCP response queue is empty */
1006 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
1007 };
1008
1009 /*
1010 * Chip Io Status codes
1011 */
1012 enum hda_vendor_status_chipio {
1013 /* Success */
1014 VENDOR_STATUS_CHIPIO_OK = 0x00,
1015 /* Busy, unable to accept new command, the host must retry */
1016 VENDOR_STATUS_CHIPIO_BUSY = 0x01
1017 };
1018
1019 /*
1020 * CA0132 sample rate
1021 */
1022 enum ca0132_sample_rate {
1023 SR_6_000 = 0x00,
1024 SR_8_000 = 0x01,
1025 SR_9_600 = 0x02,
1026 SR_11_025 = 0x03,
1027 SR_16_000 = 0x04,
1028 SR_22_050 = 0x05,
1029 SR_24_000 = 0x06,
1030 SR_32_000 = 0x07,
1031 SR_44_100 = 0x08,
1032 SR_48_000 = 0x09,
1033 SR_88_200 = 0x0A,
1034 SR_96_000 = 0x0B,
1035 SR_144_000 = 0x0C,
1036 SR_176_400 = 0x0D,
1037 SR_192_000 = 0x0E,
1038 SR_384_000 = 0x0F,
1039
1040 SR_COUNT = 0x10,
1041
1042 SR_RATE_UNKNOWN = 0x1F
1043 };
1044
1045 enum dsp_download_state {
1046 DSP_DOWNLOAD_FAILED = -1,
1047 DSP_DOWNLOAD_INIT = 0,
1048 DSP_DOWNLOADING = 1,
1049 DSP_DOWNLOADED = 2
1050 };
1051
1052 /* retrieve parameters from hda format */
1053 #define get_hdafmt_chs(fmt) (fmt & 0xf)
1054 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
1055 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
1056 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
1057
1058 /*
1059 * CA0132 specific
1060 */
1061
1062 struct ca0132_spec {
1063 const struct snd_kcontrol_new *mixers[5];
1064 unsigned int num_mixers;
1065 const struct hda_verb *base_init_verbs;
1066 const struct hda_verb *base_exit_verbs;
1067 const struct hda_verb *chip_init_verbs;
1068 const struct hda_verb *desktop_init_verbs;
1069 struct hda_verb *spec_init_verbs;
1070 struct auto_pin_cfg autocfg;
1071
1072 /* Nodes configurations */
1073 struct hda_multi_out multiout;
1074 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
1075 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
1076 unsigned int num_outputs;
1077 hda_nid_t input_pins[AUTO_PIN_LAST];
1078 hda_nid_t adcs[AUTO_PIN_LAST];
1079 hda_nid_t dig_out;
1080 hda_nid_t dig_in;
1081 unsigned int num_inputs;
1082 hda_nid_t shared_mic_nid;
1083 hda_nid_t shared_out_nid;
1084 hda_nid_t unsol_tag_hp;
1085 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
1086 hda_nid_t unsol_tag_amic1;
1087
1088 /* chip access */
1089 struct mutex chipio_mutex; /* chip access mutex */
1090 u32 curr_chip_addx;
1091
1092 /* DSP download related */
1093 enum dsp_download_state dsp_state;
1094 unsigned int dsp_stream_id;
1095 unsigned int wait_scp;
1096 unsigned int wait_scp_header;
1097 unsigned int wait_num_data;
1098 unsigned int scp_resp_header;
1099 unsigned int scp_resp_data[4];
1100 unsigned int scp_resp_count;
1101 bool startup_check_entered;
1102 bool dsp_reload;
1103
1104 /* mixer and effects related */
1105 unsigned char dmic_ctl;
1106 int cur_out_type;
1107 int cur_mic_type;
1108 long vnode_lvol[VNODES_COUNT];
1109 long vnode_rvol[VNODES_COUNT];
1110 long vnode_lswitch[VNODES_COUNT];
1111 long vnode_rswitch[VNODES_COUNT];
1112 long effects_switch[EFFECTS_COUNT];
1113 long voicefx_val;
1114 long cur_mic_boost;
1115 /* ca0132_alt control related values */
1116 unsigned char in_enum_val;
1117 unsigned char out_enum_val;
1118 unsigned char channel_cfg_val;
1119 unsigned char speaker_range_val[2];
1120 unsigned char mic_boost_enum_val;
1121 unsigned char smart_volume_setting;
1122 unsigned char bass_redirection_val;
1123 long bass_redirect_xover_freq;
1124 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1125 long xbass_xover_freq;
1126 long eq_preset_val;
1127 unsigned int tlv[4];
1128 struct hda_vmaster_mute_hook vmaster_mute;
1129 /* AE-5 Control values */
1130 unsigned char ae5_headphone_gain_val;
1131 unsigned char ae5_filter_val;
1132 /* ZxR Control Values */
1133 unsigned char zxr_gain_set;
1134
1135 struct hda_codec *codec;
1136 struct delayed_work unsol_hp_work;
1137 int quirk;
1138
1139 #ifdef ENABLE_TUNING_CONTROLS
1140 long cur_ctl_vals[TUNING_CTLS_COUNT];
1141 #endif
1142 /*
1143 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1144 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1145 * things.
1146 */
1147 bool use_pci_mmio;
1148 void __iomem *mem_base;
1149
1150 /*
1151 * Whether or not to use the alt functions like alt_select_out,
1152 * alt_select_in, etc. Only used on desktop codecs for now, because of
1153 * surround sound support.
1154 */
1155 bool use_alt_functions;
1156
1157 /*
1158 * Whether or not to use alt controls: volume effect sliders, EQ
1159 * presets, smart volume presets, and new control names with FX prefix.
1160 * Renames PlayEnhancement and CrystalVoice too.
1161 */
1162 bool use_alt_controls;
1163 };
1164
1165 /*
1166 * CA0132 quirks table
1167 */
1168 enum {
1169 QUIRK_NONE,
1170 QUIRK_ALIENWARE,
1171 QUIRK_ALIENWARE_M17XR4,
1172 QUIRK_SBZ,
1173 QUIRK_ZXR,
1174 QUIRK_ZXR_DBPRO,
1175 QUIRK_R3DI,
1176 QUIRK_R3D,
1177 QUIRK_AE5,
1178 QUIRK_AE7,
1179 };
1180
1181 #ifdef CONFIG_PCI
1182 #define ca0132_quirk(spec) ((spec)->quirk)
1183 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio)
1184 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions)
1185 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls)
1186 #else
1187 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; })
1188 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; })
1189 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; })
1190 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; })
1191 #endif
1192
1193 static const struct hda_pintbl alienware_pincfgs[] = {
1194 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1195 { 0x0c, 0x411111f0 }, /* N/A */
1196 { 0x0d, 0x411111f0 }, /* N/A */
1197 { 0x0e, 0x411111f0 }, /* N/A */
1198 { 0x0f, 0x0321101f }, /* HP */
1199 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1200 { 0x11, 0x03a11021 }, /* Mic */
1201 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1202 { 0x13, 0x411111f0 }, /* N/A */
1203 { 0x18, 0x411111f0 }, /* N/A */
1204 {}
1205 };
1206
1207 /* Sound Blaster Z pin configs taken from Windows Driver */
1208 static const struct hda_pintbl sbz_pincfgs[] = {
1209 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1210 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1211 { 0x0d, 0x014510f0 }, /* Digital Out */
1212 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1213 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1214 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1215 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1216 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1217 { 0x13, 0x908700f0 }, /* What U Hear In*/
1218 { 0x18, 0x50d000f0 }, /* N/A */
1219 {}
1220 };
1221
1222 /* Sound Blaster ZxR pin configs taken from Windows Driver */
1223 static const struct hda_pintbl zxr_pincfgs[] = {
1224 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1225 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1226 { 0x0d, 0x014510f0 }, /* Digital Out */
1227 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1228 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1229 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1230 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1231 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1232 { 0x13, 0x908700f0 }, /* What U Hear In*/
1233 { 0x18, 0x50d000f0 }, /* N/A */
1234 {}
1235 };
1236
1237 /* Recon3D pin configs taken from Windows Driver */
1238 static const struct hda_pintbl r3d_pincfgs[] = {
1239 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1240 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1241 { 0x0d, 0x014510f0 }, /* Digital Out */
1242 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1243 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1244 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1245 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1246 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1247 { 0x13, 0x908700f0 }, /* What U Hear In*/
1248 { 0x18, 0x50d000f0 }, /* N/A */
1249 {}
1250 };
1251
1252 /* Sound Blaster AE-5 pin configs taken from Windows Driver */
1253 static const struct hda_pintbl ae5_pincfgs[] = {
1254 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1255 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1256 { 0x0d, 0x014510f0 }, /* Digital Out */
1257 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1258 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1259 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1260 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1261 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1262 { 0x13, 0x908700f0 }, /* What U Hear In*/
1263 { 0x18, 0x50d000f0 }, /* N/A */
1264 {}
1265 };
1266
1267 /* Recon3D integrated pin configs taken from Windows Driver */
1268 static const struct hda_pintbl r3di_pincfgs[] = {
1269 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1270 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1271 { 0x0d, 0x014510f0 }, /* Digital Out */
1272 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1273 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1274 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1275 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1276 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1277 { 0x13, 0x908700f0 }, /* What U Hear In*/
1278 { 0x18, 0x500000f0 }, /* N/A */
1279 {}
1280 };
1281
1282 static const struct hda_pintbl ae7_pincfgs[] = {
1283 { 0x0b, 0x01017010 },
1284 { 0x0c, 0x014510f0 },
1285 { 0x0d, 0x414510f0 },
1286 { 0x0e, 0x01c520f0 },
1287 { 0x0f, 0x01017114 },
1288 { 0x10, 0x01017011 },
1289 { 0x11, 0x018170ff },
1290 { 0x12, 0x01a170f0 },
1291 { 0x13, 0x908700f0 },
1292 { 0x18, 0x500000f0 },
1293 {}
1294 };
1295
1296 static const struct snd_pci_quirk ca0132_quirks[] = {
1297 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1298 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1299 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1300 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1301 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1302 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1303 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1304 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1305 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1306 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1307 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1308 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1309 SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI),
1310 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1311 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1312 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1313 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1314 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1315 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1316 {}
1317 };
1318
1319 /* Output selection quirk info structures. */
1320 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3
1321 #define MAX_QUIRK_SCP_SET_VALS 2
1322 struct ca0132_alt_out_set_info {
1323 unsigned int dac2port; /* ParamID 0x0d value. */
1324
1325 bool has_hda_gpio;
1326 char hda_gpio_pin;
1327 char hda_gpio_set;
1328
1329 unsigned int mmio_gpio_count;
1330 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1331 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1332
1333 unsigned int scp_cmds_count;
1334 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS];
1335 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS];
1336 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS];
1337
1338 bool has_chipio_write;
1339 unsigned int chipio_write_addr;
1340 unsigned int chipio_write_data;
1341 };
1342
1343 struct ca0132_alt_out_set_quirk_data {
1344 int quirk_id;
1345
1346 bool has_headphone_gain;
1347 bool is_ae_series;
1348
1349 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS];
1350 };
1351
1352 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = {
1353 { .quirk_id = QUIRK_R3DI,
1354 .has_headphone_gain = false,
1355 .is_ae_series = false,
1356 .out_set_info = {
1357 /* Speakers. */
1358 { .dac2port = 0x24,
1359 .has_hda_gpio = true,
1360 .hda_gpio_pin = 2,
1361 .hda_gpio_set = 1,
1362 .mmio_gpio_count = 0,
1363 .scp_cmds_count = 0,
1364 .has_chipio_write = false,
1365 },
1366 /* Headphones. */
1367 { .dac2port = 0x21,
1368 .has_hda_gpio = true,
1369 .hda_gpio_pin = 2,
1370 .hda_gpio_set = 0,
1371 .mmio_gpio_count = 0,
1372 .scp_cmds_count = 0,
1373 .has_chipio_write = false,
1374 } },
1375 },
1376 { .quirk_id = QUIRK_R3D,
1377 .has_headphone_gain = false,
1378 .is_ae_series = false,
1379 .out_set_info = {
1380 /* Speakers. */
1381 { .dac2port = 0x24,
1382 .has_hda_gpio = false,
1383 .mmio_gpio_count = 1,
1384 .mmio_gpio_pin = { 1 },
1385 .mmio_gpio_set = { 1 },
1386 .scp_cmds_count = 0,
1387 .has_chipio_write = false,
1388 },
1389 /* Headphones. */
1390 { .dac2port = 0x21,
1391 .has_hda_gpio = false,
1392 .mmio_gpio_count = 1,
1393 .mmio_gpio_pin = { 1 },
1394 .mmio_gpio_set = { 0 },
1395 .scp_cmds_count = 0,
1396 .has_chipio_write = false,
1397 } },
1398 },
1399 { .quirk_id = QUIRK_SBZ,
1400 .has_headphone_gain = false,
1401 .is_ae_series = false,
1402 .out_set_info = {
1403 /* Speakers. */
1404 { .dac2port = 0x18,
1405 .has_hda_gpio = false,
1406 .mmio_gpio_count = 3,
1407 .mmio_gpio_pin = { 7, 4, 1 },
1408 .mmio_gpio_set = { 0, 1, 1 },
1409 .scp_cmds_count = 0,
1410 .has_chipio_write = false, },
1411 /* Headphones. */
1412 { .dac2port = 0x12,
1413 .has_hda_gpio = false,
1414 .mmio_gpio_count = 3,
1415 .mmio_gpio_pin = { 7, 4, 1 },
1416 .mmio_gpio_set = { 1, 1, 0 },
1417 .scp_cmds_count = 0,
1418 .has_chipio_write = false,
1419 } },
1420 },
1421 { .quirk_id = QUIRK_ZXR,
1422 .has_headphone_gain = true,
1423 .is_ae_series = false,
1424 .out_set_info = {
1425 /* Speakers. */
1426 { .dac2port = 0x24,
1427 .has_hda_gpio = false,
1428 .mmio_gpio_count = 3,
1429 .mmio_gpio_pin = { 2, 3, 5 },
1430 .mmio_gpio_set = { 1, 1, 0 },
1431 .scp_cmds_count = 0,
1432 .has_chipio_write = false,
1433 },
1434 /* Headphones. */
1435 { .dac2port = 0x21,
1436 .has_hda_gpio = false,
1437 .mmio_gpio_count = 3,
1438 .mmio_gpio_pin = { 2, 3, 5 },
1439 .mmio_gpio_set = { 0, 1, 1 },
1440 .scp_cmds_count = 0,
1441 .has_chipio_write = false,
1442 } },
1443 },
1444 { .quirk_id = QUIRK_AE5,
1445 .has_headphone_gain = true,
1446 .is_ae_series = true,
1447 .out_set_info = {
1448 /* Speakers. */
1449 { .dac2port = 0xa4,
1450 .has_hda_gpio = false,
1451 .mmio_gpio_count = 0,
1452 .scp_cmds_count = 2,
1453 .scp_cmd_mid = { 0x96, 0x96 },
1454 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1455 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1456 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO },
1457 .has_chipio_write = true,
1458 .chipio_write_addr = 0x0018b03c,
1459 .chipio_write_data = 0x00000012
1460 },
1461 /* Headphones. */
1462 { .dac2port = 0xa1,
1463 .has_hda_gpio = false,
1464 .mmio_gpio_count = 0,
1465 .scp_cmds_count = 2,
1466 .scp_cmd_mid = { 0x96, 0x96 },
1467 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1468 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1469 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE },
1470 .has_chipio_write = true,
1471 .chipio_write_addr = 0x0018b03c,
1472 .chipio_write_data = 0x00000012
1473 } },
1474 },
1475 { .quirk_id = QUIRK_AE7,
1476 .has_headphone_gain = true,
1477 .is_ae_series = true,
1478 .out_set_info = {
1479 /* Speakers. */
1480 { .dac2port = 0x58,
1481 .has_hda_gpio = false,
1482 .mmio_gpio_count = 1,
1483 .mmio_gpio_pin = { 0 },
1484 .mmio_gpio_set = { 1 },
1485 .scp_cmds_count = 2,
1486 .scp_cmd_mid = { 0x96, 0x96 },
1487 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1488 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1489 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO },
1490 .has_chipio_write = true,
1491 .chipio_write_addr = 0x0018b03c,
1492 .chipio_write_data = 0x00000000
1493 },
1494 /* Headphones. */
1495 { .dac2port = 0x58,
1496 .has_hda_gpio = false,
1497 .mmio_gpio_count = 1,
1498 .mmio_gpio_pin = { 0 },
1499 .mmio_gpio_set = { 1 },
1500 .scp_cmds_count = 2,
1501 .scp_cmd_mid = { 0x96, 0x96 },
1502 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1503 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1504 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE },
1505 .has_chipio_write = true,
1506 .chipio_write_addr = 0x0018b03c,
1507 .chipio_write_data = 0x00000010
1508 } },
1509 }
1510 };
1511
1512 /*
1513 * CA0132 codec access
1514 */
codec_send_command(struct hda_codec * codec,hda_nid_t nid,unsigned int verb,unsigned int parm,unsigned int * res)1515 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1516 unsigned int verb, unsigned int parm, unsigned int *res)
1517 {
1518 unsigned int response;
1519 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1520 *res = response;
1521
1522 return ((response == -1) ? -1 : 0);
1523 }
1524
codec_set_converter_format(struct hda_codec * codec,hda_nid_t nid,unsigned short converter_format,unsigned int * res)1525 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1526 unsigned short converter_format, unsigned int *res)
1527 {
1528 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1529 converter_format & 0xffff, res);
1530 }
1531
codec_set_converter_stream_channel(struct hda_codec * codec,hda_nid_t nid,unsigned char stream,unsigned char channel,unsigned int * res)1532 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1533 hda_nid_t nid, unsigned char stream,
1534 unsigned char channel, unsigned int *res)
1535 {
1536 unsigned char converter_stream_channel = 0;
1537
1538 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1539 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1540 converter_stream_channel, res);
1541 }
1542
1543 /* Chip access helper function */
chipio_send(struct hda_codec * codec,unsigned int reg,unsigned int data)1544 static int chipio_send(struct hda_codec *codec,
1545 unsigned int reg,
1546 unsigned int data)
1547 {
1548 unsigned int res;
1549 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1550
1551 /* send bits of data specified by reg */
1552 do {
1553 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1554 reg, data);
1555 if (res == VENDOR_STATUS_CHIPIO_OK)
1556 return 0;
1557 msleep(20);
1558 } while (time_before(jiffies, timeout));
1559
1560 return -EIO;
1561 }
1562
1563 /*
1564 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1565 */
chipio_write_address(struct hda_codec * codec,unsigned int chip_addx)1566 static int chipio_write_address(struct hda_codec *codec,
1567 unsigned int chip_addx)
1568 {
1569 struct ca0132_spec *spec = codec->spec;
1570 int res;
1571
1572 if (spec->curr_chip_addx == chip_addx)
1573 return 0;
1574
1575 /* send low 16 bits of the address */
1576 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1577 chip_addx & 0xffff);
1578
1579 if (res != -EIO) {
1580 /* send high 16 bits of the address */
1581 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1582 chip_addx >> 16);
1583 }
1584
1585 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1586
1587 return res;
1588 }
1589
1590 /*
1591 * Write data through the vendor widget -- NOT protected by the Mutex!
1592 */
chipio_write_data(struct hda_codec * codec,unsigned int data)1593 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1594 {
1595 struct ca0132_spec *spec = codec->spec;
1596 int res;
1597
1598 /* send low 16 bits of the data */
1599 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1600
1601 if (res != -EIO) {
1602 /* send high 16 bits of the data */
1603 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1604 data >> 16);
1605 }
1606
1607 /*If no error encountered, automatically increment the address
1608 as per chip behaviour*/
1609 spec->curr_chip_addx = (res != -EIO) ?
1610 (spec->curr_chip_addx + 4) : ~0U;
1611 return res;
1612 }
1613
1614 /*
1615 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1616 */
chipio_write_data_multiple(struct hda_codec * codec,const u32 * data,unsigned int count)1617 static int chipio_write_data_multiple(struct hda_codec *codec,
1618 const u32 *data,
1619 unsigned int count)
1620 {
1621 int status = 0;
1622
1623 if (data == NULL) {
1624 codec_dbg(codec, "chipio_write_data null ptr\n");
1625 return -EINVAL;
1626 }
1627
1628 while ((count-- != 0) && (status == 0))
1629 status = chipio_write_data(codec, *data++);
1630
1631 return status;
1632 }
1633
1634
1635 /*
1636 * Read data through the vendor widget -- NOT protected by the Mutex!
1637 */
chipio_read_data(struct hda_codec * codec,unsigned int * data)1638 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1639 {
1640 struct ca0132_spec *spec = codec->spec;
1641 int res;
1642
1643 /* post read */
1644 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1645
1646 if (res != -EIO) {
1647 /* read status */
1648 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1649 }
1650
1651 if (res != -EIO) {
1652 /* read data */
1653 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1654 VENDOR_CHIPIO_HIC_READ_DATA,
1655 0);
1656 }
1657
1658 /*If no error encountered, automatically increment the address
1659 as per chip behaviour*/
1660 spec->curr_chip_addx = (res != -EIO) ?
1661 (spec->curr_chip_addx + 4) : ~0U;
1662 return res;
1663 }
1664
1665 /*
1666 * Write given value to the given address through the chip I/O widget.
1667 * protected by the Mutex
1668 */
chipio_write(struct hda_codec * codec,unsigned int chip_addx,const unsigned int data)1669 static int chipio_write(struct hda_codec *codec,
1670 unsigned int chip_addx, const unsigned int data)
1671 {
1672 struct ca0132_spec *spec = codec->spec;
1673 int err;
1674
1675 mutex_lock(&spec->chipio_mutex);
1676
1677 /* write the address, and if successful proceed to write data */
1678 err = chipio_write_address(codec, chip_addx);
1679 if (err < 0)
1680 goto exit;
1681
1682 err = chipio_write_data(codec, data);
1683 if (err < 0)
1684 goto exit;
1685
1686 exit:
1687 mutex_unlock(&spec->chipio_mutex);
1688 return err;
1689 }
1690
1691 /*
1692 * Write given value to the given address through the chip I/O widget.
1693 * not protected by the Mutex
1694 */
chipio_write_no_mutex(struct hda_codec * codec,unsigned int chip_addx,const unsigned int data)1695 static int chipio_write_no_mutex(struct hda_codec *codec,
1696 unsigned int chip_addx, const unsigned int data)
1697 {
1698 int err;
1699
1700
1701 /* write the address, and if successful proceed to write data */
1702 err = chipio_write_address(codec, chip_addx);
1703 if (err < 0)
1704 goto exit;
1705
1706 err = chipio_write_data(codec, data);
1707 if (err < 0)
1708 goto exit;
1709
1710 exit:
1711 return err;
1712 }
1713
1714 /*
1715 * Write multiple values to the given address through the chip I/O widget.
1716 * protected by the Mutex
1717 */
chipio_write_multiple(struct hda_codec * codec,u32 chip_addx,const u32 * data,unsigned int count)1718 static int chipio_write_multiple(struct hda_codec *codec,
1719 u32 chip_addx,
1720 const u32 *data,
1721 unsigned int count)
1722 {
1723 struct ca0132_spec *spec = codec->spec;
1724 int status;
1725
1726 mutex_lock(&spec->chipio_mutex);
1727 status = chipio_write_address(codec, chip_addx);
1728 if (status < 0)
1729 goto error;
1730
1731 status = chipio_write_data_multiple(codec, data, count);
1732 error:
1733 mutex_unlock(&spec->chipio_mutex);
1734
1735 return status;
1736 }
1737
1738 /*
1739 * Read the given address through the chip I/O widget
1740 * protected by the Mutex
1741 */
chipio_read(struct hda_codec * codec,unsigned int chip_addx,unsigned int * data)1742 static int chipio_read(struct hda_codec *codec,
1743 unsigned int chip_addx, unsigned int *data)
1744 {
1745 struct ca0132_spec *spec = codec->spec;
1746 int err;
1747
1748 mutex_lock(&spec->chipio_mutex);
1749
1750 /* write the address, and if successful proceed to write data */
1751 err = chipio_write_address(codec, chip_addx);
1752 if (err < 0)
1753 goto exit;
1754
1755 err = chipio_read_data(codec, data);
1756 if (err < 0)
1757 goto exit;
1758
1759 exit:
1760 mutex_unlock(&spec->chipio_mutex);
1761 return err;
1762 }
1763
1764 /*
1765 * Set chip control flags through the chip I/O widget.
1766 */
chipio_set_control_flag(struct hda_codec * codec,enum control_flag_id flag_id,bool flag_state)1767 static void chipio_set_control_flag(struct hda_codec *codec,
1768 enum control_flag_id flag_id,
1769 bool flag_state)
1770 {
1771 unsigned int val;
1772 unsigned int flag_bit;
1773
1774 flag_bit = (flag_state ? 1 : 0);
1775 val = (flag_bit << 7) | (flag_id);
1776 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1777 VENDOR_CHIPIO_FLAG_SET, val);
1778 }
1779
1780 /*
1781 * Set chip parameters through the chip I/O widget.
1782 */
chipio_set_control_param(struct hda_codec * codec,enum control_param_id param_id,int param_val)1783 static void chipio_set_control_param(struct hda_codec *codec,
1784 enum control_param_id param_id, int param_val)
1785 {
1786 struct ca0132_spec *spec = codec->spec;
1787 int val;
1788
1789 if ((param_id < 32) && (param_val < 8)) {
1790 val = (param_val << 5) | (param_id);
1791 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1792 VENDOR_CHIPIO_PARAM_SET, val);
1793 } else {
1794 mutex_lock(&spec->chipio_mutex);
1795 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1796 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1797 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1798 param_id);
1799 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1800 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1801 param_val);
1802 }
1803 mutex_unlock(&spec->chipio_mutex);
1804 }
1805 }
1806
1807 /*
1808 * Set chip parameters through the chip I/O widget. NO MUTEX.
1809 */
chipio_set_control_param_no_mutex(struct hda_codec * codec,enum control_param_id param_id,int param_val)1810 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1811 enum control_param_id param_id, int param_val)
1812 {
1813 int val;
1814
1815 if ((param_id < 32) && (param_val < 8)) {
1816 val = (param_val << 5) | (param_id);
1817 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1818 VENDOR_CHIPIO_PARAM_SET, val);
1819 } else {
1820 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1821 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1822 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1823 param_id);
1824 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1825 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1826 param_val);
1827 }
1828 }
1829 }
1830 /*
1831 * Connect stream to a source point, and then connect
1832 * that source point to a destination point.
1833 */
chipio_set_stream_source_dest(struct hda_codec * codec,int streamid,int source_point,int dest_point)1834 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1835 int streamid, int source_point, int dest_point)
1836 {
1837 chipio_set_control_param_no_mutex(codec,
1838 CONTROL_PARAM_STREAM_ID, streamid);
1839 chipio_set_control_param_no_mutex(codec,
1840 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1841 chipio_set_control_param_no_mutex(codec,
1842 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1843 }
1844
1845 /*
1846 * Set number of channels in the selected stream.
1847 */
chipio_set_stream_channels(struct hda_codec * codec,int streamid,unsigned int channels)1848 static void chipio_set_stream_channels(struct hda_codec *codec,
1849 int streamid, unsigned int channels)
1850 {
1851 chipio_set_control_param_no_mutex(codec,
1852 CONTROL_PARAM_STREAM_ID, streamid);
1853 chipio_set_control_param_no_mutex(codec,
1854 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1855 }
1856
1857 /*
1858 * Enable/Disable audio stream.
1859 */
chipio_set_stream_control(struct hda_codec * codec,int streamid,int enable)1860 static void chipio_set_stream_control(struct hda_codec *codec,
1861 int streamid, int enable)
1862 {
1863 chipio_set_control_param_no_mutex(codec,
1864 CONTROL_PARAM_STREAM_ID, streamid);
1865 chipio_set_control_param_no_mutex(codec,
1866 CONTROL_PARAM_STREAM_CONTROL, enable);
1867 }
1868
1869 /*
1870 * Get ChipIO audio stream's status.
1871 */
chipio_get_stream_control(struct hda_codec * codec,int streamid,unsigned int * enable)1872 static void chipio_get_stream_control(struct hda_codec *codec,
1873 int streamid, unsigned int *enable)
1874 {
1875 chipio_set_control_param_no_mutex(codec,
1876 CONTROL_PARAM_STREAM_ID, streamid);
1877 *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1878 VENDOR_CHIPIO_PARAM_GET,
1879 CONTROL_PARAM_STREAM_CONTROL);
1880 }
1881
1882 /*
1883 * Set sampling rate of the connection point. NO MUTEX.
1884 */
chipio_set_conn_rate_no_mutex(struct hda_codec * codec,int connid,enum ca0132_sample_rate rate)1885 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1886 int connid, enum ca0132_sample_rate rate)
1887 {
1888 chipio_set_control_param_no_mutex(codec,
1889 CONTROL_PARAM_CONN_POINT_ID, connid);
1890 chipio_set_control_param_no_mutex(codec,
1891 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1892 }
1893
1894 /*
1895 * Set sampling rate of the connection point.
1896 */
chipio_set_conn_rate(struct hda_codec * codec,int connid,enum ca0132_sample_rate rate)1897 static void chipio_set_conn_rate(struct hda_codec *codec,
1898 int connid, enum ca0132_sample_rate rate)
1899 {
1900 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1901 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1902 rate);
1903 }
1904
1905 /*
1906 * Writes to the 8051's internal address space directly instead of indirectly,
1907 * giving access to the special function registers located at addresses
1908 * 0x80-0xFF.
1909 */
chipio_8051_write_direct(struct hda_codec * codec,unsigned int addr,unsigned int data)1910 static void chipio_8051_write_direct(struct hda_codec *codec,
1911 unsigned int addr, unsigned int data)
1912 {
1913 unsigned int verb;
1914
1915 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1916 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1917 }
1918
1919 /*
1920 * Writes to the 8051's exram, which has 16-bits of address space.
1921 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff.
1922 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by
1923 * setting the pmem bank selection SFR.
1924 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff
1925 * being writable.
1926 */
chipio_8051_set_address(struct hda_codec * codec,unsigned int addr)1927 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr)
1928 {
1929 unsigned int tmp;
1930
1931 /* Lower 8-bits. */
1932 tmp = addr & 0xff;
1933 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1934 VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp);
1935
1936 /* Upper 8-bits. */
1937 tmp = (addr >> 8) & 0xff;
1938 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1939 VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp);
1940 }
1941
chipio_8051_set_data(struct hda_codec * codec,unsigned int data)1942 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data)
1943 {
1944 /* 8-bits of data. */
1945 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1946 VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff);
1947 }
1948
chipio_8051_get_data(struct hda_codec * codec)1949 static unsigned int chipio_8051_get_data(struct hda_codec *codec)
1950 {
1951 return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1952 VENDOR_CHIPIO_8051_DATA_READ, 0);
1953 }
1954
1955 /* PLL_PMU writes share the lower address register of the 8051 exram writes. */
chipio_8051_set_data_pll(struct hda_codec * codec,unsigned int data)1956 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data)
1957 {
1958 /* 8-bits of data. */
1959 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1960 VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff);
1961 }
1962
chipio_8051_write_exram(struct hda_codec * codec,unsigned int addr,unsigned int data)1963 static void chipio_8051_write_exram(struct hda_codec *codec,
1964 unsigned int addr, unsigned int data)
1965 {
1966 struct ca0132_spec *spec = codec->spec;
1967
1968 mutex_lock(&spec->chipio_mutex);
1969
1970 chipio_8051_set_address(codec, addr);
1971 chipio_8051_set_data(codec, data);
1972
1973 mutex_unlock(&spec->chipio_mutex);
1974 }
1975
chipio_8051_write_exram_no_mutex(struct hda_codec * codec,unsigned int addr,unsigned int data)1976 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec,
1977 unsigned int addr, unsigned int data)
1978 {
1979 chipio_8051_set_address(codec, addr);
1980 chipio_8051_set_data(codec, data);
1981 }
1982
1983 /* Readback data from the 8051's exram. No mutex. */
chipio_8051_read_exram(struct hda_codec * codec,unsigned int addr,unsigned int * data)1984 static void chipio_8051_read_exram(struct hda_codec *codec,
1985 unsigned int addr, unsigned int *data)
1986 {
1987 chipio_8051_set_address(codec, addr);
1988 *data = chipio_8051_get_data(codec);
1989 }
1990
chipio_8051_write_pll_pmu(struct hda_codec * codec,unsigned int addr,unsigned int data)1991 static void chipio_8051_write_pll_pmu(struct hda_codec *codec,
1992 unsigned int addr, unsigned int data)
1993 {
1994 struct ca0132_spec *spec = codec->spec;
1995
1996 mutex_lock(&spec->chipio_mutex);
1997
1998 chipio_8051_set_address(codec, addr & 0xff);
1999 chipio_8051_set_data_pll(codec, data);
2000
2001 mutex_unlock(&spec->chipio_mutex);
2002 }
2003
chipio_8051_write_pll_pmu_no_mutex(struct hda_codec * codec,unsigned int addr,unsigned int data)2004 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec,
2005 unsigned int addr, unsigned int data)
2006 {
2007 chipio_8051_set_address(codec, addr & 0xff);
2008 chipio_8051_set_data_pll(codec, data);
2009 }
2010
2011 /*
2012 * Enable clocks.
2013 */
chipio_enable_clocks(struct hda_codec * codec)2014 static void chipio_enable_clocks(struct hda_codec *codec)
2015 {
2016 struct ca0132_spec *spec = codec->spec;
2017
2018 mutex_lock(&spec->chipio_mutex);
2019
2020 chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff);
2021 chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b);
2022 chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff);
2023
2024 mutex_unlock(&spec->chipio_mutex);
2025 }
2026
2027 /*
2028 * CA0132 DSP IO stuffs
2029 */
dspio_send(struct hda_codec * codec,unsigned int reg,unsigned int data)2030 static int dspio_send(struct hda_codec *codec, unsigned int reg,
2031 unsigned int data)
2032 {
2033 int res;
2034 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2035
2036 /* send bits of data specified by reg to dsp */
2037 do {
2038 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
2039 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
2040 return res;
2041 msleep(20);
2042 } while (time_before(jiffies, timeout));
2043
2044 return -EIO;
2045 }
2046
2047 /*
2048 * Wait for DSP to be ready for commands
2049 */
dspio_write_wait(struct hda_codec * codec)2050 static void dspio_write_wait(struct hda_codec *codec)
2051 {
2052 int status;
2053 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2054
2055 do {
2056 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2057 VENDOR_DSPIO_STATUS, 0);
2058 if ((status == VENDOR_STATUS_DSPIO_OK) ||
2059 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
2060 break;
2061 msleep(1);
2062 } while (time_before(jiffies, timeout));
2063 }
2064
2065 /*
2066 * Write SCP data to DSP
2067 */
dspio_write(struct hda_codec * codec,unsigned int scp_data)2068 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
2069 {
2070 struct ca0132_spec *spec = codec->spec;
2071 int status;
2072
2073 dspio_write_wait(codec);
2074
2075 mutex_lock(&spec->chipio_mutex);
2076 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
2077 scp_data & 0xffff);
2078 if (status < 0)
2079 goto error;
2080
2081 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
2082 scp_data >> 16);
2083 if (status < 0)
2084 goto error;
2085
2086 /* OK, now check if the write itself has executed*/
2087 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2088 VENDOR_DSPIO_STATUS, 0);
2089 error:
2090 mutex_unlock(&spec->chipio_mutex);
2091
2092 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
2093 -EIO : 0;
2094 }
2095
2096 /*
2097 * Write multiple SCP data to DSP
2098 */
dspio_write_multiple(struct hda_codec * codec,unsigned int * buffer,unsigned int size)2099 static int dspio_write_multiple(struct hda_codec *codec,
2100 unsigned int *buffer, unsigned int size)
2101 {
2102 int status = 0;
2103 unsigned int count;
2104
2105 if (buffer == NULL)
2106 return -EINVAL;
2107
2108 count = 0;
2109 while (count < size) {
2110 status = dspio_write(codec, *buffer++);
2111 if (status != 0)
2112 break;
2113 count++;
2114 }
2115
2116 return status;
2117 }
2118
dspio_read(struct hda_codec * codec,unsigned int * data)2119 static int dspio_read(struct hda_codec *codec, unsigned int *data)
2120 {
2121 int status;
2122
2123 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
2124 if (status == -EIO)
2125 return status;
2126
2127 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
2128 if (status == -EIO ||
2129 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
2130 return -EIO;
2131
2132 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2133 VENDOR_DSPIO_SCP_READ_DATA, 0);
2134
2135 return 0;
2136 }
2137
dspio_read_multiple(struct hda_codec * codec,unsigned int * buffer,unsigned int * buf_size,unsigned int size_count)2138 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
2139 unsigned int *buf_size, unsigned int size_count)
2140 {
2141 int status = 0;
2142 unsigned int size = *buf_size;
2143 unsigned int count;
2144 unsigned int skip_count;
2145 unsigned int dummy;
2146
2147 if (buffer == NULL)
2148 return -1;
2149
2150 count = 0;
2151 while (count < size && count < size_count) {
2152 status = dspio_read(codec, buffer++);
2153 if (status != 0)
2154 break;
2155 count++;
2156 }
2157
2158 skip_count = count;
2159 if (status == 0) {
2160 while (skip_count < size) {
2161 status = dspio_read(codec, &dummy);
2162 if (status != 0)
2163 break;
2164 skip_count++;
2165 }
2166 }
2167 *buf_size = count;
2168
2169 return status;
2170 }
2171
2172 /*
2173 * Construct the SCP header using corresponding fields
2174 */
2175 static inline unsigned int
make_scp_header(unsigned int target_id,unsigned int source_id,unsigned int get_flag,unsigned int req,unsigned int device_flag,unsigned int resp_flag,unsigned int error_flag,unsigned int data_size)2176 make_scp_header(unsigned int target_id, unsigned int source_id,
2177 unsigned int get_flag, unsigned int req,
2178 unsigned int device_flag, unsigned int resp_flag,
2179 unsigned int error_flag, unsigned int data_size)
2180 {
2181 unsigned int header = 0;
2182
2183 header = (data_size & 0x1f) << 27;
2184 header |= (error_flag & 0x01) << 26;
2185 header |= (resp_flag & 0x01) << 25;
2186 header |= (device_flag & 0x01) << 24;
2187 header |= (req & 0x7f) << 17;
2188 header |= (get_flag & 0x01) << 16;
2189 header |= (source_id & 0xff) << 8;
2190 header |= target_id & 0xff;
2191
2192 return header;
2193 }
2194
2195 /*
2196 * Extract corresponding fields from SCP header
2197 */
2198 static inline void
extract_scp_header(unsigned int header,unsigned int * target_id,unsigned int * source_id,unsigned int * get_flag,unsigned int * req,unsigned int * device_flag,unsigned int * resp_flag,unsigned int * error_flag,unsigned int * data_size)2199 extract_scp_header(unsigned int header,
2200 unsigned int *target_id, unsigned int *source_id,
2201 unsigned int *get_flag, unsigned int *req,
2202 unsigned int *device_flag, unsigned int *resp_flag,
2203 unsigned int *error_flag, unsigned int *data_size)
2204 {
2205 if (data_size)
2206 *data_size = (header >> 27) & 0x1f;
2207 if (error_flag)
2208 *error_flag = (header >> 26) & 0x01;
2209 if (resp_flag)
2210 *resp_flag = (header >> 25) & 0x01;
2211 if (device_flag)
2212 *device_flag = (header >> 24) & 0x01;
2213 if (req)
2214 *req = (header >> 17) & 0x7f;
2215 if (get_flag)
2216 *get_flag = (header >> 16) & 0x01;
2217 if (source_id)
2218 *source_id = (header >> 8) & 0xff;
2219 if (target_id)
2220 *target_id = header & 0xff;
2221 }
2222
2223 #define SCP_MAX_DATA_WORDS (16)
2224
2225 /* Structure to contain any SCP message */
2226 struct scp_msg {
2227 unsigned int hdr;
2228 unsigned int data[SCP_MAX_DATA_WORDS];
2229 };
2230
dspio_clear_response_queue(struct hda_codec * codec)2231 static void dspio_clear_response_queue(struct hda_codec *codec)
2232 {
2233 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2234 unsigned int dummy = 0;
2235 int status;
2236
2237 /* clear all from the response queue */
2238 do {
2239 status = dspio_read(codec, &dummy);
2240 } while (status == 0 && time_before(jiffies, timeout));
2241 }
2242
dspio_get_response_data(struct hda_codec * codec)2243 static int dspio_get_response_data(struct hda_codec *codec)
2244 {
2245 struct ca0132_spec *spec = codec->spec;
2246 unsigned int data = 0;
2247 unsigned int count;
2248
2249 if (dspio_read(codec, &data) < 0)
2250 return -EIO;
2251
2252 if ((data & 0x00ffffff) == spec->wait_scp_header) {
2253 spec->scp_resp_header = data;
2254 spec->scp_resp_count = data >> 27;
2255 count = spec->wait_num_data;
2256 dspio_read_multiple(codec, spec->scp_resp_data,
2257 &spec->scp_resp_count, count);
2258 return 0;
2259 }
2260
2261 return -EIO;
2262 }
2263
2264 /*
2265 * Send SCP message to DSP
2266 */
dspio_send_scp_message(struct hda_codec * codec,unsigned char * send_buf,unsigned int send_buf_size,unsigned char * return_buf,unsigned int return_buf_size,unsigned int * bytes_returned)2267 static int dspio_send_scp_message(struct hda_codec *codec,
2268 unsigned char *send_buf,
2269 unsigned int send_buf_size,
2270 unsigned char *return_buf,
2271 unsigned int return_buf_size,
2272 unsigned int *bytes_returned)
2273 {
2274 struct ca0132_spec *spec = codec->spec;
2275 int status;
2276 unsigned int scp_send_size = 0;
2277 unsigned int total_size;
2278 bool waiting_for_resp = false;
2279 unsigned int header;
2280 struct scp_msg *ret_msg;
2281 unsigned int resp_src_id, resp_target_id;
2282 unsigned int data_size, src_id, target_id, get_flag, device_flag;
2283
2284 if (bytes_returned)
2285 *bytes_returned = 0;
2286
2287 /* get scp header from buffer */
2288 header = *((unsigned int *)send_buf);
2289 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
2290 &device_flag, NULL, NULL, &data_size);
2291 scp_send_size = data_size + 1;
2292 total_size = (scp_send_size * 4);
2293
2294 if (send_buf_size < total_size)
2295 return -EINVAL;
2296
2297 if (get_flag || device_flag) {
2298 if (!return_buf || return_buf_size < 4 || !bytes_returned)
2299 return -EINVAL;
2300
2301 spec->wait_scp_header = *((unsigned int *)send_buf);
2302
2303 /* swap source id with target id */
2304 resp_target_id = src_id;
2305 resp_src_id = target_id;
2306 spec->wait_scp_header &= 0xffff0000;
2307 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
2308 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
2309 spec->wait_scp = 1;
2310 waiting_for_resp = true;
2311 }
2312
2313 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
2314 scp_send_size);
2315 if (status < 0) {
2316 spec->wait_scp = 0;
2317 return status;
2318 }
2319
2320 if (waiting_for_resp) {
2321 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2322 memset(return_buf, 0, return_buf_size);
2323 do {
2324 msleep(20);
2325 } while (spec->wait_scp && time_before(jiffies, timeout));
2326 waiting_for_resp = false;
2327 if (!spec->wait_scp) {
2328 ret_msg = (struct scp_msg *)return_buf;
2329 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
2330 memcpy(&ret_msg->data, spec->scp_resp_data,
2331 spec->wait_num_data);
2332 *bytes_returned = (spec->scp_resp_count + 1) * 4;
2333 status = 0;
2334 } else {
2335 status = -EIO;
2336 }
2337 spec->wait_scp = 0;
2338 }
2339
2340 return status;
2341 }
2342
2343 /**
2344 * dspio_scp - Prepare and send the SCP message to DSP
2345 * @codec: the HDA codec
2346 * @mod_id: ID of the DSP module to send the command
2347 * @src_id: ID of the source
2348 * @req: ID of request to send to the DSP module
2349 * @dir: SET or GET
2350 * @data: pointer to the data to send with the request, request specific
2351 * @len: length of the data, in bytes
2352 * @reply: point to the buffer to hold data returned for a reply
2353 * @reply_len: length of the reply buffer returned from GET
2354 *
2355 * Returns zero or a negative error code.
2356 */
dspio_scp(struct hda_codec * codec,int mod_id,int src_id,int req,int dir,const void * data,unsigned int len,void * reply,unsigned int * reply_len)2357 static int dspio_scp(struct hda_codec *codec,
2358 int mod_id, int src_id, int req, int dir, const void *data,
2359 unsigned int len, void *reply, unsigned int *reply_len)
2360 {
2361 int status = 0;
2362 struct scp_msg scp_send, scp_reply;
2363 unsigned int ret_bytes, send_size, ret_size;
2364 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
2365 unsigned int reply_data_size;
2366
2367 memset(&scp_send, 0, sizeof(scp_send));
2368 memset(&scp_reply, 0, sizeof(scp_reply));
2369
2370 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
2371 return -EINVAL;
2372
2373 if (dir == SCP_GET && reply == NULL) {
2374 codec_dbg(codec, "dspio_scp get but has no buffer\n");
2375 return -EINVAL;
2376 }
2377
2378 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
2379 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
2380 return -EINVAL;
2381 }
2382
2383 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
2384 0, 0, 0, len/sizeof(unsigned int));
2385 if (data != NULL && len > 0) {
2386 len = min((unsigned int)(sizeof(scp_send.data)), len);
2387 memcpy(scp_send.data, data, len);
2388 }
2389
2390 ret_bytes = 0;
2391 send_size = sizeof(unsigned int) + len;
2392 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
2393 send_size, (unsigned char *)&scp_reply,
2394 sizeof(scp_reply), &ret_bytes);
2395
2396 if (status < 0) {
2397 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
2398 return status;
2399 }
2400
2401 /* extract send and reply headers members */
2402 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
2403 NULL, NULL, NULL, NULL, NULL);
2404 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
2405 &reply_resp_flag, &reply_error_flag,
2406 &reply_data_size);
2407
2408 if (!send_get_flag)
2409 return 0;
2410
2411 if (reply_resp_flag && !reply_error_flag) {
2412 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
2413 / sizeof(unsigned int);
2414
2415 if (*reply_len < ret_size*sizeof(unsigned int)) {
2416 codec_dbg(codec, "reply too long for buf\n");
2417 return -EINVAL;
2418 } else if (ret_size != reply_data_size) {
2419 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
2420 return -EINVAL;
2421 } else if (!reply) {
2422 codec_dbg(codec, "NULL reply\n");
2423 return -EINVAL;
2424 } else {
2425 *reply_len = ret_size*sizeof(unsigned int);
2426 memcpy(reply, scp_reply.data, *reply_len);
2427 }
2428 } else {
2429 codec_dbg(codec, "reply ill-formed or errflag set\n");
2430 return -EIO;
2431 }
2432
2433 return status;
2434 }
2435
2436 /*
2437 * Set DSP parameters
2438 */
dspio_set_param(struct hda_codec * codec,int mod_id,int src_id,int req,const void * data,unsigned int len)2439 static int dspio_set_param(struct hda_codec *codec, int mod_id,
2440 int src_id, int req, const void *data, unsigned int len)
2441 {
2442 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2443 NULL);
2444 }
2445
dspio_set_uint_param(struct hda_codec * codec,int mod_id,int req,const unsigned int data)2446 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
2447 int req, const unsigned int data)
2448 {
2449 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2450 sizeof(unsigned int));
2451 }
2452
2453 /*
2454 * Allocate a DSP DMA channel via an SCP message
2455 */
dspio_alloc_dma_chan(struct hda_codec * codec,unsigned int * dma_chan)2456 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2457 {
2458 int status = 0;
2459 unsigned int size = sizeof(*dma_chan);
2460
2461 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
2462 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2463 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2464 dma_chan, &size);
2465
2466 if (status < 0) {
2467 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
2468 return status;
2469 }
2470
2471 if ((*dma_chan + 1) == 0) {
2472 codec_dbg(codec, "no free dma channels to allocate\n");
2473 return -EBUSY;
2474 }
2475
2476 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2477 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
2478
2479 return status;
2480 }
2481
2482 /*
2483 * Free a DSP DMA via an SCP message
2484 */
dspio_free_dma_chan(struct hda_codec * codec,unsigned int dma_chan)2485 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2486 {
2487 int status = 0;
2488 unsigned int dummy = 0;
2489
2490 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2491 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
2492
2493 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2494 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2495 sizeof(dma_chan), NULL, &dummy);
2496
2497 if (status < 0) {
2498 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
2499 return status;
2500 }
2501
2502 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
2503
2504 return status;
2505 }
2506
2507 /*
2508 * (Re)start the DSP
2509 */
dsp_set_run_state(struct hda_codec * codec)2510 static int dsp_set_run_state(struct hda_codec *codec)
2511 {
2512 unsigned int dbg_ctrl_reg;
2513 unsigned int halt_state;
2514 int err;
2515
2516 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2517 if (err < 0)
2518 return err;
2519
2520 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2521 DSP_DBGCNTL_STATE_LOBIT;
2522
2523 if (halt_state != 0) {
2524 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2525 DSP_DBGCNTL_SS_MASK);
2526 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2527 dbg_ctrl_reg);
2528 if (err < 0)
2529 return err;
2530
2531 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2532 DSP_DBGCNTL_EXEC_MASK;
2533 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2534 dbg_ctrl_reg);
2535 if (err < 0)
2536 return err;
2537 }
2538
2539 return 0;
2540 }
2541
2542 /*
2543 * Reset the DSP
2544 */
dsp_reset(struct hda_codec * codec)2545 static int dsp_reset(struct hda_codec *codec)
2546 {
2547 unsigned int res;
2548 int retry = 20;
2549
2550 codec_dbg(codec, "dsp_reset\n");
2551 do {
2552 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2553 retry--;
2554 } while (res == -EIO && retry);
2555
2556 if (!retry) {
2557 codec_dbg(codec, "dsp_reset timeout\n");
2558 return -EIO;
2559 }
2560
2561 return 0;
2562 }
2563
2564 /*
2565 * Convert chip address to DSP address
2566 */
dsp_chip_to_dsp_addx(unsigned int chip_addx,bool * code,bool * yram)2567 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2568 bool *code, bool *yram)
2569 {
2570 *code = *yram = false;
2571
2572 if (UC_RANGE(chip_addx, 1)) {
2573 *code = true;
2574 return UC_OFF(chip_addx);
2575 } else if (X_RANGE_ALL(chip_addx, 1)) {
2576 return X_OFF(chip_addx);
2577 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2578 *yram = true;
2579 return Y_OFF(chip_addx);
2580 }
2581
2582 return INVALID_CHIP_ADDRESS;
2583 }
2584
2585 /*
2586 * Check if the DSP DMA is active
2587 */
dsp_is_dma_active(struct hda_codec * codec,unsigned int dma_chan)2588 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2589 {
2590 unsigned int dma_chnlstart_reg;
2591
2592 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2593
2594 return ((dma_chnlstart_reg & (1 <<
2595 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2596 }
2597
dsp_dma_setup_common(struct hda_codec * codec,unsigned int chip_addx,unsigned int dma_chan,unsigned int port_map_mask,bool ovly)2598 static int dsp_dma_setup_common(struct hda_codec *codec,
2599 unsigned int chip_addx,
2600 unsigned int dma_chan,
2601 unsigned int port_map_mask,
2602 bool ovly)
2603 {
2604 int status = 0;
2605 unsigned int chnl_prop;
2606 unsigned int dsp_addx;
2607 unsigned int active;
2608 bool code, yram;
2609
2610 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2611
2612 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2613 codec_dbg(codec, "dma chan num invalid\n");
2614 return -EINVAL;
2615 }
2616
2617 if (dsp_is_dma_active(codec, dma_chan)) {
2618 codec_dbg(codec, "dma already active\n");
2619 return -EBUSY;
2620 }
2621
2622 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2623
2624 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2625 codec_dbg(codec, "invalid chip addr\n");
2626 return -ENXIO;
2627 }
2628
2629 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2630 active = 0;
2631
2632 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
2633
2634 if (ovly) {
2635 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2636 &chnl_prop);
2637
2638 if (status < 0) {
2639 codec_dbg(codec, "read CHNLPROP Reg fail\n");
2640 return status;
2641 }
2642 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2643 }
2644
2645 if (!code)
2646 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2647 else
2648 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2649
2650 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2651
2652 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2653 if (status < 0) {
2654 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2655 return status;
2656 }
2657 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
2658
2659 if (ovly) {
2660 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2661 &active);
2662
2663 if (status < 0) {
2664 codec_dbg(codec, "read ACTIVE Reg fail\n");
2665 return status;
2666 }
2667 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2668 }
2669
2670 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2671 DSPDMAC_ACTIVE_AAR_MASK;
2672
2673 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2674 if (status < 0) {
2675 codec_dbg(codec, "write ACTIVE Reg fail\n");
2676 return status;
2677 }
2678
2679 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
2680
2681 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2682 port_map_mask);
2683 if (status < 0) {
2684 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2685 return status;
2686 }
2687 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
2688
2689 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2690 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2691 if (status < 0) {
2692 codec_dbg(codec, "write IRQCNT Reg fail\n");
2693 return status;
2694 }
2695 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
2696
2697 codec_dbg(codec,
2698 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2699 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2700 chip_addx, dsp_addx, dma_chan,
2701 port_map_mask, chnl_prop, active);
2702
2703 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2704
2705 return 0;
2706 }
2707
2708 /*
2709 * Setup the DSP DMA per-transfer-specific registers
2710 */
dsp_dma_setup(struct hda_codec * codec,unsigned int chip_addx,unsigned int count,unsigned int dma_chan)2711 static int dsp_dma_setup(struct hda_codec *codec,
2712 unsigned int chip_addx,
2713 unsigned int count,
2714 unsigned int dma_chan)
2715 {
2716 int status = 0;
2717 bool code, yram;
2718 unsigned int dsp_addx;
2719 unsigned int addr_field;
2720 unsigned int incr_field;
2721 unsigned int base_cnt;
2722 unsigned int cur_cnt;
2723 unsigned int dma_cfg = 0;
2724 unsigned int adr_ofs = 0;
2725 unsigned int xfr_cnt = 0;
2726 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2727 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2728
2729 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2730
2731 if (count > max_dma_count) {
2732 codec_dbg(codec, "count too big\n");
2733 return -EINVAL;
2734 }
2735
2736 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2737 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2738 codec_dbg(codec, "invalid chip addr\n");
2739 return -ENXIO;
2740 }
2741
2742 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
2743
2744 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2745 incr_field = 0;
2746
2747 if (!code) {
2748 addr_field <<= 1;
2749 if (yram)
2750 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2751
2752 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2753 }
2754
2755 dma_cfg = addr_field + incr_field;
2756 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2757 dma_cfg);
2758 if (status < 0) {
2759 codec_dbg(codec, "write DMACFG Reg fail\n");
2760 return status;
2761 }
2762 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
2763
2764 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2765 (code ? 0 : 1));
2766
2767 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2768 adr_ofs);
2769 if (status < 0) {
2770 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2771 return status;
2772 }
2773 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
2774
2775 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2776
2777 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2778
2779 xfr_cnt = base_cnt | cur_cnt;
2780
2781 status = chipio_write(codec,
2782 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2783 if (status < 0) {
2784 codec_dbg(codec, "write XFRCNT Reg fail\n");
2785 return status;
2786 }
2787 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
2788
2789 codec_dbg(codec,
2790 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2791 "ADROFS=0x%x, XFRCNT=0x%x\n",
2792 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2793
2794 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2795
2796 return 0;
2797 }
2798
2799 /*
2800 * Start the DSP DMA
2801 */
dsp_dma_start(struct hda_codec * codec,unsigned int dma_chan,bool ovly)2802 static int dsp_dma_start(struct hda_codec *codec,
2803 unsigned int dma_chan, bool ovly)
2804 {
2805 unsigned int reg = 0;
2806 int status = 0;
2807
2808 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2809
2810 if (ovly) {
2811 status = chipio_read(codec,
2812 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
2813
2814 if (status < 0) {
2815 codec_dbg(codec, "read CHNLSTART reg fail\n");
2816 return status;
2817 }
2818 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
2819
2820 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2821 DSPDMAC_CHNLSTART_DIS_MASK);
2822 }
2823
2824 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2825 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2826 if (status < 0) {
2827 codec_dbg(codec, "write CHNLSTART reg fail\n");
2828 return status;
2829 }
2830 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2831
2832 return status;
2833 }
2834
2835 /*
2836 * Stop the DSP DMA
2837 */
dsp_dma_stop(struct hda_codec * codec,unsigned int dma_chan,bool ovly)2838 static int dsp_dma_stop(struct hda_codec *codec,
2839 unsigned int dma_chan, bool ovly)
2840 {
2841 unsigned int reg = 0;
2842 int status = 0;
2843
2844 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2845
2846 if (ovly) {
2847 status = chipio_read(codec,
2848 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
2849
2850 if (status < 0) {
2851 codec_dbg(codec, "read CHNLSTART reg fail\n");
2852 return status;
2853 }
2854 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
2855 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2856 DSPDMAC_CHNLSTART_DIS_MASK);
2857 }
2858
2859 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2860 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2861 if (status < 0) {
2862 codec_dbg(codec, "write CHNLSTART reg fail\n");
2863 return status;
2864 }
2865 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2866
2867 return status;
2868 }
2869
2870 /**
2871 * dsp_allocate_router_ports - Allocate router ports
2872 *
2873 * @codec: the HDA codec
2874 * @num_chans: number of channels in the stream
2875 * @ports_per_channel: number of ports per channel
2876 * @start_device: start device
2877 * @port_map: pointer to the port list to hold the allocated ports
2878 *
2879 * Returns zero or a negative error code.
2880 */
dsp_allocate_router_ports(struct hda_codec * codec,unsigned int num_chans,unsigned int ports_per_channel,unsigned int start_device,unsigned int * port_map)2881 static int dsp_allocate_router_ports(struct hda_codec *codec,
2882 unsigned int num_chans,
2883 unsigned int ports_per_channel,
2884 unsigned int start_device,
2885 unsigned int *port_map)
2886 {
2887 int status = 0;
2888 int res;
2889 u8 val;
2890
2891 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2892 if (status < 0)
2893 return status;
2894
2895 val = start_device << 6;
2896 val |= (ports_per_channel - 1) << 4;
2897 val |= num_chans - 1;
2898
2899 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2900 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2901 val);
2902
2903 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2904 VENDOR_CHIPIO_PORT_ALLOC_SET,
2905 MEM_CONNID_DSP);
2906
2907 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2908 if (status < 0)
2909 return status;
2910
2911 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2912 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2913
2914 *port_map = res;
2915
2916 return (res < 0) ? res : 0;
2917 }
2918
2919 /*
2920 * Free router ports
2921 */
dsp_free_router_ports(struct hda_codec * codec)2922 static int dsp_free_router_ports(struct hda_codec *codec)
2923 {
2924 int status = 0;
2925
2926 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2927 if (status < 0)
2928 return status;
2929
2930 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2931 VENDOR_CHIPIO_PORT_FREE_SET,
2932 MEM_CONNID_DSP);
2933
2934 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2935
2936 return status;
2937 }
2938
2939 /*
2940 * Allocate DSP ports for the download stream
2941 */
dsp_allocate_ports(struct hda_codec * codec,unsigned int num_chans,unsigned int rate_multi,unsigned int * port_map)2942 static int dsp_allocate_ports(struct hda_codec *codec,
2943 unsigned int num_chans,
2944 unsigned int rate_multi, unsigned int *port_map)
2945 {
2946 int status;
2947
2948 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
2949
2950 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2951 codec_dbg(codec, "bad rate multiple\n");
2952 return -EINVAL;
2953 }
2954
2955 status = dsp_allocate_router_ports(codec, num_chans,
2956 rate_multi, 0, port_map);
2957
2958 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
2959
2960 return status;
2961 }
2962
dsp_allocate_ports_format(struct hda_codec * codec,const unsigned short fmt,unsigned int * port_map)2963 static int dsp_allocate_ports_format(struct hda_codec *codec,
2964 const unsigned short fmt,
2965 unsigned int *port_map)
2966 {
2967 int status;
2968 unsigned int num_chans;
2969
2970 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2971 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2972 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2973
2974 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2975 codec_dbg(codec, "bad rate multiple\n");
2976 return -EINVAL;
2977 }
2978
2979 num_chans = get_hdafmt_chs(fmt) + 1;
2980
2981 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2982
2983 return status;
2984 }
2985
2986 /*
2987 * free DSP ports
2988 */
dsp_free_ports(struct hda_codec * codec)2989 static int dsp_free_ports(struct hda_codec *codec)
2990 {
2991 int status;
2992
2993 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2994
2995 status = dsp_free_router_ports(codec);
2996 if (status < 0) {
2997 codec_dbg(codec, "free router ports fail\n");
2998 return status;
2999 }
3000 codec_dbg(codec, " dsp_free_ports() -- complete\n");
3001
3002 return status;
3003 }
3004
3005 /*
3006 * HDA DMA engine stuffs for DSP code download
3007 */
3008 struct dma_engine {
3009 struct hda_codec *codec;
3010 unsigned short m_converter_format;
3011 struct snd_dma_buffer *dmab;
3012 unsigned int buf_size;
3013 };
3014
3015
3016 enum dma_state {
3017 DMA_STATE_STOP = 0,
3018 DMA_STATE_RUN = 1
3019 };
3020
dma_convert_to_hda_format(struct hda_codec * codec,unsigned int sample_rate,unsigned short channels,unsigned short * hda_format)3021 static int dma_convert_to_hda_format(struct hda_codec *codec,
3022 unsigned int sample_rate,
3023 unsigned short channels,
3024 unsigned short *hda_format)
3025 {
3026 unsigned int format_val;
3027
3028 format_val = snd_hdac_calc_stream_format(sample_rate,
3029 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
3030
3031 if (hda_format)
3032 *hda_format = (unsigned short)format_val;
3033
3034 return 0;
3035 }
3036
3037 /*
3038 * Reset DMA for DSP download
3039 */
dma_reset(struct dma_engine * dma)3040 static int dma_reset(struct dma_engine *dma)
3041 {
3042 struct hda_codec *codec = dma->codec;
3043 struct ca0132_spec *spec = codec->spec;
3044 int status;
3045
3046 if (dma->dmab->area)
3047 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
3048
3049 status = snd_hda_codec_load_dsp_prepare(codec,
3050 dma->m_converter_format,
3051 dma->buf_size,
3052 dma->dmab);
3053 if (status < 0)
3054 return status;
3055 spec->dsp_stream_id = status;
3056 return 0;
3057 }
3058
dma_set_state(struct dma_engine * dma,enum dma_state state)3059 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
3060 {
3061 bool cmd;
3062
3063 switch (state) {
3064 case DMA_STATE_STOP:
3065 cmd = false;
3066 break;
3067 case DMA_STATE_RUN:
3068 cmd = true;
3069 break;
3070 default:
3071 return 0;
3072 }
3073
3074 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
3075 return 0;
3076 }
3077
dma_get_buffer_size(struct dma_engine * dma)3078 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
3079 {
3080 return dma->dmab->bytes;
3081 }
3082
dma_get_buffer_addr(struct dma_engine * dma)3083 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
3084 {
3085 return dma->dmab->area;
3086 }
3087
dma_xfer(struct dma_engine * dma,const unsigned int * data,unsigned int count)3088 static int dma_xfer(struct dma_engine *dma,
3089 const unsigned int *data,
3090 unsigned int count)
3091 {
3092 memcpy(dma->dmab->area, data, count);
3093 return 0;
3094 }
3095
dma_get_converter_format(struct dma_engine * dma,unsigned short * format)3096 static void dma_get_converter_format(
3097 struct dma_engine *dma,
3098 unsigned short *format)
3099 {
3100 if (format)
3101 *format = dma->m_converter_format;
3102 }
3103
dma_get_stream_id(struct dma_engine * dma)3104 static unsigned int dma_get_stream_id(struct dma_engine *dma)
3105 {
3106 struct ca0132_spec *spec = dma->codec->spec;
3107
3108 return spec->dsp_stream_id;
3109 }
3110
3111 struct dsp_image_seg {
3112 u32 magic;
3113 u32 chip_addr;
3114 u32 count;
3115 u32 data[];
3116 };
3117
3118 static const u32 g_magic_value = 0x4c46584d;
3119 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
3120
is_valid(const struct dsp_image_seg * p)3121 static bool is_valid(const struct dsp_image_seg *p)
3122 {
3123 return p->magic == g_magic_value;
3124 }
3125
is_hci_prog_list_seg(const struct dsp_image_seg * p)3126 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
3127 {
3128 return g_chip_addr_magic_value == p->chip_addr;
3129 }
3130
is_last(const struct dsp_image_seg * p)3131 static bool is_last(const struct dsp_image_seg *p)
3132 {
3133 return p->count == 0;
3134 }
3135
dsp_sizeof(const struct dsp_image_seg * p)3136 static size_t dsp_sizeof(const struct dsp_image_seg *p)
3137 {
3138 return struct_size(p, data, p->count);
3139 }
3140
get_next_seg_ptr(const struct dsp_image_seg * p)3141 static const struct dsp_image_seg *get_next_seg_ptr(
3142 const struct dsp_image_seg *p)
3143 {
3144 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
3145 }
3146
3147 /*
3148 * CA0132 chip DSP transfer stuffs. For DSP download.
3149 */
3150 #define INVALID_DMA_CHANNEL (~0U)
3151
3152 /*
3153 * Program a list of address/data pairs via the ChipIO widget.
3154 * The segment data is in the format of successive pairs of words.
3155 * These are repeated as indicated by the segment's count field.
3156 */
dspxfr_hci_write(struct hda_codec * codec,const struct dsp_image_seg * fls)3157 static int dspxfr_hci_write(struct hda_codec *codec,
3158 const struct dsp_image_seg *fls)
3159 {
3160 int status;
3161 const u32 *data;
3162 unsigned int count;
3163
3164 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
3165 codec_dbg(codec, "hci_write invalid params\n");
3166 return -EINVAL;
3167 }
3168
3169 count = fls->count;
3170 data = (u32 *)(fls->data);
3171 while (count >= 2) {
3172 status = chipio_write(codec, data[0], data[1]);
3173 if (status < 0) {
3174 codec_dbg(codec, "hci_write chipio failed\n");
3175 return status;
3176 }
3177 count -= 2;
3178 data += 2;
3179 }
3180 return 0;
3181 }
3182
3183 /**
3184 * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine.
3185 *
3186 * @codec: the HDA codec
3187 * @fls: pointer to a fast load image
3188 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3189 * no relocation
3190 * @dma_engine: pointer to DMA engine to be used for DSP download
3191 * @dma_chan: The number of DMA channels used for DSP download
3192 * @port_map_mask: port mapping
3193 * @ovly: TRUE if overlay format is required
3194 *
3195 * Returns zero or a negative error code.
3196 */
dspxfr_one_seg(struct hda_codec * codec,const struct dsp_image_seg * fls,unsigned int reloc,struct dma_engine * dma_engine,unsigned int dma_chan,unsigned int port_map_mask,bool ovly)3197 static int dspxfr_one_seg(struct hda_codec *codec,
3198 const struct dsp_image_seg *fls,
3199 unsigned int reloc,
3200 struct dma_engine *dma_engine,
3201 unsigned int dma_chan,
3202 unsigned int port_map_mask,
3203 bool ovly)
3204 {
3205 int status = 0;
3206 bool comm_dma_setup_done = false;
3207 const unsigned int *data;
3208 unsigned int chip_addx;
3209 unsigned int words_to_write;
3210 unsigned int buffer_size_words;
3211 unsigned char *buffer_addx;
3212 unsigned short hda_format;
3213 unsigned int sample_rate_div;
3214 unsigned int sample_rate_mul;
3215 unsigned int num_chans;
3216 unsigned int hda_frame_size_words;
3217 unsigned int remainder_words;
3218 const u32 *data_remainder;
3219 u32 chip_addx_remainder;
3220 unsigned int run_size_words;
3221 const struct dsp_image_seg *hci_write = NULL;
3222 unsigned long timeout;
3223 bool dma_active;
3224
3225 if (fls == NULL)
3226 return -EINVAL;
3227 if (is_hci_prog_list_seg(fls)) {
3228 hci_write = fls;
3229 fls = get_next_seg_ptr(fls);
3230 }
3231
3232 if (hci_write && (!fls || is_last(fls))) {
3233 codec_dbg(codec, "hci_write\n");
3234 return dspxfr_hci_write(codec, hci_write);
3235 }
3236
3237 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
3238 codec_dbg(codec, "Invalid Params\n");
3239 return -EINVAL;
3240 }
3241
3242 data = fls->data;
3243 chip_addx = fls->chip_addr;
3244 words_to_write = fls->count;
3245
3246 if (!words_to_write)
3247 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
3248 if (reloc)
3249 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
3250
3251 if (!UC_RANGE(chip_addx, words_to_write) &&
3252 !X_RANGE_ALL(chip_addx, words_to_write) &&
3253 !Y_RANGE_ALL(chip_addx, words_to_write)) {
3254 codec_dbg(codec, "Invalid chip_addx Params\n");
3255 return -EINVAL;
3256 }
3257
3258 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
3259 sizeof(u32);
3260
3261 buffer_addx = dma_get_buffer_addr(dma_engine);
3262
3263 if (buffer_addx == NULL) {
3264 codec_dbg(codec, "dma_engine buffer NULL\n");
3265 return -EINVAL;
3266 }
3267
3268 dma_get_converter_format(dma_engine, &hda_format);
3269 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
3270 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
3271 num_chans = get_hdafmt_chs(hda_format) + 1;
3272
3273 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
3274 (num_chans * sample_rate_mul / sample_rate_div));
3275
3276 if (hda_frame_size_words == 0) {
3277 codec_dbg(codec, "frmsz zero\n");
3278 return -EINVAL;
3279 }
3280
3281 buffer_size_words = min(buffer_size_words,
3282 (unsigned int)(UC_RANGE(chip_addx, 1) ?
3283 65536 : 32768));
3284 buffer_size_words -= buffer_size_words % hda_frame_size_words;
3285 codec_dbg(codec,
3286 "chpadr=0x%08x frmsz=%u nchan=%u "
3287 "rate_mul=%u div=%u bufsz=%u\n",
3288 chip_addx, hda_frame_size_words, num_chans,
3289 sample_rate_mul, sample_rate_div, buffer_size_words);
3290
3291 if (buffer_size_words < hda_frame_size_words) {
3292 codec_dbg(codec, "dspxfr_one_seg:failed\n");
3293 return -EINVAL;
3294 }
3295
3296 remainder_words = words_to_write % hda_frame_size_words;
3297 data_remainder = data;
3298 chip_addx_remainder = chip_addx;
3299
3300 data += remainder_words;
3301 chip_addx += remainder_words*sizeof(u32);
3302 words_to_write -= remainder_words;
3303
3304 while (words_to_write != 0) {
3305 run_size_words = min(buffer_size_words, words_to_write);
3306 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
3307 words_to_write, run_size_words, remainder_words);
3308 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
3309 if (!comm_dma_setup_done) {
3310 status = dsp_dma_stop(codec, dma_chan, ovly);
3311 if (status < 0)
3312 return status;
3313 status = dsp_dma_setup_common(codec, chip_addx,
3314 dma_chan, port_map_mask, ovly);
3315 if (status < 0)
3316 return status;
3317 comm_dma_setup_done = true;
3318 }
3319
3320 status = dsp_dma_setup(codec, chip_addx,
3321 run_size_words, dma_chan);
3322 if (status < 0)
3323 return status;
3324 status = dsp_dma_start(codec, dma_chan, ovly);
3325 if (status < 0)
3326 return status;
3327 if (!dsp_is_dma_active(codec, dma_chan)) {
3328 codec_dbg(codec, "dspxfr:DMA did not start\n");
3329 return -EIO;
3330 }
3331 status = dma_set_state(dma_engine, DMA_STATE_RUN);
3332 if (status < 0)
3333 return status;
3334 if (remainder_words != 0) {
3335 status = chipio_write_multiple(codec,
3336 chip_addx_remainder,
3337 data_remainder,
3338 remainder_words);
3339 if (status < 0)
3340 return status;
3341 remainder_words = 0;
3342 }
3343 if (hci_write) {
3344 status = dspxfr_hci_write(codec, hci_write);
3345 if (status < 0)
3346 return status;
3347 hci_write = NULL;
3348 }
3349
3350 timeout = jiffies + msecs_to_jiffies(2000);
3351 do {
3352 dma_active = dsp_is_dma_active(codec, dma_chan);
3353 if (!dma_active)
3354 break;
3355 msleep(20);
3356 } while (time_before(jiffies, timeout));
3357 if (dma_active)
3358 break;
3359
3360 codec_dbg(codec, "+++++ DMA complete\n");
3361 dma_set_state(dma_engine, DMA_STATE_STOP);
3362 status = dma_reset(dma_engine);
3363
3364 if (status < 0)
3365 return status;
3366
3367 data += run_size_words;
3368 chip_addx += run_size_words*sizeof(u32);
3369 words_to_write -= run_size_words;
3370 }
3371
3372 if (remainder_words != 0) {
3373 status = chipio_write_multiple(codec, chip_addx_remainder,
3374 data_remainder, remainder_words);
3375 }
3376
3377 return status;
3378 }
3379
3380 /**
3381 * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories
3382 *
3383 * @codec: the HDA codec
3384 * @fls_data: pointer to a fast load image
3385 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3386 * no relocation
3387 * @sample_rate: sampling rate of the stream used for DSP download
3388 * @channels: channels of the stream used for DSP download
3389 * @ovly: TRUE if overlay format is required
3390 *
3391 * Returns zero or a negative error code.
3392 */
dspxfr_image(struct hda_codec * codec,const struct dsp_image_seg * fls_data,unsigned int reloc,unsigned int sample_rate,unsigned short channels,bool ovly)3393 static int dspxfr_image(struct hda_codec *codec,
3394 const struct dsp_image_seg *fls_data,
3395 unsigned int reloc,
3396 unsigned int sample_rate,
3397 unsigned short channels,
3398 bool ovly)
3399 {
3400 struct ca0132_spec *spec = codec->spec;
3401 int status;
3402 unsigned short hda_format = 0;
3403 unsigned int response;
3404 unsigned char stream_id = 0;
3405 struct dma_engine *dma_engine;
3406 unsigned int dma_chan;
3407 unsigned int port_map_mask;
3408
3409 if (fls_data == NULL)
3410 return -EINVAL;
3411
3412 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
3413 if (!dma_engine)
3414 return -ENOMEM;
3415
3416 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3417 if (!dma_engine->dmab) {
3418 kfree(dma_engine);
3419 return -ENOMEM;
3420 }
3421
3422 dma_engine->codec = codec;
3423 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
3424 dma_engine->m_converter_format = hda_format;
3425 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3426 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3427
3428 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3429
3430 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3431 hda_format, &response);
3432
3433 if (status < 0) {
3434 codec_dbg(codec, "set converter format fail\n");
3435 goto exit;
3436 }
3437
3438 status = snd_hda_codec_load_dsp_prepare(codec,
3439 dma_engine->m_converter_format,
3440 dma_engine->buf_size,
3441 dma_engine->dmab);
3442 if (status < 0)
3443 goto exit;
3444 spec->dsp_stream_id = status;
3445
3446 if (ovly) {
3447 status = dspio_alloc_dma_chan(codec, &dma_chan);
3448 if (status < 0) {
3449 codec_dbg(codec, "alloc dmachan fail\n");
3450 dma_chan = INVALID_DMA_CHANNEL;
3451 goto exit;
3452 }
3453 }
3454
3455 port_map_mask = 0;
3456 status = dsp_allocate_ports_format(codec, hda_format,
3457 &port_map_mask);
3458 if (status < 0) {
3459 codec_dbg(codec, "alloc ports fail\n");
3460 goto exit;
3461 }
3462
3463 stream_id = dma_get_stream_id(dma_engine);
3464 status = codec_set_converter_stream_channel(codec,
3465 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3466 if (status < 0) {
3467 codec_dbg(codec, "set stream chan fail\n");
3468 goto exit;
3469 }
3470
3471 while ((fls_data != NULL) && !is_last(fls_data)) {
3472 if (!is_valid(fls_data)) {
3473 codec_dbg(codec, "FLS check fail\n");
3474 status = -EINVAL;
3475 goto exit;
3476 }
3477 status = dspxfr_one_seg(codec, fls_data, reloc,
3478 dma_engine, dma_chan,
3479 port_map_mask, ovly);
3480 if (status < 0)
3481 break;
3482
3483 if (is_hci_prog_list_seg(fls_data))
3484 fls_data = get_next_seg_ptr(fls_data);
3485
3486 if ((fls_data != NULL) && !is_last(fls_data))
3487 fls_data = get_next_seg_ptr(fls_data);
3488 }
3489
3490 if (port_map_mask != 0)
3491 status = dsp_free_ports(codec);
3492
3493 if (status < 0)
3494 goto exit;
3495
3496 status = codec_set_converter_stream_channel(codec,
3497 WIDGET_CHIP_CTRL, 0, 0, &response);
3498
3499 exit:
3500 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3501 dspio_free_dma_chan(codec, dma_chan);
3502
3503 if (dma_engine->dmab->area)
3504 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3505 kfree(dma_engine->dmab);
3506 kfree(dma_engine);
3507
3508 return status;
3509 }
3510
3511 /*
3512 * CA0132 DSP download stuffs.
3513 */
dspload_post_setup(struct hda_codec * codec)3514 static void dspload_post_setup(struct hda_codec *codec)
3515 {
3516 struct ca0132_spec *spec = codec->spec;
3517 codec_dbg(codec, "---- dspload_post_setup ------\n");
3518 if (!ca0132_use_alt_functions(spec)) {
3519 /*set DSP speaker to 2.0 configuration*/
3520 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3521 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3522
3523 /*update write pointer*/
3524 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3525 }
3526 }
3527
3528 /**
3529 * dspload_image - Download DSP from a DSP Image Fast Load structure.
3530 *
3531 * @codec: the HDA codec
3532 * @fls: pointer to a fast load image
3533 * @ovly: TRUE if overlay format is required
3534 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3535 * no relocation
3536 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3537 * @router_chans: number of audio router channels to be allocated (0 means use
3538 * internal defaults; max is 32)
3539 *
3540 * Download DSP from a DSP Image Fast Load structure. This structure is a
3541 * linear, non-constant sized element array of structures, each of which
3542 * contain the count of the data to be loaded, the data itself, and the
3543 * corresponding starting chip address of the starting data location.
3544 * Returns zero or a negative error code.
3545 */
dspload_image(struct hda_codec * codec,const struct dsp_image_seg * fls,bool ovly,unsigned int reloc,bool autostart,int router_chans)3546 static int dspload_image(struct hda_codec *codec,
3547 const struct dsp_image_seg *fls,
3548 bool ovly,
3549 unsigned int reloc,
3550 bool autostart,
3551 int router_chans)
3552 {
3553 int status = 0;
3554 unsigned int sample_rate;
3555 unsigned short channels;
3556
3557 codec_dbg(codec, "---- dspload_image begin ------\n");
3558 if (router_chans == 0) {
3559 if (!ovly)
3560 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3561 else
3562 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3563 }
3564
3565 sample_rate = 48000;
3566 channels = (unsigned short)router_chans;
3567
3568 while (channels > 16) {
3569 sample_rate *= 2;
3570 channels /= 2;
3571 }
3572
3573 do {
3574 codec_dbg(codec, "Ready to program DMA\n");
3575 if (!ovly)
3576 status = dsp_reset(codec);
3577
3578 if (status < 0)
3579 break;
3580
3581 codec_dbg(codec, "dsp_reset() complete\n");
3582 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3583 ovly);
3584
3585 if (status < 0)
3586 break;
3587
3588 codec_dbg(codec, "dspxfr_image() complete\n");
3589 if (autostart && !ovly) {
3590 dspload_post_setup(codec);
3591 status = dsp_set_run_state(codec);
3592 }
3593
3594 codec_dbg(codec, "LOAD FINISHED\n");
3595 } while (0);
3596
3597 return status;
3598 }
3599
3600 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
dspload_is_loaded(struct hda_codec * codec)3601 static bool dspload_is_loaded(struct hda_codec *codec)
3602 {
3603 unsigned int data = 0;
3604 int status = 0;
3605
3606 status = chipio_read(codec, 0x40004, &data);
3607 if ((status < 0) || (data != 1))
3608 return false;
3609
3610 return true;
3611 }
3612 #else
3613 #define dspload_is_loaded(codec) false
3614 #endif
3615
dspload_wait_loaded(struct hda_codec * codec)3616 static bool dspload_wait_loaded(struct hda_codec *codec)
3617 {
3618 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3619
3620 do {
3621 if (dspload_is_loaded(codec)) {
3622 codec_info(codec, "ca0132 DSP downloaded and running\n");
3623 return true;
3624 }
3625 msleep(20);
3626 } while (time_before(jiffies, timeout));
3627
3628 codec_err(codec, "ca0132 failed to download DSP\n");
3629 return false;
3630 }
3631
3632 /*
3633 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3634 * based cards, and has a second mmio region, region2, that's used for special
3635 * commands.
3636 */
3637
3638 /*
3639 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3640 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3641 * The first eight bits are just the number of the pin. So far, I've only seen
3642 * this number go to 7.
3643 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3644 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3645 * then off to send that bit.
3646 */
ca0113_mmio_gpio_set(struct hda_codec * codec,unsigned int gpio_pin,bool enable)3647 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3648 bool enable)
3649 {
3650 struct ca0132_spec *spec = codec->spec;
3651 unsigned short gpio_data;
3652
3653 gpio_data = gpio_pin & 0xF;
3654 gpio_data |= ((enable << 8) & 0x100);
3655
3656 writew(gpio_data, spec->mem_base + 0x320);
3657 }
3658
3659 /*
3660 * Special pci region2 commands that are only used by the AE-5. They follow
3661 * a set format, and require reads at certain points to seemingly 'clear'
3662 * the response data. My first tests didn't do these reads, and would cause
3663 * the card to get locked up until the memory was read. These commands
3664 * seem to work with three distinct values that I've taken to calling group,
3665 * target-id, and value.
3666 */
ca0113_mmio_command_set(struct hda_codec * codec,unsigned int group,unsigned int target,unsigned int value)3667 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3668 unsigned int target, unsigned int value)
3669 {
3670 struct ca0132_spec *spec = codec->spec;
3671 unsigned int write_val;
3672
3673 writel(0x0000007e, spec->mem_base + 0x210);
3674 readl(spec->mem_base + 0x210);
3675 writel(0x0000005a, spec->mem_base + 0x210);
3676 readl(spec->mem_base + 0x210);
3677 readl(spec->mem_base + 0x210);
3678
3679 writel(0x00800005, spec->mem_base + 0x20c);
3680 writel(group, spec->mem_base + 0x804);
3681
3682 writel(0x00800005, spec->mem_base + 0x20c);
3683 write_val = (target & 0xff);
3684 write_val |= (value << 8);
3685
3686
3687 writel(write_val, spec->mem_base + 0x204);
3688 /*
3689 * Need delay here or else it goes too fast and works inconsistently.
3690 */
3691 msleep(20);
3692
3693 readl(spec->mem_base + 0x860);
3694 readl(spec->mem_base + 0x854);
3695 readl(spec->mem_base + 0x840);
3696
3697 writel(0x00800004, spec->mem_base + 0x20c);
3698 writel(0x00000000, spec->mem_base + 0x210);
3699 readl(spec->mem_base + 0x210);
3700 readl(spec->mem_base + 0x210);
3701 }
3702
3703 /*
3704 * This second type of command is used for setting the sound filter type.
3705 */
ca0113_mmio_command_set_type2(struct hda_codec * codec,unsigned int group,unsigned int target,unsigned int value)3706 static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3707 unsigned int group, unsigned int target, unsigned int value)
3708 {
3709 struct ca0132_spec *spec = codec->spec;
3710 unsigned int write_val;
3711
3712 writel(0x0000007e, spec->mem_base + 0x210);
3713 readl(spec->mem_base + 0x210);
3714 writel(0x0000005a, spec->mem_base + 0x210);
3715 readl(spec->mem_base + 0x210);
3716 readl(spec->mem_base + 0x210);
3717
3718 writel(0x00800003, spec->mem_base + 0x20c);
3719 writel(group, spec->mem_base + 0x804);
3720
3721 writel(0x00800005, spec->mem_base + 0x20c);
3722 write_val = (target & 0xff);
3723 write_val |= (value << 8);
3724
3725
3726 writel(write_val, spec->mem_base + 0x204);
3727 msleep(20);
3728 readl(spec->mem_base + 0x860);
3729 readl(spec->mem_base + 0x854);
3730 readl(spec->mem_base + 0x840);
3731
3732 writel(0x00800004, spec->mem_base + 0x20c);
3733 writel(0x00000000, spec->mem_base + 0x210);
3734 readl(spec->mem_base + 0x210);
3735 readl(spec->mem_base + 0x210);
3736 }
3737
3738 /*
3739 * Setup GPIO for the other variants of Core3D.
3740 */
3741
3742 /*
3743 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3744 * the card shows as having no GPIO pins.
3745 */
ca0132_gpio_init(struct hda_codec * codec)3746 static void ca0132_gpio_init(struct hda_codec *codec)
3747 {
3748 struct ca0132_spec *spec = codec->spec;
3749
3750 switch (ca0132_quirk(spec)) {
3751 case QUIRK_SBZ:
3752 case QUIRK_AE5:
3753 case QUIRK_AE7:
3754 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3755 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3756 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3757 break;
3758 case QUIRK_R3DI:
3759 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3760 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3761 break;
3762 default:
3763 break;
3764 }
3765
3766 }
3767
3768 /* Sets the GPIO for audio output. */
ca0132_gpio_setup(struct hda_codec * codec)3769 static void ca0132_gpio_setup(struct hda_codec *codec)
3770 {
3771 struct ca0132_spec *spec = codec->spec;
3772
3773 switch (ca0132_quirk(spec)) {
3774 case QUIRK_SBZ:
3775 snd_hda_codec_write(codec, 0x01, 0,
3776 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3777 snd_hda_codec_write(codec, 0x01, 0,
3778 AC_VERB_SET_GPIO_MASK, 0x07);
3779 snd_hda_codec_write(codec, 0x01, 0,
3780 AC_VERB_SET_GPIO_DATA, 0x04);
3781 snd_hda_codec_write(codec, 0x01, 0,
3782 AC_VERB_SET_GPIO_DATA, 0x06);
3783 break;
3784 case QUIRK_R3DI:
3785 snd_hda_codec_write(codec, 0x01, 0,
3786 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3787 snd_hda_codec_write(codec, 0x01, 0,
3788 AC_VERB_SET_GPIO_MASK, 0x1F);
3789 snd_hda_codec_write(codec, 0x01, 0,
3790 AC_VERB_SET_GPIO_DATA, 0x0C);
3791 break;
3792 default:
3793 break;
3794 }
3795 }
3796
3797 /*
3798 * GPIO control functions for the Recon3D integrated.
3799 */
3800
3801 enum r3di_gpio_bit {
3802 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3803 R3DI_MIC_SELECT_BIT = 1,
3804 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3805 R3DI_OUT_SELECT_BIT = 2,
3806 /*
3807 * I dunno what this actually does, but it stays on until the dsp
3808 * is downloaded.
3809 */
3810 R3DI_GPIO_DSP_DOWNLOADING = 3,
3811 /*
3812 * Same as above, no clue what it does, but it comes on after the dsp
3813 * is downloaded.
3814 */
3815 R3DI_GPIO_DSP_DOWNLOADED = 4
3816 };
3817
3818 enum r3di_mic_select {
3819 /* Set GPIO bit 1 to 0 for rear mic */
3820 R3DI_REAR_MIC = 0,
3821 /* Set GPIO bit 1 to 1 for front microphone*/
3822 R3DI_FRONT_MIC = 1
3823 };
3824
3825 enum r3di_out_select {
3826 /* Set GPIO bit 2 to 0 for headphone */
3827 R3DI_HEADPHONE_OUT = 0,
3828 /* Set GPIO bit 2 to 1 for speaker */
3829 R3DI_LINE_OUT = 1
3830 };
3831 enum r3di_dsp_status {
3832 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3833 R3DI_DSP_DOWNLOADING = 0,
3834 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3835 R3DI_DSP_DOWNLOADED = 1
3836 };
3837
3838
r3di_gpio_mic_set(struct hda_codec * codec,enum r3di_mic_select cur_mic)3839 static void r3di_gpio_mic_set(struct hda_codec *codec,
3840 enum r3di_mic_select cur_mic)
3841 {
3842 unsigned int cur_gpio;
3843
3844 /* Get the current GPIO Data setup */
3845 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3846
3847 switch (cur_mic) {
3848 case R3DI_REAR_MIC:
3849 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3850 break;
3851 case R3DI_FRONT_MIC:
3852 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3853 break;
3854 }
3855 snd_hda_codec_write(codec, codec->core.afg, 0,
3856 AC_VERB_SET_GPIO_DATA, cur_gpio);
3857 }
3858
r3di_gpio_dsp_status_set(struct hda_codec * codec,enum r3di_dsp_status dsp_status)3859 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3860 enum r3di_dsp_status dsp_status)
3861 {
3862 unsigned int cur_gpio;
3863
3864 /* Get the current GPIO Data setup */
3865 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3866
3867 switch (dsp_status) {
3868 case R3DI_DSP_DOWNLOADING:
3869 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3870 snd_hda_codec_write(codec, codec->core.afg, 0,
3871 AC_VERB_SET_GPIO_DATA, cur_gpio);
3872 break;
3873 case R3DI_DSP_DOWNLOADED:
3874 /* Set DOWNLOADING bit to 0. */
3875 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3876
3877 snd_hda_codec_write(codec, codec->core.afg, 0,
3878 AC_VERB_SET_GPIO_DATA, cur_gpio);
3879
3880 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3881 break;
3882 }
3883
3884 snd_hda_codec_write(codec, codec->core.afg, 0,
3885 AC_VERB_SET_GPIO_DATA, cur_gpio);
3886 }
3887
3888 /*
3889 * PCM callbacks
3890 */
ca0132_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3891 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3892 struct hda_codec *codec,
3893 unsigned int stream_tag,
3894 unsigned int format,
3895 struct snd_pcm_substream *substream)
3896 {
3897 struct ca0132_spec *spec = codec->spec;
3898
3899 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3900
3901 return 0;
3902 }
3903
ca0132_playback_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3904 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3905 struct hda_codec *codec,
3906 struct snd_pcm_substream *substream)
3907 {
3908 struct ca0132_spec *spec = codec->spec;
3909
3910 if (spec->dsp_state == DSP_DOWNLOADING)
3911 return 0;
3912
3913 /*If Playback effects are on, allow stream some time to flush
3914 *effects tail*/
3915 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3916 msleep(50);
3917
3918 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3919
3920 return 0;
3921 }
3922
ca0132_playback_pcm_delay(struct hda_pcm_stream * info,struct hda_codec * codec,struct snd_pcm_substream * substream)3923 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3924 struct hda_codec *codec,
3925 struct snd_pcm_substream *substream)
3926 {
3927 struct ca0132_spec *spec = codec->spec;
3928 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3929 struct snd_pcm_runtime *runtime = substream->runtime;
3930
3931 if (spec->dsp_state != DSP_DOWNLOADED)
3932 return 0;
3933
3934 /* Add latency if playback enhancement and either effect is enabled. */
3935 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3936 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3937 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3938 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3939 }
3940
3941 /* Applying Speaker EQ adds latency as well. */
3942 if (spec->cur_out_type == SPEAKER_OUT)
3943 latency += DSP_SPEAKER_OUT_LATENCY;
3944
3945 return (latency * runtime->rate) / 1000;
3946 }
3947
3948 /*
3949 * Digital out
3950 */
ca0132_dig_playback_pcm_open(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3951 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3952 struct hda_codec *codec,
3953 struct snd_pcm_substream *substream)
3954 {
3955 struct ca0132_spec *spec = codec->spec;
3956 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3957 }
3958
ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3959 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3960 struct hda_codec *codec,
3961 unsigned int stream_tag,
3962 unsigned int format,
3963 struct snd_pcm_substream *substream)
3964 {
3965 struct ca0132_spec *spec = codec->spec;
3966 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3967 stream_tag, format, substream);
3968 }
3969
ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3970 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3971 struct hda_codec *codec,
3972 struct snd_pcm_substream *substream)
3973 {
3974 struct ca0132_spec *spec = codec->spec;
3975 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3976 }
3977
ca0132_dig_playback_pcm_close(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3978 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3979 struct hda_codec *codec,
3980 struct snd_pcm_substream *substream)
3981 {
3982 struct ca0132_spec *spec = codec->spec;
3983 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3984 }
3985
3986 /*
3987 * Analog capture
3988 */
ca0132_capture_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3989 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3990 struct hda_codec *codec,
3991 unsigned int stream_tag,
3992 unsigned int format,
3993 struct snd_pcm_substream *substream)
3994 {
3995 snd_hda_codec_setup_stream(codec, hinfo->nid,
3996 stream_tag, 0, format);
3997
3998 return 0;
3999 }
4000
ca0132_capture_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)4001 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
4002 struct hda_codec *codec,
4003 struct snd_pcm_substream *substream)
4004 {
4005 struct ca0132_spec *spec = codec->spec;
4006
4007 if (spec->dsp_state == DSP_DOWNLOADING)
4008 return 0;
4009
4010 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
4011 return 0;
4012 }
4013
ca0132_capture_pcm_delay(struct hda_pcm_stream * info,struct hda_codec * codec,struct snd_pcm_substream * substream)4014 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
4015 struct hda_codec *codec,
4016 struct snd_pcm_substream *substream)
4017 {
4018 struct ca0132_spec *spec = codec->spec;
4019 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
4020 struct snd_pcm_runtime *runtime = substream->runtime;
4021
4022 if (spec->dsp_state != DSP_DOWNLOADED)
4023 return 0;
4024
4025 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4026 latency += DSP_CRYSTAL_VOICE_LATENCY;
4027
4028 return (latency * runtime->rate) / 1000;
4029 }
4030
4031 /*
4032 * Controls stuffs.
4033 */
4034
4035 /*
4036 * Mixer controls helpers.
4037 */
4038 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
4039 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4040 .name = xname, \
4041 .subdevice = HDA_SUBDEV_AMP_FLAG, \
4042 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4043 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4044 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4045 .info = ca0132_volume_info, \
4046 .get = ca0132_volume_get, \
4047 .put = ca0132_volume_put, \
4048 .tlv = { .c = ca0132_volume_tlv }, \
4049 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4050
4051 /*
4052 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
4053 * volume put, which is used for setting the DSP volume. This was done because
4054 * the ca0132 functions were taking too much time and causing lag.
4055 */
4056 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
4057 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4058 .name = xname, \
4059 .subdevice = HDA_SUBDEV_AMP_FLAG, \
4060 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4061 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4062 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4063 .info = snd_hda_mixer_amp_volume_info, \
4064 .get = snd_hda_mixer_amp_volume_get, \
4065 .put = ca0132_alt_volume_put, \
4066 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
4067 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4068
4069 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
4070 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4071 .name = xname, \
4072 .subdevice = HDA_SUBDEV_AMP_FLAG, \
4073 .info = snd_hda_mixer_amp_switch_info, \
4074 .get = ca0132_switch_get, \
4075 .put = ca0132_switch_put, \
4076 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4077
4078 /* stereo */
4079 #define CA0132_CODEC_VOL(xname, nid, dir) \
4080 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
4081 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
4082 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
4083 #define CA0132_CODEC_MUTE(xname, nid, dir) \
4084 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
4085
4086 /* lookup tables */
4087 /*
4088 * Lookup table with decibel values for the DSP. When volume is changed in
4089 * Windows, the DSP is also sent the dB value in floating point. In Windows,
4090 * these values have decimal points, probably because the Windows driver
4091 * actually uses floating point. We can't here, so I made a lookup table of
4092 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
4093 * DAC's, and 9 is the maximum.
4094 */
4095 static const unsigned int float_vol_db_lookup[] = {
4096 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
4097 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
4098 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
4099 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
4100 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
4101 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
4102 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
4103 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
4104 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
4105 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
4106 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
4107 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4108 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4109 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4110 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4111 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4112 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
4113 };
4114
4115 /*
4116 * This table counts from float 0 to 1 in increments of .01, which is
4117 * useful for a few different sliders.
4118 */
4119 static const unsigned int float_zero_to_one_lookup[] = {
4120 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4121 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4122 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4123 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4124 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4125 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4126 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4127 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4128 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4129 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4130 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4131 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4132 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4133 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4134 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4135 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4136 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4137 };
4138
4139 /*
4140 * This table counts from float 10 to 1000, which is the range of the x-bass
4141 * crossover slider in Windows.
4142 */
4143 static const unsigned int float_xbass_xover_lookup[] = {
4144 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
4145 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
4146 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
4147 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
4148 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
4149 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
4150 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
4151 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
4152 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
4153 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
4154 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
4155 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
4156 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
4157 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
4158 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
4159 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
4160 0x44728000, 0x44750000, 0x44778000, 0x447A0000
4161 };
4162
4163 /* The following are for tuning of products */
4164 #ifdef ENABLE_TUNING_CONTROLS
4165
4166 static const unsigned int voice_focus_vals_lookup[] = {
4167 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
4168 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
4169 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
4170 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
4171 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
4172 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
4173 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
4174 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
4175 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
4176 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
4177 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
4178 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
4179 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
4180 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
4181 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
4182 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
4183 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
4184 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
4185 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
4186 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
4187 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
4188 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
4189 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
4190 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
4191 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
4192 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
4193 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
4194 };
4195
4196 static const unsigned int mic_svm_vals_lookup[] = {
4197 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4198 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4199 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4200 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4201 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4202 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4203 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4204 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4205 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4206 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4207 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4208 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4209 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4210 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4211 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4212 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4213 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4214 };
4215
4216 static const unsigned int equalizer_vals_lookup[] = {
4217 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4218 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4219 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4220 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4221 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4222 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
4223 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
4224 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
4225 0x41C00000
4226 };
4227
tuning_ctl_set(struct hda_codec * codec,hda_nid_t nid,const unsigned int * lookup,int idx)4228 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4229 const unsigned int *lookup, int idx)
4230 {
4231 int i = 0;
4232
4233 for (i = 0; i < TUNING_CTLS_COUNT; i++)
4234 if (nid == ca0132_tuning_ctls[i].nid)
4235 goto found;
4236
4237 return -EINVAL;
4238 found:
4239 snd_hda_power_up(codec);
4240 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
4241 ca0132_tuning_ctls[i].req,
4242 &(lookup[idx]), sizeof(unsigned int));
4243 snd_hda_power_down(codec);
4244
4245 return 1;
4246 }
4247
tuning_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4248 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
4249 struct snd_ctl_elem_value *ucontrol)
4250 {
4251 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4252 struct ca0132_spec *spec = codec->spec;
4253 hda_nid_t nid = get_amp_nid(kcontrol);
4254 long *valp = ucontrol->value.integer.value;
4255 int idx = nid - TUNING_CTL_START_NID;
4256
4257 *valp = spec->cur_ctl_vals[idx];
4258 return 0;
4259 }
4260
voice_focus_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4261 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
4262 struct snd_ctl_elem_info *uinfo)
4263 {
4264 int chs = get_amp_channels(kcontrol);
4265 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4266 uinfo->count = chs == 3 ? 2 : 1;
4267 uinfo->value.integer.min = 20;
4268 uinfo->value.integer.max = 180;
4269 uinfo->value.integer.step = 1;
4270
4271 return 0;
4272 }
4273
voice_focus_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4274 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
4275 struct snd_ctl_elem_value *ucontrol)
4276 {
4277 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4278 struct ca0132_spec *spec = codec->spec;
4279 hda_nid_t nid = get_amp_nid(kcontrol);
4280 long *valp = ucontrol->value.integer.value;
4281 int idx;
4282
4283 idx = nid - TUNING_CTL_START_NID;
4284 /* any change? */
4285 if (spec->cur_ctl_vals[idx] == *valp)
4286 return 0;
4287
4288 spec->cur_ctl_vals[idx] = *valp;
4289
4290 idx = *valp - 20;
4291 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
4292
4293 return 1;
4294 }
4295
mic_svm_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4296 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
4297 struct snd_ctl_elem_info *uinfo)
4298 {
4299 int chs = get_amp_channels(kcontrol);
4300 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4301 uinfo->count = chs == 3 ? 2 : 1;
4302 uinfo->value.integer.min = 0;
4303 uinfo->value.integer.max = 100;
4304 uinfo->value.integer.step = 1;
4305
4306 return 0;
4307 }
4308
mic_svm_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4309 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
4310 struct snd_ctl_elem_value *ucontrol)
4311 {
4312 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4313 struct ca0132_spec *spec = codec->spec;
4314 hda_nid_t nid = get_amp_nid(kcontrol);
4315 long *valp = ucontrol->value.integer.value;
4316 int idx;
4317
4318 idx = nid - TUNING_CTL_START_NID;
4319 /* any change? */
4320 if (spec->cur_ctl_vals[idx] == *valp)
4321 return 0;
4322
4323 spec->cur_ctl_vals[idx] = *valp;
4324
4325 idx = *valp;
4326 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
4327
4328 return 0;
4329 }
4330
equalizer_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4331 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
4332 struct snd_ctl_elem_info *uinfo)
4333 {
4334 int chs = get_amp_channels(kcontrol);
4335 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4336 uinfo->count = chs == 3 ? 2 : 1;
4337 uinfo->value.integer.min = 0;
4338 uinfo->value.integer.max = 48;
4339 uinfo->value.integer.step = 1;
4340
4341 return 0;
4342 }
4343
equalizer_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4344 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
4345 struct snd_ctl_elem_value *ucontrol)
4346 {
4347 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4348 struct ca0132_spec *spec = codec->spec;
4349 hda_nid_t nid = get_amp_nid(kcontrol);
4350 long *valp = ucontrol->value.integer.value;
4351 int idx;
4352
4353 idx = nid - TUNING_CTL_START_NID;
4354 /* any change? */
4355 if (spec->cur_ctl_vals[idx] == *valp)
4356 return 0;
4357
4358 spec->cur_ctl_vals[idx] = *valp;
4359
4360 idx = *valp;
4361 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
4362
4363 return 1;
4364 }
4365
4366 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
4367 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
4368
add_tuning_control(struct hda_codec * codec,hda_nid_t pnid,hda_nid_t nid,const char * name,int dir)4369 static int add_tuning_control(struct hda_codec *codec,
4370 hda_nid_t pnid, hda_nid_t nid,
4371 const char *name, int dir)
4372 {
4373 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4374 int type = dir ? HDA_INPUT : HDA_OUTPUT;
4375 struct snd_kcontrol_new knew =
4376 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
4377
4378 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
4379 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
4380 knew.tlv.c = 0;
4381 knew.tlv.p = 0;
4382 switch (pnid) {
4383 case VOICE_FOCUS:
4384 knew.info = voice_focus_ctl_info;
4385 knew.get = tuning_ctl_get;
4386 knew.put = voice_focus_ctl_put;
4387 knew.tlv.p = voice_focus_db_scale;
4388 break;
4389 case MIC_SVM:
4390 knew.info = mic_svm_ctl_info;
4391 knew.get = tuning_ctl_get;
4392 knew.put = mic_svm_ctl_put;
4393 break;
4394 case EQUALIZER:
4395 knew.info = equalizer_ctl_info;
4396 knew.get = tuning_ctl_get;
4397 knew.put = equalizer_ctl_put;
4398 knew.tlv.p = eq_db_scale;
4399 break;
4400 default:
4401 return 0;
4402 }
4403 knew.private_value =
4404 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4405 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4406 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4407 }
4408
add_tuning_ctls(struct hda_codec * codec)4409 static int add_tuning_ctls(struct hda_codec *codec)
4410 {
4411 int i;
4412 int err;
4413
4414 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4415 err = add_tuning_control(codec,
4416 ca0132_tuning_ctls[i].parent_nid,
4417 ca0132_tuning_ctls[i].nid,
4418 ca0132_tuning_ctls[i].name,
4419 ca0132_tuning_ctls[i].direct);
4420 if (err < 0)
4421 return err;
4422 }
4423
4424 return 0;
4425 }
4426
ca0132_init_tuning_defaults(struct hda_codec * codec)4427 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4428 {
4429 struct ca0132_spec *spec = codec->spec;
4430 int i;
4431
4432 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
4433 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4434 /* SVM level defaults to 0.74. */
4435 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4436
4437 /* EQ defaults to 0dB. */
4438 for (i = 2; i < TUNING_CTLS_COUNT; i++)
4439 spec->cur_ctl_vals[i] = 24;
4440 }
4441 #endif /*ENABLE_TUNING_CONTROLS*/
4442
4443 /*
4444 * Select the active output.
4445 * If autodetect is enabled, output will be selected based on jack detection.
4446 * If jack inserted, headphone will be selected, else built-in speakers
4447 * If autodetect is disabled, output will be selected based on selection.
4448 */
ca0132_select_out(struct hda_codec * codec)4449 static int ca0132_select_out(struct hda_codec *codec)
4450 {
4451 struct ca0132_spec *spec = codec->spec;
4452 unsigned int pin_ctl;
4453 int jack_present;
4454 int auto_jack;
4455 unsigned int tmp;
4456 int err;
4457
4458 codec_dbg(codec, "ca0132_select_out\n");
4459
4460 snd_hda_power_up_pm(codec);
4461
4462 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4463
4464 if (auto_jack)
4465 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
4466 else
4467 jack_present =
4468 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4469
4470 if (jack_present)
4471 spec->cur_out_type = HEADPHONE_OUT;
4472 else
4473 spec->cur_out_type = SPEAKER_OUT;
4474
4475 if (spec->cur_out_type == SPEAKER_OUT) {
4476 codec_dbg(codec, "ca0132_select_out speaker\n");
4477 /*speaker out config*/
4478 tmp = FLOAT_ONE;
4479 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4480 if (err < 0)
4481 goto exit;
4482 /*enable speaker EQ*/
4483 tmp = FLOAT_ONE;
4484 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4485 if (err < 0)
4486 goto exit;
4487
4488 /* Setup EAPD */
4489 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4490 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4491 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4492 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4493 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4494 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4495 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4496 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4497
4498 /* disable headphone node */
4499 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4500 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4501 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4502 pin_ctl & ~PIN_HP);
4503 /* enable speaker node */
4504 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4505 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4506 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4507 pin_ctl | PIN_OUT);
4508 } else {
4509 codec_dbg(codec, "ca0132_select_out hp\n");
4510 /*headphone out config*/
4511 tmp = FLOAT_ZERO;
4512 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4513 if (err < 0)
4514 goto exit;
4515 /*disable speaker EQ*/
4516 tmp = FLOAT_ZERO;
4517 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4518 if (err < 0)
4519 goto exit;
4520
4521 /* Setup EAPD */
4522 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4523 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4524 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4525 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4526 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4527 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4528 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4529 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4530
4531 /* disable speaker*/
4532 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4533 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4534 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4535 pin_ctl & ~PIN_HP);
4536 /* enable headphone*/
4537 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4538 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4539 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4540 pin_ctl | PIN_HP);
4541 }
4542
4543 exit:
4544 snd_hda_power_down_pm(codec);
4545
4546 return err < 0 ? err : 0;
4547 }
4548
4549 static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4550 static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
4551 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4552
ae5_mmio_select_out(struct hda_codec * codec)4553 static void ae5_mmio_select_out(struct hda_codec *codec)
4554 {
4555 struct ca0132_spec *spec = codec->spec;
4556 const struct ae_ca0113_output_set *out_cmds;
4557 unsigned int i;
4558
4559 if (ca0132_quirk(spec) == QUIRK_AE5)
4560 out_cmds = &ae5_ca0113_output_presets;
4561 else
4562 out_cmds = &ae7_ca0113_output_presets;
4563
4564 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++)
4565 ca0113_mmio_command_set(codec, out_cmds->group[i],
4566 out_cmds->target[i],
4567 out_cmds->vals[spec->cur_out_type][i]);
4568 }
4569
ca0132_alt_set_full_range_speaker(struct hda_codec * codec)4570 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)
4571 {
4572 struct ca0132_spec *spec = codec->spec;
4573 int quirk = ca0132_quirk(spec);
4574 unsigned int tmp;
4575 int err;
4576
4577 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */
4578 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0
4579 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4580 return 0;
4581
4582 /* Set front L/R full range. Zero for full-range, one for redirection. */
4583 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
4584 err = dspio_set_uint_param(codec, 0x96,
4585 SPEAKER_FULL_RANGE_FRONT_L_R, tmp);
4586 if (err < 0)
4587 return err;
4588
4589 /* When setting full-range rear, both rear and center/lfe are set. */
4590 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE;
4591 err = dspio_set_uint_param(codec, 0x96,
4592 SPEAKER_FULL_RANGE_CENTER_LFE, tmp);
4593 if (err < 0)
4594 return err;
4595
4596 err = dspio_set_uint_param(codec, 0x96,
4597 SPEAKER_FULL_RANGE_REAR_L_R, tmp);
4598 if (err < 0)
4599 return err;
4600
4601 /*
4602 * Only the AE series cards set this value when setting full-range,
4603 * and it's always 1.0f.
4604 */
4605 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) {
4606 err = dspio_set_uint_param(codec, 0x96,
4607 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE);
4608 if (err < 0)
4609 return err;
4610 }
4611
4612 return 0;
4613 }
4614
ca0132_alt_surround_set_bass_redirection(struct hda_codec * codec,bool val)4615 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec,
4616 bool val)
4617 {
4618 struct ca0132_spec *spec = codec->spec;
4619 unsigned int tmp;
4620 int err;
4621
4622 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 &&
4623 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0)
4624 tmp = FLOAT_ONE;
4625 else
4626 tmp = FLOAT_ZERO;
4627
4628 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
4629 if (err < 0)
4630 return err;
4631
4632 /* If it is enabled, make sure to set the crossover frequency. */
4633 if (tmp) {
4634 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq];
4635 err = dspio_set_uint_param(codec, 0x96,
4636 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp);
4637 if (err < 0)
4638 return err;
4639 }
4640
4641 return 0;
4642 }
4643
4644 /*
4645 * These are the commands needed to setup output on each of the different card
4646 * types.
4647 */
ca0132_alt_select_out_get_quirk_data(struct hda_codec * codec,const struct ca0132_alt_out_set_quirk_data ** quirk_data)4648 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec,
4649 const struct ca0132_alt_out_set_quirk_data **quirk_data)
4650 {
4651 struct ca0132_spec *spec = codec->spec;
4652 int quirk = ca0132_quirk(spec);
4653 unsigned int i;
4654
4655 *quirk_data = NULL;
4656 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) {
4657 if (quirk_out_set_data[i].quirk_id == quirk) {
4658 *quirk_data = &quirk_out_set_data[i];
4659 return;
4660 }
4661 }
4662 }
4663
ca0132_alt_select_out_quirk_set(struct hda_codec * codec)4664 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)
4665 {
4666 const struct ca0132_alt_out_set_quirk_data *quirk_data;
4667 const struct ca0132_alt_out_set_info *out_info;
4668 struct ca0132_spec *spec = codec->spec;
4669 unsigned int i, gpio_data;
4670 int err;
4671
4672 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data);
4673 if (!quirk_data)
4674 return 0;
4675
4676 out_info = &quirk_data->out_set_info[spec->cur_out_type];
4677 if (quirk_data->is_ae_series)
4678 ae5_mmio_select_out(codec);
4679
4680 if (out_info->has_hda_gpio) {
4681 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
4682 AC_VERB_GET_GPIO_DATA, 0);
4683
4684 if (out_info->hda_gpio_set)
4685 gpio_data |= (1 << out_info->hda_gpio_pin);
4686 else
4687 gpio_data &= ~(1 << out_info->hda_gpio_pin);
4688
4689 snd_hda_codec_write(codec, codec->core.afg, 0,
4690 AC_VERB_SET_GPIO_DATA, gpio_data);
4691 }
4692
4693 if (out_info->mmio_gpio_count) {
4694 for (i = 0; i < out_info->mmio_gpio_count; i++) {
4695 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i],
4696 out_info->mmio_gpio_set[i]);
4697 }
4698 }
4699
4700 if (out_info->scp_cmds_count) {
4701 for (i = 0; i < out_info->scp_cmds_count; i++) {
4702 err = dspio_set_uint_param(codec,
4703 out_info->scp_cmd_mid[i],
4704 out_info->scp_cmd_req[i],
4705 out_info->scp_cmd_val[i]);
4706 if (err < 0)
4707 return err;
4708 }
4709 }
4710
4711 chipio_set_control_param(codec, 0x0d, out_info->dac2port);
4712
4713 if (out_info->has_chipio_write) {
4714 chipio_write(codec, out_info->chipio_write_addr,
4715 out_info->chipio_write_data);
4716 }
4717
4718 if (quirk_data->has_headphone_gain) {
4719 if (spec->cur_out_type != HEADPHONE_OUT) {
4720 if (quirk_data->is_ae_series)
4721 ae5_headphone_gain_set(codec, 2);
4722 else
4723 zxr_headphone_gain_set(codec, 0);
4724 } else {
4725 if (quirk_data->is_ae_series)
4726 ae5_headphone_gain_set(codec,
4727 spec->ae5_headphone_gain_val);
4728 else
4729 zxr_headphone_gain_set(codec,
4730 spec->zxr_gain_set);
4731 }
4732 }
4733
4734 return 0;
4735 }
4736
ca0132_set_out_node_pincfg(struct hda_codec * codec,hda_nid_t nid,bool out_enable,bool hp_enable)4737 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid,
4738 bool out_enable, bool hp_enable)
4739 {
4740 unsigned int pin_ctl;
4741
4742 pin_ctl = snd_hda_codec_read(codec, nid, 0,
4743 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4744
4745 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP;
4746 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT;
4747 snd_hda_set_pin_ctl(codec, nid, pin_ctl);
4748 }
4749
4750 /*
4751 * This function behaves similarly to the ca0132_select_out funciton above,
4752 * except with a few differences. It adds the ability to select the current
4753 * output with an enumerated control "output source" if the auto detect
4754 * mute switch is set to off. If the auto detect mute switch is enabled, it
4755 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4756 * It also adds the ability to auto-detect the front headphone port.
4757 */
ca0132_alt_select_out(struct hda_codec * codec)4758 static int ca0132_alt_select_out(struct hda_codec *codec)
4759 {
4760 struct ca0132_spec *spec = codec->spec;
4761 unsigned int tmp, outfx_set;
4762 int jack_present;
4763 int auto_jack;
4764 int err;
4765 /* Default Headphone is rear headphone */
4766 hda_nid_t headphone_nid = spec->out_pins[1];
4767
4768 codec_dbg(codec, "%s\n", __func__);
4769
4770 snd_hda_power_up_pm(codec);
4771
4772 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4773
4774 /*
4775 * If headphone rear or front is plugged in, set to headphone.
4776 * If neither is plugged in, set to rear line out. Only if
4777 * hp/speaker auto detect is enabled.
4778 */
4779 if (auto_jack) {
4780 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4781 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4782
4783 if (jack_present)
4784 spec->cur_out_type = HEADPHONE_OUT;
4785 else
4786 spec->cur_out_type = SPEAKER_OUT;
4787 } else
4788 spec->cur_out_type = spec->out_enum_val;
4789
4790 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID];
4791
4792 /* Begin DSP output switch, mute DSP volume. */
4793 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);
4794 if (err < 0)
4795 goto exit;
4796
4797 if (ca0132_alt_select_out_quirk_set(codec) < 0)
4798 goto exit;
4799
4800 switch (spec->cur_out_type) {
4801 case SPEAKER_OUT:
4802 codec_dbg(codec, "%s speaker\n", __func__);
4803
4804 /* Enable EAPD */
4805 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4806 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4807
4808 /* Disable headphone node. */
4809 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);
4810 /* Set front L-R to output. */
4811 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);
4812 /* Set Center/LFE to output. */
4813 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);
4814 /* Set rear surround to output. */
4815 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);
4816
4817 /*
4818 * Without PlayEnhancement being enabled, if we've got a 2.0
4819 * setup, set it to floating point eight to disable any DSP
4820 * processing effects.
4821 */
4822 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4823 tmp = FLOAT_EIGHT;
4824 else
4825 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val;
4826
4827 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4828 if (err < 0)
4829 goto exit;
4830
4831 break;
4832 case HEADPHONE_OUT:
4833 codec_dbg(codec, "%s hp\n", __func__);
4834 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4835 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4836
4837 /* Disable all speaker nodes. */
4838 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);
4839 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);
4840 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);
4841
4842 /* enable headphone, either front or rear */
4843 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4844 headphone_nid = spec->out_pins[2];
4845 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4846 headphone_nid = spec->out_pins[1];
4847
4848 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1);
4849
4850 if (outfx_set)
4851 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4852 else
4853 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4854
4855 if (err < 0)
4856 goto exit;
4857 break;
4858 }
4859 /*
4860 * If output effects are enabled, set the X-Bass effect value again to
4861 * make sure that it's properly enabled/disabled for speaker
4862 * configurations with an LFE channel.
4863 */
4864 if (outfx_set)
4865 ca0132_effects_set(codec, X_BASS,
4866 spec->effects_switch[X_BASS - EFFECT_START_NID]);
4867
4868 /* Set speaker EQ bypass attenuation to 0. */
4869 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);
4870 if (err < 0)
4871 goto exit;
4872
4873 /*
4874 * Although unused on all cards but the AE series, this is always set
4875 * to zero when setting the output.
4876 */
4877 err = dspio_set_uint_param(codec, 0x96,
4878 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO);
4879 if (err < 0)
4880 goto exit;
4881
4882 if (spec->cur_out_type == SPEAKER_OUT)
4883 err = ca0132_alt_surround_set_bass_redirection(codec,
4884 spec->bass_redirection_val);
4885 else
4886 err = ca0132_alt_surround_set_bass_redirection(codec, 0);
4887
4888 /* Unmute DSP now that we're done with output selection. */
4889 err = dspio_set_uint_param(codec, 0x96,
4890 SPEAKER_TUNING_MUTE, FLOAT_ZERO);
4891 if (err < 0)
4892 goto exit;
4893
4894 if (spec->cur_out_type == SPEAKER_OUT) {
4895 err = ca0132_alt_set_full_range_speaker(codec);
4896 if (err < 0)
4897 goto exit;
4898 }
4899
4900 exit:
4901 snd_hda_power_down_pm(codec);
4902
4903 return err < 0 ? err : 0;
4904 }
4905
ca0132_unsol_hp_delayed(struct work_struct * work)4906 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4907 {
4908 struct ca0132_spec *spec = container_of(
4909 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4910 struct hda_jack_tbl *jack;
4911
4912 if (ca0132_use_alt_functions(spec))
4913 ca0132_alt_select_out(spec->codec);
4914 else
4915 ca0132_select_out(spec->codec);
4916
4917 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4918 if (jack) {
4919 jack->block_report = 0;
4920 snd_hda_jack_report_sync(spec->codec);
4921 }
4922 }
4923
4924 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4925 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4926 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4927 static int stop_mic1(struct hda_codec *codec);
4928 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4929 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4930
4931 /*
4932 * Select the active VIP source
4933 */
ca0132_set_vipsource(struct hda_codec * codec,int val)4934 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4935 {
4936 struct ca0132_spec *spec = codec->spec;
4937 unsigned int tmp;
4938
4939 if (spec->dsp_state != DSP_DOWNLOADED)
4940 return 0;
4941
4942 /* if CrystalVoice if off, vipsource should be 0 */
4943 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4944 (val == 0)) {
4945 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4946 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4947 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4948 if (spec->cur_mic_type == DIGITAL_MIC)
4949 tmp = FLOAT_TWO;
4950 else
4951 tmp = FLOAT_ONE;
4952 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4953 tmp = FLOAT_ZERO;
4954 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4955 } else {
4956 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4957 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4958 if (spec->cur_mic_type == DIGITAL_MIC)
4959 tmp = FLOAT_TWO;
4960 else
4961 tmp = FLOAT_ONE;
4962 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4963 tmp = FLOAT_ONE;
4964 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4965 msleep(20);
4966 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4967 }
4968
4969 return 1;
4970 }
4971
ca0132_alt_set_vipsource(struct hda_codec * codec,int val)4972 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4973 {
4974 struct ca0132_spec *spec = codec->spec;
4975 unsigned int tmp;
4976
4977 if (spec->dsp_state != DSP_DOWNLOADED)
4978 return 0;
4979
4980 codec_dbg(codec, "%s\n", __func__);
4981
4982 chipio_set_stream_control(codec, 0x03, 0);
4983 chipio_set_stream_control(codec, 0x04, 0);
4984
4985 /* if CrystalVoice is off, vipsource should be 0 */
4986 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4987 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4988 codec_dbg(codec, "%s: off.", __func__);
4989 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4990
4991 tmp = FLOAT_ZERO;
4992 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4993
4994 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4995 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4996 if (ca0132_quirk(spec) == QUIRK_R3DI)
4997 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4998
4999
5000 if (spec->in_enum_val == REAR_LINE_IN)
5001 tmp = FLOAT_ZERO;
5002 else {
5003 if (ca0132_quirk(spec) == QUIRK_SBZ)
5004 tmp = FLOAT_THREE;
5005 else
5006 tmp = FLOAT_ONE;
5007 }
5008
5009 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5010
5011 } else {
5012 codec_dbg(codec, "%s: on.", __func__);
5013 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
5014 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
5015 if (ca0132_quirk(spec) == QUIRK_R3DI)
5016 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
5017
5018 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
5019 tmp = FLOAT_TWO;
5020 else
5021 tmp = FLOAT_ONE;
5022 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5023
5024 tmp = FLOAT_ONE;
5025 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
5026
5027 msleep(20);
5028 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
5029 }
5030
5031 chipio_set_stream_control(codec, 0x03, 1);
5032 chipio_set_stream_control(codec, 0x04, 1);
5033
5034 return 1;
5035 }
5036
5037 /*
5038 * Select the active microphone.
5039 * If autodetect is enabled, mic will be selected based on jack detection.
5040 * If jack inserted, ext.mic will be selected, else built-in mic
5041 * If autodetect is disabled, mic will be selected based on selection.
5042 */
ca0132_select_mic(struct hda_codec * codec)5043 static int ca0132_select_mic(struct hda_codec *codec)
5044 {
5045 struct ca0132_spec *spec = codec->spec;
5046 int jack_present;
5047 int auto_jack;
5048
5049 codec_dbg(codec, "ca0132_select_mic\n");
5050
5051 snd_hda_power_up_pm(codec);
5052
5053 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5054
5055 if (auto_jack)
5056 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5057 else
5058 jack_present =
5059 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
5060
5061 if (jack_present)
5062 spec->cur_mic_type = LINE_MIC_IN;
5063 else
5064 spec->cur_mic_type = DIGITAL_MIC;
5065
5066 if (spec->cur_mic_type == DIGITAL_MIC) {
5067 /* enable digital Mic */
5068 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
5069 ca0132_set_dmic(codec, 1);
5070 ca0132_mic_boost_set(codec, 0);
5071 /* set voice focus */
5072 ca0132_effects_set(codec, VOICE_FOCUS,
5073 spec->effects_switch
5074 [VOICE_FOCUS - EFFECT_START_NID]);
5075 } else {
5076 /* disable digital Mic */
5077 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
5078 ca0132_set_dmic(codec, 0);
5079 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
5080 /* disable voice focus */
5081 ca0132_effects_set(codec, VOICE_FOCUS, 0);
5082 }
5083
5084 snd_hda_power_down_pm(codec);
5085
5086 return 0;
5087 }
5088
5089 /*
5090 * Select the active input.
5091 * Mic detection isn't used, because it's kind of pointless on the SBZ.
5092 * The front mic has no jack-detection, so the only way to switch to it
5093 * is to do it manually in alsamixer.
5094 */
ca0132_alt_select_in(struct hda_codec * codec)5095 static int ca0132_alt_select_in(struct hda_codec *codec)
5096 {
5097 struct ca0132_spec *spec = codec->spec;
5098 unsigned int tmp;
5099
5100 codec_dbg(codec, "%s\n", __func__);
5101
5102 snd_hda_power_up_pm(codec);
5103
5104 chipio_set_stream_control(codec, 0x03, 0);
5105 chipio_set_stream_control(codec, 0x04, 0);
5106
5107 spec->cur_mic_type = spec->in_enum_val;
5108
5109 switch (spec->cur_mic_type) {
5110 case REAR_MIC:
5111 switch (ca0132_quirk(spec)) {
5112 case QUIRK_SBZ:
5113 case QUIRK_R3D:
5114 ca0113_mmio_gpio_set(codec, 0, false);
5115 tmp = FLOAT_THREE;
5116 break;
5117 case QUIRK_ZXR:
5118 tmp = FLOAT_THREE;
5119 break;
5120 case QUIRK_R3DI:
5121 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5122 tmp = FLOAT_ONE;
5123 break;
5124 case QUIRK_AE5:
5125 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5126 tmp = FLOAT_THREE;
5127 break;
5128 case QUIRK_AE7:
5129 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5130 tmp = FLOAT_THREE;
5131 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5132 SR_96_000);
5133 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5134 SR_96_000);
5135 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5136 break;
5137 default:
5138 tmp = FLOAT_ONE;
5139 break;
5140 }
5141
5142 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5143 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5144 if (ca0132_quirk(spec) == QUIRK_R3DI)
5145 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5146
5147 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5148
5149 chipio_set_stream_control(codec, 0x03, 1);
5150 chipio_set_stream_control(codec, 0x04, 1);
5151 switch (ca0132_quirk(spec)) {
5152 case QUIRK_SBZ:
5153 chipio_write(codec, 0x18B098, 0x0000000C);
5154 chipio_write(codec, 0x18B09C, 0x0000000C);
5155 break;
5156 case QUIRK_ZXR:
5157 chipio_write(codec, 0x18B098, 0x0000000C);
5158 chipio_write(codec, 0x18B09C, 0x000000CC);
5159 break;
5160 case QUIRK_AE5:
5161 chipio_write(codec, 0x18B098, 0x0000000C);
5162 chipio_write(codec, 0x18B09C, 0x0000004C);
5163 break;
5164 default:
5165 break;
5166 }
5167 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5168 break;
5169 case REAR_LINE_IN:
5170 ca0132_mic_boost_set(codec, 0);
5171 switch (ca0132_quirk(spec)) {
5172 case QUIRK_SBZ:
5173 case QUIRK_R3D:
5174 ca0113_mmio_gpio_set(codec, 0, false);
5175 break;
5176 case QUIRK_R3DI:
5177 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5178 break;
5179 case QUIRK_AE5:
5180 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5181 break;
5182 case QUIRK_AE7:
5183 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5184 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5185 SR_96_000);
5186 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5187 SR_96_000);
5188 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5189 break;
5190 default:
5191 break;
5192 }
5193
5194 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5195 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5196 if (ca0132_quirk(spec) == QUIRK_R3DI)
5197 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5198
5199 if (ca0132_quirk(spec) == QUIRK_AE7)
5200 tmp = FLOAT_THREE;
5201 else
5202 tmp = FLOAT_ZERO;
5203 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5204
5205 switch (ca0132_quirk(spec)) {
5206 case QUIRK_SBZ:
5207 case QUIRK_AE5:
5208 chipio_write(codec, 0x18B098, 0x00000000);
5209 chipio_write(codec, 0x18B09C, 0x00000000);
5210 break;
5211 default:
5212 break;
5213 }
5214 chipio_set_stream_control(codec, 0x03, 1);
5215 chipio_set_stream_control(codec, 0x04, 1);
5216 break;
5217 case FRONT_MIC:
5218 switch (ca0132_quirk(spec)) {
5219 case QUIRK_SBZ:
5220 case QUIRK_R3D:
5221 ca0113_mmio_gpio_set(codec, 0, true);
5222 ca0113_mmio_gpio_set(codec, 5, false);
5223 tmp = FLOAT_THREE;
5224 break;
5225 case QUIRK_R3DI:
5226 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
5227 tmp = FLOAT_ONE;
5228 break;
5229 case QUIRK_AE5:
5230 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5231 tmp = FLOAT_THREE;
5232 break;
5233 default:
5234 tmp = FLOAT_ONE;
5235 break;
5236 }
5237
5238 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5239 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5240 if (ca0132_quirk(spec) == QUIRK_R3DI)
5241 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5242
5243 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5244
5245 chipio_set_stream_control(codec, 0x03, 1);
5246 chipio_set_stream_control(codec, 0x04, 1);
5247
5248 switch (ca0132_quirk(spec)) {
5249 case QUIRK_SBZ:
5250 chipio_write(codec, 0x18B098, 0x0000000C);
5251 chipio_write(codec, 0x18B09C, 0x000000CC);
5252 break;
5253 case QUIRK_AE5:
5254 chipio_write(codec, 0x18B098, 0x0000000C);
5255 chipio_write(codec, 0x18B09C, 0x0000004C);
5256 break;
5257 default:
5258 break;
5259 }
5260 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5261 break;
5262 }
5263 ca0132_cvoice_switch_set(codec);
5264
5265 snd_hda_power_down_pm(codec);
5266 return 0;
5267 }
5268
5269 /*
5270 * Check if VNODE settings take effect immediately.
5271 */
ca0132_is_vnode_effective(struct hda_codec * codec,hda_nid_t vnid,hda_nid_t * shared_nid)5272 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
5273 hda_nid_t vnid,
5274 hda_nid_t *shared_nid)
5275 {
5276 struct ca0132_spec *spec = codec->spec;
5277 hda_nid_t nid;
5278
5279 switch (vnid) {
5280 case VNID_SPK:
5281 nid = spec->shared_out_nid;
5282 break;
5283 case VNID_MIC:
5284 nid = spec->shared_mic_nid;
5285 break;
5286 default:
5287 return false;
5288 }
5289
5290 if (shared_nid)
5291 *shared_nid = nid;
5292
5293 return true;
5294 }
5295
5296 /*
5297 * The following functions are control change helpers.
5298 * They return 0 if no changed. Return 1 if changed.
5299 */
ca0132_voicefx_set(struct hda_codec * codec,int enable)5300 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
5301 {
5302 struct ca0132_spec *spec = codec->spec;
5303 unsigned int tmp;
5304
5305 /* based on CrystalVoice state to enable VoiceFX. */
5306 if (enable) {
5307 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
5308 FLOAT_ONE : FLOAT_ZERO;
5309 } else {
5310 tmp = FLOAT_ZERO;
5311 }
5312
5313 dspio_set_uint_param(codec, ca0132_voicefx.mid,
5314 ca0132_voicefx.reqs[0], tmp);
5315
5316 return 1;
5317 }
5318
5319 /*
5320 * Set the effects parameters
5321 */
ca0132_effects_set(struct hda_codec * codec,hda_nid_t nid,long val)5322 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
5323 {
5324 struct ca0132_spec *spec = codec->spec;
5325 unsigned int on, tmp, channel_cfg;
5326 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5327 int err = 0;
5328 int idx = nid - EFFECT_START_NID;
5329
5330 if ((idx < 0) || (idx >= num_fx))
5331 return 0; /* no changed */
5332
5333 /* for out effect, qualify with PE */
5334 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
5335 /* if PE if off, turn off out effects. */
5336 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
5337 val = 0;
5338 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) {
5339 channel_cfg = spec->channel_cfg_val;
5340 if (channel_cfg != SPEAKER_CHANNELS_2_0 &&
5341 channel_cfg != SPEAKER_CHANNELS_4_0)
5342 val = 0;
5343 }
5344 }
5345
5346 /* for in effect, qualify with CrystalVoice */
5347 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
5348 /* if CrystalVoice if off, turn off in effects. */
5349 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
5350 val = 0;
5351
5352 /* Voice Focus applies to 2-ch Mic, Digital Mic */
5353 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
5354 val = 0;
5355
5356 /* If Voice Focus on SBZ, set to two channel. */
5357 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)
5358 && (spec->cur_mic_type != REAR_LINE_IN)) {
5359 if (spec->effects_switch[CRYSTAL_VOICE -
5360 EFFECT_START_NID]) {
5361
5362 if (spec->effects_switch[VOICE_FOCUS -
5363 EFFECT_START_NID]) {
5364 tmp = FLOAT_TWO;
5365 val = 1;
5366 } else
5367 tmp = FLOAT_ONE;
5368
5369 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5370 }
5371 }
5372 /*
5373 * For SBZ noise reduction, there's an extra command
5374 * to module ID 0x47. No clue why.
5375 */
5376 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)
5377 && (spec->cur_mic_type != REAR_LINE_IN)) {
5378 if (spec->effects_switch[CRYSTAL_VOICE -
5379 EFFECT_START_NID]) {
5380 if (spec->effects_switch[NOISE_REDUCTION -
5381 EFFECT_START_NID])
5382 tmp = FLOAT_ONE;
5383 else
5384 tmp = FLOAT_ZERO;
5385 } else
5386 tmp = FLOAT_ZERO;
5387
5388 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
5389 }
5390
5391 /* If rear line in disable effects. */
5392 if (ca0132_use_alt_functions(spec) &&
5393 spec->in_enum_val == REAR_LINE_IN)
5394 val = 0;
5395 }
5396
5397 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5398 nid, val);
5399
5400 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
5401 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5402 ca0132_effects[idx].reqs[0], on);
5403
5404 if (err < 0)
5405 return 0; /* no changed */
5406
5407 return 1;
5408 }
5409
5410 /*
5411 * Turn on/off Playback Enhancements
5412 */
ca0132_pe_switch_set(struct hda_codec * codec)5413 static int ca0132_pe_switch_set(struct hda_codec *codec)
5414 {
5415 struct ca0132_spec *spec = codec->spec;
5416 hda_nid_t nid;
5417 int i, ret = 0;
5418
5419 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
5420 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
5421
5422 if (ca0132_use_alt_functions(spec))
5423 ca0132_alt_select_out(codec);
5424
5425 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
5426 nid = OUT_EFFECT_START_NID;
5427 /* PE affects all out effects */
5428 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
5429 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5430
5431 return ret;
5432 }
5433
5434 /* Check if Mic1 is streaming, if so, stop streaming */
stop_mic1(struct hda_codec * codec)5435 static int stop_mic1(struct hda_codec *codec)
5436 {
5437 struct ca0132_spec *spec = codec->spec;
5438 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
5439 AC_VERB_GET_CONV, 0);
5440 if (oldval != 0)
5441 snd_hda_codec_write(codec, spec->adcs[0], 0,
5442 AC_VERB_SET_CHANNEL_STREAMID,
5443 0);
5444 return oldval;
5445 }
5446
5447 /* Resume Mic1 streaming if it was stopped. */
resume_mic1(struct hda_codec * codec,unsigned int oldval)5448 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
5449 {
5450 struct ca0132_spec *spec = codec->spec;
5451 /* Restore the previous stream and channel */
5452 if (oldval != 0)
5453 snd_hda_codec_write(codec, spec->adcs[0], 0,
5454 AC_VERB_SET_CHANNEL_STREAMID,
5455 oldval);
5456 }
5457
5458 /*
5459 * Turn on/off CrystalVoice
5460 */
ca0132_cvoice_switch_set(struct hda_codec * codec)5461 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
5462 {
5463 struct ca0132_spec *spec = codec->spec;
5464 hda_nid_t nid;
5465 int i, ret = 0;
5466 unsigned int oldval;
5467
5468 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
5469 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
5470
5471 i = IN_EFFECT_START_NID - EFFECT_START_NID;
5472 nid = IN_EFFECT_START_NID;
5473 /* CrystalVoice affects all in effects */
5474 for (; nid < IN_EFFECT_END_NID; nid++, i++)
5475 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5476
5477 /* including VoiceFX */
5478 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5479
5480 /* set correct vipsource */
5481 oldval = stop_mic1(codec);
5482 if (ca0132_use_alt_functions(spec))
5483 ret |= ca0132_alt_set_vipsource(codec, 1);
5484 else
5485 ret |= ca0132_set_vipsource(codec, 1);
5486 resume_mic1(codec, oldval);
5487 return ret;
5488 }
5489
ca0132_mic_boost_set(struct hda_codec * codec,long val)5490 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5491 {
5492 struct ca0132_spec *spec = codec->spec;
5493 int ret = 0;
5494
5495 if (val) /* on */
5496 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5497 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5498 else /* off */
5499 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5500 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5501
5502 return ret;
5503 }
5504
ca0132_alt_mic_boost_set(struct hda_codec * codec,long val)5505 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5506 {
5507 struct ca0132_spec *spec = codec->spec;
5508 int ret = 0;
5509
5510 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5511 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5512 return ret;
5513 }
5514
ae5_headphone_gain_set(struct hda_codec * codec,long val)5515 static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5516 {
5517 unsigned int i;
5518
5519 for (i = 0; i < 4; i++)
5520 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5521 ae5_headphone_gain_presets[val].vals[i]);
5522 return 0;
5523 }
5524
5525 /*
5526 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5527 * amplifier to handle a 600 ohm load.
5528 */
zxr_headphone_gain_set(struct hda_codec * codec,long val)5529 static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5530 {
5531 ca0113_mmio_gpio_set(codec, 1, val);
5532
5533 return 0;
5534 }
5535
ca0132_vnode_switch_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5536 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5537 struct snd_ctl_elem_value *ucontrol)
5538 {
5539 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5540 hda_nid_t nid = get_amp_nid(kcontrol);
5541 hda_nid_t shared_nid = 0;
5542 bool effective;
5543 int ret = 0;
5544 struct ca0132_spec *spec = codec->spec;
5545 int auto_jack;
5546
5547 if (nid == VNID_HP_SEL) {
5548 auto_jack =
5549 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5550 if (!auto_jack) {
5551 if (ca0132_use_alt_functions(spec))
5552 ca0132_alt_select_out(codec);
5553 else
5554 ca0132_select_out(codec);
5555 }
5556 return 1;
5557 }
5558
5559 if (nid == VNID_AMIC1_SEL) {
5560 auto_jack =
5561 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5562 if (!auto_jack)
5563 ca0132_select_mic(codec);
5564 return 1;
5565 }
5566
5567 if (nid == VNID_HP_ASEL) {
5568 if (ca0132_use_alt_functions(spec))
5569 ca0132_alt_select_out(codec);
5570 else
5571 ca0132_select_out(codec);
5572 return 1;
5573 }
5574
5575 if (nid == VNID_AMIC1_ASEL) {
5576 ca0132_select_mic(codec);
5577 return 1;
5578 }
5579
5580 /* if effective conditions, then update hw immediately. */
5581 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5582 if (effective) {
5583 int dir = get_amp_direction(kcontrol);
5584 int ch = get_amp_channels(kcontrol);
5585 unsigned long pval;
5586
5587 mutex_lock(&codec->control_mutex);
5588 pval = kcontrol->private_value;
5589 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5590 0, dir);
5591 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5592 kcontrol->private_value = pval;
5593 mutex_unlock(&codec->control_mutex);
5594 }
5595
5596 return ret;
5597 }
5598 /* End of control change helpers. */
5599
ca0132_alt_bass_redirection_xover_set(struct hda_codec * codec,long idx)5600 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec,
5601 long idx)
5602 {
5603 snd_hda_power_up(codec);
5604
5605 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ,
5606 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int));
5607
5608 snd_hda_power_down(codec);
5609 }
5610
5611 /*
5612 * Below I've added controls to mess with the effect levels, I've only enabled
5613 * them on the Sound Blaster Z, but they would probably also work on the
5614 * Chromebook. I figured they were probably tuned specifically for it, and left
5615 * out for a reason.
5616 */
5617
5618 /* Sets DSP effect level from the sliders above the controls */
5619
ca0132_alt_slider_ctl_set(struct hda_codec * codec,hda_nid_t nid,const unsigned int * lookup,int idx)5620 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5621 const unsigned int *lookup, int idx)
5622 {
5623 int i = 0;
5624 unsigned int y;
5625 /*
5626 * For X_BASS, req 2 is actually crossover freq instead of
5627 * effect level
5628 */
5629 if (nid == X_BASS)
5630 y = 2;
5631 else
5632 y = 1;
5633
5634 snd_hda_power_up(codec);
5635 if (nid == XBASS_XOVER) {
5636 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5637 if (ca0132_effects[i].nid == X_BASS)
5638 break;
5639
5640 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5641 ca0132_effects[i].reqs[1],
5642 &(lookup[idx - 1]), sizeof(unsigned int));
5643 } else {
5644 /* Find the actual effect structure */
5645 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5646 if (nid == ca0132_effects[i].nid)
5647 break;
5648
5649 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5650 ca0132_effects[i].reqs[y],
5651 &(lookup[idx]), sizeof(unsigned int));
5652 }
5653
5654 snd_hda_power_down(codec);
5655
5656 return 0;
5657 }
5658
ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5659 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5660 struct snd_ctl_elem_value *ucontrol)
5661 {
5662 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5663 struct ca0132_spec *spec = codec->spec;
5664 long *valp = ucontrol->value.integer.value;
5665 hda_nid_t nid = get_amp_nid(kcontrol);
5666
5667 if (nid == BASS_REDIRECTION_XOVER)
5668 *valp = spec->bass_redirect_xover_freq;
5669 else
5670 *valp = spec->xbass_xover_freq;
5671
5672 return 0;
5673 }
5674
ca0132_alt_slider_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5675 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5676 struct snd_ctl_elem_value *ucontrol)
5677 {
5678 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5679 struct ca0132_spec *spec = codec->spec;
5680 hda_nid_t nid = get_amp_nid(kcontrol);
5681 long *valp = ucontrol->value.integer.value;
5682 int idx = nid - OUT_EFFECT_START_NID;
5683
5684 *valp = spec->fx_ctl_val[idx];
5685 return 0;
5686 }
5687
5688 /*
5689 * The X-bass crossover starts at 10hz, so the min is 1. The
5690 * frequency is set in multiples of 10.
5691 */
ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5692 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5693 struct snd_ctl_elem_info *uinfo)
5694 {
5695 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5696 uinfo->count = 1;
5697 uinfo->value.integer.min = 1;
5698 uinfo->value.integer.max = 100;
5699 uinfo->value.integer.step = 1;
5700
5701 return 0;
5702 }
5703
ca0132_alt_effect_slider_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5704 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5705 struct snd_ctl_elem_info *uinfo)
5706 {
5707 int chs = get_amp_channels(kcontrol);
5708
5709 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5710 uinfo->count = chs == 3 ? 2 : 1;
5711 uinfo->value.integer.min = 0;
5712 uinfo->value.integer.max = 100;
5713 uinfo->value.integer.step = 1;
5714
5715 return 0;
5716 }
5717
ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5718 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5719 struct snd_ctl_elem_value *ucontrol)
5720 {
5721 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5722 struct ca0132_spec *spec = codec->spec;
5723 hda_nid_t nid = get_amp_nid(kcontrol);
5724 long *valp = ucontrol->value.integer.value;
5725 long *cur_val;
5726 int idx;
5727
5728 if (nid == BASS_REDIRECTION_XOVER)
5729 cur_val = &spec->bass_redirect_xover_freq;
5730 else
5731 cur_val = &spec->xbass_xover_freq;
5732
5733 /* any change? */
5734 if (*cur_val == *valp)
5735 return 0;
5736
5737 *cur_val = *valp;
5738
5739 idx = *valp;
5740 if (nid == BASS_REDIRECTION_XOVER)
5741 ca0132_alt_bass_redirection_xover_set(codec, *cur_val);
5742 else
5743 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5744
5745 return 0;
5746 }
5747
ca0132_alt_effect_slider_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5748 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5749 struct snd_ctl_elem_value *ucontrol)
5750 {
5751 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5752 struct ca0132_spec *spec = codec->spec;
5753 hda_nid_t nid = get_amp_nid(kcontrol);
5754 long *valp = ucontrol->value.integer.value;
5755 int idx;
5756
5757 idx = nid - EFFECT_START_NID;
5758 /* any change? */
5759 if (spec->fx_ctl_val[idx] == *valp)
5760 return 0;
5761
5762 spec->fx_ctl_val[idx] = *valp;
5763
5764 idx = *valp;
5765 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5766
5767 return 0;
5768 }
5769
5770
5771 /*
5772 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5773 * only has off or full 30 dB, and didn't like making a volume slider that has
5774 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5775 */
5776 #define MIC_BOOST_NUM_OF_STEPS 4
5777 #define MIC_BOOST_ENUM_MAX_STRLEN 10
5778
ca0132_alt_mic_boost_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5779 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5780 struct snd_ctl_elem_info *uinfo)
5781 {
5782 char *sfx = "dB";
5783 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5784
5785 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5786 uinfo->count = 1;
5787 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5788 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5789 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5790 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5791 strcpy(uinfo->value.enumerated.name, namestr);
5792 return 0;
5793 }
5794
ca0132_alt_mic_boost_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5795 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5796 struct snd_ctl_elem_value *ucontrol)
5797 {
5798 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5799 struct ca0132_spec *spec = codec->spec;
5800
5801 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5802 return 0;
5803 }
5804
ca0132_alt_mic_boost_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5805 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5806 struct snd_ctl_elem_value *ucontrol)
5807 {
5808 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5809 struct ca0132_spec *spec = codec->spec;
5810 int sel = ucontrol->value.enumerated.item[0];
5811 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5812
5813 if (sel >= items)
5814 return 0;
5815
5816 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5817 sel);
5818
5819 spec->mic_boost_enum_val = sel;
5820
5821 if (spec->in_enum_val != REAR_LINE_IN)
5822 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5823
5824 return 1;
5825 }
5826
5827 /*
5828 * Sound BlasterX AE-5 Headphone Gain Controls.
5829 */
5830 #define AE5_HEADPHONE_GAIN_MAX 3
ae5_headphone_gain_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5831 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5832 struct snd_ctl_elem_info *uinfo)
5833 {
5834 char *sfx = " Ohms)";
5835 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5836
5837 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5838 uinfo->count = 1;
5839 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5840 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5841 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5842 sprintf(namestr, "%s %s",
5843 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5844 sfx);
5845 strcpy(uinfo->value.enumerated.name, namestr);
5846 return 0;
5847 }
5848
ae5_headphone_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5849 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5850 struct snd_ctl_elem_value *ucontrol)
5851 {
5852 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5853 struct ca0132_spec *spec = codec->spec;
5854
5855 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5856 return 0;
5857 }
5858
ae5_headphone_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5859 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5860 struct snd_ctl_elem_value *ucontrol)
5861 {
5862 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5863 struct ca0132_spec *spec = codec->spec;
5864 int sel = ucontrol->value.enumerated.item[0];
5865 unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5866
5867 if (sel >= items)
5868 return 0;
5869
5870 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5871 sel);
5872
5873 spec->ae5_headphone_gain_val = sel;
5874
5875 if (spec->out_enum_val == HEADPHONE_OUT)
5876 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5877
5878 return 1;
5879 }
5880
5881 /*
5882 * Sound BlasterX AE-5 sound filter enumerated control.
5883 */
5884 #define AE5_SOUND_FILTER_MAX 3
5885
ae5_sound_filter_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5886 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5887 struct snd_ctl_elem_info *uinfo)
5888 {
5889 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5890
5891 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5892 uinfo->count = 1;
5893 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5894 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5895 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5896 sprintf(namestr, "%s",
5897 ae5_filter_presets[uinfo->value.enumerated.item].name);
5898 strcpy(uinfo->value.enumerated.name, namestr);
5899 return 0;
5900 }
5901
ae5_sound_filter_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5902 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5903 struct snd_ctl_elem_value *ucontrol)
5904 {
5905 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5906 struct ca0132_spec *spec = codec->spec;
5907
5908 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5909 return 0;
5910 }
5911
ae5_sound_filter_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5912 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5913 struct snd_ctl_elem_value *ucontrol)
5914 {
5915 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5916 struct ca0132_spec *spec = codec->spec;
5917 int sel = ucontrol->value.enumerated.item[0];
5918 unsigned int items = AE5_SOUND_FILTER_MAX;
5919
5920 if (sel >= items)
5921 return 0;
5922
5923 codec_dbg(codec, "ae5_sound_filter: %s\n",
5924 ae5_filter_presets[sel].name);
5925
5926 spec->ae5_filter_val = sel;
5927
5928 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5929 ae5_filter_presets[sel].val);
5930
5931 return 1;
5932 }
5933
5934 /*
5935 * Input Select Control for alternative ca0132 codecs. This exists because
5936 * front microphone has no auto-detect, and we need a way to set the rear
5937 * as line-in
5938 */
ca0132_alt_input_source_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5939 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5940 struct snd_ctl_elem_info *uinfo)
5941 {
5942 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5943 uinfo->count = 1;
5944 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5945 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5946 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5947 strcpy(uinfo->value.enumerated.name,
5948 in_src_str[uinfo->value.enumerated.item]);
5949 return 0;
5950 }
5951
ca0132_alt_input_source_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5952 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5953 struct snd_ctl_elem_value *ucontrol)
5954 {
5955 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5956 struct ca0132_spec *spec = codec->spec;
5957
5958 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5959 return 0;
5960 }
5961
ca0132_alt_input_source_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5962 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5963 struct snd_ctl_elem_value *ucontrol)
5964 {
5965 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5966 struct ca0132_spec *spec = codec->spec;
5967 int sel = ucontrol->value.enumerated.item[0];
5968 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5969
5970 /*
5971 * The AE-7 has no front microphone, so limit items to 2: rear mic and
5972 * line-in.
5973 */
5974 if (ca0132_quirk(spec) == QUIRK_AE7)
5975 items = 2;
5976
5977 if (sel >= items)
5978 return 0;
5979
5980 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5981 sel, in_src_str[sel]);
5982
5983 spec->in_enum_val = sel;
5984
5985 ca0132_alt_select_in(codec);
5986
5987 return 1;
5988 }
5989
5990 /* Sound Blaster Z Output Select Control */
ca0132_alt_output_select_get_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5991 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5992 struct snd_ctl_elem_info *uinfo)
5993 {
5994 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5995 uinfo->count = 1;
5996 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5997 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5998 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5999 strcpy(uinfo->value.enumerated.name,
6000 out_type_str[uinfo->value.enumerated.item]);
6001 return 0;
6002 }
6003
ca0132_alt_output_select_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6004 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
6005 struct snd_ctl_elem_value *ucontrol)
6006 {
6007 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6008 struct ca0132_spec *spec = codec->spec;
6009
6010 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
6011 return 0;
6012 }
6013
ca0132_alt_output_select_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6014 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
6015 struct snd_ctl_elem_value *ucontrol)
6016 {
6017 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6018 struct ca0132_spec *spec = codec->spec;
6019 int sel = ucontrol->value.enumerated.item[0];
6020 unsigned int items = NUM_OF_OUTPUTS;
6021 unsigned int auto_jack;
6022
6023 if (sel >= items)
6024 return 0;
6025
6026 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
6027 sel, out_type_str[sel]);
6028
6029 spec->out_enum_val = sel;
6030
6031 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
6032
6033 if (!auto_jack)
6034 ca0132_alt_select_out(codec);
6035
6036 return 1;
6037 }
6038
6039 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */
ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6040 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol,
6041 struct snd_ctl_elem_info *uinfo)
6042 {
6043 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
6044
6045 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6046 uinfo->count = 1;
6047 uinfo->value.enumerated.items = items;
6048 if (uinfo->value.enumerated.item >= items)
6049 uinfo->value.enumerated.item = items - 1;
6050 strcpy(uinfo->value.enumerated.name,
6051 speaker_channel_cfgs[uinfo->value.enumerated.item].name);
6052 return 0;
6053 }
6054
ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6055 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol,
6056 struct snd_ctl_elem_value *ucontrol)
6057 {
6058 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6059 struct ca0132_spec *spec = codec->spec;
6060
6061 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val;
6062 return 0;
6063 }
6064
ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6065 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol,
6066 struct snd_ctl_elem_value *ucontrol)
6067 {
6068 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6069 struct ca0132_spec *spec = codec->spec;
6070 int sel = ucontrol->value.enumerated.item[0];
6071 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
6072
6073 if (sel >= items)
6074 return 0;
6075
6076 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n",
6077 sel, speaker_channel_cfgs[sel].name);
6078
6079 spec->channel_cfg_val = sel;
6080
6081 if (spec->out_enum_val == SPEAKER_OUT)
6082 ca0132_alt_select_out(codec);
6083
6084 return 1;
6085 }
6086
6087 /*
6088 * Smart Volume output setting control. Three different settings, Normal,
6089 * which takes the value from the smart volume slider. The two others, loud
6090 * and night, disregard the slider value and have uneditable values.
6091 */
6092 #define NUM_OF_SVM_SETTINGS 3
6093 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
6094
ca0132_alt_svm_setting_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6095 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
6096 struct snd_ctl_elem_info *uinfo)
6097 {
6098 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6099 uinfo->count = 1;
6100 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
6101 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
6102 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
6103 strcpy(uinfo->value.enumerated.name,
6104 out_svm_set_enum_str[uinfo->value.enumerated.item]);
6105 return 0;
6106 }
6107
ca0132_alt_svm_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6108 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
6109 struct snd_ctl_elem_value *ucontrol)
6110 {
6111 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6112 struct ca0132_spec *spec = codec->spec;
6113
6114 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
6115 return 0;
6116 }
6117
ca0132_alt_svm_setting_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6118 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
6119 struct snd_ctl_elem_value *ucontrol)
6120 {
6121 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6122 struct ca0132_spec *spec = codec->spec;
6123 int sel = ucontrol->value.enumerated.item[0];
6124 unsigned int items = NUM_OF_SVM_SETTINGS;
6125 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
6126 unsigned int tmp;
6127
6128 if (sel >= items)
6129 return 0;
6130
6131 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
6132 sel, out_svm_set_enum_str[sel]);
6133
6134 spec->smart_volume_setting = sel;
6135
6136 switch (sel) {
6137 case 0:
6138 tmp = FLOAT_ZERO;
6139 break;
6140 case 1:
6141 tmp = FLOAT_ONE;
6142 break;
6143 case 2:
6144 tmp = FLOAT_TWO;
6145 break;
6146 default:
6147 tmp = FLOAT_ZERO;
6148 break;
6149 }
6150 /* Req 2 is the Smart Volume Setting req. */
6151 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6152 ca0132_effects[idx].reqs[2], tmp);
6153 return 1;
6154 }
6155
6156 /* Sound Blaster Z EQ preset controls */
ca0132_alt_eq_preset_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6157 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
6158 struct snd_ctl_elem_info *uinfo)
6159 {
6160 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6161
6162 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6163 uinfo->count = 1;
6164 uinfo->value.enumerated.items = items;
6165 if (uinfo->value.enumerated.item >= items)
6166 uinfo->value.enumerated.item = items - 1;
6167 strcpy(uinfo->value.enumerated.name,
6168 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
6169 return 0;
6170 }
6171
ca0132_alt_eq_preset_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6172 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
6173 struct snd_ctl_elem_value *ucontrol)
6174 {
6175 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6176 struct ca0132_spec *spec = codec->spec;
6177
6178 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
6179 return 0;
6180 }
6181
ca0132_alt_eq_preset_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6182 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
6183 struct snd_ctl_elem_value *ucontrol)
6184 {
6185 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6186 struct ca0132_spec *spec = codec->spec;
6187 int i, err = 0;
6188 int sel = ucontrol->value.enumerated.item[0];
6189 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6190
6191 if (sel >= items)
6192 return 0;
6193
6194 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
6195 ca0132_alt_eq_presets[sel].name);
6196 /*
6197 * Idx 0 is default.
6198 * Default needs to qualify with CrystalVoice state.
6199 */
6200 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
6201 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
6202 ca0132_alt_eq_enum.reqs[i],
6203 ca0132_alt_eq_presets[sel].vals[i]);
6204 if (err < 0)
6205 break;
6206 }
6207
6208 if (err >= 0)
6209 spec->eq_preset_val = sel;
6210
6211 return 1;
6212 }
6213
ca0132_voicefx_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6214 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
6215 struct snd_ctl_elem_info *uinfo)
6216 {
6217 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
6218
6219 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6220 uinfo->count = 1;
6221 uinfo->value.enumerated.items = items;
6222 if (uinfo->value.enumerated.item >= items)
6223 uinfo->value.enumerated.item = items - 1;
6224 strcpy(uinfo->value.enumerated.name,
6225 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
6226 return 0;
6227 }
6228
ca0132_voicefx_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6229 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
6230 struct snd_ctl_elem_value *ucontrol)
6231 {
6232 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6233 struct ca0132_spec *spec = codec->spec;
6234
6235 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
6236 return 0;
6237 }
6238
ca0132_voicefx_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6239 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
6240 struct snd_ctl_elem_value *ucontrol)
6241 {
6242 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6243 struct ca0132_spec *spec = codec->spec;
6244 int i, err = 0;
6245 int sel = ucontrol->value.enumerated.item[0];
6246
6247 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
6248 return 0;
6249
6250 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
6251 sel, ca0132_voicefx_presets[sel].name);
6252
6253 /*
6254 * Idx 0 is default.
6255 * Default needs to qualify with CrystalVoice state.
6256 */
6257 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
6258 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
6259 ca0132_voicefx.reqs[i],
6260 ca0132_voicefx_presets[sel].vals[i]);
6261 if (err < 0)
6262 break;
6263 }
6264
6265 if (err >= 0) {
6266 spec->voicefx_val = sel;
6267 /* enable voice fx */
6268 ca0132_voicefx_set(codec, (sel ? 1 : 0));
6269 }
6270
6271 return 1;
6272 }
6273
ca0132_switch_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6274 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
6275 struct snd_ctl_elem_value *ucontrol)
6276 {
6277 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6278 struct ca0132_spec *spec = codec->spec;
6279 hda_nid_t nid = get_amp_nid(kcontrol);
6280 int ch = get_amp_channels(kcontrol);
6281 long *valp = ucontrol->value.integer.value;
6282
6283 /* vnode */
6284 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6285 if (ch & 1) {
6286 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
6287 valp++;
6288 }
6289 if (ch & 2) {
6290 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
6291 valp++;
6292 }
6293 return 0;
6294 }
6295
6296 /* effects, include PE and CrystalVoice */
6297 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
6298 *valp = spec->effects_switch[nid - EFFECT_START_NID];
6299 return 0;
6300 }
6301
6302 /* mic boost */
6303 if (nid == spec->input_pins[0]) {
6304 *valp = spec->cur_mic_boost;
6305 return 0;
6306 }
6307
6308 if (nid == ZXR_HEADPHONE_GAIN) {
6309 *valp = spec->zxr_gain_set;
6310 return 0;
6311 }
6312
6313 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6314 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT];
6315 return 0;
6316 }
6317
6318 if (nid == BASS_REDIRECTION) {
6319 *valp = spec->bass_redirection_val;
6320 return 0;
6321 }
6322
6323 return 0;
6324 }
6325
ca0132_switch_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6326 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
6327 struct snd_ctl_elem_value *ucontrol)
6328 {
6329 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6330 struct ca0132_spec *spec = codec->spec;
6331 hda_nid_t nid = get_amp_nid(kcontrol);
6332 int ch = get_amp_channels(kcontrol);
6333 long *valp = ucontrol->value.integer.value;
6334 int changed = 1;
6335
6336 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
6337 nid, *valp);
6338
6339 snd_hda_power_up(codec);
6340 /* vnode */
6341 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6342 if (ch & 1) {
6343 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
6344 valp++;
6345 }
6346 if (ch & 2) {
6347 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
6348 valp++;
6349 }
6350 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
6351 goto exit;
6352 }
6353
6354 /* PE */
6355 if (nid == PLAY_ENHANCEMENT) {
6356 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6357 changed = ca0132_pe_switch_set(codec);
6358 goto exit;
6359 }
6360
6361 /* CrystalVoice */
6362 if (nid == CRYSTAL_VOICE) {
6363 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6364 changed = ca0132_cvoice_switch_set(codec);
6365 goto exit;
6366 }
6367
6368 /* out and in effects */
6369 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
6370 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
6371 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6372 changed = ca0132_effects_set(codec, nid, *valp);
6373 goto exit;
6374 }
6375
6376 /* mic boost */
6377 if (nid == spec->input_pins[0]) {
6378 spec->cur_mic_boost = *valp;
6379 if (ca0132_use_alt_functions(spec)) {
6380 if (spec->in_enum_val != REAR_LINE_IN)
6381 changed = ca0132_mic_boost_set(codec, *valp);
6382 } else {
6383 /* Mic boost does not apply to Digital Mic */
6384 if (spec->cur_mic_type != DIGITAL_MIC)
6385 changed = ca0132_mic_boost_set(codec, *valp);
6386 }
6387
6388 goto exit;
6389 }
6390
6391 if (nid == ZXR_HEADPHONE_GAIN) {
6392 spec->zxr_gain_set = *valp;
6393 if (spec->cur_out_type == HEADPHONE_OUT)
6394 changed = zxr_headphone_gain_set(codec, *valp);
6395 else
6396 changed = 0;
6397
6398 goto exit;
6399 }
6400
6401 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6402 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp;
6403 if (spec->cur_out_type == SPEAKER_OUT)
6404 ca0132_alt_set_full_range_speaker(codec);
6405
6406 changed = 0;
6407 }
6408
6409 if (nid == BASS_REDIRECTION) {
6410 spec->bass_redirection_val = *valp;
6411 if (spec->cur_out_type == SPEAKER_OUT)
6412 ca0132_alt_surround_set_bass_redirection(codec, *valp);
6413
6414 changed = 0;
6415 }
6416
6417 exit:
6418 snd_hda_power_down(codec);
6419 return changed;
6420 }
6421
6422 /*
6423 * Volume related
6424 */
6425 /*
6426 * Sets the internal DSP decibel level to match the DAC for output, and the
6427 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
6428 * all alternative codecs set DSP playback volume.
6429 */
ca0132_alt_dsp_volume_put(struct hda_codec * codec,hda_nid_t nid)6430 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
6431 {
6432 struct ca0132_spec *spec = codec->spec;
6433 unsigned int dsp_dir;
6434 unsigned int lookup_val;
6435
6436 if (nid == VNID_SPK)
6437 dsp_dir = DSP_VOL_OUT;
6438 else
6439 dsp_dir = DSP_VOL_IN;
6440
6441 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
6442
6443 dspio_set_uint_param(codec,
6444 ca0132_alt_vol_ctls[dsp_dir].mid,
6445 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
6446 float_vol_db_lookup[lookup_val]);
6447
6448 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
6449
6450 dspio_set_uint_param(codec,
6451 ca0132_alt_vol_ctls[dsp_dir].mid,
6452 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
6453 float_vol_db_lookup[lookup_val]);
6454
6455 dspio_set_uint_param(codec,
6456 ca0132_alt_vol_ctls[dsp_dir].mid,
6457 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
6458 }
6459
ca0132_volume_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6460 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
6461 struct snd_ctl_elem_info *uinfo)
6462 {
6463 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6464 struct ca0132_spec *spec = codec->spec;
6465 hda_nid_t nid = get_amp_nid(kcontrol);
6466 int ch = get_amp_channels(kcontrol);
6467 int dir = get_amp_direction(kcontrol);
6468 unsigned long pval;
6469 int err;
6470
6471 switch (nid) {
6472 case VNID_SPK:
6473 /* follow shared_out info */
6474 nid = spec->shared_out_nid;
6475 mutex_lock(&codec->control_mutex);
6476 pval = kcontrol->private_value;
6477 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6478 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6479 kcontrol->private_value = pval;
6480 mutex_unlock(&codec->control_mutex);
6481 break;
6482 case VNID_MIC:
6483 /* follow shared_mic info */
6484 nid = spec->shared_mic_nid;
6485 mutex_lock(&codec->control_mutex);
6486 pval = kcontrol->private_value;
6487 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6488 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6489 kcontrol->private_value = pval;
6490 mutex_unlock(&codec->control_mutex);
6491 break;
6492 default:
6493 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6494 }
6495 return err;
6496 }
6497
ca0132_volume_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6498 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
6499 struct snd_ctl_elem_value *ucontrol)
6500 {
6501 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6502 struct ca0132_spec *spec = codec->spec;
6503 hda_nid_t nid = get_amp_nid(kcontrol);
6504 int ch = get_amp_channels(kcontrol);
6505 long *valp = ucontrol->value.integer.value;
6506
6507 /* store the left and right volume */
6508 if (ch & 1) {
6509 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
6510 valp++;
6511 }
6512 if (ch & 2) {
6513 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
6514 valp++;
6515 }
6516 return 0;
6517 }
6518
ca0132_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6519 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
6520 struct snd_ctl_elem_value *ucontrol)
6521 {
6522 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6523 struct ca0132_spec *spec = codec->spec;
6524 hda_nid_t nid = get_amp_nid(kcontrol);
6525 int ch = get_amp_channels(kcontrol);
6526 long *valp = ucontrol->value.integer.value;
6527 hda_nid_t shared_nid = 0;
6528 bool effective;
6529 int changed = 1;
6530
6531 /* store the left and right volume */
6532 if (ch & 1) {
6533 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
6534 valp++;
6535 }
6536 if (ch & 2) {
6537 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
6538 valp++;
6539 }
6540
6541 /* if effective conditions, then update hw immediately. */
6542 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
6543 if (effective) {
6544 int dir = get_amp_direction(kcontrol);
6545 unsigned long pval;
6546
6547 snd_hda_power_up(codec);
6548 mutex_lock(&codec->control_mutex);
6549 pval = kcontrol->private_value;
6550 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
6551 0, dir);
6552 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6553 kcontrol->private_value = pval;
6554 mutex_unlock(&codec->control_mutex);
6555 snd_hda_power_down(codec);
6556 }
6557
6558 return changed;
6559 }
6560
6561 /*
6562 * This function is the same as the one above, because using an if statement
6563 * inside of the above volume control for the DSP volume would cause too much
6564 * lag. This is a lot more smooth.
6565 */
ca0132_alt_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6566 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
6567 struct snd_ctl_elem_value *ucontrol)
6568 {
6569 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6570 struct ca0132_spec *spec = codec->spec;
6571 hda_nid_t nid = get_amp_nid(kcontrol);
6572 int ch = get_amp_channels(kcontrol);
6573 long *valp = ucontrol->value.integer.value;
6574 hda_nid_t vnid = 0;
6575 int changed;
6576
6577 switch (nid) {
6578 case 0x02:
6579 vnid = VNID_SPK;
6580 break;
6581 case 0x07:
6582 vnid = VNID_MIC;
6583 break;
6584 }
6585
6586 /* store the left and right volume */
6587 if (ch & 1) {
6588 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
6589 valp++;
6590 }
6591 if (ch & 2) {
6592 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6593 valp++;
6594 }
6595
6596 snd_hda_power_up(codec);
6597 ca0132_alt_dsp_volume_put(codec, vnid);
6598 mutex_lock(&codec->control_mutex);
6599 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6600 mutex_unlock(&codec->control_mutex);
6601 snd_hda_power_down(codec);
6602
6603 return changed;
6604 }
6605
ca0132_volume_tlv(struct snd_kcontrol * kcontrol,int op_flag,unsigned int size,unsigned int __user * tlv)6606 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
6607 unsigned int size, unsigned int __user *tlv)
6608 {
6609 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6610 struct ca0132_spec *spec = codec->spec;
6611 hda_nid_t nid = get_amp_nid(kcontrol);
6612 int ch = get_amp_channels(kcontrol);
6613 int dir = get_amp_direction(kcontrol);
6614 unsigned long pval;
6615 int err;
6616
6617 switch (nid) {
6618 case VNID_SPK:
6619 /* follow shared_out tlv */
6620 nid = spec->shared_out_nid;
6621 mutex_lock(&codec->control_mutex);
6622 pval = kcontrol->private_value;
6623 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6624 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6625 kcontrol->private_value = pval;
6626 mutex_unlock(&codec->control_mutex);
6627 break;
6628 case VNID_MIC:
6629 /* follow shared_mic tlv */
6630 nid = spec->shared_mic_nid;
6631 mutex_lock(&codec->control_mutex);
6632 pval = kcontrol->private_value;
6633 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6634 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6635 kcontrol->private_value = pval;
6636 mutex_unlock(&codec->control_mutex);
6637 break;
6638 default:
6639 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6640 }
6641 return err;
6642 }
6643
6644 /* Add volume slider control for effect level */
ca0132_alt_add_effect_slider(struct hda_codec * codec,hda_nid_t nid,const char * pfx,int dir)6645 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6646 const char *pfx, int dir)
6647 {
6648 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6649 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6650 struct snd_kcontrol_new knew =
6651 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6652
6653 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
6654
6655 knew.tlv.c = NULL;
6656
6657 switch (nid) {
6658 case XBASS_XOVER:
6659 knew.info = ca0132_alt_xbass_xover_slider_info;
6660 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6661 knew.put = ca0132_alt_xbass_xover_slider_put;
6662 break;
6663 default:
6664 knew.info = ca0132_alt_effect_slider_info;
6665 knew.get = ca0132_alt_slider_ctl_get;
6666 knew.put = ca0132_alt_effect_slider_put;
6667 knew.private_value =
6668 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6669 break;
6670 }
6671
6672 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6673 }
6674
6675 /*
6676 * Added FX: prefix for the alternative codecs, because otherwise the surround
6677 * effect would conflict with the Surround sound volume control. Also seems more
6678 * clear as to what the switches do. Left alone for others.
6679 */
add_fx_switch(struct hda_codec * codec,hda_nid_t nid,const char * pfx,int dir)6680 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6681 const char *pfx, int dir)
6682 {
6683 struct ca0132_spec *spec = codec->spec;
6684 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6685 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6686 struct snd_kcontrol_new knew =
6687 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
6688 /* If using alt_controls, add FX: prefix. But, don't add FX:
6689 * prefix to OutFX or InFX enable controls.
6690 */
6691 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID))
6692 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
6693 else
6694 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6695
6696 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6697 }
6698
add_voicefx(struct hda_codec * codec)6699 static int add_voicefx(struct hda_codec *codec)
6700 {
6701 struct snd_kcontrol_new knew =
6702 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6703 VOICEFX, 1, 0, HDA_INPUT);
6704 knew.info = ca0132_voicefx_info;
6705 knew.get = ca0132_voicefx_get;
6706 knew.put = ca0132_voicefx_put;
6707 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
6708 }
6709
6710 /* Create the EQ Preset control */
add_ca0132_alt_eq_presets(struct hda_codec * codec)6711 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6712 {
6713 struct snd_kcontrol_new knew =
6714 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6715 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6716 knew.info = ca0132_alt_eq_preset_info;
6717 knew.get = ca0132_alt_eq_preset_get;
6718 knew.put = ca0132_alt_eq_preset_put;
6719 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6720 snd_ctl_new1(&knew, codec));
6721 }
6722
6723 /*
6724 * Add enumerated control for the three different settings of the smart volume
6725 * output effect. Normal just uses the slider value, and loud and night are
6726 * their own things that ignore that value.
6727 */
ca0132_alt_add_svm_enum(struct hda_codec * codec)6728 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6729 {
6730 struct snd_kcontrol_new knew =
6731 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6732 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6733 knew.info = ca0132_alt_svm_setting_info;
6734 knew.get = ca0132_alt_svm_setting_get;
6735 knew.put = ca0132_alt_svm_setting_put;
6736 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6737 snd_ctl_new1(&knew, codec));
6738
6739 }
6740
6741 /*
6742 * Create an Output Select enumerated control for codecs with surround
6743 * out capabilities.
6744 */
ca0132_alt_add_output_enum(struct hda_codec * codec)6745 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6746 {
6747 struct snd_kcontrol_new knew =
6748 HDA_CODEC_MUTE_MONO("Output Select",
6749 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6750 knew.info = ca0132_alt_output_select_get_info;
6751 knew.get = ca0132_alt_output_select_get;
6752 knew.put = ca0132_alt_output_select_put;
6753 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6754 snd_ctl_new1(&knew, codec));
6755 }
6756
6757 /*
6758 * Add a control for selecting channel count on speaker output. Setting this
6759 * allows the DSP to do bass redirection and channel upmixing on surround
6760 * configurations.
6761 */
ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec * codec)6762 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec)
6763 {
6764 struct snd_kcontrol_new knew =
6765 HDA_CODEC_MUTE_MONO("Surround Channel Config",
6766 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT);
6767 knew.info = ca0132_alt_speaker_channel_cfg_get_info;
6768 knew.get = ca0132_alt_speaker_channel_cfg_get;
6769 knew.put = ca0132_alt_speaker_channel_cfg_put;
6770 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM,
6771 snd_ctl_new1(&knew, codec));
6772 }
6773
6774 /*
6775 * Full range front stereo and rear surround switches. When these are set to
6776 * full range, the lower frequencies from these channels are no longer
6777 * redirected to the LFE channel.
6778 */
ca0132_alt_add_front_full_range_switch(struct hda_codec * codec)6779 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec)
6780 {
6781 struct snd_kcontrol_new knew =
6782 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers",
6783 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT);
6784
6785 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT,
6786 snd_ctl_new1(&knew, codec));
6787 }
6788
ca0132_alt_add_rear_full_range_switch(struct hda_codec * codec)6789 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec)
6790 {
6791 struct snd_kcontrol_new knew =
6792 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers",
6793 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT);
6794
6795 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR,
6796 snd_ctl_new1(&knew, codec));
6797 }
6798
6799 /*
6800 * Bass redirection redirects audio below the crossover frequency to the LFE
6801 * channel on speakers that are set as not being full-range. On configurations
6802 * without an LFE channel, it does nothing. Bass redirection seems to be the
6803 * replacement for X-Bass on configurations with an LFE channel.
6804 */
ca0132_alt_add_bass_redirection_crossover(struct hda_codec * codec)6805 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec)
6806 {
6807 const char *namestr = "Bass Redirection Crossover";
6808 struct snd_kcontrol_new knew =
6809 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0,
6810 HDA_OUTPUT);
6811
6812 knew.tlv.c = NULL;
6813 knew.info = ca0132_alt_xbass_xover_slider_info;
6814 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6815 knew.put = ca0132_alt_xbass_xover_slider_put;
6816
6817 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER,
6818 snd_ctl_new1(&knew, codec));
6819 }
6820
ca0132_alt_add_bass_redirection_switch(struct hda_codec * codec)6821 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec)
6822 {
6823 const char *namestr = "Bass Redirection";
6824 struct snd_kcontrol_new knew =
6825 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1,
6826 HDA_OUTPUT);
6827
6828 return snd_hda_ctl_add(codec, BASS_REDIRECTION,
6829 snd_ctl_new1(&knew, codec));
6830 }
6831
6832 /*
6833 * Create an Input Source enumerated control for the alternate ca0132 codecs
6834 * because the front microphone has no auto-detect, and Line-in has to be set
6835 * somehow.
6836 */
ca0132_alt_add_input_enum(struct hda_codec * codec)6837 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6838 {
6839 struct snd_kcontrol_new knew =
6840 HDA_CODEC_MUTE_MONO("Input Source",
6841 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6842 knew.info = ca0132_alt_input_source_info;
6843 knew.get = ca0132_alt_input_source_get;
6844 knew.put = ca0132_alt_input_source_put;
6845 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6846 snd_ctl_new1(&knew, codec));
6847 }
6848
6849 /*
6850 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6851 * more control than the original mic boost, which is either full 30dB or off.
6852 */
ca0132_alt_add_mic_boost_enum(struct hda_codec * codec)6853 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6854 {
6855 struct snd_kcontrol_new knew =
6856 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6857 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6858 knew.info = ca0132_alt_mic_boost_info;
6859 knew.get = ca0132_alt_mic_boost_get;
6860 knew.put = ca0132_alt_mic_boost_put;
6861 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6862 snd_ctl_new1(&knew, codec));
6863
6864 }
6865
6866 /*
6867 * Add headphone gain enumerated control for the AE-5. This switches between
6868 * three modes, low, medium, and high. When non-headphone outputs are selected,
6869 * it is automatically set to high. This is the same behavior as Windows.
6870 */
ae5_add_headphone_gain_enum(struct hda_codec * codec)6871 static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6872 {
6873 struct snd_kcontrol_new knew =
6874 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
6875 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6876 knew.info = ae5_headphone_gain_info;
6877 knew.get = ae5_headphone_gain_get;
6878 knew.put = ae5_headphone_gain_put;
6879 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6880 snd_ctl_new1(&knew, codec));
6881 }
6882
6883 /*
6884 * Add sound filter enumerated control for the AE-5. This adds three different
6885 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6886 * read into it, it changes the DAC's interpolation filter.
6887 */
ae5_add_sound_filter_enum(struct hda_codec * codec)6888 static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6889 {
6890 struct snd_kcontrol_new knew =
6891 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
6892 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6893 knew.info = ae5_sound_filter_info;
6894 knew.get = ae5_sound_filter_get;
6895 knew.put = ae5_sound_filter_put;
6896 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6897 snd_ctl_new1(&knew, codec));
6898 }
6899
zxr_add_headphone_gain_switch(struct hda_codec * codec)6900 static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6901 {
6902 struct snd_kcontrol_new knew =
6903 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6904 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6905
6906 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6907 snd_ctl_new1(&knew, codec));
6908 }
6909
6910 /*
6911 * Need to create follower controls for the alternate codecs that have surround
6912 * capabilities.
6913 */
6914 static const char * const ca0132_alt_follower_pfxs[] = {
6915 "Front", "Surround", "Center", "LFE", NULL,
6916 };
6917
6918 /*
6919 * Also need special channel map, because the default one is incorrect.
6920 * I think this has to do with the pin for rear surround being 0x11,
6921 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6922 */
6923 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
6924 { .channels = 2,
6925 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6926 { .channels = 4,
6927 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6928 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6929 { .channels = 6,
6930 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6931 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6932 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6933 { }
6934 };
6935
6936 /* Add the correct chmap for streams with 6 channels. */
ca0132_alt_add_chmap_ctls(struct hda_codec * codec)6937 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6938 {
6939 int err = 0;
6940 struct hda_pcm *pcm;
6941
6942 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6943 struct hda_pcm_stream *hinfo =
6944 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6945 struct snd_pcm_chmap *chmap;
6946 const struct snd_pcm_chmap_elem *elem;
6947
6948 elem = ca0132_alt_chmaps;
6949 if (hinfo->channels_max == 6) {
6950 err = snd_pcm_add_chmap_ctls(pcm->pcm,
6951 SNDRV_PCM_STREAM_PLAYBACK,
6952 elem, hinfo->channels_max, 0, &chmap);
6953 if (err < 0)
6954 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6955 }
6956 }
6957 }
6958
6959 /*
6960 * When changing Node IDs for Mixer Controls below, make sure to update
6961 * Node IDs in ca0132_config() as well.
6962 */
6963 static const struct snd_kcontrol_new ca0132_mixer[] = {
6964 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6965 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6966 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6967 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6968 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6969 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6970 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6971 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6972 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6973 0x12, 1, HDA_INPUT),
6974 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6975 VNID_HP_SEL, 1, HDA_OUTPUT),
6976 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6977 VNID_AMIC1_SEL, 1, HDA_INPUT),
6978 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6979 VNID_HP_ASEL, 1, HDA_OUTPUT),
6980 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6981 VNID_AMIC1_ASEL, 1, HDA_INPUT),
6982 { } /* end */
6983 };
6984
6985 /*
6986 * Desktop specific control mixer. Removes auto-detect for mic, and adds
6987 * surround controls. Also sets both the Front Playback and Capture Volume
6988 * controls to alt so they set the DSP's decibel level.
6989 */
6990 static const struct snd_kcontrol_new desktop_mixer[] = {
6991 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6992 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6993 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6994 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6995 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6996 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6997 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6998 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6999 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
7000 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
7001 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
7002 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
7003 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
7004 VNID_HP_ASEL, 1, HDA_OUTPUT),
7005 { } /* end */
7006 };
7007
7008 /*
7009 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
7010 * because it doesn't set decibel levels for the DSP for capture.
7011 */
7012 static const struct snd_kcontrol_new r3di_mixer[] = {
7013 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
7014 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
7015 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
7016 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
7017 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
7018 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
7019 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
7020 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
7021 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
7022 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
7023 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
7024 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
7025 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
7026 VNID_HP_ASEL, 1, HDA_OUTPUT),
7027 { } /* end */
7028 };
7029
ca0132_build_controls(struct hda_codec * codec)7030 static int ca0132_build_controls(struct hda_codec *codec)
7031 {
7032 struct ca0132_spec *spec = codec->spec;
7033 int i, num_fx, num_sliders;
7034 int err = 0;
7035
7036 /* Add Mixer controls */
7037 for (i = 0; i < spec->num_mixers; i++) {
7038 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
7039 if (err < 0)
7040 return err;
7041 }
7042 /* Setup vmaster with surround followers for desktop ca0132 devices */
7043 if (ca0132_use_alt_functions(spec)) {
7044 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
7045 spec->tlv);
7046 snd_hda_add_vmaster(codec, "Master Playback Volume",
7047 spec->tlv, ca0132_alt_follower_pfxs,
7048 "Playback Volume", 0);
7049 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
7050 NULL, ca0132_alt_follower_pfxs,
7051 "Playback Switch",
7052 true, 0, &spec->vmaster_mute.sw_kctl);
7053 if (err < 0)
7054 return err;
7055 }
7056
7057 /* Add in and out effects controls.
7058 * VoiceFX, PE and CrystalVoice are added separately.
7059 */
7060 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7061 for (i = 0; i < num_fx; i++) {
7062 /* Desktop cards break if Echo Cancellation is used. */
7063 if (ca0132_use_pci_mmio(spec)) {
7064 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
7065 OUT_EFFECTS_COUNT))
7066 continue;
7067 }
7068
7069 err = add_fx_switch(codec, ca0132_effects[i].nid,
7070 ca0132_effects[i].name,
7071 ca0132_effects[i].direct);
7072 if (err < 0)
7073 return err;
7074 }
7075 /*
7076 * If codec has use_alt_controls set to true, add effect level sliders,
7077 * EQ presets, and Smart Volume presets. Also, change names to add FX
7078 * prefix, and change PlayEnhancement and CrystalVoice to match.
7079 */
7080 if (ca0132_use_alt_controls(spec)) {
7081 err = ca0132_alt_add_svm_enum(codec);
7082 if (err < 0)
7083 return err;
7084
7085 err = add_ca0132_alt_eq_presets(codec);
7086 if (err < 0)
7087 return err;
7088
7089 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7090 "Enable OutFX", 0);
7091 if (err < 0)
7092 return err;
7093
7094 err = add_fx_switch(codec, CRYSTAL_VOICE,
7095 "Enable InFX", 1);
7096 if (err < 0)
7097 return err;
7098
7099 num_sliders = OUT_EFFECTS_COUNT - 1;
7100 for (i = 0; i < num_sliders; i++) {
7101 err = ca0132_alt_add_effect_slider(codec,
7102 ca0132_effects[i].nid,
7103 ca0132_effects[i].name,
7104 ca0132_effects[i].direct);
7105 if (err < 0)
7106 return err;
7107 }
7108
7109 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
7110 "X-Bass Crossover", EFX_DIR_OUT);
7111
7112 if (err < 0)
7113 return err;
7114 } else {
7115 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7116 "PlayEnhancement", 0);
7117 if (err < 0)
7118 return err;
7119
7120 err = add_fx_switch(codec, CRYSTAL_VOICE,
7121 "CrystalVoice", 1);
7122 if (err < 0)
7123 return err;
7124 }
7125 err = add_voicefx(codec);
7126 if (err < 0)
7127 return err;
7128
7129 /*
7130 * If the codec uses alt_functions, you need the enumerated controls
7131 * to select the new outputs and inputs, plus add the new mic boost
7132 * setting control.
7133 */
7134 if (ca0132_use_alt_functions(spec)) {
7135 err = ca0132_alt_add_output_enum(codec);
7136 if (err < 0)
7137 return err;
7138 err = ca0132_alt_add_speaker_channel_cfg_enum(codec);
7139 if (err < 0)
7140 return err;
7141 err = ca0132_alt_add_front_full_range_switch(codec);
7142 if (err < 0)
7143 return err;
7144 err = ca0132_alt_add_rear_full_range_switch(codec);
7145 if (err < 0)
7146 return err;
7147 err = ca0132_alt_add_bass_redirection_crossover(codec);
7148 if (err < 0)
7149 return err;
7150 err = ca0132_alt_add_bass_redirection_switch(codec);
7151 if (err < 0)
7152 return err;
7153 err = ca0132_alt_add_mic_boost_enum(codec);
7154 if (err < 0)
7155 return err;
7156 /*
7157 * ZxR only has microphone input, there is no front panel
7158 * header on the card, and aux-in is handled by the DBPro board.
7159 */
7160 if (ca0132_quirk(spec) != QUIRK_ZXR) {
7161 err = ca0132_alt_add_input_enum(codec);
7162 if (err < 0)
7163 return err;
7164 }
7165 }
7166
7167 switch (ca0132_quirk(spec)) {
7168 case QUIRK_AE5:
7169 case QUIRK_AE7:
7170 err = ae5_add_headphone_gain_enum(codec);
7171 if (err < 0)
7172 return err;
7173 err = ae5_add_sound_filter_enum(codec);
7174 if (err < 0)
7175 return err;
7176 break;
7177 case QUIRK_ZXR:
7178 err = zxr_add_headphone_gain_switch(codec);
7179 if (err < 0)
7180 return err;
7181 break;
7182 default:
7183 break;
7184 }
7185
7186 #ifdef ENABLE_TUNING_CONTROLS
7187 add_tuning_ctls(codec);
7188 #endif
7189
7190 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
7191 if (err < 0)
7192 return err;
7193
7194 if (spec->dig_out) {
7195 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7196 spec->dig_out);
7197 if (err < 0)
7198 return err;
7199 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
7200 if (err < 0)
7201 return err;
7202 /* spec->multiout.share_spdif = 1; */
7203 }
7204
7205 if (spec->dig_in) {
7206 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7207 if (err < 0)
7208 return err;
7209 }
7210
7211 if (ca0132_use_alt_functions(spec))
7212 ca0132_alt_add_chmap_ctls(codec);
7213
7214 return 0;
7215 }
7216
dbpro_build_controls(struct hda_codec * codec)7217 static int dbpro_build_controls(struct hda_codec *codec)
7218 {
7219 struct ca0132_spec *spec = codec->spec;
7220 int err = 0;
7221
7222 if (spec->dig_out) {
7223 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7224 spec->dig_out);
7225 if (err < 0)
7226 return err;
7227 }
7228
7229 if (spec->dig_in) {
7230 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7231 if (err < 0)
7232 return err;
7233 }
7234
7235 return 0;
7236 }
7237
7238 /*
7239 * PCM
7240 */
7241 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
7242 .substreams = 1,
7243 .channels_min = 2,
7244 .channels_max = 6,
7245 .ops = {
7246 .prepare = ca0132_playback_pcm_prepare,
7247 .cleanup = ca0132_playback_pcm_cleanup,
7248 .get_delay = ca0132_playback_pcm_delay,
7249 },
7250 };
7251
7252 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
7253 .substreams = 1,
7254 .channels_min = 2,
7255 .channels_max = 2,
7256 .ops = {
7257 .prepare = ca0132_capture_pcm_prepare,
7258 .cleanup = ca0132_capture_pcm_cleanup,
7259 .get_delay = ca0132_capture_pcm_delay,
7260 },
7261 };
7262
7263 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
7264 .substreams = 1,
7265 .channels_min = 2,
7266 .channels_max = 2,
7267 .ops = {
7268 .open = ca0132_dig_playback_pcm_open,
7269 .close = ca0132_dig_playback_pcm_close,
7270 .prepare = ca0132_dig_playback_pcm_prepare,
7271 .cleanup = ca0132_dig_playback_pcm_cleanup
7272 },
7273 };
7274
7275 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
7276 .substreams = 1,
7277 .channels_min = 2,
7278 .channels_max = 2,
7279 };
7280
ca0132_build_pcms(struct hda_codec * codec)7281 static int ca0132_build_pcms(struct hda_codec *codec)
7282 {
7283 struct ca0132_spec *spec = codec->spec;
7284 struct hda_pcm *info;
7285
7286 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
7287 if (!info)
7288 return -ENOMEM;
7289 if (ca0132_use_alt_functions(spec)) {
7290 info->own_chmap = true;
7291 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
7292 = ca0132_alt_chmaps;
7293 }
7294 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
7295 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
7296 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
7297 spec->multiout.max_channels;
7298 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7299 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7300 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7301
7302 /* With the DSP enabled, desktops don't use this ADC. */
7303 if (!ca0132_use_alt_functions(spec)) {
7304 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
7305 if (!info)
7306 return -ENOMEM;
7307 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7308 ca0132_pcm_analog_capture;
7309 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7310 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
7311 }
7312
7313 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
7314 if (!info)
7315 return -ENOMEM;
7316 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7317 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7318 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
7319
7320 if (!spec->dig_out && !spec->dig_in)
7321 return 0;
7322
7323 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7324 if (!info)
7325 return -ENOMEM;
7326 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7327 if (spec->dig_out) {
7328 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7329 ca0132_pcm_digital_playback;
7330 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7331 }
7332 if (spec->dig_in) {
7333 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7334 ca0132_pcm_digital_capture;
7335 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7336 }
7337
7338 return 0;
7339 }
7340
dbpro_build_pcms(struct hda_codec * codec)7341 static int dbpro_build_pcms(struct hda_codec *codec)
7342 {
7343 struct ca0132_spec *spec = codec->spec;
7344 struct hda_pcm *info;
7345
7346 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
7347 if (!info)
7348 return -ENOMEM;
7349 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7350 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7351 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7352
7353
7354 if (!spec->dig_out && !spec->dig_in)
7355 return 0;
7356
7357 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7358 if (!info)
7359 return -ENOMEM;
7360 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7361 if (spec->dig_out) {
7362 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7363 ca0132_pcm_digital_playback;
7364 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7365 }
7366 if (spec->dig_in) {
7367 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7368 ca0132_pcm_digital_capture;
7369 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7370 }
7371
7372 return 0;
7373 }
7374
init_output(struct hda_codec * codec,hda_nid_t pin,hda_nid_t dac)7375 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
7376 {
7377 if (pin) {
7378 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
7379 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
7380 snd_hda_codec_write(codec, pin, 0,
7381 AC_VERB_SET_AMP_GAIN_MUTE,
7382 AMP_OUT_UNMUTE);
7383 }
7384 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
7385 snd_hda_codec_write(codec, dac, 0,
7386 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
7387 }
7388
init_input(struct hda_codec * codec,hda_nid_t pin,hda_nid_t adc)7389 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
7390 {
7391 if (pin) {
7392 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
7393 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
7394 snd_hda_codec_write(codec, pin, 0,
7395 AC_VERB_SET_AMP_GAIN_MUTE,
7396 AMP_IN_UNMUTE(0));
7397 }
7398 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
7399 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
7400 AMP_IN_UNMUTE(0));
7401
7402 /* init to 0 dB and unmute. */
7403 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7404 HDA_AMP_VOLMASK, 0x5a);
7405 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7406 HDA_AMP_MUTE, 0);
7407 }
7408 }
7409
refresh_amp_caps(struct hda_codec * codec,hda_nid_t nid,int dir)7410 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
7411 {
7412 unsigned int caps;
7413
7414 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
7415 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
7416 snd_hda_override_amp_caps(codec, nid, dir, caps);
7417 }
7418
7419 /*
7420 * Switch between Digital built-in mic and analog mic.
7421 */
ca0132_set_dmic(struct hda_codec * codec,int enable)7422 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
7423 {
7424 struct ca0132_spec *spec = codec->spec;
7425 unsigned int tmp;
7426 u8 val;
7427 unsigned int oldval;
7428
7429 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
7430
7431 oldval = stop_mic1(codec);
7432 ca0132_set_vipsource(codec, 0);
7433 if (enable) {
7434 /* set DMic input as 2-ch */
7435 tmp = FLOAT_TWO;
7436 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7437
7438 val = spec->dmic_ctl;
7439 val |= 0x80;
7440 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7441 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7442
7443 if (!(spec->dmic_ctl & 0x20))
7444 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
7445 } else {
7446 /* set AMic input as mono */
7447 tmp = FLOAT_ONE;
7448 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7449
7450 val = spec->dmic_ctl;
7451 /* clear bit7 and bit5 to disable dmic */
7452 val &= 0x5f;
7453 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7454 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7455
7456 if (!(spec->dmic_ctl & 0x20))
7457 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
7458 }
7459 ca0132_set_vipsource(codec, 1);
7460 resume_mic1(codec, oldval);
7461 }
7462
7463 /*
7464 * Initialization for Digital Mic.
7465 */
ca0132_init_dmic(struct hda_codec * codec)7466 static void ca0132_init_dmic(struct hda_codec *codec)
7467 {
7468 struct ca0132_spec *spec = codec->spec;
7469 u8 val;
7470
7471 /* Setup Digital Mic here, but don't enable.
7472 * Enable based on jack detect.
7473 */
7474
7475 /* MCLK uses MPIO1, set to enable.
7476 * Bit 2-0: MPIO select
7477 * Bit 3: set to disable
7478 * Bit 7-4: reserved
7479 */
7480 val = 0x01;
7481 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7482 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
7483
7484 /* Data1 uses MPIO3. Data2 not use
7485 * Bit 2-0: Data1 MPIO select
7486 * Bit 3: set disable Data1
7487 * Bit 6-4: Data2 MPIO select
7488 * Bit 7: set disable Data2
7489 */
7490 val = 0x83;
7491 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7492 VENDOR_CHIPIO_DMIC_PIN_SET, val);
7493
7494 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
7495 * Bit 3-0: Channel mask
7496 * Bit 4: set for 48KHz, clear for 32KHz
7497 * Bit 5: mode
7498 * Bit 6: set to select Data2, clear for Data1
7499 * Bit 7: set to enable DMic, clear for AMic
7500 */
7501 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4)
7502 val = 0x33;
7503 else
7504 val = 0x23;
7505 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
7506 spec->dmic_ctl = val;
7507 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7508 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7509 }
7510
7511 /*
7512 * Initialization for Analog Mic 2
7513 */
ca0132_init_analog_mic2(struct hda_codec * codec)7514 static void ca0132_init_analog_mic2(struct hda_codec *codec)
7515 {
7516 struct ca0132_spec *spec = codec->spec;
7517
7518 mutex_lock(&spec->chipio_mutex);
7519
7520 chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00);
7521 chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00);
7522
7523 mutex_unlock(&spec->chipio_mutex);
7524 }
7525
ca0132_refresh_widget_caps(struct hda_codec * codec)7526 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
7527 {
7528 struct ca0132_spec *spec = codec->spec;
7529 int i;
7530
7531 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7532 snd_hda_codec_update_widgets(codec);
7533
7534 for (i = 0; i < spec->multiout.num_dacs; i++)
7535 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
7536
7537 for (i = 0; i < spec->num_outputs; i++)
7538 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
7539
7540 for (i = 0; i < spec->num_inputs; i++) {
7541 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
7542 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
7543 }
7544 }
7545
7546
7547 /* If there is an active channel for some reason, find it and free it. */
ca0132_alt_free_active_dma_channels(struct hda_codec * codec)7548 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec)
7549 {
7550 unsigned int i, tmp;
7551 int status;
7552
7553 /* Read active DSPDMAC channel register. */
7554 status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp);
7555 if (status >= 0) {
7556 /* AND against 0xfff to get the active channel bits. */
7557 tmp = tmp & 0xfff;
7558
7559 /* If there are no active channels, nothing to free. */
7560 if (!tmp)
7561 return;
7562 } else {
7563 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n",
7564 __func__);
7565 return;
7566 }
7567
7568 /*
7569 * Check each DSP DMA channel for activity, and if the channel is
7570 * active, free it.
7571 */
7572 for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) {
7573 if (dsp_is_dma_active(codec, i)) {
7574 status = dspio_free_dma_chan(codec, i);
7575 if (status < 0)
7576 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n",
7577 __func__, i);
7578 }
7579 }
7580 }
7581
7582 /*
7583 * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in
7584 * use, audio is no longer routed directly to the DAC/ADC from the HDA stream.
7585 * Instead, audio is now routed through the DSP's DMA controllers, which
7586 * the DSP is tasked with setting up itself. Through debugging, it seems the
7587 * cause of most of the no-audio on startup issues were due to improperly
7588 * configured DSP DMA channels.
7589 *
7590 * Normally, the DSP configures these the first time an HDA audio stream is
7591 * started post DSP firmware download. That is why creating a 'dummy' stream
7592 * worked in fixing the audio in some cases. This works most of the time, but
7593 * sometimes if a stream is started/stopped before the DSP can setup the DMA
7594 * configuration registers, it ends up in a broken state. Issues can also
7595 * arise if streams are started in an unusual order, i.e the audio output dma
7596 * channel being sandwiched between the mic1 and mic2 dma channels.
7597 *
7598 * The solution to this is to make sure that the DSP has no DMA channels
7599 * in use post DSP firmware download, and then to manually start each default
7600 * DSP stream that uses the DMA channels. These are 0x0c, the audio output
7601 * stream, 0x03, analog mic 1, and 0x04, analog mic 2.
7602 */
ca0132_alt_start_dsp_audio_streams(struct hda_codec * codec)7603 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec)
7604 {
7605 static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 };
7606 struct ca0132_spec *spec = codec->spec;
7607 unsigned int i, tmp;
7608
7609 /*
7610 * Check if any of the default streams are active, and if they are,
7611 * stop them.
7612 */
7613 mutex_lock(&spec->chipio_mutex);
7614
7615 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7616 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp);
7617
7618 if (tmp) {
7619 chipio_set_stream_control(codec,
7620 dsp_dma_stream_ids[i], 0);
7621 }
7622 }
7623
7624 mutex_unlock(&spec->chipio_mutex);
7625
7626 /*
7627 * If all DSP streams are inactive, there should be no active DSP DMA
7628 * channels. Check and make sure this is the case, and if it isn't,
7629 * free any active channels.
7630 */
7631 ca0132_alt_free_active_dma_channels(codec);
7632
7633 mutex_lock(&spec->chipio_mutex);
7634
7635 /* Make sure stream 0x0c is six channels. */
7636 chipio_set_stream_channels(codec, 0x0c, 6);
7637
7638 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7639 chipio_set_stream_control(codec,
7640 dsp_dma_stream_ids[i], 1);
7641
7642 /* Give the DSP some time to setup the DMA channel. */
7643 msleep(75);
7644 }
7645
7646 mutex_unlock(&spec->chipio_mutex);
7647 }
7648
7649 /*
7650 * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio
7651 * router', where each entry represents a 48khz audio channel, with a format
7652 * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number
7653 * value. The 2-bit number value is seemingly 0 if inactive, 1 if active,
7654 * and 3 if it's using Sample Rate Converter ports.
7655 * An example is:
7656 * 0x0001f8c0
7657 * In this case, f8 is the destination, and c0 is the source. The number value
7658 * is 1.
7659 * This region of memory is normally managed internally by the 8051, where
7660 * the region of exram memory from 0x1477-0x1575 has each byte represent an
7661 * entry within the 0x190000 range, and when a range of entries is in use, the
7662 * ending value is overwritten with 0xff.
7663 * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO
7664 * streamID's, where each entry is a starting 0x190000 port offset.
7665 * 0x159d in exram is the same as 0x1578, except it contains the ending port
7666 * offset for the corresponding streamID.
7667 *
7668 * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by
7669 * the 8051, then manually overwritten to remap the ports to work with the
7670 * new DACs.
7671 *
7672 * Currently known portID's:
7673 * 0x00-0x1f: HDA audio stream input/output ports.
7674 * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to
7675 * have the lower-nibble set to 0x1, 0x2, and 0x9.
7676 * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned.
7677 * 0xe0-0xff: DAC/ADC audio input/output ports.
7678 *
7679 * Currently known streamID's:
7680 * 0x03: Mic1 ADC to DSP.
7681 * 0x04: Mic2 ADC to DSP.
7682 * 0x05: HDA node 0x02 audio stream to DSP.
7683 * 0x0f: DSP Mic exit to HDA node 0x07.
7684 * 0x0c: DSP processed audio to DACs.
7685 * 0x14: DAC0, front L/R.
7686 *
7687 * It is possible to route the HDA audio streams directly to the DAC and
7688 * bypass the DSP entirely, with the only downside being that since the DSP
7689 * does volume control, the only volume control you'll get is through PCM on
7690 * the PC side, in the same way volume is handled for optical out. This may be
7691 * useful for debugging.
7692 */
chipio_remap_stream(struct hda_codec * codec,const struct chipio_stream_remap_data * remap_data)7693 static void chipio_remap_stream(struct hda_codec *codec,
7694 const struct chipio_stream_remap_data *remap_data)
7695 {
7696 unsigned int i, stream_offset;
7697
7698 /* Get the starting port for the stream to be remapped. */
7699 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7700 &stream_offset);
7701
7702 /*
7703 * Check if the stream's port value is 0xff, because the 8051 may not
7704 * have gotten around to setting up the stream yet. Wait until it's
7705 * setup to remap it's ports.
7706 */
7707 if (stream_offset == 0xff) {
7708 for (i = 0; i < 5; i++) {
7709 msleep(25);
7710
7711 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7712 &stream_offset);
7713
7714 if (stream_offset != 0xff)
7715 break;
7716 }
7717 }
7718
7719 if (stream_offset == 0xff) {
7720 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n",
7721 __func__, remap_data->stream_id);
7722 return;
7723 }
7724
7725 /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */
7726 stream_offset *= 0x04;
7727 stream_offset += 0x190000;
7728
7729 for (i = 0; i < remap_data->count; i++) {
7730 chipio_write_no_mutex(codec,
7731 stream_offset + remap_data->offset[i],
7732 remap_data->value[i]);
7733 }
7734
7735 /* Update stream map configuration. */
7736 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7737 }
7738
7739 /*
7740 * Default speaker tuning values setup for alternative codecs.
7741 */
7742 static const unsigned int sbz_default_delay_values[] = {
7743 /* Non-zero values are floating point 0.000198. */
7744 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000
7745 };
7746
7747 static const unsigned int zxr_default_delay_values[] = {
7748 /* Non-zero values are floating point 0.000220. */
7749 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd
7750 };
7751
7752 static const unsigned int ae5_default_delay_values[] = {
7753 /* Non-zero values are floating point 0.000100. */
7754 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717
7755 };
7756
7757 /*
7758 * If we never change these, probably only need them on initialization.
7759 */
ca0132_alt_init_speaker_tuning(struct hda_codec * codec)7760 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec)
7761 {
7762 struct ca0132_spec *spec = codec->spec;
7763 unsigned int i, tmp, start_req, end_req;
7764 const unsigned int *values;
7765
7766 switch (ca0132_quirk(spec)) {
7767 case QUIRK_SBZ:
7768 values = sbz_default_delay_values;
7769 break;
7770 case QUIRK_ZXR:
7771 values = zxr_default_delay_values;
7772 break;
7773 case QUIRK_AE5:
7774 case QUIRK_AE7:
7775 values = ae5_default_delay_values;
7776 break;
7777 default:
7778 values = sbz_default_delay_values;
7779 break;
7780 }
7781
7782 tmp = FLOAT_ZERO;
7783 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp);
7784
7785 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL;
7786 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL;
7787 for (i = start_req; i < end_req + 1; i++)
7788 dspio_set_uint_param(codec, 0x96, i, tmp);
7789
7790 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT;
7791 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT;
7792 for (i = start_req; i < end_req + 1; i++)
7793 dspio_set_uint_param(codec, 0x96, i, tmp);
7794
7795
7796 for (i = 0; i < 6; i++)
7797 dspio_set_uint_param(codec, 0x96,
7798 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]);
7799 }
7800
7801 /*
7802 * Initialize mic for non-chromebook ca0132 implementations.
7803 */
ca0132_alt_init_analog_mics(struct hda_codec * codec)7804 static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
7805 {
7806 struct ca0132_spec *spec = codec->spec;
7807 unsigned int tmp;
7808
7809 /* Mic 1 Setup */
7810 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7811 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7812 if (ca0132_quirk(spec) == QUIRK_R3DI) {
7813 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7814 tmp = FLOAT_ONE;
7815 } else
7816 tmp = FLOAT_THREE;
7817 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7818
7819 /* Mic 2 setup (not present on desktop cards) */
7820 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
7821 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
7822 if (ca0132_quirk(spec) == QUIRK_R3DI)
7823 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7824 tmp = FLOAT_ZERO;
7825 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7826 }
7827
7828 /*
7829 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
7830 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
7831 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
7832 * having an updated DAC, which changes the destination to that DAC.
7833 */
sbz_connect_streams(struct hda_codec * codec)7834 static void sbz_connect_streams(struct hda_codec *codec)
7835 {
7836 struct ca0132_spec *spec = codec->spec;
7837
7838 mutex_lock(&spec->chipio_mutex);
7839
7840 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
7841
7842 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
7843 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
7844
7845 /* Setup stream 0x14 with it's source and destination points */
7846 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
7847 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
7848 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
7849 chipio_set_stream_channels(codec, 0x14, 2);
7850 chipio_set_stream_control(codec, 0x14, 1);
7851
7852 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
7853
7854 mutex_unlock(&spec->chipio_mutex);
7855 }
7856
7857 /*
7858 * Write data through ChipIO to setup proper stream destinations.
7859 * Not sure how it exactly works, but it seems to direct data
7860 * to different destinations. Example is f8 to c0, e0 to c0.
7861 * All I know is, if you don't set these, you get no sound.
7862 */
sbz_chipio_startup_data(struct hda_codec * codec)7863 static void sbz_chipio_startup_data(struct hda_codec *codec)
7864 {
7865 const struct chipio_stream_remap_data *dsp_out_remap_data;
7866 struct ca0132_spec *spec = codec->spec;
7867
7868 mutex_lock(&spec->chipio_mutex);
7869 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
7870
7871 /* Remap DAC0's output ports. */
7872 chipio_remap_stream(codec, &stream_remap_data[0]);
7873
7874 /* Remap DSP audio output stream ports. */
7875 switch (ca0132_quirk(spec)) {
7876 case QUIRK_SBZ:
7877 dsp_out_remap_data = &stream_remap_data[1];
7878 break;
7879
7880 case QUIRK_ZXR:
7881 dsp_out_remap_data = &stream_remap_data[2];
7882 break;
7883
7884 default:
7885 dsp_out_remap_data = NULL;
7886 break;
7887 }
7888
7889 if (dsp_out_remap_data)
7890 chipio_remap_stream(codec, dsp_out_remap_data);
7891
7892 codec_dbg(codec, "Startup Data exited, mutex released.\n");
7893 mutex_unlock(&spec->chipio_mutex);
7894 }
7895
ca0132_alt_dsp_initial_mic_setup(struct hda_codec * codec)7896 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
7897 {
7898 struct ca0132_spec *spec = codec->spec;
7899 unsigned int tmp;
7900
7901 chipio_set_stream_control(codec, 0x03, 0);
7902 chipio_set_stream_control(codec, 0x04, 0);
7903
7904 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7905 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7906
7907 tmp = FLOAT_THREE;
7908 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7909
7910 chipio_set_stream_control(codec, 0x03, 1);
7911 chipio_set_stream_control(codec, 0x04, 1);
7912
7913 switch (ca0132_quirk(spec)) {
7914 case QUIRK_SBZ:
7915 chipio_write(codec, 0x18b098, 0x0000000c);
7916 chipio_write(codec, 0x18b09C, 0x0000000c);
7917 break;
7918 case QUIRK_AE5:
7919 chipio_write(codec, 0x18b098, 0x0000000c);
7920 chipio_write(codec, 0x18b09c, 0x0000004c);
7921 break;
7922 default:
7923 break;
7924 }
7925 }
7926
ae5_post_dsp_register_set(struct hda_codec * codec)7927 static void ae5_post_dsp_register_set(struct hda_codec *codec)
7928 {
7929 struct ca0132_spec *spec = codec->spec;
7930
7931 chipio_8051_write_direct(codec, 0x93, 0x10);
7932 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
7933
7934 writeb(0xff, spec->mem_base + 0x304);
7935 writeb(0xff, spec->mem_base + 0x304);
7936 writeb(0xff, spec->mem_base + 0x304);
7937 writeb(0xff, spec->mem_base + 0x304);
7938 writeb(0x00, spec->mem_base + 0x100);
7939 writeb(0xff, spec->mem_base + 0x304);
7940 writeb(0x00, spec->mem_base + 0x100);
7941 writeb(0xff, spec->mem_base + 0x304);
7942 writeb(0x00, spec->mem_base + 0x100);
7943 writeb(0xff, spec->mem_base + 0x304);
7944 writeb(0x00, spec->mem_base + 0x100);
7945 writeb(0xff, spec->mem_base + 0x304);
7946
7947 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7948 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7949 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7950 }
7951
ae5_post_dsp_param_setup(struct hda_codec * codec)7952 static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7953 {
7954 /*
7955 * Param3 in the 8051's memory is represented by the ascii string 'mch'
7956 * which seems to be 'multichannel'. This is also mentioned in the
7957 * AE-5's registry values in Windows.
7958 */
7959 chipio_set_control_param(codec, 3, 0);
7960 /*
7961 * I believe ASI is 'audio serial interface' and that it's used to
7962 * change colors on the external LED strip connected to the AE-5.
7963 */
7964 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7965
7966 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7967 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7968
7969 chipio_8051_write_exram(codec, 0xfa92, 0x22);
7970 }
7971
ae5_post_dsp_pll_setup(struct hda_codec * codec)7972 static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7973 {
7974 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
7975 chipio_8051_write_pll_pmu(codec, 0x45, 0xcc);
7976 chipio_8051_write_pll_pmu(codec, 0x40, 0xcb);
7977 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
7978 chipio_8051_write_pll_pmu(codec, 0x51, 0x8d);
7979 }
7980
ae5_post_dsp_stream_setup(struct hda_codec * codec)7981 static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7982 {
7983 struct ca0132_spec *spec = codec->spec;
7984
7985 mutex_lock(&spec->chipio_mutex);
7986
7987 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7988
7989 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7990
7991 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7992
7993 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7994 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7995 chipio_set_stream_channels(codec, 0x18, 6);
7996 chipio_set_stream_control(codec, 0x18, 1);
7997
7998 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7999
8000 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
8001
8002 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
8003
8004 mutex_unlock(&spec->chipio_mutex);
8005 }
8006
ae5_post_dsp_startup_data(struct hda_codec * codec)8007 static void ae5_post_dsp_startup_data(struct hda_codec *codec)
8008 {
8009 struct ca0132_spec *spec = codec->spec;
8010
8011 mutex_lock(&spec->chipio_mutex);
8012
8013 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8014 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8015 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8016 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8017
8018 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
8019 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8020 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
8021 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
8022 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
8023 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
8024 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8025 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8026 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8027 ca0113_mmio_gpio_set(codec, 0, true);
8028 ca0113_mmio_gpio_set(codec, 1, true);
8029 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
8030
8031 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
8032
8033 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8034 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8035
8036 mutex_unlock(&spec->chipio_mutex);
8037 }
8038
ae7_post_dsp_setup_ports(struct hda_codec * codec)8039 static void ae7_post_dsp_setup_ports(struct hda_codec *codec)
8040 {
8041 struct ca0132_spec *spec = codec->spec;
8042
8043 mutex_lock(&spec->chipio_mutex);
8044
8045 /* Seems to share the same port remapping as the SBZ. */
8046 chipio_remap_stream(codec, &stream_remap_data[1]);
8047
8048 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8049 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
8050 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00);
8051 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00);
8052 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff);
8053 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff);
8054 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff);
8055 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f);
8056
8057 mutex_unlock(&spec->chipio_mutex);
8058 }
8059
ae7_post_dsp_asi_stream_setup(struct hda_codec * codec)8060 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec)
8061 {
8062 struct ca0132_spec *spec = codec->spec;
8063
8064 mutex_lock(&spec->chipio_mutex);
8065
8066 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
8067 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8068
8069 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
8070
8071 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8072 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8073
8074 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8075 chipio_set_stream_channels(codec, 0x18, 6);
8076 chipio_set_stream_control(codec, 0x18, 1);
8077
8078 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
8079
8080 mutex_unlock(&spec->chipio_mutex);
8081 }
8082
ae7_post_dsp_pll_setup(struct hda_codec * codec)8083 static void ae7_post_dsp_pll_setup(struct hda_codec *codec)
8084 {
8085 static const unsigned int addr[] = {
8086 0x41, 0x45, 0x40, 0x43, 0x51
8087 };
8088 static const unsigned int data[] = {
8089 0xc8, 0xcc, 0xcb, 0xc7, 0x8d
8090 };
8091 unsigned int i;
8092
8093 for (i = 0; i < ARRAY_SIZE(addr); i++)
8094 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]);
8095 }
8096
ae7_post_dsp_asi_setup_ports(struct hda_codec * codec)8097 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec)
8098 {
8099 struct ca0132_spec *spec = codec->spec;
8100 static const unsigned int target[] = {
8101 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14
8102 };
8103 static const unsigned int data[] = {
8104 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f
8105 };
8106 unsigned int i;
8107
8108 mutex_lock(&spec->chipio_mutex);
8109
8110 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
8111
8112 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8113 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8114 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8115 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8116
8117 ae7_post_dsp_pll_setup(codec);
8118 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8119
8120 for (i = 0; i < ARRAY_SIZE(target); i++)
8121 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]);
8122
8123 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8124 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8125 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8126
8127 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56);
8128 chipio_set_stream_channels(codec, 0x21, 2);
8129 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000);
8130
8131 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09);
8132 /*
8133 * In the 8051's memory, this param is referred to as 'n2sid', which I
8134 * believe is 'node to streamID'. It seems to be a way to assign a
8135 * stream to a given HDA node.
8136 */
8137 chipio_set_control_param_no_mutex(codec, 0x20, 0x21);
8138
8139 chipio_write_no_mutex(codec, 0x18b038, 0x00000088);
8140
8141 /*
8142 * Now, at this point on Windows, an actual stream is setup and
8143 * seemingly sends data to the HDA node 0x09, which is the digital
8144 * audio input node. This is left out here, because obviously I don't
8145 * know what data is being sent. Interestingly, the AE-5 seems to go
8146 * through the motions of getting here and never actually takes this
8147 * step, but the AE-7 does.
8148 */
8149
8150 ca0113_mmio_gpio_set(codec, 0, 1);
8151 ca0113_mmio_gpio_set(codec, 1, 1);
8152
8153 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8154 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000);
8155 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8156 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8157
8158 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8159 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8160
8161 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8162 chipio_set_stream_channels(codec, 0x18, 6);
8163
8164 /*
8165 * Runs again, this has been repeated a few times, but I'm just
8166 * following what the Windows driver does.
8167 */
8168 ae7_post_dsp_pll_setup(codec);
8169 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8170
8171 mutex_unlock(&spec->chipio_mutex);
8172 }
8173
8174 /*
8175 * The Windows driver has commands that seem to setup ASI, which I believe to
8176 * be some sort of audio serial interface. My current speculation is that it's
8177 * related to communicating with the new DAC.
8178 */
ae7_post_dsp_asi_setup(struct hda_codec * codec)8179 static void ae7_post_dsp_asi_setup(struct hda_codec *codec)
8180 {
8181 chipio_8051_write_direct(codec, 0x93, 0x10);
8182
8183 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
8184
8185 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8186 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8187
8188 chipio_set_control_param(codec, 3, 3);
8189 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
8190
8191 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
8192 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8193 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);
8194
8195 chipio_8051_write_exram(codec, 0xfa92, 0x22);
8196
8197 ae7_post_dsp_pll_setup(codec);
8198 ae7_post_dsp_asi_stream_setup(codec);
8199
8200 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
8201
8202 ae7_post_dsp_asi_setup_ports(codec);
8203 }
8204
8205 /*
8206 * Setup default parameters for DSP
8207 */
ca0132_setup_defaults(struct hda_codec * codec)8208 static void ca0132_setup_defaults(struct hda_codec *codec)
8209 {
8210 struct ca0132_spec *spec = codec->spec;
8211 unsigned int tmp;
8212 int num_fx;
8213 int idx, i;
8214
8215 if (spec->dsp_state != DSP_DOWNLOADED)
8216 return;
8217
8218 /* out, in effects + voicefx */
8219 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8220 for (idx = 0; idx < num_fx; idx++) {
8221 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8222 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
8223 ca0132_effects[idx].reqs[i],
8224 ca0132_effects[idx].def_vals[i]);
8225 }
8226 }
8227
8228 /*remove DSP headroom*/
8229 tmp = FLOAT_ZERO;
8230 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8231
8232 /*set speaker EQ bypass attenuation*/
8233 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
8234
8235 /* set AMic1 and AMic2 as mono mic */
8236 tmp = FLOAT_ONE;
8237 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
8238 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
8239
8240 /* set AMic1 as CrystalVoice input */
8241 tmp = FLOAT_ONE;
8242 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
8243
8244 /* set WUH source */
8245 tmp = FLOAT_TWO;
8246 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8247 }
8248
8249 /*
8250 * Setup default parameters for Recon3D/Recon3Di DSP.
8251 */
8252
r3d_setup_defaults(struct hda_codec * codec)8253 static void r3d_setup_defaults(struct hda_codec *codec)
8254 {
8255 struct ca0132_spec *spec = codec->spec;
8256 unsigned int tmp;
8257 int num_fx;
8258 int idx, i;
8259
8260 if (spec->dsp_state != DSP_DOWNLOADED)
8261 return;
8262
8263 ca0132_alt_init_analog_mics(codec);
8264 ca0132_alt_start_dsp_audio_streams(codec);
8265
8266 /*remove DSP headroom*/
8267 tmp = FLOAT_ZERO;
8268 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8269
8270 /* set WUH source */
8271 tmp = FLOAT_TWO;
8272 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8273 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8274
8275 /* Set speaker source? */
8276 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8277
8278 if (ca0132_quirk(spec) == QUIRK_R3DI)
8279 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
8280
8281 /* Disable mute on Center/LFE. */
8282 if (ca0132_quirk(spec) == QUIRK_R3D) {
8283 ca0113_mmio_gpio_set(codec, 2, false);
8284 ca0113_mmio_gpio_set(codec, 4, true);
8285 }
8286
8287 /* Setup effect defaults */
8288 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8289 for (idx = 0; idx < num_fx; idx++) {
8290 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8291 dspio_set_uint_param(codec,
8292 ca0132_effects[idx].mid,
8293 ca0132_effects[idx].reqs[i],
8294 ca0132_effects[idx].def_vals[i]);
8295 }
8296 }
8297 }
8298
8299 /*
8300 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
8301 * than the Chromebook setup.
8302 */
sbz_setup_defaults(struct hda_codec * codec)8303 static void sbz_setup_defaults(struct hda_codec *codec)
8304 {
8305 struct ca0132_spec *spec = codec->spec;
8306 unsigned int tmp;
8307 int num_fx;
8308 int idx, i;
8309
8310 if (spec->dsp_state != DSP_DOWNLOADED)
8311 return;
8312
8313 ca0132_alt_init_analog_mics(codec);
8314 ca0132_alt_start_dsp_audio_streams(codec);
8315 sbz_connect_streams(codec);
8316 sbz_chipio_startup_data(codec);
8317
8318 /*
8319 * Sets internal input loopback to off, used to have a switch to
8320 * enable input loopback, but turned out to be way too buggy.
8321 */
8322 tmp = FLOAT_ONE;
8323 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8324 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8325
8326 /*remove DSP headroom*/
8327 tmp = FLOAT_ZERO;
8328 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8329
8330 /* set WUH source */
8331 tmp = FLOAT_TWO;
8332 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8333 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8334
8335 /* Set speaker source? */
8336 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8337
8338 ca0132_alt_dsp_initial_mic_setup(codec);
8339
8340 /* out, in effects + voicefx */
8341 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8342 for (idx = 0; idx < num_fx; idx++) {
8343 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8344 dspio_set_uint_param(codec,
8345 ca0132_effects[idx].mid,
8346 ca0132_effects[idx].reqs[i],
8347 ca0132_effects[idx].def_vals[i]);
8348 }
8349 }
8350
8351 ca0132_alt_init_speaker_tuning(codec);
8352 }
8353
8354 /*
8355 * Setup default parameters for the Sound BlasterX AE-5 DSP.
8356 */
ae5_setup_defaults(struct hda_codec * codec)8357 static void ae5_setup_defaults(struct hda_codec *codec)
8358 {
8359 struct ca0132_spec *spec = codec->spec;
8360 unsigned int tmp;
8361 int num_fx;
8362 int idx, i;
8363
8364 if (spec->dsp_state != DSP_DOWNLOADED)
8365 return;
8366
8367 ca0132_alt_init_analog_mics(codec);
8368 ca0132_alt_start_dsp_audio_streams(codec);
8369
8370 /* New, unknown SCP req's */
8371 tmp = FLOAT_ZERO;
8372 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
8373 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
8374 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8375 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8376
8377 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8378 ca0113_mmio_gpio_set(codec, 0, false);
8379 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8380
8381 /* Internal loopback off */
8382 tmp = FLOAT_ONE;
8383 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8384 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8385
8386 /*remove DSP headroom*/
8387 tmp = FLOAT_ZERO;
8388 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8389
8390 /* set WUH source */
8391 tmp = FLOAT_TWO;
8392 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8393 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8394
8395 /* Set speaker source? */
8396 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8397
8398 ca0132_alt_dsp_initial_mic_setup(codec);
8399 ae5_post_dsp_register_set(codec);
8400 ae5_post_dsp_param_setup(codec);
8401 ae5_post_dsp_pll_setup(codec);
8402 ae5_post_dsp_stream_setup(codec);
8403 ae5_post_dsp_startup_data(codec);
8404
8405 /* out, in effects + voicefx */
8406 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8407 for (idx = 0; idx < num_fx; idx++) {
8408 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8409 dspio_set_uint_param(codec,
8410 ca0132_effects[idx].mid,
8411 ca0132_effects[idx].reqs[i],
8412 ca0132_effects[idx].def_vals[i]);
8413 }
8414 }
8415
8416 ca0132_alt_init_speaker_tuning(codec);
8417 }
8418
8419 /*
8420 * Setup default parameters for the Sound Blaster AE-7 DSP.
8421 */
ae7_setup_defaults(struct hda_codec * codec)8422 static void ae7_setup_defaults(struct hda_codec *codec)
8423 {
8424 struct ca0132_spec *spec = codec->spec;
8425 unsigned int tmp;
8426 int num_fx;
8427 int idx, i;
8428
8429 if (spec->dsp_state != DSP_DOWNLOADED)
8430 return;
8431
8432 ca0132_alt_init_analog_mics(codec);
8433 ca0132_alt_start_dsp_audio_streams(codec);
8434 ae7_post_dsp_setup_ports(codec);
8435
8436 tmp = FLOAT_ZERO;
8437 dspio_set_uint_param(codec, 0x96,
8438 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp);
8439 dspio_set_uint_param(codec, 0x96,
8440 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp);
8441
8442 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8443
8444 /* New, unknown SCP req's */
8445 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8446 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8447
8448 ca0113_mmio_gpio_set(codec, 0, false);
8449
8450 /* Internal loopback off */
8451 tmp = FLOAT_ONE;
8452 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8453 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8454
8455 /*remove DSP headroom*/
8456 tmp = FLOAT_ZERO;
8457 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8458
8459 /* set WUH source */
8460 tmp = FLOAT_TWO;
8461 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8462 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8463
8464 /* Set speaker source? */
8465 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8466 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8467
8468 /*
8469 * This is the second time we've called this, but this is seemingly
8470 * what Windows does.
8471 */
8472 ca0132_alt_init_analog_mics(codec);
8473
8474 ae7_post_dsp_asi_setup(codec);
8475
8476 /*
8477 * Not sure why, but these are both set to 1. They're only set to 0
8478 * upon shutdown.
8479 */
8480 ca0113_mmio_gpio_set(codec, 0, true);
8481 ca0113_mmio_gpio_set(codec, 1, true);
8482
8483 /* Volume control related. */
8484 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04);
8485 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04);
8486 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80);
8487
8488 /* out, in effects + voicefx */
8489 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8490 for (idx = 0; idx < num_fx; idx++) {
8491 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8492 dspio_set_uint_param(codec,
8493 ca0132_effects[idx].mid,
8494 ca0132_effects[idx].reqs[i],
8495 ca0132_effects[idx].def_vals[i]);
8496 }
8497 }
8498
8499 ca0132_alt_init_speaker_tuning(codec);
8500 }
8501
8502 /*
8503 * Initialization of flags in chip
8504 */
ca0132_init_flags(struct hda_codec * codec)8505 static void ca0132_init_flags(struct hda_codec *codec)
8506 {
8507 struct ca0132_spec *spec = codec->spec;
8508
8509 if (ca0132_use_alt_functions(spec)) {
8510 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
8511 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
8512 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
8513 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
8514 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
8515 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8516 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
8517 chipio_set_control_flag(codec,
8518 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8519 chipio_set_control_flag(codec,
8520 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
8521 } else {
8522 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8523 chipio_set_control_flag(codec,
8524 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
8525 chipio_set_control_flag(codec,
8526 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
8527 chipio_set_control_flag(codec,
8528 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
8529 chipio_set_control_flag(codec,
8530 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8531 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
8532 }
8533 }
8534
8535 /*
8536 * Initialization of parameters in chip
8537 */
ca0132_init_params(struct hda_codec * codec)8538 static void ca0132_init_params(struct hda_codec *codec)
8539 {
8540 struct ca0132_spec *spec = codec->spec;
8541
8542 if (ca0132_use_alt_functions(spec)) {
8543 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8544 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
8545 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
8546 chipio_set_control_param(codec, 0, 0);
8547 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
8548 }
8549
8550 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
8551 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
8552 }
8553
ca0132_set_dsp_msr(struct hda_codec * codec,bool is96k)8554 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
8555 {
8556 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
8557 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
8558 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
8559 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
8560 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
8561 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
8562
8563 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
8564 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
8565 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8566 }
8567
ca0132_download_dsp_images(struct hda_codec * codec)8568 static bool ca0132_download_dsp_images(struct hda_codec *codec)
8569 {
8570 bool dsp_loaded = false;
8571 struct ca0132_spec *spec = codec->spec;
8572 const struct dsp_image_seg *dsp_os_image;
8573 const struct firmware *fw_entry = NULL;
8574 /*
8575 * Alternate firmwares for different variants. The Recon3Di apparently
8576 * can use the default firmware, but I'll leave the option in case
8577 * it needs it again.
8578 */
8579 switch (ca0132_quirk(spec)) {
8580 case QUIRK_SBZ:
8581 case QUIRK_R3D:
8582 case QUIRK_AE5:
8583 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
8584 codec->card->dev) != 0)
8585 codec_dbg(codec, "Desktop firmware not found.");
8586 else
8587 codec_dbg(codec, "Desktop firmware selected.");
8588 break;
8589 case QUIRK_R3DI:
8590 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
8591 codec->card->dev) != 0)
8592 codec_dbg(codec, "Recon3Di alt firmware not detected.");
8593 else
8594 codec_dbg(codec, "Recon3Di firmware selected.");
8595 break;
8596 default:
8597 break;
8598 }
8599 /*
8600 * Use default ctefx.bin if no alt firmware is detected, or if none
8601 * exists for your particular codec.
8602 */
8603 if (!fw_entry) {
8604 codec_dbg(codec, "Default firmware selected.");
8605 if (request_firmware(&fw_entry, EFX_FILE,
8606 codec->card->dev) != 0)
8607 return false;
8608 }
8609
8610 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
8611 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
8612 codec_err(codec, "ca0132 DSP load image failed\n");
8613 goto exit_download;
8614 }
8615
8616 dsp_loaded = dspload_wait_loaded(codec);
8617
8618 exit_download:
8619 release_firmware(fw_entry);
8620
8621 return dsp_loaded;
8622 }
8623
ca0132_download_dsp(struct hda_codec * codec)8624 static void ca0132_download_dsp(struct hda_codec *codec)
8625 {
8626 struct ca0132_spec *spec = codec->spec;
8627
8628 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
8629 return; /* NOP */
8630 #endif
8631
8632 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
8633 return; /* don't retry failures */
8634
8635 chipio_enable_clocks(codec);
8636 if (spec->dsp_state != DSP_DOWNLOADED) {
8637 spec->dsp_state = DSP_DOWNLOADING;
8638
8639 if (!ca0132_download_dsp_images(codec))
8640 spec->dsp_state = DSP_DOWNLOAD_FAILED;
8641 else
8642 spec->dsp_state = DSP_DOWNLOADED;
8643 }
8644
8645 /* For codecs using alt functions, this is already done earlier */
8646 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
8647 ca0132_set_dsp_msr(codec, true);
8648 }
8649
ca0132_process_dsp_response(struct hda_codec * codec,struct hda_jack_callback * callback)8650 static void ca0132_process_dsp_response(struct hda_codec *codec,
8651 struct hda_jack_callback *callback)
8652 {
8653 struct ca0132_spec *spec = codec->spec;
8654
8655 codec_dbg(codec, "ca0132_process_dsp_response\n");
8656 snd_hda_power_up_pm(codec);
8657 if (spec->wait_scp) {
8658 if (dspio_get_response_data(codec) >= 0)
8659 spec->wait_scp = 0;
8660 }
8661
8662 dspio_clear_response_queue(codec);
8663 snd_hda_power_down_pm(codec);
8664 }
8665
hp_callback(struct hda_codec * codec,struct hda_jack_callback * cb)8666 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8667 {
8668 struct ca0132_spec *spec = codec->spec;
8669 struct hda_jack_tbl *tbl;
8670
8671 /* Delay enabling the HP amp, to let the mic-detection
8672 * state machine run.
8673 */
8674 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
8675 if (tbl)
8676 tbl->block_report = 1;
8677 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
8678 }
8679
amic_callback(struct hda_codec * codec,struct hda_jack_callback * cb)8680 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8681 {
8682 struct ca0132_spec *spec = codec->spec;
8683
8684 if (ca0132_use_alt_functions(spec))
8685 ca0132_alt_select_in(codec);
8686 else
8687 ca0132_select_mic(codec);
8688 }
8689
ca0132_setup_unsol(struct hda_codec * codec)8690 static void ca0132_setup_unsol(struct hda_codec *codec)
8691 {
8692 struct ca0132_spec *spec = codec->spec;
8693 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
8694 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
8695 amic_callback);
8696 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
8697 ca0132_process_dsp_response);
8698 /* Front headphone jack detection */
8699 if (ca0132_use_alt_functions(spec))
8700 snd_hda_jack_detect_enable_callback(codec,
8701 spec->unsol_tag_front_hp, hp_callback);
8702 }
8703
8704 /*
8705 * Verbs tables.
8706 */
8707
8708 /* Sends before DSP download. */
8709 static const struct hda_verb ca0132_base_init_verbs[] = {
8710 /*enable ct extension*/
8711 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
8712 {}
8713 };
8714
8715 /* Send at exit. */
8716 static const struct hda_verb ca0132_base_exit_verbs[] = {
8717 /*set afg to D3*/
8718 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
8719 /*disable ct extension*/
8720 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
8721 {}
8722 };
8723
8724 /* Other verbs tables. Sends after DSP download. */
8725
8726 static const struct hda_verb ca0132_init_verbs0[] = {
8727 /* chip init verbs */
8728 {0x15, 0x70D, 0xF0},
8729 {0x15, 0x70E, 0xFE},
8730 {0x15, 0x707, 0x75},
8731 {0x15, 0x707, 0xD3},
8732 {0x15, 0x707, 0x09},
8733 {0x15, 0x707, 0x53},
8734 {0x15, 0x707, 0xD4},
8735 {0x15, 0x707, 0xEF},
8736 {0x15, 0x707, 0x75},
8737 {0x15, 0x707, 0xD3},
8738 {0x15, 0x707, 0x09},
8739 {0x15, 0x707, 0x02},
8740 {0x15, 0x707, 0x37},
8741 {0x15, 0x707, 0x78},
8742 {0x15, 0x53C, 0xCE},
8743 {0x15, 0x575, 0xC9},
8744 {0x15, 0x53D, 0xCE},
8745 {0x15, 0x5B7, 0xC9},
8746 {0x15, 0x70D, 0xE8},
8747 {0x15, 0x70E, 0xFE},
8748 {0x15, 0x707, 0x02},
8749 {0x15, 0x707, 0x68},
8750 {0x15, 0x707, 0x62},
8751 {0x15, 0x53A, 0xCE},
8752 {0x15, 0x546, 0xC9},
8753 {0x15, 0x53B, 0xCE},
8754 {0x15, 0x5E8, 0xC9},
8755 {}
8756 };
8757
8758 /* Extra init verbs for desktop cards. */
8759 static const struct hda_verb ca0132_init_verbs1[] = {
8760 {0x15, 0x70D, 0x20},
8761 {0x15, 0x70E, 0x19},
8762 {0x15, 0x707, 0x00},
8763 {0x15, 0x539, 0xCE},
8764 {0x15, 0x546, 0xC9},
8765 {0x15, 0x70D, 0xB7},
8766 {0x15, 0x70E, 0x09},
8767 {0x15, 0x707, 0x10},
8768 {0x15, 0x70D, 0xAF},
8769 {0x15, 0x70E, 0x09},
8770 {0x15, 0x707, 0x01},
8771 {0x15, 0x707, 0x05},
8772 {0x15, 0x70D, 0x73},
8773 {0x15, 0x70E, 0x09},
8774 {0x15, 0x707, 0x14},
8775 {0x15, 0x6FF, 0xC4},
8776 {}
8777 };
8778
ca0132_init_chip(struct hda_codec * codec)8779 static void ca0132_init_chip(struct hda_codec *codec)
8780 {
8781 struct ca0132_spec *spec = codec->spec;
8782 int num_fx;
8783 int i;
8784 unsigned int on;
8785
8786 mutex_init(&spec->chipio_mutex);
8787
8788 /*
8789 * The Windows driver always does this upon startup, which seems to
8790 * clear out any previous configuration. This should help issues where
8791 * a boot into Windows prior to a boot into Linux breaks things. Also,
8792 * Windows always sends the reset twice.
8793 */
8794 if (ca0132_use_alt_functions(spec)) {
8795 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8796 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2);
8797
8798 snd_hda_codec_write(codec, codec->core.afg, 0,
8799 AC_VERB_SET_CODEC_RESET, 0);
8800 snd_hda_codec_write(codec, codec->core.afg, 0,
8801 AC_VERB_SET_CODEC_RESET, 0);
8802 }
8803
8804 spec->cur_out_type = SPEAKER_OUT;
8805 if (!ca0132_use_alt_functions(spec))
8806 spec->cur_mic_type = DIGITAL_MIC;
8807 else
8808 spec->cur_mic_type = REAR_MIC;
8809
8810 spec->cur_mic_boost = 0;
8811
8812 for (i = 0; i < VNODES_COUNT; i++) {
8813 spec->vnode_lvol[i] = 0x5a;
8814 spec->vnode_rvol[i] = 0x5a;
8815 spec->vnode_lswitch[i] = 0;
8816 spec->vnode_rswitch[i] = 0;
8817 }
8818
8819 /*
8820 * Default states for effects are in ca0132_effects[].
8821 */
8822 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
8823 for (i = 0; i < num_fx; i++) {
8824 on = (unsigned int)ca0132_effects[i].reqs[0];
8825 spec->effects_switch[i] = on ? 1 : 0;
8826 }
8827 /*
8828 * Sets defaults for the effect slider controls, only for alternative
8829 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
8830 */
8831 if (ca0132_use_alt_controls(spec)) {
8832 /* Set speakers to default to full range. */
8833 spec->speaker_range_val[0] = 1;
8834 spec->speaker_range_val[1] = 1;
8835
8836 spec->xbass_xover_freq = 8;
8837 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
8838 spec->fx_ctl_val[i] = effect_slider_defaults[i];
8839
8840 spec->bass_redirect_xover_freq = 8;
8841 }
8842
8843 spec->voicefx_val = 0;
8844 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
8845 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
8846
8847 /*
8848 * The ZxR doesn't have a front panel header, and it's line-in is on
8849 * the daughter board. So, there is no input enum control, and we need
8850 * to make sure that spec->in_enum_val is set properly.
8851 */
8852 if (ca0132_quirk(spec) == QUIRK_ZXR)
8853 spec->in_enum_val = REAR_MIC;
8854
8855 #ifdef ENABLE_TUNING_CONTROLS
8856 ca0132_init_tuning_defaults(codec);
8857 #endif
8858 }
8859
8860 /*
8861 * Recon3Di exit specific commands.
8862 */
8863 /* prevents popping noise on shutdown */
r3di_gpio_shutdown(struct hda_codec * codec)8864 static void r3di_gpio_shutdown(struct hda_codec *codec)
8865 {
8866 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
8867 }
8868
8869 /*
8870 * Sound Blaster Z exit specific commands.
8871 */
sbz_region2_exit(struct hda_codec * codec)8872 static void sbz_region2_exit(struct hda_codec *codec)
8873 {
8874 struct ca0132_spec *spec = codec->spec;
8875 unsigned int i;
8876
8877 for (i = 0; i < 4; i++)
8878 writeb(0x0, spec->mem_base + 0x100);
8879 for (i = 0; i < 8; i++)
8880 writeb(0xb3, spec->mem_base + 0x304);
8881
8882 ca0113_mmio_gpio_set(codec, 0, false);
8883 ca0113_mmio_gpio_set(codec, 1, false);
8884 ca0113_mmio_gpio_set(codec, 4, true);
8885 ca0113_mmio_gpio_set(codec, 5, false);
8886 ca0113_mmio_gpio_set(codec, 7, false);
8887 }
8888
sbz_set_pin_ctl_default(struct hda_codec * codec)8889 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
8890 {
8891 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
8892 unsigned int i;
8893
8894 snd_hda_codec_write(codec, 0x11, 0,
8895 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
8896
8897 for (i = 0; i < ARRAY_SIZE(pins); i++)
8898 snd_hda_codec_write(codec, pins[i], 0,
8899 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
8900 }
8901
ca0132_clear_unsolicited(struct hda_codec * codec)8902 static void ca0132_clear_unsolicited(struct hda_codec *codec)
8903 {
8904 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
8905 unsigned int i;
8906
8907 for (i = 0; i < ARRAY_SIZE(pins); i++) {
8908 snd_hda_codec_write(codec, pins[i], 0,
8909 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
8910 }
8911 }
8912
8913 /* On shutdown, sends commands in sets of three */
sbz_gpio_shutdown_commands(struct hda_codec * codec,int dir,int mask,int data)8914 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
8915 int mask, int data)
8916 {
8917 if (dir >= 0)
8918 snd_hda_codec_write(codec, 0x01, 0,
8919 AC_VERB_SET_GPIO_DIRECTION, dir);
8920 if (mask >= 0)
8921 snd_hda_codec_write(codec, 0x01, 0,
8922 AC_VERB_SET_GPIO_MASK, mask);
8923
8924 if (data >= 0)
8925 snd_hda_codec_write(codec, 0x01, 0,
8926 AC_VERB_SET_GPIO_DATA, data);
8927 }
8928
zxr_dbpro_power_state_shutdown(struct hda_codec * codec)8929 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
8930 {
8931 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
8932 unsigned int i;
8933
8934 for (i = 0; i < ARRAY_SIZE(pins); i++)
8935 snd_hda_codec_write(codec, pins[i], 0,
8936 AC_VERB_SET_POWER_STATE, 0x03);
8937 }
8938
sbz_exit_chip(struct hda_codec * codec)8939 static void sbz_exit_chip(struct hda_codec *codec)
8940 {
8941 chipio_set_stream_control(codec, 0x03, 0);
8942 chipio_set_stream_control(codec, 0x04, 0);
8943
8944 /* Mess with GPIO */
8945 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
8946 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
8947 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
8948
8949 chipio_set_stream_control(codec, 0x14, 0);
8950 chipio_set_stream_control(codec, 0x0C, 0);
8951
8952 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8953 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8954
8955 chipio_write(codec, 0x18a020, 0x00000083);
8956
8957 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
8958 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
8959 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
8960
8961 chipio_set_stream_control(codec, 0x0C, 0);
8962
8963 chipio_set_control_param(codec, 0x0D, 0x24);
8964
8965 ca0132_clear_unsolicited(codec);
8966 sbz_set_pin_ctl_default(codec);
8967
8968 snd_hda_codec_write(codec, 0x0B, 0,
8969 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8970
8971 sbz_region2_exit(codec);
8972 }
8973
r3d_exit_chip(struct hda_codec * codec)8974 static void r3d_exit_chip(struct hda_codec *codec)
8975 {
8976 ca0132_clear_unsolicited(codec);
8977 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8978 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
8979 }
8980
ae5_exit_chip(struct hda_codec * codec)8981 static void ae5_exit_chip(struct hda_codec *codec)
8982 {
8983 chipio_set_stream_control(codec, 0x03, 0);
8984 chipio_set_stream_control(codec, 0x04, 0);
8985
8986 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8987 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8988 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8989 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8990 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8991 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
8992 ca0113_mmio_gpio_set(codec, 0, false);
8993 ca0113_mmio_gpio_set(codec, 1, false);
8994
8995 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8996 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8997
8998 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8999
9000 chipio_set_stream_control(codec, 0x18, 0);
9001 chipio_set_stream_control(codec, 0x0c, 0);
9002
9003 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
9004 }
9005
ae7_exit_chip(struct hda_codec * codec)9006 static void ae7_exit_chip(struct hda_codec *codec)
9007 {
9008 chipio_set_stream_control(codec, 0x18, 0);
9009 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);
9010 chipio_set_stream_channels(codec, 0x21, 0);
9011 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);
9012 chipio_set_control_param(codec, 0x20, 0x01);
9013
9014 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
9015
9016 chipio_set_stream_control(codec, 0x18, 0);
9017 chipio_set_stream_control(codec, 0x0c, 0);
9018
9019 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
9020 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);
9021 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9022 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
9023 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);
9024 ca0113_mmio_gpio_set(codec, 0, false);
9025 ca0113_mmio_gpio_set(codec, 1, false);
9026 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9027
9028 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9029 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9030 }
9031
zxr_exit_chip(struct hda_codec * codec)9032 static void zxr_exit_chip(struct hda_codec *codec)
9033 {
9034 chipio_set_stream_control(codec, 0x03, 0);
9035 chipio_set_stream_control(codec, 0x04, 0);
9036 chipio_set_stream_control(codec, 0x14, 0);
9037 chipio_set_stream_control(codec, 0x0C, 0);
9038
9039 chipio_set_conn_rate(codec, 0x41, SR_192_000);
9040 chipio_set_conn_rate(codec, 0x91, SR_192_000);
9041
9042 chipio_write(codec, 0x18a020, 0x00000083);
9043
9044 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9045 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9046
9047 ca0132_clear_unsolicited(codec);
9048 sbz_set_pin_ctl_default(codec);
9049 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
9050
9051 ca0113_mmio_gpio_set(codec, 5, false);
9052 ca0113_mmio_gpio_set(codec, 2, false);
9053 ca0113_mmio_gpio_set(codec, 3, false);
9054 ca0113_mmio_gpio_set(codec, 0, false);
9055 ca0113_mmio_gpio_set(codec, 4, true);
9056 ca0113_mmio_gpio_set(codec, 0, true);
9057 ca0113_mmio_gpio_set(codec, 5, true);
9058 ca0113_mmio_gpio_set(codec, 2, false);
9059 ca0113_mmio_gpio_set(codec, 3, false);
9060 }
9061
ca0132_exit_chip(struct hda_codec * codec)9062 static void ca0132_exit_chip(struct hda_codec *codec)
9063 {
9064 /* put any chip cleanup stuffs here. */
9065
9066 if (dspload_is_loaded(codec))
9067 dsp_reset(codec);
9068 }
9069
9070 /*
9071 * This fixes a problem that was hard to reproduce. Very rarely, I would
9072 * boot up, and there would be no sound, but the DSP indicated it had loaded
9073 * properly. I did a few memory dumps to see if anything was different, and
9074 * there were a few areas of memory uninitialized with a1a2a3a4. This function
9075 * checks if those areas are uninitialized, and if they are, it'll attempt to
9076 * reload the card 3 times. Usually it fixes by the second.
9077 */
sbz_dsp_startup_check(struct hda_codec * codec)9078 static void sbz_dsp_startup_check(struct hda_codec *codec)
9079 {
9080 struct ca0132_spec *spec = codec->spec;
9081 unsigned int dsp_data_check[4];
9082 unsigned int cur_address = 0x390;
9083 unsigned int i;
9084 unsigned int failure = 0;
9085 unsigned int reload = 3;
9086
9087 if (spec->startup_check_entered)
9088 return;
9089
9090 spec->startup_check_entered = true;
9091
9092 for (i = 0; i < 4; i++) {
9093 chipio_read(codec, cur_address, &dsp_data_check[i]);
9094 cur_address += 0x4;
9095 }
9096 for (i = 0; i < 4; i++) {
9097 if (dsp_data_check[i] == 0xa1a2a3a4)
9098 failure = 1;
9099 }
9100
9101 codec_dbg(codec, "Startup Check: %d ", failure);
9102 if (failure)
9103 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
9104 /*
9105 * While the failure condition is true, and we haven't reached our
9106 * three reload limit, continue trying to reload the driver and
9107 * fix the issue.
9108 */
9109 while (failure && (reload != 0)) {
9110 codec_info(codec, "Reloading... Tries left: %d", reload);
9111 sbz_exit_chip(codec);
9112 spec->dsp_state = DSP_DOWNLOAD_INIT;
9113 codec->patch_ops.init(codec);
9114 failure = 0;
9115 for (i = 0; i < 4; i++) {
9116 chipio_read(codec, cur_address, &dsp_data_check[i]);
9117 cur_address += 0x4;
9118 }
9119 for (i = 0; i < 4; i++) {
9120 if (dsp_data_check[i] == 0xa1a2a3a4)
9121 failure = 1;
9122 }
9123 reload--;
9124 }
9125
9126 if (!failure && reload < 3)
9127 codec_info(codec, "DSP fixed.");
9128
9129 if (!failure)
9130 return;
9131
9132 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
9133 }
9134
9135 /*
9136 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
9137 * extra precision for decibel values. If you had the dB value in floating point
9138 * you would take the value after the decimal point, multiply by 64, and divide
9139 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
9140 * implement fixed point or floating point dB volumes. For now, I'll set them
9141 * to 0 just incase a value has lingered from a boot into Windows.
9142 */
ca0132_alt_vol_setup(struct hda_codec * codec)9143 static void ca0132_alt_vol_setup(struct hda_codec *codec)
9144 {
9145 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
9146 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
9147 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
9148 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
9149 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
9150 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
9151 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
9152 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
9153 }
9154
9155 /*
9156 * Extra commands that don't really fit anywhere else.
9157 */
sbz_pre_dsp_setup(struct hda_codec * codec)9158 static void sbz_pre_dsp_setup(struct hda_codec *codec)
9159 {
9160 struct ca0132_spec *spec = codec->spec;
9161
9162 writel(0x00820680, spec->mem_base + 0x01C);
9163 writel(0x00820680, spec->mem_base + 0x01C);
9164
9165 chipio_write(codec, 0x18b0a4, 0x000000c2);
9166
9167 snd_hda_codec_write(codec, 0x11, 0,
9168 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9169 }
9170
r3d_pre_dsp_setup(struct hda_codec * codec)9171 static void r3d_pre_dsp_setup(struct hda_codec *codec)
9172 {
9173 chipio_write(codec, 0x18b0a4, 0x000000c2);
9174
9175 chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9176
9177 snd_hda_codec_write(codec, 0x11, 0,
9178 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9179 }
9180
r3di_pre_dsp_setup(struct hda_codec * codec)9181 static void r3di_pre_dsp_setup(struct hda_codec *codec)
9182 {
9183 chipio_write(codec, 0x18b0a4, 0x000000c2);
9184
9185 chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9186 chipio_8051_write_exram(codec, 0x1920, 0x00);
9187 chipio_8051_write_exram(codec, 0x1921, 0x40);
9188
9189 snd_hda_codec_write(codec, 0x11, 0,
9190 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
9191 }
9192
9193 /*
9194 * The ZxR seems to use alternative DAC's for the surround channels, which
9195 * require PLL PMU setup for the clock rate, I'm guessing. Without setting
9196 * this up, we get no audio out of the surround jacks.
9197 */
zxr_pre_dsp_setup(struct hda_codec * codec)9198 static void zxr_pre_dsp_setup(struct hda_codec *codec)
9199 {
9200 static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 };
9201 static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d };
9202 unsigned int i;
9203
9204 chipio_write(codec, 0x189000, 0x0001f100);
9205 msleep(50);
9206 chipio_write(codec, 0x18900c, 0x0001f100);
9207 msleep(50);
9208
9209 /*
9210 * This writes a RET instruction at the entry point of the function at
9211 * 0xfa92 in exram. This function seems to have something to do with
9212 * ASI. Might be some way to prevent the card from reconfiguring the
9213 * ASI stuff itself.
9214 */
9215 chipio_8051_write_exram(codec, 0xfa92, 0x22);
9216
9217 chipio_8051_write_pll_pmu(codec, 0x51, 0x98);
9218
9219 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82);
9220 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3);
9221
9222 chipio_write(codec, 0x18902c, 0x00000000);
9223 msleep(50);
9224 chipio_write(codec, 0x18902c, 0x00000003);
9225 msleep(50);
9226
9227 for (i = 0; i < ARRAY_SIZE(addr); i++)
9228 chipio_8051_write_pll_pmu(codec, addr[i], data[i]);
9229 }
9230
9231 /*
9232 * These are sent before the DSP is downloaded. Not sure
9233 * what they do, or if they're necessary. Could possibly
9234 * be removed. Figure they're better to leave in.
9235 */
9236 static const unsigned int ca0113_mmio_init_address_sbz[] = {
9237 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c,
9238 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04
9239 };
9240
9241 static const unsigned int ca0113_mmio_init_data_sbz[] = {
9242 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9243 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7,
9244 0x000000c1, 0x00000080
9245 };
9246
9247 static const unsigned int ca0113_mmio_init_data_zxr[] = {
9248 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003,
9249 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7,
9250 0x000000c1, 0x00000080
9251 };
9252
9253 static const unsigned int ca0113_mmio_init_address_ae5[] = {
9254 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408,
9255 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800,
9256 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c,
9257 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c
9258 };
9259
9260 static const unsigned int ca0113_mmio_init_data_ae5[] = {
9261 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9262 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
9263 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f,
9264 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b,
9265 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030,
9266 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9267 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1,
9268 0x00000080, 0x00880680
9269 };
9270
ca0132_mmio_init_sbz(struct hda_codec * codec)9271 static void ca0132_mmio_init_sbz(struct hda_codec *codec)
9272 {
9273 struct ca0132_spec *spec = codec->spec;
9274 unsigned int tmp[2], i, count, cur_addr;
9275 const unsigned int *addr, *data;
9276
9277 addr = ca0113_mmio_init_address_sbz;
9278 for (i = 0; i < 3; i++)
9279 writel(0x00000000, spec->mem_base + addr[i]);
9280
9281 cur_addr = i;
9282 switch (ca0132_quirk(spec)) {
9283 case QUIRK_ZXR:
9284 tmp[0] = 0x00880480;
9285 tmp[1] = 0x00000080;
9286 break;
9287 case QUIRK_SBZ:
9288 tmp[0] = 0x00820680;
9289 tmp[1] = 0x00000083;
9290 break;
9291 case QUIRK_R3D:
9292 tmp[0] = 0x00880680;
9293 tmp[1] = 0x00000083;
9294 break;
9295 default:
9296 tmp[0] = 0x00000000;
9297 tmp[1] = 0x00000000;
9298 break;
9299 }
9300
9301 for (i = 0; i < 2; i++)
9302 writel(tmp[i], spec->mem_base + addr[cur_addr + i]);
9303
9304 cur_addr += i;
9305
9306 switch (ca0132_quirk(spec)) {
9307 case QUIRK_ZXR:
9308 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr);
9309 data = ca0113_mmio_init_data_zxr;
9310 break;
9311 default:
9312 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz);
9313 data = ca0113_mmio_init_data_sbz;
9314 break;
9315 }
9316
9317 for (i = 0; i < count; i++)
9318 writel(data[i], spec->mem_base + addr[cur_addr + i]);
9319 }
9320
ca0132_mmio_init_ae5(struct hda_codec * codec)9321 static void ca0132_mmio_init_ae5(struct hda_codec *codec)
9322 {
9323 struct ca0132_spec *spec = codec->spec;
9324 const unsigned int *addr, *data;
9325 unsigned int i, count;
9326
9327 addr = ca0113_mmio_init_address_ae5;
9328 data = ca0113_mmio_init_data_ae5;
9329 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5);
9330
9331 if (ca0132_quirk(spec) == QUIRK_AE7) {
9332 writel(0x00000680, spec->mem_base + 0x1c);
9333 writel(0x00880680, spec->mem_base + 0x1c);
9334 }
9335
9336 for (i = 0; i < count; i++) {
9337 /*
9338 * AE-7 shares all writes with the AE-5, except that it writes
9339 * a different value to 0x20c.
9340 */
9341 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) {
9342 writel(0x00800001, spec->mem_base + addr[i]);
9343 continue;
9344 }
9345
9346 writel(data[i], spec->mem_base + addr[i]);
9347 }
9348
9349 if (ca0132_quirk(spec) == QUIRK_AE5)
9350 writel(0x00880680, spec->mem_base + 0x1c);
9351 }
9352
ca0132_mmio_init(struct hda_codec * codec)9353 static void ca0132_mmio_init(struct hda_codec *codec)
9354 {
9355 struct ca0132_spec *spec = codec->spec;
9356
9357 switch (ca0132_quirk(spec)) {
9358 case QUIRK_R3D:
9359 case QUIRK_SBZ:
9360 case QUIRK_ZXR:
9361 ca0132_mmio_init_sbz(codec);
9362 break;
9363 case QUIRK_AE5:
9364 ca0132_mmio_init_ae5(codec);
9365 break;
9366 default:
9367 break;
9368 }
9369 }
9370
9371 static const unsigned int ca0132_ae5_register_set_addresses[] = {
9372 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304,
9373 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804
9374 };
9375
9376 static const unsigned char ca0132_ae5_register_set_data[] = {
9377 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b,
9378 0x01, 0x6b, 0x57
9379 };
9380
9381 /*
9382 * This function writes to some SFR's, does some region2 writes, and then
9383 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
9384 * what it does.
9385 */
ae5_register_set(struct hda_codec * codec)9386 static void ae5_register_set(struct hda_codec *codec)
9387 {
9388 struct ca0132_spec *spec = codec->spec;
9389 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses);
9390 const unsigned int *addr = ca0132_ae5_register_set_addresses;
9391 const unsigned char *data = ca0132_ae5_register_set_data;
9392 unsigned int i, cur_addr;
9393 unsigned char tmp[3];
9394
9395 if (ca0132_quirk(spec) == QUIRK_AE7)
9396 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
9397
9398 chipio_8051_write_direct(codec, 0x93, 0x10);
9399 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
9400
9401 if (ca0132_quirk(spec) == QUIRK_AE7) {
9402 tmp[0] = 0x03;
9403 tmp[1] = 0x03;
9404 tmp[2] = 0x07;
9405 } else {
9406 tmp[0] = 0x0f;
9407 tmp[1] = 0x0f;
9408 tmp[2] = 0x0f;
9409 }
9410
9411 for (i = cur_addr = 0; i < 3; i++, cur_addr++)
9412 writeb(tmp[i], spec->mem_base + addr[cur_addr]);
9413
9414 /*
9415 * First writes are in single bytes, final are in 4 bytes. So, we use
9416 * writeb, then writel.
9417 */
9418 for (i = 0; cur_addr < 12; i++, cur_addr++)
9419 writeb(data[i], spec->mem_base + addr[cur_addr]);
9420
9421 for (; cur_addr < count; i++, cur_addr++)
9422 writel(data[i], spec->mem_base + addr[cur_addr]);
9423
9424 writel(0x00800001, spec->mem_base + 0x20c);
9425
9426 if (ca0132_quirk(spec) == QUIRK_AE7) {
9427 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9428 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
9429 } else {
9430 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
9431 }
9432
9433 chipio_8051_write_direct(codec, 0x90, 0x00);
9434 chipio_8051_write_direct(codec, 0x90, 0x10);
9435
9436 if (ca0132_quirk(spec) == QUIRK_AE5)
9437 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
9438 }
9439
9440 /*
9441 * Extra init functions for alternative ca0132 codecs. Done
9442 * here so they don't clutter up the main ca0132_init function
9443 * anymore than they have to.
9444 */
ca0132_alt_init(struct hda_codec * codec)9445 static void ca0132_alt_init(struct hda_codec *codec)
9446 {
9447 struct ca0132_spec *spec = codec->spec;
9448
9449 ca0132_alt_vol_setup(codec);
9450
9451 switch (ca0132_quirk(spec)) {
9452 case QUIRK_SBZ:
9453 codec_dbg(codec, "SBZ alt_init");
9454 ca0132_gpio_init(codec);
9455 sbz_pre_dsp_setup(codec);
9456 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9457 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9458 break;
9459 case QUIRK_R3DI:
9460 codec_dbg(codec, "R3DI alt_init");
9461 ca0132_gpio_init(codec);
9462 ca0132_gpio_setup(codec);
9463 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
9464 r3di_pre_dsp_setup(codec);
9465 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9466 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
9467 break;
9468 case QUIRK_R3D:
9469 r3d_pre_dsp_setup(codec);
9470 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9471 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9472 break;
9473 case QUIRK_AE5:
9474 ca0132_gpio_init(codec);
9475 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9476 chipio_write(codec, 0x18b030, 0x00000020);
9477 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9478 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9479 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9480 break;
9481 case QUIRK_AE7:
9482 ca0132_gpio_init(codec);
9483 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9484 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9485 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9486 chipio_write(codec, 0x18b008, 0x000000f8);
9487 chipio_write(codec, 0x18b008, 0x000000f0);
9488 chipio_write(codec, 0x18b030, 0x00000020);
9489 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9490 break;
9491 case QUIRK_ZXR:
9492 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9493 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9494 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9495 zxr_pre_dsp_setup(codec);
9496 break;
9497 default:
9498 break;
9499 }
9500 }
9501
ca0132_init(struct hda_codec * codec)9502 static int ca0132_init(struct hda_codec *codec)
9503 {
9504 struct ca0132_spec *spec = codec->spec;
9505 struct auto_pin_cfg *cfg = &spec->autocfg;
9506 int i;
9507 bool dsp_loaded;
9508
9509 /*
9510 * If the DSP is already downloaded, and init has been entered again,
9511 * there's only two reasons for it. One, the codec has awaken from a
9512 * suspended state, and in that case dspload_is_loaded will return
9513 * false, and the init will be ran again. The other reason it gets
9514 * re entered is on startup for some reason it triggers a suspend and
9515 * resume state. In this case, it will check if the DSP is downloaded,
9516 * and not run the init function again. For codecs using alt_functions,
9517 * it will check if the DSP is loaded properly.
9518 */
9519 if (spec->dsp_state == DSP_DOWNLOADED) {
9520 dsp_loaded = dspload_is_loaded(codec);
9521 if (!dsp_loaded) {
9522 spec->dsp_reload = true;
9523 spec->dsp_state = DSP_DOWNLOAD_INIT;
9524 } else {
9525 if (ca0132_quirk(spec) == QUIRK_SBZ)
9526 sbz_dsp_startup_check(codec);
9527 return 0;
9528 }
9529 }
9530
9531 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
9532 spec->dsp_state = DSP_DOWNLOAD_INIT;
9533 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
9534
9535 if (ca0132_use_pci_mmio(spec))
9536 ca0132_mmio_init(codec);
9537
9538 snd_hda_power_up_pm(codec);
9539
9540 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7)
9541 ae5_register_set(codec);
9542
9543 ca0132_init_params(codec);
9544 ca0132_init_flags(codec);
9545
9546 snd_hda_sequence_write(codec, spec->base_init_verbs);
9547
9548 if (ca0132_use_alt_functions(spec))
9549 ca0132_alt_init(codec);
9550
9551 ca0132_download_dsp(codec);
9552
9553 ca0132_refresh_widget_caps(codec);
9554
9555 switch (ca0132_quirk(spec)) {
9556 case QUIRK_R3DI:
9557 case QUIRK_R3D:
9558 r3d_setup_defaults(codec);
9559 break;
9560 case QUIRK_SBZ:
9561 case QUIRK_ZXR:
9562 sbz_setup_defaults(codec);
9563 break;
9564 case QUIRK_AE5:
9565 ae5_setup_defaults(codec);
9566 break;
9567 case QUIRK_AE7:
9568 ae7_setup_defaults(codec);
9569 break;
9570 default:
9571 ca0132_setup_defaults(codec);
9572 ca0132_init_analog_mic2(codec);
9573 ca0132_init_dmic(codec);
9574 break;
9575 }
9576
9577 for (i = 0; i < spec->num_outputs; i++)
9578 init_output(codec, spec->out_pins[i], spec->dacs[0]);
9579
9580 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9581
9582 for (i = 0; i < spec->num_inputs; i++)
9583 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9584
9585 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9586
9587 if (!ca0132_use_alt_functions(spec)) {
9588 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9589 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9590 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
9591 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9592 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
9593 }
9594
9595 if (ca0132_quirk(spec) == QUIRK_SBZ)
9596 ca0132_gpio_setup(codec);
9597
9598 snd_hda_sequence_write(codec, spec->spec_init_verbs);
9599 if (ca0132_use_alt_functions(spec)) {
9600 ca0132_alt_select_out(codec);
9601 ca0132_alt_select_in(codec);
9602 } else {
9603 ca0132_select_out(codec);
9604 ca0132_select_mic(codec);
9605 }
9606
9607 snd_hda_jack_report_sync(codec);
9608
9609 /*
9610 * Re set the PlayEnhancement switch on a resume event, because the
9611 * controls will not be reloaded.
9612 */
9613 if (spec->dsp_reload) {
9614 spec->dsp_reload = false;
9615 ca0132_pe_switch_set(codec);
9616 }
9617
9618 snd_hda_power_down_pm(codec);
9619
9620 return 0;
9621 }
9622
dbpro_init(struct hda_codec * codec)9623 static int dbpro_init(struct hda_codec *codec)
9624 {
9625 struct ca0132_spec *spec = codec->spec;
9626 struct auto_pin_cfg *cfg = &spec->autocfg;
9627 unsigned int i;
9628
9629 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9630 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9631
9632 for (i = 0; i < spec->num_inputs; i++)
9633 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9634
9635 return 0;
9636 }
9637
ca0132_free(struct hda_codec * codec)9638 static void ca0132_free(struct hda_codec *codec)
9639 {
9640 struct ca0132_spec *spec = codec->spec;
9641
9642 cancel_delayed_work_sync(&spec->unsol_hp_work);
9643 snd_hda_power_up(codec);
9644 switch (ca0132_quirk(spec)) {
9645 case QUIRK_SBZ:
9646 sbz_exit_chip(codec);
9647 break;
9648 case QUIRK_ZXR:
9649 zxr_exit_chip(codec);
9650 break;
9651 case QUIRK_R3D:
9652 r3d_exit_chip(codec);
9653 break;
9654 case QUIRK_AE5:
9655 ae5_exit_chip(codec);
9656 break;
9657 case QUIRK_AE7:
9658 ae7_exit_chip(codec);
9659 break;
9660 case QUIRK_R3DI:
9661 r3di_gpio_shutdown(codec);
9662 break;
9663 default:
9664 break;
9665 }
9666
9667 snd_hda_sequence_write(codec, spec->base_exit_verbs);
9668 ca0132_exit_chip(codec);
9669
9670 snd_hda_power_down(codec);
9671 #ifdef CONFIG_PCI
9672 if (spec->mem_base)
9673 pci_iounmap(codec->bus->pci, spec->mem_base);
9674 #endif
9675 kfree(spec->spec_init_verbs);
9676 kfree(codec->spec);
9677 }
9678
dbpro_free(struct hda_codec * codec)9679 static void dbpro_free(struct hda_codec *codec)
9680 {
9681 struct ca0132_spec *spec = codec->spec;
9682
9683 zxr_dbpro_power_state_shutdown(codec);
9684
9685 kfree(spec->spec_init_verbs);
9686 kfree(codec->spec);
9687 }
9688
9689 #ifdef CONFIG_PM
ca0132_suspend(struct hda_codec * codec)9690 static int ca0132_suspend(struct hda_codec *codec)
9691 {
9692 struct ca0132_spec *spec = codec->spec;
9693
9694 cancel_delayed_work_sync(&spec->unsol_hp_work);
9695 return 0;
9696 }
9697 #endif
9698
9699 static const struct hda_codec_ops ca0132_patch_ops = {
9700 .build_controls = ca0132_build_controls,
9701 .build_pcms = ca0132_build_pcms,
9702 .init = ca0132_init,
9703 .free = ca0132_free,
9704 .unsol_event = snd_hda_jack_unsol_event,
9705 #ifdef CONFIG_PM
9706 .suspend = ca0132_suspend,
9707 #endif
9708 };
9709
9710 static const struct hda_codec_ops dbpro_patch_ops = {
9711 .build_controls = dbpro_build_controls,
9712 .build_pcms = dbpro_build_pcms,
9713 .init = dbpro_init,
9714 .free = dbpro_free,
9715 };
9716
ca0132_config(struct hda_codec * codec)9717 static void ca0132_config(struct hda_codec *codec)
9718 {
9719 struct ca0132_spec *spec = codec->spec;
9720
9721 spec->dacs[0] = 0x2;
9722 spec->dacs[1] = 0x3;
9723 spec->dacs[2] = 0x4;
9724
9725 spec->multiout.dac_nids = spec->dacs;
9726 spec->multiout.num_dacs = 3;
9727
9728 if (!ca0132_use_alt_functions(spec))
9729 spec->multiout.max_channels = 2;
9730 else
9731 spec->multiout.max_channels = 6;
9732
9733 switch (ca0132_quirk(spec)) {
9734 case QUIRK_ALIENWARE:
9735 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
9736 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
9737 break;
9738 case QUIRK_SBZ:
9739 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
9740 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
9741 break;
9742 case QUIRK_ZXR:
9743 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
9744 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
9745 break;
9746 case QUIRK_R3D:
9747 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
9748 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
9749 break;
9750 case QUIRK_R3DI:
9751 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
9752 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
9753 break;
9754 case QUIRK_AE5:
9755 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
9756 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
9757 break;
9758 case QUIRK_AE7:
9759 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__);
9760 snd_hda_apply_pincfgs(codec, ae7_pincfgs);
9761 break;
9762 default:
9763 break;
9764 }
9765
9766 switch (ca0132_quirk(spec)) {
9767 case QUIRK_ALIENWARE:
9768 spec->num_outputs = 2;
9769 spec->out_pins[0] = 0x0b; /* speaker out */
9770 spec->out_pins[1] = 0x0f;
9771 spec->shared_out_nid = 0x2;
9772 spec->unsol_tag_hp = 0x0f;
9773
9774 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9775 spec->adcs[1] = 0x8; /* analog mic2 */
9776 spec->adcs[2] = 0xa; /* what u hear */
9777
9778 spec->num_inputs = 3;
9779 spec->input_pins[0] = 0x12;
9780 spec->input_pins[1] = 0x11;
9781 spec->input_pins[2] = 0x13;
9782 spec->shared_mic_nid = 0x7;
9783 spec->unsol_tag_amic1 = 0x11;
9784 break;
9785 case QUIRK_SBZ:
9786 case QUIRK_R3D:
9787 spec->num_outputs = 2;
9788 spec->out_pins[0] = 0x0B; /* Line out */
9789 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9790 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9791 spec->out_pins[3] = 0x11; /* Rear surround */
9792 spec->shared_out_nid = 0x2;
9793 spec->unsol_tag_hp = spec->out_pins[1];
9794 spec->unsol_tag_front_hp = spec->out_pins[2];
9795
9796 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9797 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9798 spec->adcs[2] = 0xa; /* what u hear */
9799
9800 spec->num_inputs = 2;
9801 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9802 spec->input_pins[1] = 0x13; /* What U Hear */
9803 spec->shared_mic_nid = 0x7;
9804 spec->unsol_tag_amic1 = spec->input_pins[0];
9805
9806 /* SPDIF I/O */
9807 spec->dig_out = 0x05;
9808 spec->multiout.dig_out_nid = spec->dig_out;
9809 spec->dig_in = 0x09;
9810 break;
9811 case QUIRK_ZXR:
9812 spec->num_outputs = 2;
9813 spec->out_pins[0] = 0x0B; /* Line out */
9814 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9815 spec->out_pins[2] = 0x10; /* Center/LFE */
9816 spec->out_pins[3] = 0x11; /* Rear surround */
9817 spec->shared_out_nid = 0x2;
9818 spec->unsol_tag_hp = spec->out_pins[1];
9819 spec->unsol_tag_front_hp = spec->out_pins[2];
9820
9821 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9822 spec->adcs[1] = 0x8; /* Not connected, no front mic */
9823 spec->adcs[2] = 0xa; /* what u hear */
9824
9825 spec->num_inputs = 2;
9826 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9827 spec->input_pins[1] = 0x13; /* What U Hear */
9828 spec->shared_mic_nid = 0x7;
9829 spec->unsol_tag_amic1 = spec->input_pins[0];
9830 break;
9831 case QUIRK_ZXR_DBPRO:
9832 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
9833
9834 spec->num_inputs = 1;
9835 spec->input_pins[0] = 0x11; /* RCA Line-in */
9836
9837 spec->dig_out = 0x05;
9838 spec->multiout.dig_out_nid = spec->dig_out;
9839
9840 spec->dig_in = 0x09;
9841 break;
9842 case QUIRK_AE5:
9843 case QUIRK_AE7:
9844 spec->num_outputs = 2;
9845 spec->out_pins[0] = 0x0B; /* Line out */
9846 spec->out_pins[1] = 0x11; /* Rear headphone out */
9847 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9848 spec->out_pins[3] = 0x0F; /* Rear surround */
9849 spec->shared_out_nid = 0x2;
9850 spec->unsol_tag_hp = spec->out_pins[1];
9851 spec->unsol_tag_front_hp = spec->out_pins[2];
9852
9853 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9854 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9855 spec->adcs[2] = 0xa; /* what u hear */
9856
9857 spec->num_inputs = 2;
9858 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9859 spec->input_pins[1] = 0x13; /* What U Hear */
9860 spec->shared_mic_nid = 0x7;
9861 spec->unsol_tag_amic1 = spec->input_pins[0];
9862
9863 /* SPDIF I/O */
9864 spec->dig_out = 0x05;
9865 spec->multiout.dig_out_nid = spec->dig_out;
9866 break;
9867 case QUIRK_R3DI:
9868 spec->num_outputs = 2;
9869 spec->out_pins[0] = 0x0B; /* Line out */
9870 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9871 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9872 spec->out_pins[3] = 0x11; /* Rear surround */
9873 spec->shared_out_nid = 0x2;
9874 spec->unsol_tag_hp = spec->out_pins[1];
9875 spec->unsol_tag_front_hp = spec->out_pins[2];
9876
9877 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
9878 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
9879 spec->adcs[2] = 0x0a; /* what u hear */
9880
9881 spec->num_inputs = 2;
9882 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9883 spec->input_pins[1] = 0x13; /* What U Hear */
9884 spec->shared_mic_nid = 0x7;
9885 spec->unsol_tag_amic1 = spec->input_pins[0];
9886
9887 /* SPDIF I/O */
9888 spec->dig_out = 0x05;
9889 spec->multiout.dig_out_nid = spec->dig_out;
9890 break;
9891 default:
9892 spec->num_outputs = 2;
9893 spec->out_pins[0] = 0x0b; /* speaker out */
9894 spec->out_pins[1] = 0x10; /* headphone out */
9895 spec->shared_out_nid = 0x2;
9896 spec->unsol_tag_hp = spec->out_pins[1];
9897
9898 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9899 spec->adcs[1] = 0x8; /* analog mic2 */
9900 spec->adcs[2] = 0xa; /* what u hear */
9901
9902 spec->num_inputs = 3;
9903 spec->input_pins[0] = 0x12;
9904 spec->input_pins[1] = 0x11;
9905 spec->input_pins[2] = 0x13;
9906 spec->shared_mic_nid = 0x7;
9907 spec->unsol_tag_amic1 = spec->input_pins[0];
9908
9909 /* SPDIF I/O */
9910 spec->dig_out = 0x05;
9911 spec->multiout.dig_out_nid = spec->dig_out;
9912 spec->dig_in = 0x09;
9913 break;
9914 }
9915 }
9916
ca0132_prepare_verbs(struct hda_codec * codec)9917 static int ca0132_prepare_verbs(struct hda_codec *codec)
9918 {
9919 /* Verbs + terminator (an empty element) */
9920 #define NUM_SPEC_VERBS 2
9921 struct ca0132_spec *spec = codec->spec;
9922
9923 spec->chip_init_verbs = ca0132_init_verbs0;
9924 /*
9925 * Since desktop cards use pci_mmio, this can be used to determine
9926 * whether or not to use these verbs instead of a separate bool.
9927 */
9928 if (ca0132_use_pci_mmio(spec))
9929 spec->desktop_init_verbs = ca0132_init_verbs1;
9930 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
9931 sizeof(struct hda_verb),
9932 GFP_KERNEL);
9933 if (!spec->spec_init_verbs)
9934 return -ENOMEM;
9935
9936 /* config EAPD */
9937 spec->spec_init_verbs[0].nid = 0x0b;
9938 spec->spec_init_verbs[0].param = 0x78D;
9939 spec->spec_init_verbs[0].verb = 0x00;
9940
9941 /* Previously commented configuration */
9942 /*
9943 spec->spec_init_verbs[2].nid = 0x0b;
9944 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
9945 spec->spec_init_verbs[2].verb = 0x02;
9946
9947 spec->spec_init_verbs[3].nid = 0x10;
9948 spec->spec_init_verbs[3].param = 0x78D;
9949 spec->spec_init_verbs[3].verb = 0x02;
9950
9951 spec->spec_init_verbs[4].nid = 0x10;
9952 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
9953 spec->spec_init_verbs[4].verb = 0x02;
9954 */
9955
9956 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
9957 return 0;
9958 }
9959
9960 /*
9961 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
9962 * Sound Blaster Z cards. However, they have different HDA codec subsystem
9963 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
9964 * daughter boards ID.
9965 */
sbz_detect_quirk(struct hda_codec * codec)9966 static void sbz_detect_quirk(struct hda_codec *codec)
9967 {
9968 struct ca0132_spec *spec = codec->spec;
9969
9970 switch (codec->core.subsystem_id) {
9971 case 0x11020033:
9972 spec->quirk = QUIRK_ZXR;
9973 break;
9974 case 0x1102003f:
9975 spec->quirk = QUIRK_ZXR_DBPRO;
9976 break;
9977 default:
9978 spec->quirk = QUIRK_SBZ;
9979 break;
9980 }
9981 }
9982
patch_ca0132(struct hda_codec * codec)9983 static int patch_ca0132(struct hda_codec *codec)
9984 {
9985 struct ca0132_spec *spec;
9986 int err;
9987 const struct snd_pci_quirk *quirk;
9988
9989 codec_dbg(codec, "patch_ca0132\n");
9990
9991 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
9992 if (!spec)
9993 return -ENOMEM;
9994 codec->spec = spec;
9995 spec->codec = codec;
9996
9997 /* Detect codec quirk */
9998 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
9999 if (quirk)
10000 spec->quirk = quirk->value;
10001 else
10002 spec->quirk = QUIRK_NONE;
10003 if (ca0132_quirk(spec) == QUIRK_SBZ)
10004 sbz_detect_quirk(codec);
10005
10006 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
10007 codec->patch_ops = dbpro_patch_ops;
10008 else
10009 codec->patch_ops = ca0132_patch_ops;
10010
10011 codec->pcm_format_first = 1;
10012 codec->no_sticky_stream = 1;
10013
10014
10015 spec->dsp_state = DSP_DOWNLOAD_INIT;
10016 spec->num_mixers = 1;
10017
10018 /* Set which mixers each quirk uses. */
10019 switch (ca0132_quirk(spec)) {
10020 case QUIRK_SBZ:
10021 spec->mixers[0] = desktop_mixer;
10022 snd_hda_codec_set_name(codec, "Sound Blaster Z");
10023 break;
10024 case QUIRK_ZXR:
10025 spec->mixers[0] = desktop_mixer;
10026 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
10027 break;
10028 case QUIRK_ZXR_DBPRO:
10029 break;
10030 case QUIRK_R3D:
10031 spec->mixers[0] = desktop_mixer;
10032 snd_hda_codec_set_name(codec, "Recon3D");
10033 break;
10034 case QUIRK_R3DI:
10035 spec->mixers[0] = r3di_mixer;
10036 snd_hda_codec_set_name(codec, "Recon3Di");
10037 break;
10038 case QUIRK_AE5:
10039 spec->mixers[0] = desktop_mixer;
10040 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
10041 break;
10042 case QUIRK_AE7:
10043 spec->mixers[0] = desktop_mixer;
10044 snd_hda_codec_set_name(codec, "Sound Blaster AE-7");
10045 break;
10046 default:
10047 spec->mixers[0] = ca0132_mixer;
10048 break;
10049 }
10050
10051 /* Setup whether or not to use alt functions/controls/pci_mmio */
10052 switch (ca0132_quirk(spec)) {
10053 case QUIRK_SBZ:
10054 case QUIRK_R3D:
10055 case QUIRK_AE5:
10056 case QUIRK_AE7:
10057 case QUIRK_ZXR:
10058 spec->use_alt_controls = true;
10059 spec->use_alt_functions = true;
10060 spec->use_pci_mmio = true;
10061 break;
10062 case QUIRK_R3DI:
10063 spec->use_alt_controls = true;
10064 spec->use_alt_functions = true;
10065 spec->use_pci_mmio = false;
10066 break;
10067 default:
10068 spec->use_alt_controls = false;
10069 spec->use_alt_functions = false;
10070 spec->use_pci_mmio = false;
10071 break;
10072 }
10073
10074 #ifdef CONFIG_PCI
10075 if (spec->use_pci_mmio) {
10076 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
10077 if (spec->mem_base == NULL) {
10078 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
10079 spec->quirk = QUIRK_NONE;
10080 }
10081 }
10082 #endif
10083
10084 spec->base_init_verbs = ca0132_base_init_verbs;
10085 spec->base_exit_verbs = ca0132_base_exit_verbs;
10086
10087 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
10088
10089 ca0132_init_chip(codec);
10090
10091 ca0132_config(codec);
10092
10093 err = ca0132_prepare_verbs(codec);
10094 if (err < 0)
10095 goto error;
10096
10097 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
10098 if (err < 0)
10099 goto error;
10100
10101 ca0132_setup_unsol(codec);
10102
10103 return 0;
10104
10105 error:
10106 ca0132_free(codec);
10107 return err;
10108 }
10109
10110 /*
10111 * patch entries
10112 */
10113 static const struct hda_device_id snd_hda_id_ca0132[] = {
10114 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
10115 {} /* terminator */
10116 };
10117 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
10118
10119 MODULE_LICENSE("GPL");
10120 MODULE_DESCRIPTION("Creative Sound Core3D codec");
10121
10122 static struct hda_codec_driver ca0132_driver = {
10123 .id = snd_hda_id_ca0132,
10124 };
10125
10126 module_hda_codec_driver(ca0132_driver);
10127