1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * rt1011.c -- rt1011 ALSA SoC amplifier component driver
4 *
5 * Copyright(c) 2019 Realtek Semiconductor Corp.
6 *
7 * Author: Shuming Fan <shumingf@realtek.com>
8 *
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/pm.h>
16 #include <linux/gpio.h>
17 #include <linux/i2c.h>
18 #include <linux/acpi.h>
19 #include <linux/regmap.h>
20 #include <linux/of_gpio.h>
21 #include <linux/platform_device.h>
22 #include <linux/firmware.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30
31 #include "rl6231.h"
32 #include "rt1011.h"
33
34 static int rt1011_calibrate(struct rt1011_priv *rt1011,
35 unsigned char cali_flag);
36
37 static const struct reg_sequence init_list[] = {
38
39 { RT1011_POWER_9, 0xa840 },
40
41 { RT1011_ADC_SET_5, 0x0a20 },
42 { RT1011_DAC_SET_2, 0xa032 },
43
44 { RT1011_SPK_PRO_DC_DET_1, 0xb00c },
45 { RT1011_SPK_PRO_DC_DET_2, 0xcccc },
46
47 { RT1011_A_TIMING_1, 0x6054 },
48
49 { RT1011_POWER_7, 0x3e55 },
50 { RT1011_POWER_8, 0x0520 },
51 { RT1011_BOOST_CON_1, 0xe188 },
52 { RT1011_POWER_4, 0x16f2 },
53
54 { RT1011_CROSS_BQ_SET_1, 0x0004 },
55 { RT1011_SIL_DET, 0xc313 },
56 { RT1011_SINE_GEN_REG_1, 0x0707 },
57
58 { RT1011_DC_CALIB_CLASSD_3, 0xcb00 },
59
60 { RT1011_DAC_SET_1, 0xe702 },
61 { RT1011_DAC_SET_3, 0x2004 },
62 };
63
64 static const struct reg_default rt1011_reg[] = {
65 {0x0000, 0x0000},
66 {0x0002, 0x0000},
67 {0x0004, 0xa000},
68 {0x0006, 0x0000},
69 {0x0008, 0x0003},
70 {0x000a, 0x087e},
71 {0x000c, 0x0020},
72 {0x000e, 0x9002},
73 {0x0010, 0x0000},
74 {0x0012, 0x0000},
75 {0x0020, 0x0c40},
76 {0x0022, 0x4313},
77 {0x0076, 0x0000},
78 {0x0078, 0x0000},
79 {0x007a, 0x0000},
80 {0x007c, 0x10ec},
81 {0x007d, 0x1011},
82 {0x00f0, 0x5000},
83 {0x00f2, 0x0374},
84 {0x00f3, 0x0000},
85 {0x00f4, 0x0000},
86 {0x0100, 0x0038},
87 {0x0102, 0xff02},
88 {0x0104, 0x0232},
89 {0x0106, 0x200c},
90 {0x0107, 0x0000},
91 {0x0108, 0x2f2f},
92 {0x010a, 0x2f2f},
93 {0x010c, 0x002f},
94 {0x010e, 0xe000},
95 {0x0110, 0x0820},
96 {0x0111, 0x4010},
97 {0x0112, 0x0000},
98 {0x0114, 0x0000},
99 {0x0116, 0x0000},
100 {0x0118, 0x0000},
101 {0x011a, 0x0101},
102 {0x011c, 0x4567},
103 {0x011e, 0x0000},
104 {0x0120, 0x0000},
105 {0x0122, 0x0000},
106 {0x0124, 0x0123},
107 {0x0126, 0x4567},
108 {0x0200, 0x0000},
109 {0x0300, 0xffdd},
110 {0x0302, 0x001e},
111 {0x0311, 0x0000},
112 {0x0313, 0x5254},
113 {0x0314, 0x0062},
114 {0x0316, 0x7f40},
115 {0x0319, 0x000f},
116 {0x031a, 0xffff},
117 {0x031b, 0x0000},
118 {0x031c, 0x009f},
119 {0x031d, 0xffff},
120 {0x031e, 0x0000},
121 {0x031f, 0x0000},
122 {0x0320, 0xe31c},
123 {0x0321, 0x0000},
124 {0x0322, 0x0000},
125 {0x0324, 0x0000},
126 {0x0326, 0x0002},
127 {0x0328, 0x20b2},
128 {0x0329, 0x0175},
129 {0x032a, 0x32ad},
130 {0x032b, 0x3455},
131 {0x032c, 0x0528},
132 {0x032d, 0xa800},
133 {0x032e, 0x030e},
134 {0x0330, 0x2080},
135 {0x0332, 0x0034},
136 {0x0334, 0x0000},
137 {0x0508, 0x0010},
138 {0x050a, 0x0018},
139 {0x050c, 0x0000},
140 {0x050d, 0xffff},
141 {0x050e, 0x1f1f},
142 {0x050f, 0x04ff},
143 {0x0510, 0x4020},
144 {0x0511, 0x01f0},
145 {0x0512, 0x0702},
146 {0x0516, 0xbb80},
147 {0x0517, 0xffff},
148 {0x0518, 0xffff},
149 {0x0519, 0x307f},
150 {0x051a, 0xffff},
151 {0x051b, 0x0000},
152 {0x051c, 0x0000},
153 {0x051d, 0x2000},
154 {0x051e, 0x0000},
155 {0x051f, 0x0000},
156 {0x0520, 0x0000},
157 {0x0521, 0x1001},
158 {0x0522, 0x7fff},
159 {0x0524, 0x7fff},
160 {0x0526, 0x0000},
161 {0x0528, 0x0000},
162 {0x052a, 0x0000},
163 {0x0530, 0x0401},
164 {0x0532, 0x3000},
165 {0x0534, 0x0000},
166 {0x0535, 0xffff},
167 {0x0536, 0x101c},
168 {0x0538, 0x1814},
169 {0x053a, 0x100c},
170 {0x053c, 0x0804},
171 {0x053d, 0x0000},
172 {0x053e, 0x0000},
173 {0x053f, 0x0000},
174 {0x0540, 0x0000},
175 {0x0541, 0x0000},
176 {0x0542, 0x0000},
177 {0x0543, 0x0000},
178 {0x0544, 0x001c},
179 {0x0545, 0x1814},
180 {0x0546, 0x100c},
181 {0x0547, 0x0804},
182 {0x0548, 0x0000},
183 {0x0549, 0x0000},
184 {0x054a, 0x0000},
185 {0x054b, 0x0000},
186 {0x054c, 0x0000},
187 {0x054d, 0x0000},
188 {0x054e, 0x0000},
189 {0x054f, 0x0000},
190 {0x0566, 0x0000},
191 {0x0568, 0x20f1},
192 {0x056a, 0x0007},
193 {0x0600, 0x9d00},
194 {0x0611, 0x2000},
195 {0x0612, 0x505f},
196 {0x0613, 0x0444},
197 {0x0614, 0x4000},
198 {0x0615, 0x4004},
199 {0x0616, 0x0606},
200 {0x0617, 0x8904},
201 {0x0618, 0xe021},
202 {0x0621, 0x2000},
203 {0x0622, 0x505f},
204 {0x0623, 0x0444},
205 {0x0624, 0x4000},
206 {0x0625, 0x4004},
207 {0x0626, 0x0606},
208 {0x0627, 0x8704},
209 {0x0628, 0xe021},
210 {0x0631, 0x2000},
211 {0x0632, 0x517f},
212 {0x0633, 0x0440},
213 {0x0634, 0x4000},
214 {0x0635, 0x4104},
215 {0x0636, 0x0306},
216 {0x0637, 0x8904},
217 {0x0638, 0xe021},
218 {0x0702, 0x0014},
219 {0x0704, 0x0000},
220 {0x0706, 0x0014},
221 {0x0708, 0x0000},
222 {0x070a, 0x0000},
223 {0x0710, 0x0200},
224 {0x0711, 0x0000},
225 {0x0712, 0x0200},
226 {0x0713, 0x0000},
227 {0x0720, 0x0200},
228 {0x0721, 0x0000},
229 {0x0722, 0x0000},
230 {0x0723, 0x0000},
231 {0x0724, 0x0000},
232 {0x0725, 0x0000},
233 {0x0726, 0x0000},
234 {0x0727, 0x0000},
235 {0x0728, 0x0000},
236 {0x0729, 0x0000},
237 {0x0730, 0x0200},
238 {0x0731, 0x0000},
239 {0x0732, 0x0000},
240 {0x0733, 0x0000},
241 {0x0734, 0x0000},
242 {0x0735, 0x0000},
243 {0x0736, 0x0000},
244 {0x0737, 0x0000},
245 {0x0738, 0x0000},
246 {0x0739, 0x0000},
247 {0x0740, 0x0200},
248 {0x0741, 0x0000},
249 {0x0742, 0x0000},
250 {0x0743, 0x0000},
251 {0x0744, 0x0000},
252 {0x0745, 0x0000},
253 {0x0746, 0x0000},
254 {0x0747, 0x0000},
255 {0x0748, 0x0000},
256 {0x0749, 0x0000},
257 {0x0750, 0x0200},
258 {0x0751, 0x0000},
259 {0x0752, 0x0000},
260 {0x0753, 0x0000},
261 {0x0754, 0x0000},
262 {0x0755, 0x0000},
263 {0x0756, 0x0000},
264 {0x0757, 0x0000},
265 {0x0758, 0x0000},
266 {0x0759, 0x0000},
267 {0x0760, 0x0200},
268 {0x0761, 0x0000},
269 {0x0762, 0x0000},
270 {0x0763, 0x0000},
271 {0x0764, 0x0000},
272 {0x0765, 0x0000},
273 {0x0766, 0x0000},
274 {0x0767, 0x0000},
275 {0x0768, 0x0000},
276 {0x0769, 0x0000},
277 {0x0770, 0x0200},
278 {0x0771, 0x0000},
279 {0x0772, 0x0000},
280 {0x0773, 0x0000},
281 {0x0774, 0x0000},
282 {0x0775, 0x0000},
283 {0x0776, 0x0000},
284 {0x0777, 0x0000},
285 {0x0778, 0x0000},
286 {0x0779, 0x0000},
287 {0x0780, 0x0200},
288 {0x0781, 0x0000},
289 {0x0782, 0x0000},
290 {0x0783, 0x0000},
291 {0x0784, 0x0000},
292 {0x0785, 0x0000},
293 {0x0786, 0x0000},
294 {0x0787, 0x0000},
295 {0x0788, 0x0000},
296 {0x0789, 0x0000},
297 {0x0790, 0x0200},
298 {0x0791, 0x0000},
299 {0x0792, 0x0000},
300 {0x0793, 0x0000},
301 {0x0794, 0x0000},
302 {0x0795, 0x0000},
303 {0x0796, 0x0000},
304 {0x0797, 0x0000},
305 {0x0798, 0x0000},
306 {0x0799, 0x0000},
307 {0x07a0, 0x0200},
308 {0x07a1, 0x0000},
309 {0x07a2, 0x0000},
310 {0x07a3, 0x0000},
311 {0x07a4, 0x0000},
312 {0x07a5, 0x0000},
313 {0x07a6, 0x0000},
314 {0x07a7, 0x0000},
315 {0x07a8, 0x0000},
316 {0x07a9, 0x0000},
317 {0x07b0, 0x0200},
318 {0x07b1, 0x0000},
319 {0x07b2, 0x0000},
320 {0x07b3, 0x0000},
321 {0x07b4, 0x0000},
322 {0x07b5, 0x0000},
323 {0x07b6, 0x0000},
324 {0x07b7, 0x0000},
325 {0x07b8, 0x0000},
326 {0x07b9, 0x0000},
327 {0x07c0, 0x0200},
328 {0x07c1, 0x0000},
329 {0x07c2, 0x0000},
330 {0x07c3, 0x0000},
331 {0x07c4, 0x0000},
332 {0x07c5, 0x0000},
333 {0x07c6, 0x0000},
334 {0x07c7, 0x0000},
335 {0x07c8, 0x0000},
336 {0x07c9, 0x0000},
337 {0x1000, 0x4040},
338 {0x1002, 0x6505},
339 {0x1004, 0x5405},
340 {0x1006, 0x5555},
341 {0x1007, 0x003f},
342 {0x1008, 0x7fd7},
343 {0x1009, 0x770f},
344 {0x100a, 0xfffe},
345 {0x100b, 0xe000},
346 {0x100c, 0x0000},
347 {0x100d, 0x0007},
348 {0x1010, 0xa433},
349 {0x1020, 0x0000},
350 {0x1022, 0x0000},
351 {0x1024, 0x0000},
352 {0x1200, 0x5a01},
353 {0x1202, 0x6324},
354 {0x1204, 0x0b00},
355 {0x1206, 0x0000},
356 {0x1208, 0x0000},
357 {0x120a, 0x0024},
358 {0x120c, 0x0000},
359 {0x120e, 0x000e},
360 {0x1210, 0x0000},
361 {0x1212, 0x0000},
362 {0x1300, 0x0701},
363 {0x1302, 0x12f9},
364 {0x1304, 0x3405},
365 {0x1305, 0x0844},
366 {0x1306, 0x5611},
367 {0x1308, 0x555e},
368 {0x130a, 0xa605},
369 {0x130c, 0x2000},
370 {0x130e, 0x0000},
371 {0x130f, 0x0001},
372 {0x1310, 0xaa48},
373 {0x1312, 0x0285},
374 {0x1314, 0xaaaa},
375 {0x1316, 0xaaa0},
376 {0x1318, 0x2aaa},
377 {0x131a, 0xaa07},
378 {0x1322, 0x0029},
379 {0x1323, 0x4a52},
380 {0x1324, 0x002c},
381 {0x1325, 0x0b02},
382 {0x1326, 0x002d},
383 {0x1327, 0x6b5a},
384 {0x1328, 0x002e},
385 {0x1329, 0xcbb2},
386 {0x132a, 0x0030},
387 {0x132b, 0x2c0b},
388 {0x1330, 0x0031},
389 {0x1331, 0x8c63},
390 {0x1332, 0x0032},
391 {0x1333, 0xecbb},
392 {0x1334, 0x0034},
393 {0x1335, 0x4d13},
394 {0x1336, 0x0037},
395 {0x1337, 0x0dc3},
396 {0x1338, 0x003d},
397 {0x1339, 0xef7b},
398 {0x133a, 0x0044},
399 {0x133b, 0xd134},
400 {0x133c, 0x0047},
401 {0x133d, 0x91e4},
402 {0x133e, 0x004d},
403 {0x133f, 0xc370},
404 {0x1340, 0x0053},
405 {0x1341, 0xf4fd},
406 {0x1342, 0x0060},
407 {0x1343, 0x5816},
408 {0x1344, 0x006c},
409 {0x1345, 0xbb2e},
410 {0x1346, 0x0072},
411 {0x1347, 0xecbb},
412 {0x1348, 0x0076},
413 {0x1349, 0x5d97},
414 {0x1500, 0x0702},
415 {0x1502, 0x002f},
416 {0x1504, 0x0000},
417 {0x1510, 0x0064},
418 {0x1512, 0x0000},
419 {0x1514, 0xdf47},
420 {0x1516, 0x079c},
421 {0x1518, 0xfbf5},
422 {0x151a, 0x00bc},
423 {0x151c, 0x3b85},
424 {0x151e, 0x02b3},
425 {0x1520, 0x3333},
426 {0x1522, 0x0000},
427 {0x1524, 0x4000},
428 {0x1528, 0x0064},
429 {0x152a, 0x0000},
430 {0x152c, 0x0000},
431 {0x152e, 0x0000},
432 {0x1530, 0x0000},
433 {0x1532, 0x0000},
434 {0x1534, 0x0000},
435 {0x1536, 0x0000},
436 {0x1538, 0x0040},
437 {0x1539, 0x0000},
438 {0x153a, 0x0040},
439 {0x153b, 0x0000},
440 {0x153c, 0x0064},
441 {0x153e, 0x0bf9},
442 {0x1540, 0xb2a9},
443 {0x1544, 0x0200},
444 {0x1546, 0x0000},
445 {0x1548, 0x00ca},
446 {0x1552, 0x03ff},
447 {0x1554, 0x017f},
448 {0x1556, 0x017f},
449 {0x155a, 0x0000},
450 {0x155c, 0x0000},
451 {0x1560, 0x0040},
452 {0x1562, 0x0000},
453 {0x1570, 0x03ff},
454 {0x1571, 0xdcff},
455 {0x1572, 0x1e00},
456 {0x1573, 0x224f},
457 {0x1574, 0x0000},
458 {0x1575, 0x0000},
459 {0x1576, 0x1e00},
460 {0x1577, 0x0000},
461 {0x1578, 0x0000},
462 {0x1579, 0x1128},
463 {0x157a, 0x03ff},
464 {0x157b, 0xdcff},
465 {0x157c, 0x1e00},
466 {0x157d, 0x224f},
467 {0x157e, 0x0000},
468 {0x157f, 0x0000},
469 {0x1580, 0x1e00},
470 {0x1581, 0x0000},
471 {0x1582, 0x0000},
472 {0x1583, 0x1128},
473 {0x1590, 0x03ff},
474 {0x1591, 0xdcff},
475 {0x1592, 0x1e00},
476 {0x1593, 0x224f},
477 {0x1594, 0x0000},
478 {0x1595, 0x0000},
479 {0x1596, 0x1e00},
480 {0x1597, 0x0000},
481 {0x1598, 0x0000},
482 {0x1599, 0x1128},
483 {0x159a, 0x03ff},
484 {0x159b, 0xdcff},
485 {0x159c, 0x1e00},
486 {0x159d, 0x224f},
487 {0x159e, 0x0000},
488 {0x159f, 0x0000},
489 {0x15a0, 0x1e00},
490 {0x15a1, 0x0000},
491 {0x15a2, 0x0000},
492 {0x15a3, 0x1128},
493 {0x15b0, 0x007f},
494 {0x15b1, 0xffff},
495 {0x15b2, 0x007f},
496 {0x15b3, 0xffff},
497 {0x15b4, 0x007f},
498 {0x15b5, 0xffff},
499 {0x15b8, 0x007f},
500 {0x15b9, 0xffff},
501 {0x15bc, 0x0000},
502 {0x15bd, 0x0000},
503 {0x15be, 0xff00},
504 {0x15bf, 0x0000},
505 {0x15c0, 0xff00},
506 {0x15c1, 0x0000},
507 {0x15c3, 0xfc00},
508 {0x15c4, 0xbb80},
509 {0x15d0, 0x0000},
510 {0x15d1, 0x0000},
511 {0x15d2, 0x0000},
512 {0x15d3, 0x0000},
513 {0x15d4, 0x0000},
514 {0x15d5, 0x0000},
515 {0x15d6, 0x0000},
516 {0x15d7, 0x0000},
517 {0x15d8, 0x0200},
518 {0x15d9, 0x0000},
519 {0x15da, 0x0000},
520 {0x15db, 0x0000},
521 {0x15dc, 0x0000},
522 {0x15dd, 0x0000},
523 {0x15de, 0x0000},
524 {0x15df, 0x0000},
525 {0x15e0, 0x0000},
526 {0x15e1, 0x0000},
527 {0x15e2, 0x0200},
528 {0x15e3, 0x0000},
529 {0x15e4, 0x0000},
530 {0x15e5, 0x0000},
531 {0x15e6, 0x0000},
532 {0x15e7, 0x0000},
533 {0x15e8, 0x0000},
534 {0x15e9, 0x0000},
535 {0x15ea, 0x0000},
536 {0x15eb, 0x0000},
537 {0x15ec, 0x0200},
538 {0x15ed, 0x0000},
539 {0x15ee, 0x0000},
540 {0x15ef, 0x0000},
541 {0x15f0, 0x0000},
542 {0x15f1, 0x0000},
543 {0x15f2, 0x0000},
544 {0x15f3, 0x0000},
545 {0x15f4, 0x0000},
546 {0x15f5, 0x0000},
547 {0x15f6, 0x0200},
548 {0x15f7, 0x0200},
549 {0x15f8, 0x8200},
550 {0x15f9, 0x0000},
551 {0x1600, 0x007d},
552 {0x1601, 0xa178},
553 {0x1602, 0x00c2},
554 {0x1603, 0x5383},
555 {0x1604, 0x0000},
556 {0x1605, 0x02c1},
557 {0x1606, 0x007d},
558 {0x1607, 0xa178},
559 {0x1608, 0x00c2},
560 {0x1609, 0x5383},
561 {0x160a, 0x003e},
562 {0x160b, 0xd37d},
563 {0x1611, 0x3210},
564 {0x1612, 0x7418},
565 {0x1613, 0xc0ff},
566 {0x1614, 0x0000},
567 {0x1615, 0x00ff},
568 {0x1616, 0x0000},
569 {0x1617, 0x0000},
570 {0x1621, 0x6210},
571 {0x1622, 0x7418},
572 {0x1623, 0xc0ff},
573 {0x1624, 0x0000},
574 {0x1625, 0x00ff},
575 {0x1626, 0x0000},
576 {0x1627, 0x0000},
577 {0x1631, 0x3a14},
578 {0x1632, 0x7418},
579 {0x1633, 0xc3ff},
580 {0x1634, 0x0000},
581 {0x1635, 0x00ff},
582 {0x1636, 0x0000},
583 {0x1637, 0x0000},
584 {0x1638, 0x0000},
585 {0x163a, 0x0000},
586 {0x163c, 0x0000},
587 {0x163e, 0x0000},
588 {0x1640, 0x0000},
589 {0x1642, 0x0000},
590 {0x1644, 0x0000},
591 {0x1646, 0x0000},
592 {0x1648, 0x0000},
593 {0x1650, 0x0000},
594 {0x1652, 0x0000},
595 {0x1654, 0x0000},
596 {0x1656, 0x0000},
597 {0x1658, 0x0000},
598 {0x1660, 0x0000},
599 {0x1662, 0x0000},
600 {0x1664, 0x0000},
601 {0x1666, 0x0000},
602 {0x1668, 0x0000},
603 {0x1670, 0x0000},
604 {0x1672, 0x0000},
605 {0x1674, 0x0000},
606 {0x1676, 0x0000},
607 {0x1678, 0x0000},
608 {0x1680, 0x0000},
609 {0x1682, 0x0000},
610 {0x1684, 0x0000},
611 {0x1686, 0x0000},
612 {0x1688, 0x0000},
613 {0x1690, 0x0000},
614 {0x1692, 0x0000},
615 {0x1694, 0x0000},
616 {0x1696, 0x0000},
617 {0x1698, 0x0000},
618 {0x1700, 0x0000},
619 {0x1702, 0x0000},
620 {0x1704, 0x0000},
621 {0x1706, 0x0000},
622 {0x1708, 0x0000},
623 {0x1710, 0x0000},
624 {0x1712, 0x0000},
625 {0x1714, 0x0000},
626 {0x1716, 0x0000},
627 {0x1718, 0x0000},
628 {0x1720, 0x0000},
629 {0x1722, 0x0000},
630 {0x1724, 0x0000},
631 {0x1726, 0x0000},
632 {0x1728, 0x0000},
633 {0x1730, 0x0000},
634 {0x1732, 0x0000},
635 {0x1734, 0x0000},
636 {0x1736, 0x0000},
637 {0x1738, 0x0000},
638 {0x173a, 0x0000},
639 {0x173c, 0x0000},
640 {0x173e, 0x0000},
641 {0x17bb, 0x0500},
642 {0x17bd, 0x0004},
643 {0x17bf, 0x0004},
644 {0x17c1, 0x0004},
645 {0x17c2, 0x7fff},
646 {0x17c3, 0x0000},
647 {0x17c5, 0x0000},
648 {0x17c7, 0x0000},
649 {0x17c9, 0x0000},
650 {0x17cb, 0x2010},
651 {0x17cd, 0x0000},
652 {0x17cf, 0x0000},
653 {0x17d1, 0x0000},
654 {0x17d3, 0x0000},
655 {0x17d5, 0x0000},
656 {0x17d7, 0x0000},
657 {0x17d9, 0x0000},
658 {0x17db, 0x0000},
659 {0x17dd, 0x0000},
660 {0x17df, 0x0000},
661 {0x17e1, 0x0000},
662 {0x17e3, 0x0000},
663 {0x17e5, 0x0000},
664 {0x17e7, 0x0000},
665 {0x17e9, 0x0000},
666 {0x17eb, 0x0000},
667 {0x17ed, 0x0000},
668 {0x17ef, 0x0000},
669 {0x17f1, 0x0000},
670 {0x17f3, 0x0000},
671 {0x17f5, 0x0000},
672 {0x17f7, 0x0000},
673 {0x17f9, 0x0000},
674 {0x17fb, 0x0000},
675 {0x17fd, 0x0000},
676 {0x17ff, 0x0000},
677 {0x1801, 0x0000},
678 {0x1803, 0x0000},
679 };
680
rt1011_reg_init(struct snd_soc_component * component)681 static int rt1011_reg_init(struct snd_soc_component *component)
682 {
683 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
684
685 regmap_multi_reg_write(rt1011->regmap,
686 init_list, ARRAY_SIZE(init_list));
687 return 0;
688 }
689
rt1011_volatile_register(struct device * dev,unsigned int reg)690 static bool rt1011_volatile_register(struct device *dev, unsigned int reg)
691 {
692 switch (reg) {
693 case RT1011_RESET:
694 case RT1011_SRC_2:
695 case RT1011_CLK_DET:
696 case RT1011_SIL_DET:
697 case RT1011_VERSION_ID:
698 case RT1011_VENDOR_ID:
699 case RT1011_DEVICE_ID:
700 case RT1011_DUM_RO:
701 case RT1011_DAC_SET_3:
702 case RT1011_PWM_CAL:
703 case RT1011_SPK_VOL_TEST_OUT:
704 case RT1011_VBAT_VOL_DET_1:
705 case RT1011_VBAT_TEST_OUT_1:
706 case RT1011_VBAT_TEST_OUT_2:
707 case RT1011_VBAT_PROTECTION:
708 case RT1011_VBAT_DET:
709 case RT1011_BOOST_CON_1:
710 case RT1011_SHORT_CIRCUIT_DET_1:
711 case RT1011_SPK_TEMP_PROTECT_3:
712 case RT1011_SPK_TEMP_PROTECT_6:
713 case RT1011_SPK_PRO_DC_DET_3:
714 case RT1011_SPK_PRO_DC_DET_7:
715 case RT1011_SPK_PRO_DC_DET_8:
716 case RT1011_SPL_1:
717 case RT1011_SPL_4:
718 case RT1011_EXCUR_PROTECT_1:
719 case RT1011_CROSS_BQ_SET_1:
720 case RT1011_CROSS_BQ_SET_2:
721 case RT1011_BQ_SET_0:
722 case RT1011_BQ_SET_1:
723 case RT1011_BQ_SET_2:
724 case RT1011_TEST_PAD_STATUS:
725 case RT1011_DC_CALIB_CLASSD_1:
726 case RT1011_DC_CALIB_CLASSD_5:
727 case RT1011_DC_CALIB_CLASSD_6:
728 case RT1011_DC_CALIB_CLASSD_7:
729 case RT1011_DC_CALIB_CLASSD_8:
730 case RT1011_SINE_GEN_REG_2:
731 case RT1011_STP_CALIB_RS_TEMP:
732 case RT1011_SPK_RESISTANCE_1:
733 case RT1011_SPK_RESISTANCE_2:
734 case RT1011_SPK_THERMAL:
735 case RT1011_ALC_BK_GAIN_O:
736 case RT1011_ALC_BK_GAIN_O_PRE:
737 case RT1011_SPK_DC_O_23_16:
738 case RT1011_SPK_DC_O_15_0:
739 case RT1011_INIT_RECIPROCAL_SYN_24_16:
740 case RT1011_INIT_RECIPROCAL_SYN_15_0:
741 case RT1011_SPK_EXCURSION_23_16:
742 case RT1011_SPK_EXCURSION_15_0:
743 case RT1011_SEP_MAIN_OUT_23_16:
744 case RT1011_SEP_MAIN_OUT_15_0:
745 case RT1011_ALC_DRC_HB_INTERNAL_5:
746 case RT1011_ALC_DRC_HB_INTERNAL_6:
747 case RT1011_ALC_DRC_HB_INTERNAL_7:
748 case RT1011_ALC_DRC_BB_INTERNAL_5:
749 case RT1011_ALC_DRC_BB_INTERNAL_6:
750 case RT1011_ALC_DRC_BB_INTERNAL_7:
751 case RT1011_ALC_DRC_POS_INTERNAL_5:
752 case RT1011_ALC_DRC_POS_INTERNAL_6:
753 case RT1011_ALC_DRC_POS_INTERNAL_7:
754 case RT1011_ALC_DRC_POS_INTERNAL_8:
755 case RT1011_ALC_DRC_POS_INTERNAL_9:
756 case RT1011_ALC_DRC_POS_INTERNAL_10:
757 case RT1011_ALC_DRC_POS_INTERNAL_11:
758 case RT1011_IRQ_1:
759 case RT1011_EFUSE_CONTROL_1:
760 case RT1011_EFUSE_CONTROL_2:
761 case RT1011_EFUSE_MATCH_DONE ... RT1011_EFUSE_READ_R0_3_15_0:
762 return true;
763
764 default:
765 return false;
766 }
767 }
768
rt1011_readable_register(struct device * dev,unsigned int reg)769 static bool rt1011_readable_register(struct device *dev, unsigned int reg)
770 {
771 switch (reg) {
772 case RT1011_RESET:
773 case RT1011_CLK_1:
774 case RT1011_CLK_2:
775 case RT1011_CLK_3:
776 case RT1011_CLK_4:
777 case RT1011_PLL_1:
778 case RT1011_PLL_2:
779 case RT1011_SRC_1:
780 case RT1011_SRC_2:
781 case RT1011_SRC_3:
782 case RT1011_CLK_DET:
783 case RT1011_SIL_DET:
784 case RT1011_PRIV_INDEX:
785 case RT1011_PRIV_DATA:
786 case RT1011_CUSTOMER_ID:
787 case RT1011_FM_VER:
788 case RT1011_VERSION_ID:
789 case RT1011_VENDOR_ID:
790 case RT1011_DEVICE_ID:
791 case RT1011_DUM_RW_0:
792 case RT1011_DUM_YUN:
793 case RT1011_DUM_RW_1:
794 case RT1011_DUM_RO:
795 case RT1011_MAN_I2C_DEV:
796 case RT1011_DAC_SET_1:
797 case RT1011_DAC_SET_2:
798 case RT1011_DAC_SET_3:
799 case RT1011_ADC_SET:
800 case RT1011_ADC_SET_1:
801 case RT1011_ADC_SET_2:
802 case RT1011_ADC_SET_3:
803 case RT1011_ADC_SET_4:
804 case RT1011_ADC_SET_5:
805 case RT1011_TDM_TOTAL_SET:
806 case RT1011_TDM1_SET_TCON:
807 case RT1011_TDM1_SET_1:
808 case RT1011_TDM1_SET_2:
809 case RT1011_TDM1_SET_3:
810 case RT1011_TDM1_SET_4:
811 case RT1011_TDM1_SET_5:
812 case RT1011_TDM2_SET_1:
813 case RT1011_TDM2_SET_2:
814 case RT1011_TDM2_SET_3:
815 case RT1011_TDM2_SET_4:
816 case RT1011_TDM2_SET_5:
817 case RT1011_PWM_CAL:
818 case RT1011_MIXER_1:
819 case RT1011_MIXER_2:
820 case RT1011_ADRC_LIMIT:
821 case RT1011_A_PRO:
822 case RT1011_A_TIMING_1:
823 case RT1011_A_TIMING_2:
824 case RT1011_A_TEMP_SEN:
825 case RT1011_SPK_VOL_DET_1:
826 case RT1011_SPK_VOL_DET_2:
827 case RT1011_SPK_VOL_TEST_OUT:
828 case RT1011_VBAT_VOL_DET_1:
829 case RT1011_VBAT_VOL_DET_2:
830 case RT1011_VBAT_TEST_OUT_1:
831 case RT1011_VBAT_TEST_OUT_2:
832 case RT1011_VBAT_PROTECTION:
833 case RT1011_VBAT_DET:
834 case RT1011_POWER_1:
835 case RT1011_POWER_2:
836 case RT1011_POWER_3:
837 case RT1011_POWER_4:
838 case RT1011_POWER_5:
839 case RT1011_POWER_6:
840 case RT1011_POWER_7:
841 case RT1011_POWER_8:
842 case RT1011_POWER_9:
843 case RT1011_CLASS_D_POS:
844 case RT1011_BOOST_CON_1:
845 case RT1011_BOOST_CON_2:
846 case RT1011_ANALOG_CTRL:
847 case RT1011_POWER_SEQ:
848 case RT1011_SHORT_CIRCUIT_DET_1:
849 case RT1011_SHORT_CIRCUIT_DET_2:
850 case RT1011_SPK_TEMP_PROTECT_0:
851 case RT1011_SPK_TEMP_PROTECT_1:
852 case RT1011_SPK_TEMP_PROTECT_2:
853 case RT1011_SPK_TEMP_PROTECT_3:
854 case RT1011_SPK_TEMP_PROTECT_4:
855 case RT1011_SPK_TEMP_PROTECT_5:
856 case RT1011_SPK_TEMP_PROTECT_6:
857 case RT1011_SPK_TEMP_PROTECT_7:
858 case RT1011_SPK_TEMP_PROTECT_8:
859 case RT1011_SPK_TEMP_PROTECT_9:
860 case RT1011_SPK_PRO_DC_DET_1:
861 case RT1011_SPK_PRO_DC_DET_2:
862 case RT1011_SPK_PRO_DC_DET_3:
863 case RT1011_SPK_PRO_DC_DET_4:
864 case RT1011_SPK_PRO_DC_DET_5:
865 case RT1011_SPK_PRO_DC_DET_6:
866 case RT1011_SPK_PRO_DC_DET_7:
867 case RT1011_SPK_PRO_DC_DET_8:
868 case RT1011_SPL_1:
869 case RT1011_SPL_2:
870 case RT1011_SPL_3:
871 case RT1011_SPL_4:
872 case RT1011_THER_FOLD_BACK_1:
873 case RT1011_THER_FOLD_BACK_2:
874 case RT1011_EXCUR_PROTECT_1:
875 case RT1011_EXCUR_PROTECT_2:
876 case RT1011_EXCUR_PROTECT_3:
877 case RT1011_EXCUR_PROTECT_4:
878 case RT1011_BAT_GAIN_1:
879 case RT1011_BAT_GAIN_2:
880 case RT1011_BAT_GAIN_3:
881 case RT1011_BAT_GAIN_4:
882 case RT1011_BAT_GAIN_5:
883 case RT1011_BAT_GAIN_6:
884 case RT1011_BAT_GAIN_7:
885 case RT1011_BAT_GAIN_8:
886 case RT1011_BAT_GAIN_9:
887 case RT1011_BAT_GAIN_10:
888 case RT1011_BAT_GAIN_11:
889 case RT1011_BAT_RT_THMAX_1:
890 case RT1011_BAT_RT_THMAX_2:
891 case RT1011_BAT_RT_THMAX_3:
892 case RT1011_BAT_RT_THMAX_4:
893 case RT1011_BAT_RT_THMAX_5:
894 case RT1011_BAT_RT_THMAX_6:
895 case RT1011_BAT_RT_THMAX_7:
896 case RT1011_BAT_RT_THMAX_8:
897 case RT1011_BAT_RT_THMAX_9:
898 case RT1011_BAT_RT_THMAX_10:
899 case RT1011_BAT_RT_THMAX_11:
900 case RT1011_BAT_RT_THMAX_12:
901 case RT1011_SPREAD_SPECTURM:
902 case RT1011_PRO_GAIN_MODE:
903 case RT1011_RT_DRC_CROSS:
904 case RT1011_RT_DRC_HB_1:
905 case RT1011_RT_DRC_HB_2:
906 case RT1011_RT_DRC_HB_3:
907 case RT1011_RT_DRC_HB_4:
908 case RT1011_RT_DRC_HB_5:
909 case RT1011_RT_DRC_HB_6:
910 case RT1011_RT_DRC_HB_7:
911 case RT1011_RT_DRC_HB_8:
912 case RT1011_RT_DRC_BB_1:
913 case RT1011_RT_DRC_BB_2:
914 case RT1011_RT_DRC_BB_3:
915 case RT1011_RT_DRC_BB_4:
916 case RT1011_RT_DRC_BB_5:
917 case RT1011_RT_DRC_BB_6:
918 case RT1011_RT_DRC_BB_7:
919 case RT1011_RT_DRC_BB_8:
920 case RT1011_RT_DRC_POS_1:
921 case RT1011_RT_DRC_POS_2:
922 case RT1011_RT_DRC_POS_3:
923 case RT1011_RT_DRC_POS_4:
924 case RT1011_RT_DRC_POS_5:
925 case RT1011_RT_DRC_POS_6:
926 case RT1011_RT_DRC_POS_7:
927 case RT1011_RT_DRC_POS_8:
928 case RT1011_CROSS_BQ_SET_1:
929 case RT1011_CROSS_BQ_SET_2:
930 case RT1011_BQ_SET_0:
931 case RT1011_BQ_SET_1:
932 case RT1011_BQ_SET_2:
933 case RT1011_BQ_PRE_GAIN_28_16:
934 case RT1011_BQ_PRE_GAIN_15_0:
935 case RT1011_BQ_POST_GAIN_28_16:
936 case RT1011_BQ_POST_GAIN_15_0:
937 case RT1011_BQ_H0_28_16 ... RT1011_BQ_A2_15_0:
938 case RT1011_BQ_1_H0_28_16 ... RT1011_BQ_1_A2_15_0:
939 case RT1011_BQ_2_H0_28_16 ... RT1011_BQ_2_A2_15_0:
940 case RT1011_BQ_3_H0_28_16 ... RT1011_BQ_3_A2_15_0:
941 case RT1011_BQ_4_H0_28_16 ... RT1011_BQ_4_A2_15_0:
942 case RT1011_BQ_5_H0_28_16 ... RT1011_BQ_5_A2_15_0:
943 case RT1011_BQ_6_H0_28_16 ... RT1011_BQ_6_A2_15_0:
944 case RT1011_BQ_7_H0_28_16 ... RT1011_BQ_7_A2_15_0:
945 case RT1011_BQ_8_H0_28_16 ... RT1011_BQ_8_A2_15_0:
946 case RT1011_BQ_9_H0_28_16 ... RT1011_BQ_9_A2_15_0:
947 case RT1011_BQ_10_H0_28_16 ... RT1011_BQ_10_A2_15_0:
948 case RT1011_TEST_PAD_STATUS ... RT1011_PLL_INTERNAL_SET:
949 case RT1011_TEST_OUT_1 ... RT1011_TEST_OUT_3:
950 case RT1011_DC_CALIB_CLASSD_1 ... RT1011_DC_CALIB_CLASSD_10:
951 case RT1011_CLASSD_INTERNAL_SET_1 ... RT1011_VREF_LV_1:
952 case RT1011_SMART_BOOST_TIMING_1 ... RT1011_SMART_BOOST_TIMING_36:
953 case RT1011_SINE_GEN_REG_1 ... RT1011_SINE_GEN_REG_3:
954 case RT1011_STP_INITIAL_RS_TEMP ... RT1011_SPK_THERMAL:
955 case RT1011_STP_OTP_TH ... RT1011_INIT_RECIPROCAL_SYN_15_0:
956 case RT1011_STP_BQ_1_A1_L_28_16 ... RT1011_STP_BQ_1_H0_R_15_0:
957 case RT1011_STP_BQ_2_A1_L_28_16 ... RT1011_SEP_RE_REG_15_0:
958 case RT1011_DRC_CF_PARAMS_1 ... RT1011_DRC_CF_PARAMS_12:
959 case RT1011_ALC_DRC_HB_INTERNAL_1 ... RT1011_ALC_DRC_HB_INTERNAL_7:
960 case RT1011_ALC_DRC_BB_INTERNAL_1 ... RT1011_ALC_DRC_BB_INTERNAL_7:
961 case RT1011_ALC_DRC_POS_INTERNAL_1 ... RT1011_ALC_DRC_POS_INTERNAL_8:
962 case RT1011_ALC_DRC_POS_INTERNAL_9 ... RT1011_BQ_1_PARAMS_CHECK_5:
963 case RT1011_BQ_2_PARAMS_CHECK_1 ... RT1011_BQ_2_PARAMS_CHECK_5:
964 case RT1011_BQ_3_PARAMS_CHECK_1 ... RT1011_BQ_3_PARAMS_CHECK_5:
965 case RT1011_BQ_4_PARAMS_CHECK_1 ... RT1011_BQ_4_PARAMS_CHECK_5:
966 case RT1011_BQ_5_PARAMS_CHECK_1 ... RT1011_BQ_5_PARAMS_CHECK_5:
967 case RT1011_BQ_6_PARAMS_CHECK_1 ... RT1011_BQ_6_PARAMS_CHECK_5:
968 case RT1011_BQ_7_PARAMS_CHECK_1 ... RT1011_BQ_7_PARAMS_CHECK_5:
969 case RT1011_BQ_8_PARAMS_CHECK_1 ... RT1011_BQ_8_PARAMS_CHECK_5:
970 case RT1011_BQ_9_PARAMS_CHECK_1 ... RT1011_BQ_9_PARAMS_CHECK_5:
971 case RT1011_BQ_10_PARAMS_CHECK_1 ... RT1011_BQ_10_PARAMS_CHECK_5:
972 case RT1011_IRQ_1 ... RT1011_PART_NUMBER_EFUSE:
973 case RT1011_EFUSE_CONTROL_1 ... RT1011_EFUSE_READ_R0_3_15_0:
974 return true;
975 default:
976 return false;
977 }
978 }
979
980 static const char * const rt1011_din_source_select[] = {
981 "Left",
982 "Right",
983 "Left + Right average",
984 };
985
986 static SOC_ENUM_SINGLE_DECL(rt1011_din_source_enum, RT1011_CROSS_BQ_SET_1, 5,
987 rt1011_din_source_select);
988
989 static const char * const rt1011_tdm_data_out_select[] = {
990 "TDM_O_LR", "BQ1", "DVOL", "BQ10", "ALC", "DMIX", "ADC_SRC_LR",
991 "ADC_O_LR", "ADC_MONO", "RSPK_BPF_LR", "DMIX_ADD", "ENVELOPE_FS",
992 "SEP_O_GAIN", "ALC_BK_GAIN", "STP_V_C", "DMIX_ABST"
993 };
994
995 static const char * const rt1011_tdm_l_ch_data_select[] = {
996 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
997 };
998 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_l_dac1_enum, RT1011_TDM1_SET_4, 12,
999 rt1011_tdm_l_ch_data_select);
1000 static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_l_dac1_enum, RT1011_TDM2_SET_4, 12,
1001 rt1011_tdm_l_ch_data_select);
1002
1003 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_dat_enum,
1004 RT1011_ADCDAT_OUT_SOURCE, 0, rt1011_tdm_data_out_select);
1005 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_loc_enum, RT1011_TDM1_SET_2, 0,
1006 rt1011_tdm_l_ch_data_select);
1007
1008 static const char * const rt1011_adc_data_mode_select[] = {
1009 "Stereo", "Mono"
1010 };
1011 static SOC_ENUM_SINGLE_DECL(rt1011_adc_dout_mode_enum, RT1011_TDM1_SET_1, 12,
1012 rt1011_adc_data_mode_select);
1013
1014 static const char * const rt1011_tdm_adc_data_len_control[] = {
1015 "1CH", "2CH", "3CH", "4CH", "5CH", "6CH", "7CH", "8CH"
1016 };
1017 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_dout_len_enum, RT1011_TDM1_SET_2, 13,
1018 rt1011_tdm_adc_data_len_control);
1019 static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_dout_len_enum, RT1011_TDM2_SET_2, 13,
1020 rt1011_tdm_adc_data_len_control);
1021
1022 static const char * const rt1011_tdm_adc_swap_select[] = {
1023 "L/R", "R/L", "L/L", "R/R"
1024 };
1025
1026 static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc1_1_enum, RT1011_TDM1_SET_3, 6,
1027 rt1011_tdm_adc_swap_select);
1028 static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc2_1_enum, RT1011_TDM1_SET_3, 4,
1029 rt1011_tdm_adc_swap_select);
1030
rt1011_reset(struct regmap * regmap)1031 static void rt1011_reset(struct regmap *regmap)
1032 {
1033 regmap_write(regmap, RT1011_RESET, 0);
1034 }
1035
rt1011_recv_spk_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1036 static int rt1011_recv_spk_mode_get(struct snd_kcontrol *kcontrol,
1037 struct snd_ctl_elem_value *ucontrol)
1038 {
1039 struct snd_soc_component *component =
1040 snd_soc_kcontrol_component(kcontrol);
1041 struct rt1011_priv *rt1011 =
1042 snd_soc_component_get_drvdata(component);
1043
1044 ucontrol->value.integer.value[0] = rt1011->recv_spk_mode;
1045
1046 return 0;
1047 }
1048
rt1011_recv_spk_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1049 static int rt1011_recv_spk_mode_put(struct snd_kcontrol *kcontrol,
1050 struct snd_ctl_elem_value *ucontrol)
1051 {
1052 struct snd_soc_component *component =
1053 snd_soc_kcontrol_component(kcontrol);
1054 struct rt1011_priv *rt1011 =
1055 snd_soc_component_get_drvdata(component);
1056
1057 if (ucontrol->value.integer.value[0] == rt1011->recv_spk_mode)
1058 return 0;
1059
1060 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1061 rt1011->recv_spk_mode = ucontrol->value.integer.value[0];
1062
1063 if (rt1011->recv_spk_mode) {
1064
1065 /* 1: recevier mode on */
1066 snd_soc_component_update_bits(component,
1067 RT1011_CLASSD_INTERNAL_SET_3,
1068 RT1011_REG_GAIN_CLASSD_RI_SPK_MASK,
1069 RT1011_REG_GAIN_CLASSD_RI_410K);
1070 snd_soc_component_update_bits(component,
1071 RT1011_CLASSD_INTERNAL_SET_1,
1072 RT1011_RECV_MODE_SPK_MASK,
1073 RT1011_RECV_MODE);
1074 } else {
1075 /* 0: speaker mode on */
1076 snd_soc_component_update_bits(component,
1077 RT1011_CLASSD_INTERNAL_SET_3,
1078 RT1011_REG_GAIN_CLASSD_RI_SPK_MASK,
1079 RT1011_REG_GAIN_CLASSD_RI_72P5K);
1080 snd_soc_component_update_bits(component,
1081 RT1011_CLASSD_INTERNAL_SET_1,
1082 RT1011_RECV_MODE_SPK_MASK,
1083 RT1011_SPK_MODE);
1084 }
1085 }
1086
1087 return 0;
1088 }
1089
rt1011_validate_bq_drc_coeff(unsigned short reg)1090 static bool rt1011_validate_bq_drc_coeff(unsigned short reg)
1091 {
1092 if ((reg == RT1011_DAC_SET_1) ||
1093 (reg >= RT1011_ADC_SET && reg <= RT1011_ADC_SET_1) ||
1094 (reg == RT1011_ADC_SET_4) || (reg == RT1011_ADC_SET_5) ||
1095 (reg == RT1011_MIXER_1) ||
1096 (reg == RT1011_A_TIMING_1) ||
1097 (reg >= RT1011_POWER_7 && reg <= RT1011_POWER_8) ||
1098 (reg == RT1011_CLASS_D_POS) || (reg == RT1011_ANALOG_CTRL) ||
1099 (reg >= RT1011_SPK_TEMP_PROTECT_0 && reg <= RT1011_SPK_TEMP_PROTECT_6) ||
1100 (reg >= RT1011_SPK_PRO_DC_DET_5 && reg <= RT1011_BAT_GAIN_1) ||
1101 (reg >= RT1011_RT_DRC_CROSS && reg <= RT1011_RT_DRC_POS_8) ||
1102 (reg >= RT1011_CROSS_BQ_SET_1 && reg <= RT1011_BQ_10_A2_15_0) ||
1103 (reg >= RT1011_SMART_BOOST_TIMING_1 && reg <= RT1011_SMART_BOOST_TIMING_36) ||
1104 (reg == RT1011_SINE_GEN_REG_1) ||
1105 (reg >= RT1011_STP_ALPHA_RECIPROCAL_MSB && reg <= RT1011_BQ_6_PARAMS_CHECK_5) ||
1106 (reg >= RT1011_BQ_7_PARAMS_CHECK_1 && reg <= RT1011_BQ_10_PARAMS_CHECK_5))
1107 return true;
1108
1109 return false;
1110 }
1111
rt1011_bq_drc_coeff_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1112 static int rt1011_bq_drc_coeff_get(struct snd_kcontrol *kcontrol,
1113 struct snd_ctl_elem_value *ucontrol)
1114 {
1115 struct snd_soc_component *component =
1116 snd_soc_kcontrol_component(kcontrol);
1117 struct rt1011_priv *rt1011 =
1118 snd_soc_component_get_drvdata(component);
1119 struct rt1011_bq_drc_params *bq_drc_info;
1120 struct rt1011_bq_drc_params *params =
1121 (struct rt1011_bq_drc_params *)ucontrol->value.integer.value;
1122 unsigned int i, mode_idx = 0;
1123
1124 if (strstr(ucontrol->id.name, "AdvanceMode Initial Set"))
1125 mode_idx = RT1011_ADVMODE_INITIAL_SET;
1126 else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff"))
1127 mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF;
1128 else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff"))
1129 mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF;
1130 else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff"))
1131 mode_idx = RT1011_ADVMODE_BQ_UI_COEFF;
1132 else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff"))
1133 mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF;
1134 else
1135 return -EINVAL;
1136
1137 pr_info("%s, id.name=%s, mode_idx=%d\n", __func__,
1138 ucontrol->id.name, mode_idx);
1139 bq_drc_info = rt1011->bq_drc_params[mode_idx];
1140
1141 for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1142 params[i].reg = bq_drc_info[i].reg;
1143 params[i].val = bq_drc_info[i].val;
1144 }
1145
1146 return 0;
1147 }
1148
rt1011_bq_drc_coeff_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1149 static int rt1011_bq_drc_coeff_put(struct snd_kcontrol *kcontrol,
1150 struct snd_ctl_elem_value *ucontrol)
1151 {
1152 struct snd_soc_component *component =
1153 snd_soc_kcontrol_component(kcontrol);
1154 struct rt1011_priv *rt1011 =
1155 snd_soc_component_get_drvdata(component);
1156 struct rt1011_bq_drc_params *bq_drc_info;
1157 struct rt1011_bq_drc_params *params =
1158 (struct rt1011_bq_drc_params *)ucontrol->value.integer.value;
1159 unsigned int i, mode_idx = 0;
1160
1161 if (strstr(ucontrol->id.name, "AdvanceMode Initial Set"))
1162 mode_idx = RT1011_ADVMODE_INITIAL_SET;
1163 else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff"))
1164 mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF;
1165 else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff"))
1166 mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF;
1167 else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff"))
1168 mode_idx = RT1011_ADVMODE_BQ_UI_COEFF;
1169 else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff"))
1170 mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF;
1171 else
1172 return -EINVAL;
1173
1174 bq_drc_info = rt1011->bq_drc_params[mode_idx];
1175 memset(bq_drc_info, 0,
1176 sizeof(struct rt1011_bq_drc_params) * RT1011_BQ_DRC_NUM);
1177
1178 pr_info("%s, id.name=%s, mode_idx=%d\n", __func__,
1179 ucontrol->id.name, mode_idx);
1180 for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1181 bq_drc_info[i].reg = params[i].reg;
1182 bq_drc_info[i].val = params[i].val;
1183 }
1184
1185 for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1186 if (bq_drc_info[i].reg == 0)
1187 break;
1188 else if (rt1011_validate_bq_drc_coeff(bq_drc_info[i].reg)) {
1189 snd_soc_component_write(component, bq_drc_info[i].reg,
1190 bq_drc_info[i].val);
1191 }
1192 }
1193
1194 return 0;
1195 }
1196
rt1011_bq_drc_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1197 static int rt1011_bq_drc_info(struct snd_kcontrol *kcontrol,
1198 struct snd_ctl_elem_info *uinfo)
1199 {
1200 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1201 uinfo->count = 128;
1202 uinfo->value.integer.max = 0x17ffffff;
1203
1204 return 0;
1205 }
1206
1207 #define RT1011_BQ_DRC(xname) \
1208 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1209 .info = rt1011_bq_drc_info, \
1210 .get = rt1011_bq_drc_coeff_get, \
1211 .put = rt1011_bq_drc_coeff_put \
1212 }
1213
rt1011_r0_cali_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1214 static int rt1011_r0_cali_get(struct snd_kcontrol *kcontrol,
1215 struct snd_ctl_elem_value *ucontrol)
1216 {
1217 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1218 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1219
1220 ucontrol->value.integer.value[0] = rt1011->cali_done;
1221
1222 return 0;
1223 }
1224
rt1011_r0_cali_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1225 static int rt1011_r0_cali_put(struct snd_kcontrol *kcontrol,
1226 struct snd_ctl_elem_value *ucontrol)
1227 {
1228 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1229 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1230
1231 rt1011->cali_done = 0;
1232 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF &&
1233 ucontrol->value.integer.value[0])
1234 rt1011_calibrate(rt1011, 1);
1235
1236 return 0;
1237 }
1238
rt1011_r0_load(struct rt1011_priv * rt1011)1239 static int rt1011_r0_load(struct rt1011_priv *rt1011)
1240 {
1241 if (!rt1011->r0_reg)
1242 return -EINVAL;
1243
1244 /* write R0 to register */
1245 regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_24_16,
1246 ((rt1011->r0_reg>>16) & 0x1ff));
1247 regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_15_0,
1248 (rt1011->r0_reg & 0xffff));
1249 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4080);
1250
1251 return 0;
1252 }
1253
rt1011_r0_load_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1254 static int rt1011_r0_load_mode_get(struct snd_kcontrol *kcontrol,
1255 struct snd_ctl_elem_value *ucontrol)
1256 {
1257 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1258 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1259
1260 ucontrol->value.integer.value[0] = rt1011->r0_reg;
1261
1262 return 0;
1263 }
1264
rt1011_r0_load_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1265 static int rt1011_r0_load_mode_put(struct snd_kcontrol *kcontrol,
1266 struct snd_ctl_elem_value *ucontrol)
1267 {
1268 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1269 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1270 struct device *dev;
1271 unsigned int r0_integer, r0_factor, format;
1272
1273 if (ucontrol->value.integer.value[0] == rt1011->r0_reg)
1274 return 0;
1275
1276 if (ucontrol->value.integer.value[0] == 0)
1277 return -EINVAL;
1278
1279 dev = regmap_get_device(rt1011->regmap);
1280 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1281 rt1011->r0_reg = ucontrol->value.integer.value[0];
1282
1283 format = 2147483648U; /* 2^24 * 128 */
1284 r0_integer = format / rt1011->r0_reg / 128;
1285 r0_factor = ((format / rt1011->r0_reg * 100) / 128)
1286 - (r0_integer * 100);
1287 dev_info(dev, "New r0 resistance about %d.%02d ohm, reg=0x%X\n",
1288 r0_integer, r0_factor, rt1011->r0_reg);
1289
1290 if (rt1011->r0_reg)
1291 rt1011_r0_load(rt1011);
1292 }
1293
1294 return 0;
1295 }
1296
rt1011_r0_load_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1297 static int rt1011_r0_load_info(struct snd_kcontrol *kcontrol,
1298 struct snd_ctl_elem_info *uinfo)
1299 {
1300 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1301 uinfo->count = 1;
1302 uinfo->value.integer.max = 0x1ffffff;
1303
1304 return 0;
1305 }
1306
1307 #define RT1011_R0_LOAD(xname) \
1308 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1309 .info = rt1011_r0_load_info, \
1310 .get = rt1011_r0_load_mode_get, \
1311 .put = rt1011_r0_load_mode_put \
1312 }
1313
1314 static const struct snd_kcontrol_new rt1011_snd_controls[] = {
1315 /* I2S Data In Selection */
1316 SOC_ENUM("DIN Source", rt1011_din_source_enum),
1317
1318 /* TDM Data In Selection */
1319 SOC_ENUM("TDM1 DIN Source", rt1011_tdm1_l_dac1_enum),
1320 SOC_ENUM("TDM2 DIN Source", rt1011_tdm2_l_dac1_enum),
1321
1322 /* TDM1 Data Out Selection */
1323 SOC_ENUM("TDM1 DOUT Source", rt1011_tdm1_adc1_dat_enum),
1324 SOC_ENUM("TDM1 DOUT Location", rt1011_tdm1_adc1_loc_enum),
1325 SOC_ENUM("TDM1 ADC1DAT Swap Select", rt1011_tdm_adc1_1_enum),
1326 SOC_ENUM("TDM1 ADC2DAT Swap Select", rt1011_tdm_adc2_1_enum),
1327
1328 /* Data Out Mode */
1329 SOC_ENUM("I2S ADC DOUT Mode", rt1011_adc_dout_mode_enum),
1330 SOC_ENUM("TDM1 DOUT Length", rt1011_tdm1_dout_len_enum),
1331 SOC_ENUM("TDM2 DOUT Length", rt1011_tdm2_dout_len_enum),
1332
1333 /* Speaker/Receiver Mode */
1334 SOC_SINGLE_EXT("RECV SPK Mode", SND_SOC_NOPM, 0, 1, 0,
1335 rt1011_recv_spk_mode_get, rt1011_recv_spk_mode_put),
1336
1337 /* BiQuad/DRC/SmartBoost Settings */
1338 RT1011_BQ_DRC("AdvanceMode Initial Set"),
1339 RT1011_BQ_DRC("AdvanceMode SEP BQ Coeff"),
1340 RT1011_BQ_DRC("AdvanceMode EQ BQ Coeff"),
1341 RT1011_BQ_DRC("AdvanceMode BQ UI Coeff"),
1342 RT1011_BQ_DRC("AdvanceMode SmartBoost Coeff"),
1343
1344 /* R0 */
1345 SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0,
1346 rt1011_r0_cali_get, rt1011_r0_cali_put),
1347 RT1011_R0_LOAD("R0 Load Mode"),
1348
1349 /* R0 temperature */
1350 SOC_SINGLE("R0 Temperature", RT1011_STP_INITIAL_RESISTANCE_TEMP,
1351 2, 255, 0),
1352 };
1353
rt1011_is_sys_clk_from_pll(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)1354 static int rt1011_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
1355 struct snd_soc_dapm_widget *sink)
1356 {
1357 struct snd_soc_component *component =
1358 snd_soc_dapm_to_component(source->dapm);
1359 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1360
1361 if (rt1011->sysclk_src == RT1011_FS_SYS_PRE_S_PLL1)
1362 return 1;
1363 else
1364 return 0;
1365 }
1366
rt1011_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1367 static int rt1011_dac_event(struct snd_soc_dapm_widget *w,
1368 struct snd_kcontrol *kcontrol, int event)
1369 {
1370 struct snd_soc_component *component =
1371 snd_soc_dapm_to_component(w->dapm);
1372
1373 switch (event) {
1374 case SND_SOC_DAPM_POST_PMU:
1375 snd_soc_component_update_bits(component,
1376 RT1011_SPK_TEMP_PROTECT_0,
1377 RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK,
1378 RT1011_STP_EN | RT1011_STP_RS_CLB_EN);
1379 snd_soc_component_update_bits(component, RT1011_POWER_9,
1380 RT1011_POW_MNL_SDB_MASK, RT1011_POW_MNL_SDB);
1381 msleep(50);
1382 snd_soc_component_update_bits(component,
1383 RT1011_CLASSD_INTERNAL_SET_1,
1384 RT1011_DRIVER_READY_SPK, RT1011_DRIVER_READY_SPK);
1385 break;
1386 case SND_SOC_DAPM_PRE_PMD:
1387 snd_soc_component_update_bits(component, RT1011_POWER_9,
1388 RT1011_POW_MNL_SDB_MASK, 0);
1389 snd_soc_component_update_bits(component,
1390 RT1011_SPK_TEMP_PROTECT_0,
1391 RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK, 0);
1392 msleep(200);
1393 snd_soc_component_update_bits(component,
1394 RT1011_CLASSD_INTERNAL_SET_1,
1395 RT1011_DRIVER_READY_SPK, 0);
1396 break;
1397
1398 default:
1399 return 0;
1400 }
1401
1402 return 0;
1403 }
1404
1405
1406 static const struct snd_soc_dapm_widget rt1011_dapm_widgets[] = {
1407 SND_SOC_DAPM_SUPPLY("LDO2", RT1011_POWER_1,
1408 RT1011_POW_LDO2_BIT, 0, NULL, 0),
1409 SND_SOC_DAPM_SUPPLY("ISENSE SPK", RT1011_POWER_1,
1410 RT1011_POW_ISENSE_SPK_BIT, 0, NULL, 0),
1411 SND_SOC_DAPM_SUPPLY("VSENSE SPK", RT1011_POWER_1,
1412 RT1011_POW_VSENSE_SPK_BIT, 0, NULL, 0),
1413
1414 SND_SOC_DAPM_SUPPLY("PLL", RT1011_POWER_2,
1415 RT1011_PLLEN_BIT, 0, NULL, 0),
1416 SND_SOC_DAPM_SUPPLY("BG", RT1011_POWER_2,
1417 RT1011_POW_BG_BIT, 0, NULL, 0),
1418 SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1011_POWER_2,
1419 RT1011_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
1420
1421 SND_SOC_DAPM_SUPPLY("DET VBAT", RT1011_POWER_3,
1422 RT1011_POW_DET_VBAT_BIT, 0, NULL, 0),
1423 SND_SOC_DAPM_SUPPLY("MBIAS", RT1011_POWER_3,
1424 RT1011_POW_MBIAS_LV_BIT, 0, NULL, 0),
1425 SND_SOC_DAPM_SUPPLY("ADC I", RT1011_POWER_3,
1426 RT1011_POW_ADC_I_BIT, 0, NULL, 0),
1427 SND_SOC_DAPM_SUPPLY("ADC V", RT1011_POWER_3,
1428 RT1011_POW_ADC_V_BIT, 0, NULL, 0),
1429 SND_SOC_DAPM_SUPPLY("ADC T", RT1011_POWER_3,
1430 RT1011_POW_ADC_T_BIT, 0, NULL, 0),
1431 SND_SOC_DAPM_SUPPLY("DITHER ADC T", RT1011_POWER_3,
1432 RT1011_POWD_ADC_T_BIT, 0, NULL, 0),
1433 SND_SOC_DAPM_SUPPLY("MIX I", RT1011_POWER_3,
1434 RT1011_POW_MIX_I_BIT, 0, NULL, 0),
1435 SND_SOC_DAPM_SUPPLY("MIX V", RT1011_POWER_3,
1436 RT1011_POW_MIX_V_BIT, 0, NULL, 0),
1437 SND_SOC_DAPM_SUPPLY("SUM I", RT1011_POWER_3,
1438 RT1011_POW_SUM_I_BIT, 0, NULL, 0),
1439 SND_SOC_DAPM_SUPPLY("SUM V", RT1011_POWER_3,
1440 RT1011_POW_SUM_V_BIT, 0, NULL, 0),
1441 SND_SOC_DAPM_SUPPLY("MIX T", RT1011_POWER_3,
1442 RT1011_POW_MIX_T_BIT, 0, NULL, 0),
1443 SND_SOC_DAPM_SUPPLY("VREF", RT1011_POWER_3,
1444 RT1011_POW_VREF_LV_BIT, 0, NULL, 0),
1445
1446 SND_SOC_DAPM_SUPPLY("BOOST SWR", RT1011_POWER_4,
1447 RT1011_POW_EN_SWR_BIT, 0, NULL, 0),
1448 SND_SOC_DAPM_SUPPLY("BGOK SWR", RT1011_POWER_4,
1449 RT1011_POW_EN_PASS_BGOK_SWR_BIT, 0, NULL, 0),
1450 SND_SOC_DAPM_SUPPLY("VPOK SWR", RT1011_POWER_4,
1451 RT1011_POW_EN_PASS_VPOK_SWR_BIT, 0, NULL, 0),
1452
1453 SND_SOC_DAPM_SUPPLY("TEMP REG", RT1011_A_TEMP_SEN,
1454 RT1011_POW_TEMP_REG_BIT, 0, NULL, 0),
1455
1456 /* Audio Interface */
1457 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1458 /* Digital Interface */
1459 SND_SOC_DAPM_SUPPLY("DAC Power", RT1011_POWER_1,
1460 RT1011_POW_DAC_BIT, 0, NULL, 0),
1461 SND_SOC_DAPM_SUPPLY("CLK12M", RT1011_POWER_1,
1462 RT1011_POW_CLK12M_BIT, 0, NULL, 0),
1463 SND_SOC_DAPM_DAC_E("DAC", NULL, RT1011_DAC_SET_3,
1464 RT1011_DA_MUTE_EN_SFT, 1, rt1011_dac_event,
1465 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1466
1467 /* Output Lines */
1468 SND_SOC_DAPM_OUTPUT("SPO"),
1469 };
1470
1471 static const struct snd_soc_dapm_route rt1011_dapm_routes[] = {
1472
1473 { "DAC", NULL, "AIF1RX" },
1474 { "DAC", NULL, "DAC Power" },
1475 { "DAC", NULL, "LDO2" },
1476 { "DAC", NULL, "ISENSE SPK" },
1477 { "DAC", NULL, "VSENSE SPK" },
1478 { "DAC", NULL, "CLK12M" },
1479
1480 { "DAC", NULL, "PLL", rt1011_is_sys_clk_from_pll },
1481 { "DAC", NULL, "BG" },
1482 { "DAC", NULL, "BG MBIAS" },
1483
1484 { "DAC", NULL, "BOOST SWR" },
1485 { "DAC", NULL, "BGOK SWR" },
1486 { "DAC", NULL, "VPOK SWR" },
1487
1488 { "DAC", NULL, "DET VBAT" },
1489 { "DAC", NULL, "MBIAS" },
1490 { "DAC", NULL, "VREF" },
1491 { "DAC", NULL, "ADC I" },
1492 { "DAC", NULL, "ADC V" },
1493 { "DAC", NULL, "ADC T" },
1494 { "DAC", NULL, "DITHER ADC T" },
1495 { "DAC", NULL, "MIX I" },
1496 { "DAC", NULL, "MIX V" },
1497 { "DAC", NULL, "SUM I" },
1498 { "DAC", NULL, "SUM V" },
1499 { "DAC", NULL, "MIX T" },
1500
1501 { "DAC", NULL, "TEMP REG" },
1502
1503 { "SPO", NULL, "DAC" },
1504 };
1505
rt1011_get_clk_info(int sclk,int rate)1506 static int rt1011_get_clk_info(int sclk, int rate)
1507 {
1508 int i;
1509 static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1510
1511 if (sclk <= 0 || rate <= 0)
1512 return -EINVAL;
1513
1514 rate = rate << 8;
1515 for (i = 0; i < ARRAY_SIZE(pd); i++)
1516 if (sclk == rate * pd[i])
1517 return i;
1518
1519 return -EINVAL;
1520 }
1521
rt1011_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1522 static int rt1011_hw_params(struct snd_pcm_substream *substream,
1523 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1524 {
1525 struct snd_soc_component *component = dai->component;
1526 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1527 unsigned int val_len = 0, ch_len = 0, val_clk, mask_clk;
1528 int pre_div, bclk_ms, frame_size;
1529
1530 rt1011->lrck = params_rate(params);
1531 pre_div = rt1011_get_clk_info(rt1011->sysclk, rt1011->lrck);
1532 if (pre_div < 0) {
1533 dev_warn(component->dev, "Force using PLL ");
1534 snd_soc_dai_set_pll(dai, 0, RT1011_PLL1_S_BCLK,
1535 rt1011->lrck * 64, rt1011->lrck * 256);
1536 snd_soc_dai_set_sysclk(dai, RT1011_FS_SYS_PRE_S_PLL1,
1537 rt1011->lrck * 256, SND_SOC_CLOCK_IN);
1538 pre_div = 0;
1539 }
1540 frame_size = snd_soc_params_to_frame_size(params);
1541 if (frame_size < 0) {
1542 dev_err(component->dev, "Unsupported frame size: %d\n",
1543 frame_size);
1544 return -EINVAL;
1545 }
1546
1547 bclk_ms = frame_size > 32;
1548 rt1011->bclk = rt1011->lrck * (32 << bclk_ms);
1549
1550 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1551 bclk_ms, pre_div, dai->id);
1552
1553 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
1554 rt1011->lrck, pre_div, dai->id);
1555
1556 switch (params_width(params)) {
1557 case 16:
1558 val_len |= RT1011_I2S_TX_DL_16B;
1559 val_len |= RT1011_I2S_RX_DL_16B;
1560 ch_len |= RT1011_I2S_CH_TX_LEN_16B;
1561 ch_len |= RT1011_I2S_CH_RX_LEN_16B;
1562 break;
1563 case 20:
1564 val_len |= RT1011_I2S_TX_DL_20B;
1565 val_len |= RT1011_I2S_RX_DL_20B;
1566 ch_len |= RT1011_I2S_CH_TX_LEN_20B;
1567 ch_len |= RT1011_I2S_CH_RX_LEN_20B;
1568 break;
1569 case 24:
1570 val_len |= RT1011_I2S_TX_DL_24B;
1571 val_len |= RT1011_I2S_RX_DL_24B;
1572 ch_len |= RT1011_I2S_CH_TX_LEN_24B;
1573 ch_len |= RT1011_I2S_CH_RX_LEN_24B;
1574 break;
1575 case 32:
1576 val_len |= RT1011_I2S_TX_DL_32B;
1577 val_len |= RT1011_I2S_RX_DL_32B;
1578 ch_len |= RT1011_I2S_CH_TX_LEN_32B;
1579 ch_len |= RT1011_I2S_CH_RX_LEN_32B;
1580 break;
1581 case 8:
1582 val_len |= RT1011_I2S_TX_DL_8B;
1583 val_len |= RT1011_I2S_RX_DL_8B;
1584 ch_len |= RT1011_I2S_CH_TX_LEN_8B;
1585 ch_len |= RT1011_I2S_CH_RX_LEN_8B;
1586 break;
1587 default:
1588 return -EINVAL;
1589 }
1590
1591 switch (dai->id) {
1592 case RT1011_AIF1:
1593 mask_clk = RT1011_FS_SYS_DIV_MASK;
1594 val_clk = pre_div << RT1011_FS_SYS_DIV_SFT;
1595 snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
1596 RT1011_I2S_TX_DL_MASK | RT1011_I2S_RX_DL_MASK,
1597 val_len);
1598 snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
1599 RT1011_I2S_CH_TX_LEN_MASK |
1600 RT1011_I2S_CH_RX_LEN_MASK,
1601 ch_len);
1602 break;
1603 default:
1604 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
1605 return -EINVAL;
1606 }
1607
1608 snd_soc_component_update_bits(component,
1609 RT1011_CLK_2, mask_clk, val_clk);
1610
1611 return 0;
1612 }
1613
rt1011_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)1614 static int rt1011_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1615 {
1616 struct snd_soc_component *component = dai->component;
1617 struct snd_soc_dapm_context *dapm =
1618 snd_soc_component_get_dapm(component);
1619 unsigned int reg_val = 0, reg_bclk_inv = 0;
1620 int ret = 0;
1621
1622 snd_soc_dapm_mutex_lock(dapm);
1623 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1624 case SND_SOC_DAIFMT_CBS_CFS:
1625 reg_val |= RT1011_I2S_TDM_MS_S;
1626 break;
1627 default:
1628 ret = -EINVAL;
1629 goto _set_fmt_err_;
1630 }
1631
1632 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1633 case SND_SOC_DAIFMT_NB_NF:
1634 break;
1635 case SND_SOC_DAIFMT_IB_NF:
1636 reg_bclk_inv |= RT1011_TDM_INV_BCLK;
1637 break;
1638 default:
1639 ret = -EINVAL;
1640 goto _set_fmt_err_;
1641 }
1642
1643 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1644 case SND_SOC_DAIFMT_I2S:
1645 break;
1646 case SND_SOC_DAIFMT_LEFT_J:
1647 reg_val |= RT1011_I2S_TDM_DF_LEFT;
1648 break;
1649 case SND_SOC_DAIFMT_DSP_A:
1650 reg_val |= RT1011_I2S_TDM_DF_PCM_A;
1651 break;
1652 case SND_SOC_DAIFMT_DSP_B:
1653 reg_val |= RT1011_I2S_TDM_DF_PCM_B;
1654 break;
1655 default:
1656 ret = -EINVAL;
1657 goto _set_fmt_err_;
1658 }
1659
1660 switch (dai->id) {
1661 case RT1011_AIF1:
1662 snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
1663 RT1011_I2S_TDM_MS_MASK | RT1011_I2S_TDM_DF_MASK,
1664 reg_val);
1665 snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
1666 RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv);
1667 snd_soc_component_update_bits(component, RT1011_TDM2_SET_1,
1668 RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv);
1669 break;
1670 default:
1671 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
1672 ret = -EINVAL;
1673 }
1674
1675 _set_fmt_err_:
1676 snd_soc_dapm_mutex_unlock(dapm);
1677 return ret;
1678 }
1679
rt1011_set_component_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)1680 static int rt1011_set_component_sysclk(struct snd_soc_component *component,
1681 int clk_id, int source, unsigned int freq, int dir)
1682 {
1683 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1684 unsigned int reg_val = 0;
1685
1686 if (freq == rt1011->sysclk && clk_id == rt1011->sysclk_src)
1687 return 0;
1688
1689 /* disable MCLK detect in default */
1690 snd_soc_component_update_bits(component, RT1011_CLK_DET,
1691 RT1011_EN_MCLK_DET_MASK, 0);
1692
1693 switch (clk_id) {
1694 case RT1011_FS_SYS_PRE_S_MCLK:
1695 reg_val |= RT1011_FS_SYS_PRE_MCLK;
1696 snd_soc_component_update_bits(component, RT1011_CLK_DET,
1697 RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET);
1698 break;
1699 case RT1011_FS_SYS_PRE_S_BCLK:
1700 reg_val |= RT1011_FS_SYS_PRE_BCLK;
1701 break;
1702 case RT1011_FS_SYS_PRE_S_PLL1:
1703 reg_val |= RT1011_FS_SYS_PRE_PLL1;
1704 break;
1705 case RT1011_FS_SYS_PRE_S_RCCLK:
1706 reg_val |= RT1011_FS_SYS_PRE_RCCLK;
1707 break;
1708 default:
1709 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
1710 return -EINVAL;
1711 }
1712 snd_soc_component_update_bits(component, RT1011_CLK_2,
1713 RT1011_FS_SYS_PRE_MASK, reg_val);
1714 rt1011->sysclk = freq;
1715 rt1011->sysclk_src = clk_id;
1716
1717 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
1718 freq, clk_id);
1719
1720 return 0;
1721 }
1722
rt1011_set_component_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)1723 static int rt1011_set_component_pll(struct snd_soc_component *component,
1724 int pll_id, int source, unsigned int freq_in,
1725 unsigned int freq_out)
1726 {
1727 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1728 struct rl6231_pll_code pll_code;
1729 int ret;
1730
1731 if (source == rt1011->pll_src && freq_in == rt1011->pll_in &&
1732 freq_out == rt1011->pll_out)
1733 return 0;
1734
1735 if (!freq_in || !freq_out) {
1736 dev_dbg(component->dev, "PLL disabled\n");
1737
1738 rt1011->pll_in = 0;
1739 rt1011->pll_out = 0;
1740 snd_soc_component_update_bits(component, RT1011_CLK_2,
1741 RT1011_FS_SYS_PRE_MASK, RT1011_FS_SYS_PRE_BCLK);
1742 return 0;
1743 }
1744
1745 switch (source) {
1746 case RT1011_PLL2_S_MCLK:
1747 snd_soc_component_update_bits(component, RT1011_CLK_2,
1748 RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_MCLK);
1749 snd_soc_component_update_bits(component, RT1011_CLK_2,
1750 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2);
1751 snd_soc_component_update_bits(component, RT1011_CLK_DET,
1752 RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET);
1753 break;
1754 case RT1011_PLL1_S_BCLK:
1755 snd_soc_component_update_bits(component, RT1011_CLK_2,
1756 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_BCLK);
1757 break;
1758 case RT1011_PLL2_S_RCCLK:
1759 snd_soc_component_update_bits(component, RT1011_CLK_2,
1760 RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_RCCLK);
1761 snd_soc_component_update_bits(component, RT1011_CLK_2,
1762 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2);
1763 break;
1764 default:
1765 dev_err(component->dev, "Unknown PLL Source %d\n", source);
1766 return -EINVAL;
1767 }
1768
1769 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1770 if (ret < 0) {
1771 dev_err(component->dev, "Unsupported input clock %d\n",
1772 freq_in);
1773 return ret;
1774 }
1775
1776 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
1777 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1778 pll_code.n_code, pll_code.k_code);
1779
1780 snd_soc_component_write(component, RT1011_PLL_1,
1781 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1011_PLL1_QM_SFT) |
1782 (pll_code.m_bp << RT1011_PLL1_BPM_SFT) |
1783 pll_code.n_code);
1784 snd_soc_component_write(component, RT1011_PLL_2,
1785 pll_code.k_code);
1786
1787 rt1011->pll_in = freq_in;
1788 rt1011->pll_out = freq_out;
1789 rt1011->pll_src = source;
1790
1791 return 0;
1792 }
1793
rt1011_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1794 static int rt1011_set_tdm_slot(struct snd_soc_dai *dai,
1795 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1796 {
1797 struct snd_soc_component *component = dai->component;
1798 struct snd_soc_dapm_context *dapm =
1799 snd_soc_component_get_dapm(component);
1800 unsigned int val = 0, tdm_en = 0, rx_slotnum, tx_slotnum;
1801 int ret = 0, first_bit, last_bit;
1802
1803 snd_soc_dapm_mutex_lock(dapm);
1804 if (rx_mask || tx_mask)
1805 tdm_en = RT1011_TDM_I2S_DOCK_EN_1;
1806
1807 switch (slots) {
1808 case 4:
1809 val |= RT1011_I2S_TX_4CH;
1810 val |= RT1011_I2S_RX_4CH;
1811 break;
1812 case 6:
1813 val |= RT1011_I2S_TX_6CH;
1814 val |= RT1011_I2S_RX_6CH;
1815 break;
1816 case 8:
1817 val |= RT1011_I2S_TX_8CH;
1818 val |= RT1011_I2S_RX_8CH;
1819 break;
1820 case 2:
1821 break;
1822 default:
1823 ret = -EINVAL;
1824 goto _set_tdm_err_;
1825 }
1826
1827 switch (slot_width) {
1828 case 20:
1829 val |= RT1011_I2S_CH_TX_LEN_20B;
1830 val |= RT1011_I2S_CH_RX_LEN_20B;
1831 break;
1832 case 24:
1833 val |= RT1011_I2S_CH_TX_LEN_24B;
1834 val |= RT1011_I2S_CH_RX_LEN_24B;
1835 break;
1836 case 32:
1837 val |= RT1011_I2S_CH_TX_LEN_32B;
1838 val |= RT1011_I2S_CH_RX_LEN_32B;
1839 break;
1840 case 16:
1841 break;
1842 default:
1843 ret = -EINVAL;
1844 goto _set_tdm_err_;
1845 }
1846
1847 /* Rx slot configuration */
1848 rx_slotnum = hweight_long(rx_mask);
1849 if (rx_slotnum > 1 || !rx_slotnum) {
1850 ret = -EINVAL;
1851 dev_err(component->dev, "too many rx slots or zero slot\n");
1852 goto _set_tdm_err_;
1853 }
1854
1855 first_bit = __ffs(rx_mask);
1856 switch (first_bit) {
1857 case 0:
1858 case 2:
1859 case 4:
1860 case 6:
1861 snd_soc_component_update_bits(component,
1862 RT1011_CROSS_BQ_SET_1, RT1011_MONO_LR_SEL_MASK,
1863 RT1011_MONO_L_CHANNEL);
1864 snd_soc_component_update_bits(component,
1865 RT1011_TDM1_SET_4,
1866 RT1011_TDM_I2S_TX_L_DAC1_1_MASK |
1867 RT1011_TDM_I2S_TX_R_DAC1_1_MASK,
1868 (first_bit << RT1011_TDM_I2S_TX_L_DAC1_1_SFT) |
1869 ((first_bit+1) << RT1011_TDM_I2S_TX_R_DAC1_1_SFT));
1870 break;
1871 case 1:
1872 case 3:
1873 case 5:
1874 case 7:
1875 snd_soc_component_update_bits(component,
1876 RT1011_CROSS_BQ_SET_1, RT1011_MONO_LR_SEL_MASK,
1877 RT1011_MONO_R_CHANNEL);
1878 snd_soc_component_update_bits(component,
1879 RT1011_TDM1_SET_4,
1880 RT1011_TDM_I2S_TX_L_DAC1_1_MASK |
1881 RT1011_TDM_I2S_TX_R_DAC1_1_MASK,
1882 ((first_bit-1) << RT1011_TDM_I2S_TX_L_DAC1_1_SFT) |
1883 (first_bit << RT1011_TDM_I2S_TX_R_DAC1_1_SFT));
1884 break;
1885 default:
1886 ret = -EINVAL;
1887 goto _set_tdm_err_;
1888 }
1889
1890 /* Tx slot configuration */
1891 tx_slotnum = hweight_long(tx_mask);
1892 if (tx_slotnum > 2 || !tx_slotnum) {
1893 ret = -EINVAL;
1894 dev_err(component->dev, "too many tx slots or zero slot\n");
1895 goto _set_tdm_err_;
1896 }
1897
1898 first_bit = __ffs(tx_mask);
1899 last_bit = __fls(tx_mask);
1900 if (last_bit - first_bit > 1) {
1901 ret = -EINVAL;
1902 dev_err(component->dev, "tx slot location error\n");
1903 goto _set_tdm_err_;
1904 }
1905
1906 if (tx_slotnum == 1) {
1907 snd_soc_component_update_bits(component, RT1011_TDM1_SET_2,
1908 RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK |
1909 RT1011_TDM_ADCDAT1_DATA_LOCATION, first_bit);
1910 switch (first_bit) {
1911 case 1:
1912 snd_soc_component_update_bits(component,
1913 RT1011_TDM1_SET_3,
1914 RT1011_TDM_I2S_RX_ADC1_1_MASK,
1915 RT1011_TDM_I2S_RX_ADC1_1_LL);
1916 break;
1917 case 3:
1918 snd_soc_component_update_bits(component,
1919 RT1011_TDM1_SET_3,
1920 RT1011_TDM_I2S_RX_ADC2_1_MASK,
1921 RT1011_TDM_I2S_RX_ADC2_1_LL);
1922 break;
1923 case 5:
1924 snd_soc_component_update_bits(component,
1925 RT1011_TDM1_SET_3,
1926 RT1011_TDM_I2S_RX_ADC3_1_MASK,
1927 RT1011_TDM_I2S_RX_ADC3_1_LL);
1928 break;
1929 case 7:
1930 snd_soc_component_update_bits(component,
1931 RT1011_TDM1_SET_3,
1932 RT1011_TDM_I2S_RX_ADC4_1_MASK,
1933 RT1011_TDM_I2S_RX_ADC4_1_LL);
1934 break;
1935 case 0:
1936 snd_soc_component_update_bits(component,
1937 RT1011_TDM1_SET_3,
1938 RT1011_TDM_I2S_RX_ADC1_1_MASK, 0);
1939 break;
1940 case 2:
1941 snd_soc_component_update_bits(component,
1942 RT1011_TDM1_SET_3,
1943 RT1011_TDM_I2S_RX_ADC2_1_MASK, 0);
1944 break;
1945 case 4:
1946 snd_soc_component_update_bits(component,
1947 RT1011_TDM1_SET_3,
1948 RT1011_TDM_I2S_RX_ADC3_1_MASK, 0);
1949 break;
1950 case 6:
1951 snd_soc_component_update_bits(component,
1952 RT1011_TDM1_SET_3,
1953 RT1011_TDM_I2S_RX_ADC4_1_MASK, 0);
1954 break;
1955 default:
1956 ret = -EINVAL;
1957 dev_dbg(component->dev,
1958 "tx slot location error\n");
1959 goto _set_tdm_err_;
1960 }
1961 } else if (tx_slotnum == 2) {
1962 switch (first_bit) {
1963 case 0:
1964 case 2:
1965 case 4:
1966 case 6:
1967 snd_soc_component_update_bits(component,
1968 RT1011_TDM1_SET_2,
1969 RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK |
1970 RT1011_TDM_ADCDAT1_DATA_LOCATION,
1971 RT1011_TDM_I2S_DOCK_ADCDAT_2CH | first_bit);
1972 break;
1973 default:
1974 ret = -EINVAL;
1975 dev_dbg(component->dev,
1976 "tx slot location should be paired and start from slot0/2/4/6\n");
1977 goto _set_tdm_err_;
1978 }
1979 }
1980
1981 snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
1982 RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK |
1983 RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val);
1984 snd_soc_component_update_bits(component, RT1011_TDM2_SET_1,
1985 RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK |
1986 RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val);
1987 snd_soc_component_update_bits(component, RT1011_TDM1_SET_2,
1988 RT1011_TDM_I2S_DOCK_EN_1_MASK, tdm_en);
1989 snd_soc_component_update_bits(component, RT1011_TDM2_SET_2,
1990 RT1011_TDM_I2S_DOCK_EN_2_MASK, tdm_en);
1991
1992 snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
1993 RT1011_ADCDAT1_PIN_CONFIG | RT1011_ADCDAT2_PIN_CONFIG,
1994 RT1011_ADCDAT1_OUTPUT | RT1011_ADCDAT2_OUTPUT);
1995
1996 _set_tdm_err_:
1997 snd_soc_dapm_mutex_unlock(dapm);
1998 return ret;
1999 }
2000
rt1011_probe(struct snd_soc_component * component)2001 static int rt1011_probe(struct snd_soc_component *component)
2002 {
2003 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2004 int i;
2005
2006 rt1011->component = component;
2007
2008 schedule_work(&rt1011->cali_work);
2009
2010 rt1011->bq_drc_params = devm_kcalloc(component->dev,
2011 RT1011_ADVMODE_NUM, sizeof(struct rt1011_bq_drc_params *),
2012 GFP_KERNEL);
2013 if (!rt1011->bq_drc_params)
2014 return -ENOMEM;
2015
2016 for (i = 0; i < RT1011_ADVMODE_NUM; i++) {
2017 rt1011->bq_drc_params[i] = devm_kcalloc(component->dev,
2018 RT1011_BQ_DRC_NUM, sizeof(struct rt1011_bq_drc_params),
2019 GFP_KERNEL);
2020 if (!rt1011->bq_drc_params[i])
2021 return -ENOMEM;
2022 }
2023
2024 return 0;
2025 }
2026
rt1011_remove(struct snd_soc_component * component)2027 static void rt1011_remove(struct snd_soc_component *component)
2028 {
2029 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2030
2031 cancel_work_sync(&rt1011->cali_work);
2032 rt1011_reset(rt1011->regmap);
2033 }
2034
2035 #ifdef CONFIG_PM
rt1011_suspend(struct snd_soc_component * component)2036 static int rt1011_suspend(struct snd_soc_component *component)
2037 {
2038 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2039
2040 regcache_cache_only(rt1011->regmap, true);
2041 regcache_mark_dirty(rt1011->regmap);
2042
2043 return 0;
2044 }
2045
rt1011_resume(struct snd_soc_component * component)2046 static int rt1011_resume(struct snd_soc_component *component)
2047 {
2048 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2049
2050 regcache_cache_only(rt1011->regmap, false);
2051 regcache_sync(rt1011->regmap);
2052
2053 return 0;
2054 }
2055 #else
2056 #define rt1011_suspend NULL
2057 #define rt1011_resume NULL
2058 #endif
2059
rt1011_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)2060 static int rt1011_set_bias_level(struct snd_soc_component *component,
2061 enum snd_soc_bias_level level)
2062 {
2063 switch (level) {
2064 case SND_SOC_BIAS_OFF:
2065 snd_soc_component_write(component,
2066 RT1011_SYSTEM_RESET_1, 0x0000);
2067 snd_soc_component_write(component,
2068 RT1011_SYSTEM_RESET_2, 0x0000);
2069 snd_soc_component_write(component,
2070 RT1011_SYSTEM_RESET_3, 0x0001);
2071 snd_soc_component_write(component,
2072 RT1011_SYSTEM_RESET_1, 0x003f);
2073 snd_soc_component_write(component,
2074 RT1011_SYSTEM_RESET_2, 0x7fd7);
2075 snd_soc_component_write(component,
2076 RT1011_SYSTEM_RESET_3, 0x770f);
2077 break;
2078 default:
2079 break;
2080 }
2081
2082 return 0;
2083 }
2084
2085 #define RT1011_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2086 #define RT1011_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
2087 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
2088 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2089
2090 static const struct snd_soc_dai_ops rt1011_aif_dai_ops = {
2091 .hw_params = rt1011_hw_params,
2092 .set_fmt = rt1011_set_dai_fmt,
2093 .set_tdm_slot = rt1011_set_tdm_slot,
2094 };
2095
2096 static struct snd_soc_dai_driver rt1011_dai[] = {
2097 {
2098 .name = "rt1011-aif",
2099 .playback = {
2100 .stream_name = "AIF1 Playback",
2101 .channels_min = 1,
2102 .channels_max = 2,
2103 .rates = RT1011_STEREO_RATES,
2104 .formats = RT1011_FORMATS,
2105 },
2106 .ops = &rt1011_aif_dai_ops,
2107 },
2108 };
2109
2110 static const struct snd_soc_component_driver soc_component_dev_rt1011 = {
2111 .probe = rt1011_probe,
2112 .remove = rt1011_remove,
2113 .suspend = rt1011_suspend,
2114 .resume = rt1011_resume,
2115 .set_bias_level = rt1011_set_bias_level,
2116 .controls = rt1011_snd_controls,
2117 .num_controls = ARRAY_SIZE(rt1011_snd_controls),
2118 .dapm_widgets = rt1011_dapm_widgets,
2119 .num_dapm_widgets = ARRAY_SIZE(rt1011_dapm_widgets),
2120 .dapm_routes = rt1011_dapm_routes,
2121 .num_dapm_routes = ARRAY_SIZE(rt1011_dapm_routes),
2122 .set_sysclk = rt1011_set_component_sysclk,
2123 .set_pll = rt1011_set_component_pll,
2124 .use_pmdown_time = 1,
2125 .endianness = 1,
2126 .non_legacy_dai_naming = 1,
2127 };
2128
2129 static const struct regmap_config rt1011_regmap = {
2130 .reg_bits = 16,
2131 .val_bits = 16,
2132 .max_register = RT1011_MAX_REG + 1,
2133 .volatile_reg = rt1011_volatile_register,
2134 .readable_reg = rt1011_readable_register,
2135 .cache_type = REGCACHE_RBTREE,
2136 .reg_defaults = rt1011_reg,
2137 .num_reg_defaults = ARRAY_SIZE(rt1011_reg),
2138 .use_single_read = true,
2139 .use_single_write = true,
2140 };
2141
2142 #if defined(CONFIG_OF)
2143 static const struct of_device_id rt1011_of_match[] = {
2144 { .compatible = "realtek,rt1011", },
2145 {},
2146 };
2147 MODULE_DEVICE_TABLE(of, rt1011_of_match);
2148 #endif
2149
2150 #ifdef CONFIG_ACPI
2151 static const struct acpi_device_id rt1011_acpi_match[] = {
2152 {"10EC1011", 0,},
2153 {},
2154 };
2155 MODULE_DEVICE_TABLE(acpi, rt1011_acpi_match);
2156 #endif
2157
2158 static const struct i2c_device_id rt1011_i2c_id[] = {
2159 { "rt1011", 0 },
2160 { }
2161 };
2162 MODULE_DEVICE_TABLE(i2c, rt1011_i2c_id);
2163
rt1011_calibrate(struct rt1011_priv * rt1011,unsigned char cali_flag)2164 static int rt1011_calibrate(struct rt1011_priv *rt1011, unsigned char cali_flag)
2165 {
2166 unsigned int value, count = 0, r0[3];
2167 unsigned int chk_cnt = 50; /* DONT change this */
2168 unsigned int dc_offset;
2169 unsigned int r0_integer, r0_factor, format;
2170 struct device *dev = regmap_get_device(rt1011->regmap);
2171 struct snd_soc_dapm_context *dapm =
2172 snd_soc_component_get_dapm(rt1011->component);
2173 int ret = 0;
2174
2175 snd_soc_dapm_mutex_lock(dapm);
2176 regcache_cache_bypass(rt1011->regmap, true);
2177
2178 regmap_write(rt1011->regmap, RT1011_RESET, 0x0000);
2179 regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x740f);
2180 regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x770f);
2181
2182 /* RC clock */
2183 regmap_write(rt1011->regmap, RT1011_CLK_2, 0x9400);
2184 regmap_write(rt1011->regmap, RT1011_PLL_1, 0x0800);
2185 regmap_write(rt1011->regmap, RT1011_PLL_2, 0x0020);
2186 regmap_write(rt1011->regmap, RT1011_CLK_DET, 0x0800);
2187
2188 /* ADC/DAC setting */
2189 regmap_write(rt1011->regmap, RT1011_ADC_SET_5, 0x0a20);
2190 regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xe232);
2191 regmap_write(rt1011->regmap, RT1011_ADC_SET_4, 0xc000);
2192
2193 /* DC detection */
2194 regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_1, 0xb00c);
2195 regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_2, 0xcccc);
2196
2197 /* Power */
2198 regmap_write(rt1011->regmap, RT1011_POWER_1, 0xe0e0);
2199 regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5003);
2200 regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa860);
2201 regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xa032);
2202
2203 /* POW_PLL / POW_BG / POW_BG_MBIAS_LV / POW_V/I */
2204 regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0007);
2205 regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5ff7);
2206 regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f44);
2207 regmap_write(rt1011->regmap, RT1011_A_TIMING_1, 0x4054);
2208 regmap_write(rt1011->regmap, RT1011_BAT_GAIN_1, 0x309c);
2209
2210 /* DC offset from EFUSE */
2211 regmap_write(rt1011->regmap, RT1011_DC_CALIB_CLASSD_3, 0xcb00);
2212 regmap_write(rt1011->regmap, RT1011_BOOST_CON_1, 0xe080);
2213 regmap_write(rt1011->regmap, RT1011_POWER_4, 0x16f2);
2214 regmap_write(rt1011->regmap, RT1011_POWER_6, 0x36ad);
2215
2216 /* mixer */
2217 regmap_write(rt1011->regmap, RT1011_MIXER_1, 0x3f1d);
2218
2219 /* EFUSE read */
2220 regmap_write(rt1011->regmap, RT1011_EFUSE_CONTROL_1, 0x0d0a);
2221 msleep(30);
2222
2223 regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_18_16, &value);
2224 dc_offset = value << 16;
2225 regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_15_0, &value);
2226 dc_offset |= (value & 0xffff);
2227 dev_info(dev, "ADC offset=0x%x\n", dc_offset);
2228 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_20_16, &value);
2229 dc_offset = value << 16;
2230 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_15_0, &value);
2231 dc_offset |= (value & 0xffff);
2232 dev_info(dev, "Gain0 offset=0x%x\n", dc_offset);
2233 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_20_16, &value);
2234 dc_offset = value << 16;
2235 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_15_0, &value);
2236 dc_offset |= (value & 0xffff);
2237 dev_info(dev, "Gain1 offset=0x%x\n", dc_offset);
2238
2239 if (cali_flag) {
2240
2241 regmap_write(rt1011->regmap, RT1011_ADC_SET_1, 0x2925);
2242 /* Class D on */
2243 regmap_write(rt1011->regmap, RT1011_CLASS_D_POS, 0x010e);
2244 regmap_write(rt1011->regmap,
2245 RT1011_CLASSD_INTERNAL_SET_1, 0x1701);
2246
2247 /* STP enable */
2248 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x8000);
2249 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_7, 0xf000);
2250 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4040);
2251 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0xc000);
2252 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x07c2);
2253
2254 r0[0] = r0[1] = r0[2] = count = 0;
2255 while (count < chk_cnt) {
2256 msleep(100);
2257 regmap_read(rt1011->regmap,
2258 RT1011_INIT_RECIPROCAL_SYN_24_16, &value);
2259 r0[count%3] = value << 16;
2260 regmap_read(rt1011->regmap,
2261 RT1011_INIT_RECIPROCAL_SYN_15_0, &value);
2262 r0[count%3] |= value;
2263
2264 if (r0[count%3] == 0)
2265 continue;
2266
2267 count++;
2268
2269 if (r0[0] == r0[1] && r0[1] == r0[2])
2270 break;
2271 }
2272 if (count > chk_cnt) {
2273 dev_err(dev, "Calibrate R0 Failure\n");
2274 ret = -EAGAIN;
2275 } else {
2276 format = 2147483648U; /* 2^24 * 128 */
2277 r0_integer = format / r0[0] / 128;
2278 r0_factor = ((format / r0[0] * 100) / 128)
2279 - (r0_integer * 100);
2280 rt1011->r0_reg = r0[0];
2281 rt1011->cali_done = 1;
2282 dev_info(dev, "r0 resistance about %d.%02d ohm, reg=0x%X\n",
2283 r0_integer, r0_factor, r0[0]);
2284 }
2285 }
2286
2287 /* depop */
2288 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x0000);
2289 msleep(400);
2290 regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa840);
2291 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x0702);
2292 regmap_write(rt1011->regmap, RT1011_MIXER_1, 0xffdd);
2293 regmap_write(rt1011->regmap, RT1011_CLASSD_INTERNAL_SET_1, 0x0701);
2294 regmap_write(rt1011->regmap, RT1011_DAC_SET_3, 0xe004);
2295 regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f40);
2296 regmap_write(rt1011->regmap, RT1011_POWER_1, 0x0000);
2297 regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0000);
2298 regmap_write(rt1011->regmap, RT1011_POWER_3, 0x0002);
2299 regmap_write(rt1011->regmap, RT1011_POWER_4, 0x00f2);
2300
2301 regmap_write(rt1011->regmap, RT1011_RESET, 0x0000);
2302
2303 if (cali_flag) {
2304 if (count <= chk_cnt) {
2305 regmap_write(rt1011->regmap,
2306 RT1011_INIT_RECIPROCAL_REG_24_16,
2307 ((r0[0]>>16) & 0x1ff));
2308 regmap_write(rt1011->regmap,
2309 RT1011_INIT_RECIPROCAL_REG_15_0,
2310 (r0[0] & 0xffff));
2311 regmap_write(rt1011->regmap,
2312 RT1011_SPK_TEMP_PROTECT_4, 0x4080);
2313 }
2314 }
2315
2316 regcache_cache_bypass(rt1011->regmap, false);
2317 regcache_mark_dirty(rt1011->regmap);
2318 regcache_sync(rt1011->regmap);
2319 snd_soc_dapm_mutex_unlock(dapm);
2320
2321 return ret;
2322 }
2323
rt1011_calibration_work(struct work_struct * work)2324 static void rt1011_calibration_work(struct work_struct *work)
2325 {
2326 struct rt1011_priv *rt1011 =
2327 container_of(work, struct rt1011_priv, cali_work);
2328 struct snd_soc_component *component = rt1011->component;
2329 unsigned int r0_integer, r0_factor, format;
2330
2331 if (rt1011->r0_calib)
2332 rt1011_calibrate(rt1011, 0);
2333 else
2334 rt1011_calibrate(rt1011, 1);
2335
2336 /*
2337 * This flag should reset after booting.
2338 * The factory test will do calibration again and use this flag to check
2339 * whether the calibration completed
2340 */
2341 rt1011->cali_done = 0;
2342
2343 /* initial */
2344 rt1011_reg_init(component);
2345
2346 /* Apply temperature and calibration data from device property */
2347 if (rt1011->temperature_calib <= 0xff &&
2348 rt1011->temperature_calib > 0) {
2349 snd_soc_component_update_bits(component,
2350 RT1011_STP_INITIAL_RESISTANCE_TEMP, 0x3ff,
2351 (rt1011->temperature_calib << 2));
2352 }
2353
2354 if (rt1011->r0_calib) {
2355 rt1011->r0_reg = rt1011->r0_calib;
2356
2357 format = 2147483648U; /* 2^24 * 128 */
2358 r0_integer = format / rt1011->r0_reg / 128;
2359 r0_factor = ((format / rt1011->r0_reg * 100) / 128)
2360 - (r0_integer * 100);
2361 dev_info(component->dev, "DP r0 resistance about %d.%02d ohm, reg=0x%X\n",
2362 r0_integer, r0_factor, rt1011->r0_reg);
2363
2364 rt1011_r0_load(rt1011);
2365 }
2366
2367 snd_soc_component_write(component, RT1011_ADC_SET_1, 0x2925);
2368 }
2369
rt1011_parse_dp(struct rt1011_priv * rt1011,struct device * dev)2370 static int rt1011_parse_dp(struct rt1011_priv *rt1011, struct device *dev)
2371 {
2372 device_property_read_u32(dev, "realtek,temperature_calib",
2373 &rt1011->temperature_calib);
2374 device_property_read_u32(dev, "realtek,r0_calib",
2375 &rt1011->r0_calib);
2376
2377 dev_dbg(dev, "%s: r0_calib: 0x%x, temperature_calib: 0x%x",
2378 __func__, rt1011->r0_calib, rt1011->temperature_calib);
2379
2380 return 0;
2381 }
2382
rt1011_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)2383 static int rt1011_i2c_probe(struct i2c_client *i2c,
2384 const struct i2c_device_id *id)
2385 {
2386 struct rt1011_priv *rt1011;
2387 int ret;
2388 unsigned int val;
2389
2390 rt1011 = devm_kzalloc(&i2c->dev, sizeof(struct rt1011_priv),
2391 GFP_KERNEL);
2392 if (!rt1011)
2393 return -ENOMEM;
2394
2395 i2c_set_clientdata(i2c, rt1011);
2396
2397 rt1011_parse_dp(rt1011, &i2c->dev);
2398
2399 rt1011->regmap = devm_regmap_init_i2c(i2c, &rt1011_regmap);
2400 if (IS_ERR(rt1011->regmap)) {
2401 ret = PTR_ERR(rt1011->regmap);
2402 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2403 ret);
2404 return ret;
2405 }
2406
2407 regmap_read(rt1011->regmap, RT1011_DEVICE_ID, &val);
2408 if (val != RT1011_DEVICE_ID_NUM) {
2409 dev_err(&i2c->dev,
2410 "Device with ID register %x is not rt1011\n", val);
2411 return -ENODEV;
2412 }
2413
2414 INIT_WORK(&rt1011->cali_work, rt1011_calibration_work);
2415
2416 return devm_snd_soc_register_component(&i2c->dev,
2417 &soc_component_dev_rt1011,
2418 rt1011_dai, ARRAY_SIZE(rt1011_dai));
2419
2420 }
2421
rt1011_i2c_shutdown(struct i2c_client * client)2422 static void rt1011_i2c_shutdown(struct i2c_client *client)
2423 {
2424 struct rt1011_priv *rt1011 = i2c_get_clientdata(client);
2425
2426 rt1011_reset(rt1011->regmap);
2427 }
2428
2429 static struct i2c_driver rt1011_i2c_driver = {
2430 .driver = {
2431 .name = "rt1011",
2432 .of_match_table = of_match_ptr(rt1011_of_match),
2433 .acpi_match_table = ACPI_PTR(rt1011_acpi_match)
2434 },
2435 .probe = rt1011_i2c_probe,
2436 .shutdown = rt1011_i2c_shutdown,
2437 .id_table = rt1011_i2c_id,
2438 };
2439 module_i2c_driver(rt1011_i2c_driver);
2440
2441 MODULE_DESCRIPTION("ASoC RT1011 amplifier driver");
2442 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
2443 MODULE_LICENSE("GPL");
2444