1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
4 //
5 // Copyright (C) 2013 Freescale Semiconductor, Inc.
6 //
7 // Based on stmp3xxx_spdif_dai.c
8 // Vladimir Barinov <vbarinov@embeddedalley.com>
9 // Copyright 2008 SigmaTel, Inc
10 // Copyright 2008 Embedded Alley Solutions, Inc
11
12 #include <linux/bitrev.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/regmap.h>
19 #include <linux/pm_runtime.h>
20
21 #include <sound/asoundef.h>
22 #include <sound/dmaengine_pcm.h>
23 #include <sound/soc.h>
24
25 #include "fsl_spdif.h"
26 #include "imx-pcm.h"
27
28 #define FSL_SPDIF_TXFIFO_WML 0x8
29 #define FSL_SPDIF_RXFIFO_WML 0x8
30
31 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
32 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
33 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
34 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
35 INT_LOSS_LOCK | INT_DPLL_LOCKED)
36
37 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
38
39 /* Index list for the values that has if (DPLL Locked) condition */
40 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
41 #define SRPC_NODPLL_START1 0x5
42 #define SRPC_NODPLL_START2 0xc
43
44 #define DEFAULT_RXCLK_SRC 1
45
46 /**
47 * struct fsl_spdif_soc_data: soc specific data
48 *
49 * @imx: for imx platform
50 * @shared_root_clock: flag of sharing a clock source with others;
51 * so the driver shouldn't set root clock rate
52 * @raw_capture_mode: if raw capture mode support
53 * @interrupts: interrupt number
54 * @tx_burst: tx maxburst size
55 * @rx_burst: rx maxburst size
56 * @tx_formats: tx supported data format
57 */
58 struct fsl_spdif_soc_data {
59 bool imx;
60 bool shared_root_clock;
61 bool raw_capture_mode;
62 u32 interrupts;
63 u32 tx_burst;
64 u32 rx_burst;
65 u64 tx_formats;
66 };
67
68 /*
69 * SPDIF control structure
70 * Defines channel status, subcode and Q sub
71 */
72 struct spdif_mixer_control {
73 /* spinlock to access control data */
74 spinlock_t ctl_lock;
75
76 /* IEC958 channel tx status bit */
77 unsigned char ch_status[4];
78
79 /* User bits */
80 unsigned char subcode[2 * SPDIF_UBITS_SIZE];
81
82 /* Q subcode part of user bits */
83 unsigned char qsub[2 * SPDIF_QSUB_SIZE];
84
85 /* Buffer offset for U/Q */
86 u32 upos;
87 u32 qpos;
88
89 /* Ready buffer index of the two buffers */
90 u32 ready_buf;
91 };
92
93 /**
94 * struct fsl_spdif_priv - Freescale SPDIF private data
95 * @soc: SPDIF soc data
96 * @fsl_spdif_control: SPDIF control data
97 * @cpu_dai_drv: cpu dai driver
98 * @pdev: platform device pointer
99 * @regmap: regmap handler
100 * @dpll_locked: dpll lock flag
101 * @txrate: the best rates for playback
102 * @txclk_df: STC_TXCLK_DF dividers value for playback
103 * @sysclk_df: STC_SYSCLK_DF dividers value for playback
104 * @txclk_src: STC_TXCLK_SRC values for playback
105 * @rxclk_src: SRPC_CLKSRC_SEL values for capture
106 * @txclk: tx clock sources for playback
107 * @rxclk: rx clock sources for capture
108 * @coreclk: core clock for register access via DMA
109 * @sysclk: system clock for rx clock rate measurement
110 * @spbaclk: SPBA clock (optional, depending on SoC design)
111 * @dma_params_tx: DMA parameters for transmit channel
112 * @dma_params_rx: DMA parameters for receive channel
113 * @regcache_srpc: regcache for SRPC
114 */
115 struct fsl_spdif_priv {
116 const struct fsl_spdif_soc_data *soc;
117 struct spdif_mixer_control fsl_spdif_control;
118 struct snd_soc_dai_driver cpu_dai_drv;
119 struct platform_device *pdev;
120 struct regmap *regmap;
121 bool dpll_locked;
122 u32 txrate[SPDIF_TXRATE_MAX];
123 u8 txclk_df[SPDIF_TXRATE_MAX];
124 u16 sysclk_df[SPDIF_TXRATE_MAX];
125 u8 txclk_src[SPDIF_TXRATE_MAX];
126 u8 rxclk_src;
127 struct clk *txclk[SPDIF_TXRATE_MAX];
128 struct clk *rxclk;
129 struct clk *coreclk;
130 struct clk *sysclk;
131 struct clk *spbaclk;
132 struct snd_dmaengine_dai_dma_data dma_params_tx;
133 struct snd_dmaengine_dai_dma_data dma_params_rx;
134 /* regcache for SRPC */
135 u32 regcache_srpc;
136 };
137
138 static struct fsl_spdif_soc_data fsl_spdif_vf610 = {
139 .imx = false,
140 .shared_root_clock = false,
141 .raw_capture_mode = false,
142 .interrupts = 1,
143 .tx_burst = FSL_SPDIF_TXFIFO_WML,
144 .rx_burst = FSL_SPDIF_RXFIFO_WML,
145 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
146 };
147
148 static struct fsl_spdif_soc_data fsl_spdif_imx35 = {
149 .imx = true,
150 .shared_root_clock = false,
151 .raw_capture_mode = false,
152 .interrupts = 1,
153 .tx_burst = FSL_SPDIF_TXFIFO_WML,
154 .rx_burst = FSL_SPDIF_RXFIFO_WML,
155 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
156 };
157
158 static struct fsl_spdif_soc_data fsl_spdif_imx6sx = {
159 .imx = true,
160 .shared_root_clock = true,
161 .raw_capture_mode = false,
162 .interrupts = 1,
163 .tx_burst = FSL_SPDIF_TXFIFO_WML,
164 .rx_burst = FSL_SPDIF_RXFIFO_WML,
165 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
166
167 };
168
169 static struct fsl_spdif_soc_data fsl_spdif_imx8qm = {
170 .imx = true,
171 .shared_root_clock = true,
172 .raw_capture_mode = false,
173 .interrupts = 2,
174 .tx_burst = 2, /* Applied for EDMA */
175 .rx_burst = 2, /* Applied for EDMA */
176 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */
177 };
178
179 static struct fsl_spdif_soc_data fsl_spdif_imx8mm = {
180 .imx = true,
181 .shared_root_clock = false,
182 .raw_capture_mode = true,
183 .interrupts = 1,
184 .tx_burst = FSL_SPDIF_TXFIFO_WML,
185 .rx_burst = FSL_SPDIF_RXFIFO_WML,
186 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,
187 };
188
189 /* Check if clk is a root clock that does not share clock source with others */
fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv * spdif,int clk)190 static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk)
191 {
192 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock;
193 }
194
195 /* DPLL locked and lock loss interrupt handler */
spdif_irq_dpll_lock(struct fsl_spdif_priv * spdif_priv)196 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
197 {
198 struct regmap *regmap = spdif_priv->regmap;
199 struct platform_device *pdev = spdif_priv->pdev;
200 u32 locked;
201
202 regmap_read(regmap, REG_SPDIF_SRPC, &locked);
203 locked &= SRPC_DPLL_LOCKED;
204
205 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
206 locked ? "locked" : "loss lock");
207
208 spdif_priv->dpll_locked = locked ? true : false;
209 }
210
211 /* Receiver found illegal symbol interrupt handler */
spdif_irq_sym_error(struct fsl_spdif_priv * spdif_priv)212 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
213 {
214 struct regmap *regmap = spdif_priv->regmap;
215 struct platform_device *pdev = spdif_priv->pdev;
216
217 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
218
219 /* Clear illegal symbol if DPLL unlocked since no audio stream */
220 if (!spdif_priv->dpll_locked)
221 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
222 }
223
224 /* U/Q Channel receive register full */
spdif_irq_uqrx_full(struct fsl_spdif_priv * spdif_priv,char name)225 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
226 {
227 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
228 struct regmap *regmap = spdif_priv->regmap;
229 struct platform_device *pdev = spdif_priv->pdev;
230 u32 *pos, size, val, reg;
231
232 switch (name) {
233 case 'U':
234 pos = &ctrl->upos;
235 size = SPDIF_UBITS_SIZE;
236 reg = REG_SPDIF_SRU;
237 break;
238 case 'Q':
239 pos = &ctrl->qpos;
240 size = SPDIF_QSUB_SIZE;
241 reg = REG_SPDIF_SRQ;
242 break;
243 default:
244 dev_err(&pdev->dev, "unsupported channel name\n");
245 return;
246 }
247
248 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
249
250 if (*pos >= size * 2) {
251 *pos = 0;
252 } else if (unlikely((*pos % size) + 3 > size)) {
253 dev_err(&pdev->dev, "User bit receive buffer overflow\n");
254 return;
255 }
256
257 regmap_read(regmap, reg, &val);
258 ctrl->subcode[*pos++] = val >> 16;
259 ctrl->subcode[*pos++] = val >> 8;
260 ctrl->subcode[*pos++] = val;
261 }
262
263 /* U/Q Channel sync found */
spdif_irq_uq_sync(struct fsl_spdif_priv * spdif_priv)264 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
265 {
266 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
267 struct platform_device *pdev = spdif_priv->pdev;
268
269 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
270
271 /* U/Q buffer reset */
272 if (ctrl->qpos == 0)
273 return;
274
275 /* Set ready to this buffer */
276 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
277 }
278
279 /* U/Q Channel framing error */
spdif_irq_uq_err(struct fsl_spdif_priv * spdif_priv)280 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
281 {
282 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
283 struct regmap *regmap = spdif_priv->regmap;
284 struct platform_device *pdev = spdif_priv->pdev;
285 u32 val;
286
287 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
288
289 /* Read U/Q data to clear the irq and do buffer reset */
290 regmap_read(regmap, REG_SPDIF_SRU, &val);
291 regmap_read(regmap, REG_SPDIF_SRQ, &val);
292
293 /* Drop this U/Q buffer */
294 ctrl->ready_buf = 0;
295 ctrl->upos = 0;
296 ctrl->qpos = 0;
297 }
298
299 /* Get spdif interrupt status and clear the interrupt */
spdif_intr_status_clear(struct fsl_spdif_priv * spdif_priv)300 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
301 {
302 struct regmap *regmap = spdif_priv->regmap;
303 u32 val, val2;
304
305 regmap_read(regmap, REG_SPDIF_SIS, &val);
306 regmap_read(regmap, REG_SPDIF_SIE, &val2);
307
308 regmap_write(regmap, REG_SPDIF_SIC, val & val2);
309
310 return val;
311 }
312
spdif_isr(int irq,void * devid)313 static irqreturn_t spdif_isr(int irq, void *devid)
314 {
315 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
316 struct platform_device *pdev = spdif_priv->pdev;
317 u32 sis;
318
319 sis = spdif_intr_status_clear(spdif_priv);
320
321 if (sis & INT_DPLL_LOCKED)
322 spdif_irq_dpll_lock(spdif_priv);
323
324 if (sis & INT_TXFIFO_UNOV)
325 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
326
327 if (sis & INT_TXFIFO_RESYNC)
328 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
329
330 if (sis & INT_CNEW)
331 dev_dbg(&pdev->dev, "isr: cstatus new\n");
332
333 if (sis & INT_VAL_NOGOOD)
334 dev_dbg(&pdev->dev, "isr: validity flag no good\n");
335
336 if (sis & INT_SYM_ERR)
337 spdif_irq_sym_error(spdif_priv);
338
339 if (sis & INT_BIT_ERR)
340 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
341
342 if (sis & INT_URX_FUL)
343 spdif_irq_uqrx_full(spdif_priv, 'U');
344
345 if (sis & INT_URX_OV)
346 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
347
348 if (sis & INT_QRX_FUL)
349 spdif_irq_uqrx_full(spdif_priv, 'Q');
350
351 if (sis & INT_QRX_OV)
352 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
353
354 if (sis & INT_UQ_SYNC)
355 spdif_irq_uq_sync(spdif_priv);
356
357 if (sis & INT_UQ_ERR)
358 spdif_irq_uq_err(spdif_priv);
359
360 if (sis & INT_RXFIFO_UNOV)
361 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
362
363 if (sis & INT_RXFIFO_RESYNC)
364 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
365
366 if (sis & INT_LOSS_LOCK)
367 spdif_irq_dpll_lock(spdif_priv);
368
369 /* FIXME: Write Tx FIFO to clear TxEm */
370 if (sis & INT_TX_EM)
371 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
372
373 /* FIXME: Read Rx FIFO to clear RxFIFOFul */
374 if (sis & INT_RXFIFO_FUL)
375 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
376
377 return IRQ_HANDLED;
378 }
379
spdif_softreset(struct fsl_spdif_priv * spdif_priv)380 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
381 {
382 struct regmap *regmap = spdif_priv->regmap;
383 u32 val, cycle = 1000;
384
385 regcache_cache_bypass(regmap, true);
386
387 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
388
389 /*
390 * RESET bit would be cleared after finishing its reset procedure,
391 * which typically lasts 8 cycles. 1000 cycles will keep it safe.
392 */
393 do {
394 regmap_read(regmap, REG_SPDIF_SCR, &val);
395 } while ((val & SCR_SOFT_RESET) && cycle--);
396
397 regcache_cache_bypass(regmap, false);
398 regcache_mark_dirty(regmap);
399 regcache_sync(regmap);
400
401 if (cycle)
402 return 0;
403 else
404 return -EBUSY;
405 }
406
spdif_set_cstatus(struct spdif_mixer_control * ctrl,u8 mask,u8 cstatus)407 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
408 u8 mask, u8 cstatus)
409 {
410 ctrl->ch_status[3] &= ~mask;
411 ctrl->ch_status[3] |= cstatus & mask;
412 }
413
spdif_write_channel_status(struct fsl_spdif_priv * spdif_priv)414 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
415 {
416 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
417 struct regmap *regmap = spdif_priv->regmap;
418 struct platform_device *pdev = spdif_priv->pdev;
419 u32 ch_status;
420
421 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
422 (bitrev8(ctrl->ch_status[1]) << 8) |
423 bitrev8(ctrl->ch_status[2]);
424 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
425
426 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
427
428 ch_status = bitrev8(ctrl->ch_status[3]) << 16;
429 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
430
431 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
432 }
433
434 /* Set SPDIF PhaseConfig register for rx clock */
spdif_set_rx_clksrc(struct fsl_spdif_priv * spdif_priv,enum spdif_gainsel gainsel,int dpll_locked)435 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
436 enum spdif_gainsel gainsel, int dpll_locked)
437 {
438 struct regmap *regmap = spdif_priv->regmap;
439 u8 clksrc = spdif_priv->rxclk_src;
440
441 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
442 return -EINVAL;
443
444 regmap_update_bits(regmap, REG_SPDIF_SRPC,
445 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
446 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
447
448 return 0;
449 }
450
spdif_set_sample_rate(struct snd_pcm_substream * substream,int sample_rate)451 static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
452 int sample_rate)
453 {
454 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
455 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
456 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
457 struct regmap *regmap = spdif_priv->regmap;
458 struct platform_device *pdev = spdif_priv->pdev;
459 unsigned long csfs = 0;
460 u32 stc, mask, rate;
461 u16 sysclk_df;
462 u8 clk, txclk_df;
463 int ret;
464
465 switch (sample_rate) {
466 case 32000:
467 rate = SPDIF_TXRATE_32000;
468 csfs = IEC958_AES3_CON_FS_32000;
469 break;
470 case 44100:
471 rate = SPDIF_TXRATE_44100;
472 csfs = IEC958_AES3_CON_FS_44100;
473 break;
474 case 48000:
475 rate = SPDIF_TXRATE_48000;
476 csfs = IEC958_AES3_CON_FS_48000;
477 break;
478 case 88200:
479 rate = SPDIF_TXRATE_88200;
480 csfs = IEC958_AES3_CON_FS_88200;
481 break;
482 case 96000:
483 rate = SPDIF_TXRATE_96000;
484 csfs = IEC958_AES3_CON_FS_96000;
485 break;
486 case 176400:
487 rate = SPDIF_TXRATE_176400;
488 csfs = IEC958_AES3_CON_FS_176400;
489 break;
490 case 192000:
491 rate = SPDIF_TXRATE_192000;
492 csfs = IEC958_AES3_CON_FS_192000;
493 break;
494 default:
495 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
496 return -EINVAL;
497 }
498
499 clk = spdif_priv->txclk_src[rate];
500 if (clk >= STC_TXCLK_SRC_MAX) {
501 dev_err(&pdev->dev, "tx clock source is out of range\n");
502 return -EINVAL;
503 }
504
505 txclk_df = spdif_priv->txclk_df[rate];
506 if (txclk_df == 0) {
507 dev_err(&pdev->dev, "the txclk_df can't be zero\n");
508 return -EINVAL;
509 }
510
511 sysclk_df = spdif_priv->sysclk_df[rate];
512
513 if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk))
514 goto clk_set_bypass;
515
516 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */
517 ret = clk_set_rate(spdif_priv->txclk[rate],
518 64 * sample_rate * txclk_df);
519 if (ret) {
520 dev_err(&pdev->dev, "failed to set tx clock rate\n");
521 return ret;
522 }
523
524 clk_set_bypass:
525 dev_dbg(&pdev->dev, "expected clock rate = %d\n",
526 (64 * sample_rate * txclk_df * sysclk_df));
527 dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
528 clk_get_rate(spdif_priv->txclk[rate]));
529
530 /* set fs field in consumer channel status */
531 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
532
533 /* select clock source and divisor */
534 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
535 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
536 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
537 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
538 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
539
540 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
541 spdif_priv->txrate[rate], sample_rate);
542
543 return 0;
544 }
545
fsl_spdif_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)546 static int fsl_spdif_startup(struct snd_pcm_substream *substream,
547 struct snd_soc_dai *cpu_dai)
548 {
549 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
550 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
551 struct platform_device *pdev = spdif_priv->pdev;
552 struct regmap *regmap = spdif_priv->regmap;
553 u32 scr, mask;
554 int ret;
555
556 /* Reset module and interrupts only for first initialization */
557 if (!snd_soc_dai_active(cpu_dai)) {
558 ret = spdif_softreset(spdif_priv);
559 if (ret) {
560 dev_err(&pdev->dev, "failed to soft reset\n");
561 return ret;
562 }
563
564 /* Disable all the interrupts */
565 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
566 }
567
568 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
569 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
570 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
571 SCR_TXFIFO_FSEL_IF8;
572 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
573 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
574 SCR_TXFIFO_FSEL_MASK;
575 } else {
576 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
577 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
578 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
579 }
580 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
581
582 /* Power up SPDIF module */
583 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
584
585 return 0;
586 }
587
fsl_spdif_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * cpu_dai)588 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
589 struct snd_soc_dai *cpu_dai)
590 {
591 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
592 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
593 struct regmap *regmap = spdif_priv->regmap;
594 u32 scr, mask;
595
596 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
597 scr = 0;
598 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
599 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
600 SCR_TXFIFO_FSEL_MASK;
601 /* Disable TX clock */
602 regmap_update_bits(regmap, REG_SPDIF_STC, STC_TXCLK_ALL_EN_MASK, 0);
603 } else {
604 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
605 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
606 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
607 }
608 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
609
610 /* Power down SPDIF module only if tx&rx are both inactive */
611 if (!snd_soc_dai_active(cpu_dai)) {
612 spdif_intr_status_clear(spdif_priv);
613 regmap_update_bits(regmap, REG_SPDIF_SCR,
614 SCR_LOW_POWER, SCR_LOW_POWER);
615 }
616 }
617
fsl_spdif_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)618 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
619 struct snd_pcm_hw_params *params,
620 struct snd_soc_dai *dai)
621 {
622 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
623 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
624 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
625 struct platform_device *pdev = spdif_priv->pdev;
626 u32 sample_rate = params_rate(params);
627 int ret = 0;
628
629 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
630 ret = spdif_set_sample_rate(substream, sample_rate);
631 if (ret) {
632 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
633 __func__, sample_rate);
634 return ret;
635 }
636 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
637 IEC958_AES3_CON_CLOCK_1000PPM);
638 spdif_write_channel_status(spdif_priv);
639 } else {
640 /* Setup rx clock source */
641 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
642 }
643
644 return ret;
645 }
646
fsl_spdif_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)647 static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
648 int cmd, struct snd_soc_dai *dai)
649 {
650 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
651 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
652 struct regmap *regmap = spdif_priv->regmap;
653 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
654 u32 intr = SIE_INTR_FOR(tx);
655 u32 dmaen = SCR_DMA_xX_EN(tx);
656
657 switch (cmd) {
658 case SNDRV_PCM_TRIGGER_START:
659 case SNDRV_PCM_TRIGGER_RESUME:
660 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
661 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
662 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
663 break;
664 case SNDRV_PCM_TRIGGER_STOP:
665 case SNDRV_PCM_TRIGGER_SUSPEND:
666 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
667 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
668 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
669 regmap_write(regmap, REG_SPDIF_STL, 0x0);
670 regmap_write(regmap, REG_SPDIF_STR, 0x0);
671 break;
672 default:
673 return -EINVAL;
674 }
675
676 return 0;
677 }
678
679 static const struct snd_soc_dai_ops fsl_spdif_dai_ops = {
680 .startup = fsl_spdif_startup,
681 .hw_params = fsl_spdif_hw_params,
682 .trigger = fsl_spdif_trigger,
683 .shutdown = fsl_spdif_shutdown,
684 };
685
686
687 /*
688 * FSL SPDIF IEC958 controller(mixer) functions
689 *
690 * Channel status get/put control
691 * User bit value get/put control
692 * Valid bit value get control
693 * DPLL lock status get control
694 * User bit sync mode selection control
695 */
696
fsl_spdif_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)697 static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
698 struct snd_ctl_elem_info *uinfo)
699 {
700 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
701 uinfo->count = 1;
702
703 return 0;
704 }
705
fsl_spdif_pb_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)706 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
707 struct snd_ctl_elem_value *uvalue)
708 {
709 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
710 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
711 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
712
713 uvalue->value.iec958.status[0] = ctrl->ch_status[0];
714 uvalue->value.iec958.status[1] = ctrl->ch_status[1];
715 uvalue->value.iec958.status[2] = ctrl->ch_status[2];
716 uvalue->value.iec958.status[3] = ctrl->ch_status[3];
717
718 return 0;
719 }
720
fsl_spdif_pb_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)721 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
722 struct snd_ctl_elem_value *uvalue)
723 {
724 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
725 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
726 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
727
728 ctrl->ch_status[0] = uvalue->value.iec958.status[0];
729 ctrl->ch_status[1] = uvalue->value.iec958.status[1];
730 ctrl->ch_status[2] = uvalue->value.iec958.status[2];
731 ctrl->ch_status[3] = uvalue->value.iec958.status[3];
732
733 spdif_write_channel_status(spdif_priv);
734
735 return 0;
736 }
737
738 /* Get channel status from SPDIF_RX_CCHAN register */
fsl_spdif_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)739 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
740 struct snd_ctl_elem_value *ucontrol)
741 {
742 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
743 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
744 struct regmap *regmap = spdif_priv->regmap;
745 u32 cstatus, val;
746
747 regmap_read(regmap, REG_SPDIF_SIS, &val);
748 if (!(val & INT_CNEW))
749 return -EAGAIN;
750
751 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
752 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
753 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
754 ucontrol->value.iec958.status[2] = cstatus & 0xFF;
755
756 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
757 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
758 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
759 ucontrol->value.iec958.status[5] = cstatus & 0xFF;
760
761 /* Clear intr */
762 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
763
764 return 0;
765 }
766
767 /*
768 * Get User bits (subcode) from chip value which readed out
769 * in UChannel register.
770 */
fsl_spdif_subcode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)771 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
772 struct snd_ctl_elem_value *ucontrol)
773 {
774 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
775 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
776 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
777 unsigned long flags;
778 int ret = -EAGAIN;
779
780 spin_lock_irqsave(&ctrl->ctl_lock, flags);
781 if (ctrl->ready_buf) {
782 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
783 memcpy(&ucontrol->value.iec958.subcode[0],
784 &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
785 ret = 0;
786 }
787 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
788
789 return ret;
790 }
791
792 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
fsl_spdif_qinfo(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)793 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
794 struct snd_ctl_elem_info *uinfo)
795 {
796 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
797 uinfo->count = SPDIF_QSUB_SIZE;
798
799 return 0;
800 }
801
802 /* Get Q subcode from chip value which readed out in QChannel register */
fsl_spdif_qget(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)803 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
804 struct snd_ctl_elem_value *ucontrol)
805 {
806 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
807 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
808 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
809 unsigned long flags;
810 int ret = -EAGAIN;
811
812 spin_lock_irqsave(&ctrl->ctl_lock, flags);
813 if (ctrl->ready_buf) {
814 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
815 memcpy(&ucontrol->value.bytes.data[0],
816 &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
817 ret = 0;
818 }
819 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
820
821 return ret;
822 }
823
824 /* Get valid good bit from interrupt status register */
fsl_spdif_rx_vbit_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)825 static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol,
826 struct snd_ctl_elem_value *ucontrol)
827 {
828 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
829 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
830 struct regmap *regmap = spdif_priv->regmap;
831 u32 val;
832
833 regmap_read(regmap, REG_SPDIF_SIS, &val);
834 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
835 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
836
837 return 0;
838 }
839
fsl_spdif_tx_vbit_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)840 static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol,
841 struct snd_ctl_elem_value *ucontrol)
842 {
843 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
844 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
845 struct regmap *regmap = spdif_priv->regmap;
846 u32 val;
847
848 regmap_read(regmap, REG_SPDIF_SCR, &val);
849 val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET;
850 val = 1 - val;
851 ucontrol->value.integer.value[0] = val;
852
853 return 0;
854 }
855
fsl_spdif_tx_vbit_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)856 static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol,
857 struct snd_ctl_elem_value *ucontrol)
858 {
859 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
860 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
861 struct regmap *regmap = spdif_priv->regmap;
862 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET;
863
864 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val);
865
866 return 0;
867 }
868
fsl_spdif_rx_rcm_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)869 static int fsl_spdif_rx_rcm_get(struct snd_kcontrol *kcontrol,
870 struct snd_ctl_elem_value *ucontrol)
871 {
872 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
873 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
874 struct regmap *regmap = spdif_priv->regmap;
875 u32 val;
876
877 regmap_read(regmap, REG_SPDIF_SCR, &val);
878 val = (val & SCR_RAW_CAPTURE_MODE) ? 1 : 0;
879 ucontrol->value.integer.value[0] = val;
880
881 return 0;
882 }
883
fsl_spdif_rx_rcm_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)884 static int fsl_spdif_rx_rcm_put(struct snd_kcontrol *kcontrol,
885 struct snd_ctl_elem_value *ucontrol)
886 {
887 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
888 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
889 struct regmap *regmap = spdif_priv->regmap;
890 u32 val = (ucontrol->value.integer.value[0] ? SCR_RAW_CAPTURE_MODE : 0);
891
892 if (val)
893 cpu_dai->driver->capture.formats |= SNDRV_PCM_FMTBIT_S32_LE;
894 else
895 cpu_dai->driver->capture.formats &= ~SNDRV_PCM_FMTBIT_S32_LE;
896
897 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_RAW_CAPTURE_MODE, val);
898
899 return 0;
900 }
901
902 /* DPLL lock information */
fsl_spdif_rxrate_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)903 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
904 struct snd_ctl_elem_info *uinfo)
905 {
906 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
907 uinfo->count = 1;
908 uinfo->value.integer.min = 16000;
909 uinfo->value.integer.max = 192000;
910
911 return 0;
912 }
913
914 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
915 24, 16, 12, 8, 6, 4, 3,
916 };
917
918 /* Get RX data clock rate given the SPDIF bus_clk */
spdif_get_rxclk_rate(struct fsl_spdif_priv * spdif_priv,enum spdif_gainsel gainsel)919 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
920 enum spdif_gainsel gainsel)
921 {
922 struct regmap *regmap = spdif_priv->regmap;
923 struct platform_device *pdev = spdif_priv->pdev;
924 u64 tmpval64, busclk_freq = 0;
925 u32 freqmeas, phaseconf;
926 u8 clksrc;
927
928 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
929 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
930
931 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
932
933 /* Get bus clock from system */
934 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
935 busclk_freq = clk_get_rate(spdif_priv->sysclk);
936
937 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
938 tmpval64 = (u64) busclk_freq * freqmeas;
939 do_div(tmpval64, gainsel_multi[gainsel] * 1024);
940 do_div(tmpval64, 128 * 1024);
941
942 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
943 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
944 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
945
946 return (int)tmpval64;
947 }
948
949 /*
950 * Get DPLL lock or not info from stable interrupt status register.
951 * User application must use this control to get locked,
952 * then can do next PCM operation
953 */
fsl_spdif_rxrate_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)954 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
955 struct snd_ctl_elem_value *ucontrol)
956 {
957 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
958 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
959 int rate = 0;
960
961 if (spdif_priv->dpll_locked)
962 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
963
964 ucontrol->value.integer.value[0] = rate;
965
966 return 0;
967 }
968
969 /*
970 * User bit sync mode:
971 * 1 CD User channel subcode
972 * 0 Non-CD data
973 */
fsl_spdif_usync_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)974 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
975 struct snd_ctl_elem_value *ucontrol)
976 {
977 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
978 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
979 struct regmap *regmap = spdif_priv->regmap;
980 u32 val;
981
982 regmap_read(regmap, REG_SPDIF_SRCD, &val);
983 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
984
985 return 0;
986 }
987
988 /*
989 * User bit sync mode:
990 * 1 CD User channel subcode
991 * 0 Non-CD data
992 */
fsl_spdif_usync_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)993 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
994 struct snd_ctl_elem_value *ucontrol)
995 {
996 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
997 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
998 struct regmap *regmap = spdif_priv->regmap;
999 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
1000
1001 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
1002
1003 return 0;
1004 }
1005
1006 /* FSL SPDIF IEC958 controller defines */
1007 static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
1008 /* Status cchanel controller */
1009 {
1010 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1011 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1012 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1013 SNDRV_CTL_ELEM_ACCESS_WRITE |
1014 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1015 .info = fsl_spdif_info,
1016 .get = fsl_spdif_pb_get,
1017 .put = fsl_spdif_pb_put,
1018 },
1019 {
1020 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1021 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
1022 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1023 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1024 .info = fsl_spdif_info,
1025 .get = fsl_spdif_capture_get,
1026 },
1027 /* User bits controller */
1028 {
1029 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1030 .name = "IEC958 Subcode Capture Default",
1031 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1032 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1033 .info = fsl_spdif_info,
1034 .get = fsl_spdif_subcode_get,
1035 },
1036 {
1037 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1038 .name = "IEC958 Q-subcode Capture Default",
1039 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1040 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1041 .info = fsl_spdif_qinfo,
1042 .get = fsl_spdif_qget,
1043 },
1044 /* Valid bit error controller */
1045 {
1046 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1047 .name = "IEC958 RX V-Bit Errors",
1048 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1049 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1050 .info = snd_ctl_boolean_mono_info,
1051 .get = fsl_spdif_rx_vbit_get,
1052 },
1053 {
1054 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1055 .name = "IEC958 TX V-Bit",
1056 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1057 SNDRV_CTL_ELEM_ACCESS_WRITE |
1058 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1059 .info = snd_ctl_boolean_mono_info,
1060 .get = fsl_spdif_tx_vbit_get,
1061 .put = fsl_spdif_tx_vbit_put,
1062 },
1063 /* DPLL lock info get controller */
1064 {
1065 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1066 .name = "RX Sample Rate",
1067 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1068 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1069 .info = fsl_spdif_rxrate_info,
1070 .get = fsl_spdif_rxrate_get,
1071 },
1072 /* User bit sync mode set/get controller */
1073 {
1074 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1075 .name = "IEC958 USyncMode CDText",
1076 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1077 SNDRV_CTL_ELEM_ACCESS_WRITE |
1078 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1079 .info = snd_ctl_boolean_mono_info,
1080 .get = fsl_spdif_usync_get,
1081 .put = fsl_spdif_usync_put,
1082 },
1083 };
1084
1085 static struct snd_kcontrol_new fsl_spdif_ctrls_rcm[] = {
1086 {
1087 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1088 .name = "IEC958 Raw Capture Mode",
1089 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1090 SNDRV_CTL_ELEM_ACCESS_WRITE |
1091 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1092 .info = snd_ctl_boolean_mono_info,
1093 .get = fsl_spdif_rx_rcm_get,
1094 .put = fsl_spdif_rx_rcm_put,
1095 },
1096 };
1097
fsl_spdif_dai_probe(struct snd_soc_dai * dai)1098 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
1099 {
1100 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
1101
1102 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
1103 &spdif_private->dma_params_rx);
1104
1105 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
1106
1107 if (spdif_private->soc->raw_capture_mode)
1108 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls_rcm,
1109 ARRAY_SIZE(fsl_spdif_ctrls_rcm));
1110
1111 /*Clear the val bit for Tx*/
1112 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR,
1113 SCR_VAL_MASK, SCR_VAL_CLEAR);
1114
1115 return 0;
1116 }
1117
1118 static struct snd_soc_dai_driver fsl_spdif_dai = {
1119 .probe = &fsl_spdif_dai_probe,
1120 .playback = {
1121 .stream_name = "CPU-Playback",
1122 .channels_min = 2,
1123 .channels_max = 2,
1124 .rates = FSL_SPDIF_RATES_PLAYBACK,
1125 .formats = FSL_SPDIF_FORMATS_PLAYBACK,
1126 },
1127 .capture = {
1128 .stream_name = "CPU-Capture",
1129 .channels_min = 2,
1130 .channels_max = 2,
1131 .rates = FSL_SPDIF_RATES_CAPTURE,
1132 .formats = FSL_SPDIF_FORMATS_CAPTURE,
1133 },
1134 .ops = &fsl_spdif_dai_ops,
1135 };
1136
1137 static const struct snd_soc_component_driver fsl_spdif_component = {
1138 .name = "fsl-spdif",
1139 };
1140
1141 /* FSL SPDIF REGMAP */
1142 static const struct reg_default fsl_spdif_reg_defaults[] = {
1143 {REG_SPDIF_SCR, 0x00000400},
1144 {REG_SPDIF_SRCD, 0x00000000},
1145 {REG_SPDIF_SIE, 0x00000000},
1146 {REG_SPDIF_STL, 0x00000000},
1147 {REG_SPDIF_STR, 0x00000000},
1148 {REG_SPDIF_STCSCH, 0x00000000},
1149 {REG_SPDIF_STCSCL, 0x00000000},
1150 {REG_SPDIF_STC, 0x00020f00},
1151 };
1152
fsl_spdif_readable_reg(struct device * dev,unsigned int reg)1153 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
1154 {
1155 switch (reg) {
1156 case REG_SPDIF_SCR:
1157 case REG_SPDIF_SRCD:
1158 case REG_SPDIF_SRPC:
1159 case REG_SPDIF_SIE:
1160 case REG_SPDIF_SIS:
1161 case REG_SPDIF_SRL:
1162 case REG_SPDIF_SRR:
1163 case REG_SPDIF_SRCSH:
1164 case REG_SPDIF_SRCSL:
1165 case REG_SPDIF_SRU:
1166 case REG_SPDIF_SRQ:
1167 case REG_SPDIF_STCSCH:
1168 case REG_SPDIF_STCSCL:
1169 case REG_SPDIF_SRFM:
1170 case REG_SPDIF_STC:
1171 return true;
1172 default:
1173 return false;
1174 }
1175 }
1176
fsl_spdif_volatile_reg(struct device * dev,unsigned int reg)1177 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
1178 {
1179 switch (reg) {
1180 case REG_SPDIF_SRPC:
1181 case REG_SPDIF_SIS:
1182 case REG_SPDIF_SRL:
1183 case REG_SPDIF_SRR:
1184 case REG_SPDIF_SRCSH:
1185 case REG_SPDIF_SRCSL:
1186 case REG_SPDIF_SRU:
1187 case REG_SPDIF_SRQ:
1188 case REG_SPDIF_SRFM:
1189 return true;
1190 default:
1191 return false;
1192 }
1193 }
1194
fsl_spdif_writeable_reg(struct device * dev,unsigned int reg)1195 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
1196 {
1197 switch (reg) {
1198 case REG_SPDIF_SCR:
1199 case REG_SPDIF_SRCD:
1200 case REG_SPDIF_SRPC:
1201 case REG_SPDIF_SIE:
1202 case REG_SPDIF_SIC:
1203 case REG_SPDIF_STL:
1204 case REG_SPDIF_STR:
1205 case REG_SPDIF_STCSCH:
1206 case REG_SPDIF_STCSCL:
1207 case REG_SPDIF_STC:
1208 return true;
1209 default:
1210 return false;
1211 }
1212 }
1213
1214 static const struct regmap_config fsl_spdif_regmap_config = {
1215 .reg_bits = 32,
1216 .reg_stride = 4,
1217 .val_bits = 32,
1218
1219 .max_register = REG_SPDIF_STC,
1220 .reg_defaults = fsl_spdif_reg_defaults,
1221 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),
1222 .readable_reg = fsl_spdif_readable_reg,
1223 .volatile_reg = fsl_spdif_volatile_reg,
1224 .writeable_reg = fsl_spdif_writeable_reg,
1225 .cache_type = REGCACHE_FLAT,
1226 };
1227
fsl_spdif_txclk_caldiv(struct fsl_spdif_priv * spdif_priv,struct clk * clk,u64 savesub,enum spdif_txrate index,bool round)1228 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
1229 struct clk *clk, u64 savesub,
1230 enum spdif_txrate index, bool round)
1231 {
1232 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400,
1233 192000, };
1234 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
1235 u64 rate_ideal, rate_actual, sub;
1236 u32 arate;
1237 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df;
1238 u8 txclk_df;
1239
1240 /* The sysclk has an extra divisor [2, 512] */
1241 sysclk_dfmin = is_sysclk ? 2 : 1;
1242 sysclk_dfmax = is_sysclk ? 512 : 1;
1243
1244 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
1245 for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
1246 rate_ideal = rate[index] * txclk_df * 64ULL;
1247 if (round)
1248 rate_actual = clk_round_rate(clk, rate_ideal);
1249 else
1250 rate_actual = clk_get_rate(clk);
1251
1252 arate = rate_actual / 64;
1253 arate /= txclk_df * sysclk_df;
1254
1255 if (arate == rate[index]) {
1256 /* We are lucky */
1257 savesub = 0;
1258 spdif_priv->txclk_df[index] = txclk_df;
1259 spdif_priv->sysclk_df[index] = sysclk_df;
1260 spdif_priv->txrate[index] = arate;
1261 goto out;
1262 } else if (arate / rate[index] == 1) {
1263 /* A little bigger than expect */
1264 sub = (u64)(arate - rate[index]) * 100000;
1265 do_div(sub, rate[index]);
1266 if (sub >= savesub)
1267 continue;
1268 savesub = sub;
1269 spdif_priv->txclk_df[index] = txclk_df;
1270 spdif_priv->sysclk_df[index] = sysclk_df;
1271 spdif_priv->txrate[index] = arate;
1272 } else if (rate[index] / arate == 1) {
1273 /* A little smaller than expect */
1274 sub = (u64)(rate[index] - arate) * 100000;
1275 do_div(sub, rate[index]);
1276 if (sub >= savesub)
1277 continue;
1278 savesub = sub;
1279 spdif_priv->txclk_df[index] = txclk_df;
1280 spdif_priv->sysclk_df[index] = sysclk_df;
1281 spdif_priv->txrate[index] = arate;
1282 }
1283 }
1284 }
1285
1286 out:
1287 return savesub;
1288 }
1289
fsl_spdif_probe_txclk(struct fsl_spdif_priv * spdif_priv,enum spdif_txrate index)1290 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
1291 enum spdif_txrate index)
1292 {
1293 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400,
1294 192000, };
1295 struct platform_device *pdev = spdif_priv->pdev;
1296 struct device *dev = &pdev->dev;
1297 u64 savesub = 100000, ret;
1298 struct clk *clk;
1299 char tmp[16];
1300 int i;
1301
1302 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
1303 sprintf(tmp, "rxtx%d", i);
1304 clk = devm_clk_get(dev, tmp);
1305 if (IS_ERR(clk)) {
1306 dev_err(dev, "no rxtx%d clock in devicetree\n", i);
1307 return PTR_ERR(clk);
1308 }
1309 if (!clk_get_rate(clk))
1310 continue;
1311
1312 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
1313 fsl_spdif_can_set_clk_rate(spdif_priv, i));
1314 if (savesub == ret)
1315 continue;
1316
1317 savesub = ret;
1318 spdif_priv->txclk[index] = clk;
1319 spdif_priv->txclk_src[index] = i;
1320
1321 /* To quick catch a divisor, we allow a 0.1% deviation */
1322 if (savesub < 100)
1323 break;
1324 }
1325
1326 dev_dbg(dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
1327 spdif_priv->txclk_src[index], rate[index]);
1328 dev_dbg(dev, "use txclk df %d for %dHz sample rate\n",
1329 spdif_priv->txclk_df[index], rate[index]);
1330 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk))
1331 dev_dbg(dev, "use sysclk df %d for %dHz sample rate\n",
1332 spdif_priv->sysclk_df[index], rate[index]);
1333 dev_dbg(dev, "the best rate for %dHz sample rate is %dHz\n",
1334 rate[index], spdif_priv->txrate[index]);
1335
1336 return 0;
1337 }
1338
fsl_spdif_probe(struct platform_device * pdev)1339 static int fsl_spdif_probe(struct platform_device *pdev)
1340 {
1341 struct fsl_spdif_priv *spdif_priv;
1342 struct spdif_mixer_control *ctrl;
1343 struct resource *res;
1344 void __iomem *regs;
1345 int irq, ret, i;
1346
1347 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL);
1348 if (!spdif_priv)
1349 return -ENOMEM;
1350
1351 spdif_priv->pdev = pdev;
1352
1353 spdif_priv->soc = of_device_get_match_data(&pdev->dev);
1354
1355 /* Initialize this copy of the CPU DAI driver structure */
1356 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
1357 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev);
1358 spdif_priv->cpu_dai_drv.playback.formats =
1359 spdif_priv->soc->tx_formats;
1360
1361 /* Get the addresses and IRQ */
1362 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1363 if (IS_ERR(regs))
1364 return PTR_ERR(regs);
1365
1366 spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config);
1367 if (IS_ERR(spdif_priv->regmap)) {
1368 dev_err(&pdev->dev, "regmap init failed\n");
1369 return PTR_ERR(spdif_priv->regmap);
1370 }
1371
1372 for (i = 0; i < spdif_priv->soc->interrupts; i++) {
1373 irq = platform_get_irq(pdev, i);
1374 if (irq < 0)
1375 return irq;
1376
1377 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
1378 dev_name(&pdev->dev), spdif_priv);
1379 if (ret) {
1380 dev_err(&pdev->dev, "could not claim irq %u\n", irq);
1381 return ret;
1382 }
1383 }
1384
1385 /* Get system clock for rx clock rate calculation */
1386 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5");
1387 if (IS_ERR(spdif_priv->sysclk)) {
1388 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
1389 return PTR_ERR(spdif_priv->sysclk);
1390 }
1391
1392 /* Get core clock for data register access via DMA */
1393 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
1394 if (IS_ERR(spdif_priv->coreclk)) {
1395 dev_err(&pdev->dev, "no core clock in devicetree\n");
1396 return PTR_ERR(spdif_priv->coreclk);
1397 }
1398
1399 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
1400 if (IS_ERR(spdif_priv->spbaclk))
1401 dev_warn(&pdev->dev, "no spba clock in devicetree\n");
1402
1403 /* Select clock source for rx/tx clock */
1404 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
1405 if (IS_ERR(spdif_priv->rxclk)) {
1406 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
1407 return PTR_ERR(spdif_priv->rxclk);
1408 }
1409 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
1410
1411 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
1412 ret = fsl_spdif_probe_txclk(spdif_priv, i);
1413 if (ret)
1414 return ret;
1415 }
1416
1417 /* Initial spinlock for control data */
1418 ctrl = &spdif_priv->fsl_spdif_control;
1419 spin_lock_init(&ctrl->ctl_lock);
1420
1421 /* Init tx channel status default value */
1422 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
1423 IEC958_AES0_CON_EMPHASIS_5015;
1424 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
1425 ctrl->ch_status[2] = 0x00;
1426 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
1427 IEC958_AES3_CON_CLOCK_1000PPM;
1428
1429 spdif_priv->dpll_locked = false;
1430
1431 spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst;
1432 spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst;
1433 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
1434 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
1435
1436 /* Register with ASoC */
1437 dev_set_drvdata(&pdev->dev, spdif_priv);
1438 pm_runtime_enable(&pdev->dev);
1439 regcache_cache_only(spdif_priv->regmap, true);
1440
1441 /*
1442 * Register platform component before registering cpu dai for there
1443 * is not defer probe for platform component in snd_soc_add_pcm_runtime().
1444 */
1445 ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE);
1446 if (ret) {
1447 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n");
1448 goto err_pm_disable;
1449 }
1450
1451 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
1452 &spdif_priv->cpu_dai_drv, 1);
1453 if (ret) {
1454 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1455 goto err_pm_disable;
1456 }
1457
1458 return ret;
1459
1460 err_pm_disable:
1461 pm_runtime_disable(&pdev->dev);
1462 return ret;
1463 }
1464
fsl_spdif_remove(struct platform_device * pdev)1465 static int fsl_spdif_remove(struct platform_device *pdev)
1466 {
1467 pm_runtime_disable(&pdev->dev);
1468
1469 return 0;
1470 }
1471
1472 #ifdef CONFIG_PM
fsl_spdif_runtime_suspend(struct device * dev)1473 static int fsl_spdif_runtime_suspend(struct device *dev)
1474 {
1475 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1476 int i;
1477
1478 /* Disable all the interrupts */
1479 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0);
1480
1481 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC,
1482 &spdif_priv->regcache_srpc);
1483 regcache_cache_only(spdif_priv->regmap, true);
1484
1485 clk_disable_unprepare(spdif_priv->rxclk);
1486
1487 for (i = 0; i < SPDIF_TXRATE_MAX; i++)
1488 clk_disable_unprepare(spdif_priv->txclk[i]);
1489
1490 if (!IS_ERR(spdif_priv->spbaclk))
1491 clk_disable_unprepare(spdif_priv->spbaclk);
1492 clk_disable_unprepare(spdif_priv->coreclk);
1493
1494 return 0;
1495 }
1496
fsl_spdif_runtime_resume(struct device * dev)1497 static int fsl_spdif_runtime_resume(struct device *dev)
1498 {
1499 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
1500 int ret;
1501 int i;
1502
1503 ret = clk_prepare_enable(spdif_priv->coreclk);
1504 if (ret) {
1505 dev_err(dev, "failed to enable core clock\n");
1506 return ret;
1507 }
1508
1509 if (!IS_ERR(spdif_priv->spbaclk)) {
1510 ret = clk_prepare_enable(spdif_priv->spbaclk);
1511 if (ret) {
1512 dev_err(dev, "failed to enable spba clock\n");
1513 goto disable_core_clk;
1514 }
1515 }
1516
1517 for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
1518 ret = clk_prepare_enable(spdif_priv->txclk[i]);
1519 if (ret)
1520 goto disable_tx_clk;
1521 }
1522
1523 ret = clk_prepare_enable(spdif_priv->rxclk);
1524 if (ret)
1525 goto disable_tx_clk;
1526
1527 regcache_cache_only(spdif_priv->regmap, false);
1528 regcache_mark_dirty(spdif_priv->regmap);
1529
1530 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC,
1531 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
1532 spdif_priv->regcache_srpc);
1533
1534 ret = regcache_sync(spdif_priv->regmap);
1535 if (ret)
1536 goto disable_rx_clk;
1537
1538 return 0;
1539
1540 disable_rx_clk:
1541 clk_disable_unprepare(spdif_priv->rxclk);
1542 disable_tx_clk:
1543 for (i--; i >= 0; i--)
1544 clk_disable_unprepare(spdif_priv->txclk[i]);
1545 if (!IS_ERR(spdif_priv->spbaclk))
1546 clk_disable_unprepare(spdif_priv->spbaclk);
1547 disable_core_clk:
1548 clk_disable_unprepare(spdif_priv->coreclk);
1549
1550 return ret;
1551 }
1552 #endif /* CONFIG_PM */
1553
1554 static const struct dev_pm_ops fsl_spdif_pm = {
1555 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1556 pm_runtime_force_resume)
1557 SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume,
1558 NULL)
1559 };
1560
1561 static const struct of_device_id fsl_spdif_dt_ids[] = {
1562 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, },
1563 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, },
1564 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, },
1565 { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, },
1566 { .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, },
1567 {}
1568 };
1569 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
1570
1571 static struct platform_driver fsl_spdif_driver = {
1572 .driver = {
1573 .name = "fsl-spdif-dai",
1574 .of_match_table = fsl_spdif_dt_ids,
1575 .pm = &fsl_spdif_pm,
1576 },
1577 .probe = fsl_spdif_probe,
1578 .remove = fsl_spdif_remove,
1579 };
1580
1581 module_platform_driver(fsl_spdif_driver);
1582
1583 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1584 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
1585 MODULE_LICENSE("GPL v2");
1586 MODULE_ALIAS("platform:fsl-spdif-dai");
1587