Lines Matching refs:RCAR_GP_PIN
1233 RCAR_GP_PIN(7, 4),
1240 RCAR_GP_PIN(7, 10),
1247 RCAR_GP_PIN(7, 5),
1254 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1264 RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),
1265 RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7),
1266 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3),
1267 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),
1268 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
1269 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8),
1281 RCAR_GP_PIN(7, 9),
1288 RCAR_GP_PIN(7, 0),
1295 RCAR_GP_PIN(7, 1),
1302 RCAR_GP_PIN(7, 2),
1311 RCAR_GP_PIN(6, 4),
1318 RCAR_GP_PIN(6, 1),
1325 RCAR_GP_PIN(6, 3),
1332 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
1342 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1343 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),
1344 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),
1345 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8),
1346 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1347 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),
1359 RCAR_GP_PIN(6, 20),
1366 RCAR_GP_PIN(6, 10),
1373 RCAR_GP_PIN(6, 11),
1380 RCAR_GP_PIN(6, 5),
1389 RCAR_GP_PIN(5, 3),
1396 RCAR_GP_PIN(5, 5),
1403 RCAR_GP_PIN(5, 4),
1410 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),
1420 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),
1421 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),
1422 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8),
1423 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),
1424 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),
1425 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9),
1437 RCAR_GP_PIN(5, 7),
1444 RCAR_GP_PIN(5, 0),
1451 RCAR_GP_PIN(5, 1),
1458 RCAR_GP_PIN(5, 2),
1467 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1476 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1485 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1494 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1503 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1512 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1521 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1530 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1539 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1548 RCAR_GP_PIN(2, 9),
1557 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
1564 RCAR_GP_PIN(1, 15),
1571 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1580 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1587 RCAR_GP_PIN(0, 18),
1594 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
1603 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1610 RCAR_GP_PIN(1, 10),
1617 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1626 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1633 RCAR_GP_PIN(8, 13),
1640 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12),
1649 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
1656 RCAR_GP_PIN(1, 25),
1663 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1672 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1679 RCAR_GP_PIN(1, 3),
1686 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1695 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0),
1704 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2),
1713 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4),
1722 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6),
1731 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8),
1740 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10),
1749 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1750 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),
1751 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),
1752 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1762 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),
1769 RCAR_GP_PIN(3, 11),
1776 RCAR_GP_PIN(3, 12),
1783 RCAR_GP_PIN(3, 4),
1792 RCAR_GP_PIN(1, 10),
1799 RCAR_GP_PIN(1, 8),
1806 RCAR_GP_PIN(1, 7),
1813 RCAR_GP_PIN(1, 6),
1820 RCAR_GP_PIN(1, 9),
1827 RCAR_GP_PIN(1, 11),
1836 RCAR_GP_PIN(1, 3),
1843 RCAR_GP_PIN(1, 2),
1850 RCAR_GP_PIN(1, 1),
1857 RCAR_GP_PIN(1, 0),
1864 RCAR_GP_PIN(1, 4),
1871 RCAR_GP_PIN(1, 5),
1880 RCAR_GP_PIN(0, 17),
1887 RCAR_GP_PIN(0, 15),
1894 RCAR_GP_PIN(0, 14),
1901 RCAR_GP_PIN(0, 13),
1908 RCAR_GP_PIN(0, 16),
1915 RCAR_GP_PIN(0, 18),
1924 RCAR_GP_PIN(0, 3),
1931 RCAR_GP_PIN(0, 6),
1938 RCAR_GP_PIN(0, 1),
1945 RCAR_GP_PIN(0, 2),
1952 RCAR_GP_PIN(0, 4),
1959 RCAR_GP_PIN(0, 5),
1968 RCAR_GP_PIN(1, 25),
1975 RCAR_GP_PIN(1, 28),
1982 RCAR_GP_PIN(1, 23),
1989 RCAR_GP_PIN(1, 24),
1996 RCAR_GP_PIN(1, 26),
2003 RCAR_GP_PIN(1, 27),
2012 RCAR_GP_PIN(0, 11),
2019 RCAR_GP_PIN(0, 9),
2026 RCAR_GP_PIN(0, 8),
2033 RCAR_GP_PIN(0, 7),
2040 RCAR_GP_PIN(0, 10),
2047 RCAR_GP_PIN(0, 12),
2056 RCAR_GP_PIN(4, 21),
2065 RCAR_GP_PIN(4, 22),
2075 RCAR_GP_PIN(1, 15),
2084 RCAR_GP_PIN(3, 13),
2093 RCAR_GP_PIN(2, 13),
2102 RCAR_GP_PIN(2, 14),
2111 RCAR_GP_PIN(1, 22),
2120 RCAR_GP_PIN(2, 15),
2129 RCAR_GP_PIN(2, 16),
2138 RCAR_GP_PIN(2, 17),
2147 RCAR_GP_PIN(2, 18),
2156 RCAR_GP_PIN(2, 19),
2165 RCAR_GP_PIN(1, 13),
2174 RCAR_GP_PIN(1, 14),
2183 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),
2190 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2191 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2201 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),
2208 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),
2209 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),
2219 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
2226 RCAR_GP_PIN(1, 15),
2233 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2242 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2249 RCAR_GP_PIN(0, 18),
2256 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
2265 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2272 RCAR_GP_PIN(1, 10),
2279 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2288 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2295 RCAR_GP_PIN(1, 4),
2302 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2311 RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
2318 RCAR_GP_PIN(1, 24),
2325 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2334 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),
2341 RCAR_GP_PIN(8, 8),
2348 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),
2357 RCAR_GP_PIN(1, 17),
2366 RCAR_GP_PIN(2, 8),
2373 RCAR_GP_PIN(2, 7),
2380 RCAR_GP_PIN(2, 12),
2387 RCAR_GP_PIN(2, 13),
2396 RCAR_GP_PIN(1, 25),
2403 RCAR_GP_PIN(1, 26),
2410 RCAR_GP_PIN(2, 0),
2417 RCAR_GP_PIN(2, 1),
2426 RCAR_GP_PIN(4, 4),
2433 RCAR_GP_PIN(4, 3),
2440 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
2450 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 12),
2451 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14),
2452 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2453 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 11),
2454 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13),
2455 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
2467 RCAR_GP_PIN(4, 20),
2474 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2),
2481 RCAR_GP_PIN(4, 6),
2488 RCAR_GP_PIN(4, 5),
3637 { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */
3638 { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */
3639 { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */
3640 { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */
3641 { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */
3642 { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */
3643 { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */
3644 { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */
3647 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */
3648 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */
3649 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */
3650 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */
3651 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */
3652 { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */
3653 { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */
3654 { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */
3657 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */
3658 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */
3659 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */
3662 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */
3663 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */
3664 { RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */
3665 { RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */
3666 { RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */
3667 { RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */
3668 { RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */
3669 { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */
3672 { RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */
3673 { RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */
3674 { RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */
3675 { RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */
3676 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */
3677 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */
3678 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */
3679 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */
3682 { RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */
3683 { RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */
3684 { RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */
3685 { RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */
3686 { RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */
3687 { RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */
3688 { RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */
3689 { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */
3692 { RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */
3693 { RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */
3694 { RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */
3695 { RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */
3696 { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */
3699 { RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */
3700 { RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */
3701 { RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */
3702 { RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */
3703 { RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */
3704 { RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */
3705 { RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */
3706 { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */
3709 { RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */
3710 { RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */
3711 { RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */
3712 { RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */
3713 { RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */
3714 { RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */
3715 { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */
3716 { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */
3719 { RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD7_RX */
3720 { RCAR_GP_PIN(2, 18), 8, 3 }, /* CANFD7_TX */
3721 { RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD4_RX */
3722 { RCAR_GP_PIN(2, 16), 0, 3 }, /* CANFD4_TX */
3725 { RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */
3726 { RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */
3727 { RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */
3728 { RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */
3729 { RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */
3730 { RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */
3731 { RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */
3732 { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */
3735 { RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */
3736 { RCAR_GP_PIN(3, 14), 24, 2 }, /* IPC_CLKOUT */
3737 { RCAR_GP_PIN(3, 13), 20, 2 }, /* IPC_CLKIN */
3738 { RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */
3739 { RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */
3740 { RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */
3741 { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/
3742 { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */
3745 { RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */
3746 { RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */
3747 { RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */
3748 { RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */
3749 { RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */
3750 { RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */
3751 { RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */
3752 { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */
3755 { RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */
3756 { RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */
3757 { RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */
3758 { RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */
3759 { RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */
3760 { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */
3763 { RCAR_GP_PIN(4, 7), 28, 3 }, /* TSN0_RX_CTL */
3764 { RCAR_GP_PIN(4, 6), 24, 3 }, /* TSN0_AVTP_CAPTURE */
3765 { RCAR_GP_PIN(4, 5), 20, 3 }, /* TSN0_AVTP_MATCH */
3766 { RCAR_GP_PIN(4, 4), 16, 3 }, /* TSN0_LINK */
3767 { RCAR_GP_PIN(4, 3), 12, 3 }, /* TSN0_PHY_INT */
3768 { RCAR_GP_PIN(4, 2), 8, 3 }, /* TSN0_AVTP_PPS1 */
3769 { RCAR_GP_PIN(4, 1), 4, 3 }, /* TSN0_MDC */
3770 { RCAR_GP_PIN(4, 0), 0, 3 }, /* TSN0_MDIO */
3773 { RCAR_GP_PIN(4, 15), 28, 3 }, /* TSN0_TD0 */
3774 { RCAR_GP_PIN(4, 14), 24, 3 }, /* TSN0_TD1 */
3775 { RCAR_GP_PIN(4, 13), 20, 3 }, /* TSN0_RD1 */
3776 { RCAR_GP_PIN(4, 12), 16, 3 }, /* TSN0_TXC */
3777 { RCAR_GP_PIN(4, 11), 12, 3 }, /* TSN0_RXC */
3778 { RCAR_GP_PIN(4, 10), 8, 3 }, /* TSN0_RD0 */
3779 { RCAR_GP_PIN(4, 9), 4, 3 }, /* TSN0_TX_CTL */
3780 { RCAR_GP_PIN(4, 8), 0, 3 }, /* TSN0_AVTP_PPS0 */
3783 { RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */
3784 { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */
3785 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */
3786 { RCAR_GP_PIN(4, 20), 16, 3 }, /* TSN0_TXCREFCLK */
3787 { RCAR_GP_PIN(4, 19), 12, 3 }, /* TSN0_TD2 */
3788 { RCAR_GP_PIN(4, 18), 8, 3 }, /* TSN0_TD3 */
3789 { RCAR_GP_PIN(4, 17), 4, 3 }, /* TSN0_RD2 */
3790 { RCAR_GP_PIN(4, 16), 0, 3 }, /* TSN0_RD3 */
3793 { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */
3796 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */
3797 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */
3798 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */
3799 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */
3800 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */
3801 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */
3802 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */
3803 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */
3806 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */
3807 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */
3808 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */
3809 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */
3810 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */
3811 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */
3812 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */
3813 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */
3816 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */
3817 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */
3818 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */
3819 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */
3820 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */
3823 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */
3824 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */
3825 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */
3826 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */
3827 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */
3828 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */
3829 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */
3830 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */
3833 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */
3834 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */
3835 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */
3836 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */
3837 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */
3838 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */
3839 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */
3840 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */
3843 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */
3844 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */
3845 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */
3846 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */
3847 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */
3850 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */
3851 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */
3852 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */
3853 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */
3854 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */
3855 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */
3856 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */
3857 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */
3860 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */
3861 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */
3862 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */
3863 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */
3864 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */
3865 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */
3866 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */
3867 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */
3870 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */
3871 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */
3872 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */
3873 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */
3874 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */
3877 { RCAR_GP_PIN(8, 7), 28, 3 }, /* SDA3 */
3878 { RCAR_GP_PIN(8, 6), 24, 3 }, /* SCL3 */
3879 { RCAR_GP_PIN(8, 5), 20, 3 }, /* SDA2 */
3880 { RCAR_GP_PIN(8, 4), 16, 3 }, /* SCL2 */
3881 { RCAR_GP_PIN(8, 3), 12, 3 }, /* SDA1 */
3882 { RCAR_GP_PIN(8, 2), 8, 3 }, /* SCL1 */
3883 { RCAR_GP_PIN(8, 1), 4, 3 }, /* SDA0 */
3884 { RCAR_GP_PIN(8, 0), 0, 3 }, /* SCL0 */
3887 { RCAR_GP_PIN(8, 13), 20, 3 }, /* GP8_13 */
3888 { RCAR_GP_PIN(8, 12), 16, 3 }, /* GP8_12 */
3889 { RCAR_GP_PIN(8, 11), 12, 3 }, /* SDA5 */
3890 { RCAR_GP_PIN(8, 10), 8, 3 }, /* SCL5 */
3891 { RCAR_GP_PIN(8, 9), 4, 3 }, /* SDA4 */
3892 { RCAR_GP_PIN(8, 8), 0, 3 }, /* SCL4 */
3925 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 18)) in r8a779g0_pin_to_pocctrl()
3929 if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 22)) in r8a779g0_pin_to_pocctrl()
3933 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 12)) in r8a779g0_pin_to_pocctrl()
3937 if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 13)) in r8a779g0_pin_to_pocctrl()
3945 [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */
3946 [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */
3947 [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */
3948 [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */
3949 [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */
3950 [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */
3951 [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */
3952 [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */
3953 [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */
3954 [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */
3955 [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */
3956 [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */
3957 [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */
3958 [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */
3959 [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */
3960 [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */
3961 [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */
3962 [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */
3963 [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */
3979 [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */
3980 [ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */
3981 [ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */
3982 [ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */
3983 [ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */
3984 [ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */
3985 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */
3986 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */
3987 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */
3988 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */
3989 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */
3990 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */
3991 [12] = RCAR_GP_PIN(1, 12), /* HTX0 */
3992 [13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */
3993 [14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */
3994 [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */
3995 [16] = RCAR_GP_PIN(1, 16), /* HRX0 */
3996 [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */
3997 [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */
3998 [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */
3999 [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */
4000 [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */
4001 [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */
4002 [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */
4003 [24] = RCAR_GP_PIN(1, 24), /* HRX3 */
4004 [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */
4005 [26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */
4006 [27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */
4007 [28] = RCAR_GP_PIN(1, 28), /* HTX3 */
4013 [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */
4014 [ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */
4015 [ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */
4016 [ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */
4017 [ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */
4018 [ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */
4019 [ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */
4020 [ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */
4021 [ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */
4022 [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */
4023 [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */
4024 [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */
4025 [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */
4026 [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */
4027 [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */
4028 [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */
4029 [16] = RCAR_GP_PIN(2, 16), /* CANFD4_TX */
4030 [17] = RCAR_GP_PIN(2, 17), /* CANFD4_RX */
4031 [18] = RCAR_GP_PIN(2, 18), /* CANFD7_TX */
4032 [19] = RCAR_GP_PIN(2, 19), /* CANFD7_RX */
4047 [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */
4048 [ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */
4049 [ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */
4050 [ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */
4051 [ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */
4052 [ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */
4053 [ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */
4054 [ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */
4055 [ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */
4056 [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */
4057 [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */
4058 [11] = RCAR_GP_PIN(3, 11), /* SD_CD */
4059 [12] = RCAR_GP_PIN(3, 12), /* SD_WP */
4060 [13] = RCAR_GP_PIN(3, 13), /* IPC_CLKIN */
4061 [14] = RCAR_GP_PIN(3, 14), /* IPC_CLKOUT */
4062 [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */
4063 [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */
4064 [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */
4065 [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */
4066 [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */
4067 [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */
4068 [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */
4069 [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */
4070 [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */
4071 [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */
4072 [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */
4073 [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */
4074 [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */
4075 [28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */
4076 [29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */
4081 [ 0] = RCAR_GP_PIN(4, 0), /* TSN0_MDIO */
4082 [ 1] = RCAR_GP_PIN(4, 1), /* TSN0_MDC */
4083 [ 2] = RCAR_GP_PIN(4, 2), /* TSN0_AVTP_PPS1 */
4084 [ 3] = RCAR_GP_PIN(4, 3), /* TSN0_PHY_INT */
4085 [ 4] = RCAR_GP_PIN(4, 4), /* TSN0_LINK */
4086 [ 5] = RCAR_GP_PIN(4, 5), /* TSN0_AVTP_MATCH */
4087 [ 6] = RCAR_GP_PIN(4, 6), /* TSN0_AVTP_CAPTURE */
4088 [ 7] = RCAR_GP_PIN(4, 7), /* TSN0_RX_CTL */
4089 [ 8] = RCAR_GP_PIN(4, 8), /* TSN0_AVTP_PPS0 */
4090 [ 9] = RCAR_GP_PIN(4, 9), /* TSN0_TX_CTL */
4091 [10] = RCAR_GP_PIN(4, 10), /* TSN0_RD0 */
4092 [11] = RCAR_GP_PIN(4, 11), /* TSN0_RXC */
4093 [12] = RCAR_GP_PIN(4, 12), /* TSN0_TXC */
4094 [13] = RCAR_GP_PIN(4, 13), /* TSN0_RD1 */
4095 [14] = RCAR_GP_PIN(4, 14), /* TSN0_TD1 */
4096 [15] = RCAR_GP_PIN(4, 15), /* TSN0_TD0 */
4097 [16] = RCAR_GP_PIN(4, 16), /* TSN0_RD3 */
4098 [17] = RCAR_GP_PIN(4, 17), /* TSN0_RD2 */
4099 [18] = RCAR_GP_PIN(4, 18), /* TSN0_TD3 */
4100 [19] = RCAR_GP_PIN(4, 19), /* TSN0_TD2 */
4101 [20] = RCAR_GP_PIN(4, 20), /* TSN0_TXCREFCLK */
4102 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */
4103 [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */
4104 [23] = RCAR_GP_PIN(4, 23), /* AVS0 */
4105 [24] = RCAR_GP_PIN(4, 24), /* AVS1 */
4115 [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */
4116 [ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */
4117 [ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */
4118 [ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */
4119 [ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */
4120 [ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */
4121 [ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */
4122 [ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */
4123 [ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */
4124 [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */
4125 [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */
4126 [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */
4127 [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */
4128 [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */
4129 [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */
4130 [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */
4131 [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */
4132 [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */
4133 [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */
4134 [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */
4135 [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */
4149 [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */
4150 [ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */
4151 [ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */
4152 [ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */
4153 [ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */
4154 [ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */
4155 [ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */
4156 [ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */
4157 [ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */
4158 [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */
4159 [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */
4160 [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */
4161 [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */
4162 [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */
4163 [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/
4164 [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */
4165 [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */
4166 [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */
4167 [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */
4168 [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */
4169 [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */
4183 [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */
4184 [ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */
4185 [ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */
4186 [ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */
4187 [ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */
4188 [ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */
4189 [ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */
4190 [ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */
4191 [ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */
4192 [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */
4193 [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */
4194 [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */
4195 [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */
4196 [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */
4197 [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */
4198 [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */
4199 [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */
4200 [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */
4201 [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */
4202 [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */
4203 [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */
4217 [ 0] = RCAR_GP_PIN(8, 0), /* SCL0 */
4218 [ 1] = RCAR_GP_PIN(8, 1), /* SDA0 */
4219 [ 2] = RCAR_GP_PIN(8, 2), /* SCL1 */
4220 [ 3] = RCAR_GP_PIN(8, 3), /* SDA1 */
4221 [ 4] = RCAR_GP_PIN(8, 4), /* SCL2 */
4222 [ 5] = RCAR_GP_PIN(8, 5), /* SDA2 */
4223 [ 6] = RCAR_GP_PIN(8, 6), /* SCL3 */
4224 [ 7] = RCAR_GP_PIN(8, 7), /* SDA3 */
4225 [ 8] = RCAR_GP_PIN(8, 8), /* SCL4 */
4226 [ 9] = RCAR_GP_PIN(8, 9), /* SDA4 */
4227 [10] = RCAR_GP_PIN(8, 10), /* SCL5 */
4228 [11] = RCAR_GP_PIN(8, 11), /* SDA5 */
4229 [12] = RCAR_GP_PIN(8, 12), /* GP8_12 */
4230 [13] = RCAR_GP_PIN(8, 13), /* GP8_13 */