1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A779A0 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
8 */
9
10 #include <linux/errno.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13
14 #include "sh_pfc.h"
15
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
17
18 #define CPU_ALL_GP(fn, sfx) \
19 PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
20 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(1, 23, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_1(1, 24, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(1, 25, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(1, 26, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_1(1, 27, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(1, 28, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_20(2, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
29 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 16, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 17, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 18, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_1(3, 19, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_1(3, 20, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_1(3, 21, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_1(3, 22, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_1(3, 23, fn, sfx, CFG_FLAGS), \
40 PORT_GP_CFG_1(3, 24, fn, sfx, CFG_FLAGS), \
41 PORT_GP_CFG_1(3, 25, fn, sfx, CFG_FLAGS), \
42 PORT_GP_CFG_1(3, 26, fn, sfx, CFG_FLAGS), \
43 PORT_GP_CFG_1(3, 27, fn, sfx, CFG_FLAGS), \
44 PORT_GP_CFG_1(3, 28, fn, sfx, CFG_FLAGS), \
45 PORT_GP_CFG_1(3, 29, fn, sfx, CFG_FLAGS), \
46 PORT_GP_CFG_25(4, fn, sfx, CFG_FLAGS), \
47 PORT_GP_CFG_21(5, fn, sfx, CFG_FLAGS), \
48 PORT_GP_CFG_21(6, fn, sfx, CFG_FLAGS), \
49 PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \
50 PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
51
52 /* GPSR0 */
53 #define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)
54 #define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)
55 #define GPSR0_16 F_(MSIOF2_TXD, IP2SR0_3_0)
56 #define GPSR0_15 F_(MSIOF2_SYNC, IP1SR0_31_28)
57 #define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24)
58 #define GPSR0_13 F_(MSIOF2_SS2, IP1SR0_23_20)
59 #define GPSR0_12 F_(MSIOF5_RXD, IP1SR0_19_16)
60 #define GPSR0_11 F_(MSIOF5_SCK, IP1SR0_15_12)
61 #define GPSR0_10 F_(MSIOF5_TXD, IP1SR0_11_8)
62 #define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4)
63 #define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0)
64 #define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28)
65 #define GPSR0_6 F_(IRQ0, IP0SR0_27_24)
66 #define GPSR0_5 F_(IRQ1, IP0SR0_23_20)
67 #define GPSR0_4 F_(IRQ2, IP0SR0_19_16)
68 #define GPSR0_3 F_(IRQ3, IP0SR0_15_12)
69 #define GPSR0_2 F_(GP0_02, IP0SR0_11_8)
70 #define GPSR0_1 F_(GP0_01, IP0SR0_7_4)
71 #define GPSR0_0 F_(GP0_00, IP0SR0_3_0)
72
73 /* GPSR1 */
74 #define GPSR1_28 F_(HTX3, IP3SR1_19_16)
75 #define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12)
76 #define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8)
77 #define GPSR1_25 F_(HSCK3, IP3SR1_7_4)
78 #define GPSR1_24 F_(HRX3, IP3SR1_3_0)
79 #define GPSR1_23 F_(GP1_23, IP2SR1_31_28)
80 #define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24)
81 #define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20)
82 #define GPSR1_20 F_(SSI_SD, IP2SR1_19_16)
83 #define GPSR1_19 F_(SSI_WS, IP2SR1_15_12)
84 #define GPSR1_18 F_(SSI_SCK, IP2SR1_11_8)
85 #define GPSR1_17 F_(SCIF_CLK, IP2SR1_7_4)
86 #define GPSR1_16 F_(HRX0, IP2SR1_3_0)
87 #define GPSR1_15 F_(HSCK0, IP1SR1_31_28)
88 #define GPSR1_14 F_(HRTS0_N, IP1SR1_27_24)
89 #define GPSR1_13 F_(HCTS0_N, IP1SR1_23_20)
90 #define GPSR1_12 F_(HTX0, IP1SR1_19_16)
91 #define GPSR1_11 F_(MSIOF0_RXD, IP1SR1_15_12)
92 #define GPSR1_10 F_(MSIOF0_SCK, IP1SR1_11_8)
93 #define GPSR1_9 F_(MSIOF0_TXD, IP1SR1_7_4)
94 #define GPSR1_8 F_(MSIOF0_SYNC, IP1SR1_3_0)
95 #define GPSR1_7 F_(MSIOF0_SS1, IP0SR1_31_28)
96 #define GPSR1_6 F_(MSIOF0_SS2, IP0SR1_27_24)
97 #define GPSR1_5 F_(MSIOF1_RXD, IP0SR1_23_20)
98 #define GPSR1_4 F_(MSIOF1_TXD, IP0SR1_19_16)
99 #define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12)
100 #define GPSR1_2 F_(MSIOF1_SYNC, IP0SR1_11_8)
101 #define GPSR1_1 F_(MSIOF1_SS1, IP0SR1_7_4)
102 #define GPSR1_0 F_(MSIOF1_SS2, IP0SR1_3_0)
103
104 /* GPSR2 */
105 #define GPSR2_19 F_(CANFD7_RX, IP2SR2_15_12)
106 #define GPSR2_18 F_(CANFD7_TX, IP2SR2_11_8)
107 #define GPSR2_17 F_(CANFD4_RX, IP2SR2_7_4)
108 #define GPSR2_16 F_(CANFD4_TX, IP2SR2_3_0)
109 #define GPSR2_15 F_(CANFD3_RX, IP1SR2_31_28)
110 #define GPSR2_14 F_(CANFD3_TX, IP1SR2_27_24)
111 #define GPSR2_13 F_(CANFD2_RX, IP1SR2_23_20)
112 #define GPSR2_12 F_(CANFD2_TX, IP1SR2_19_16)
113 #define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12)
114 #define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8)
115 #define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4)
116 #define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0)
117 #define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28)
118 #define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24)
119 #define GPSR2_5 F_(FXR_TXENB_N, IP0SR2_23_20)
120 #define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16)
121 #define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12)
122 #define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8)
123 #define GPSR2_1 F_(FXR_TXENA_N, IP0SR2_7_4)
124 #define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0)
125
126 /* GPSR3 */
127 #define GPSR3_29 F_(RPC_INT_N, IP3SR3_23_20)
128 #define GPSR3_28 F_(RPC_WP_N, IP3SR3_19_16)
129 #define GPSR3_27 F_(RPC_RESET_N, IP3SR3_15_12)
130 #define GPSR3_26 F_(QSPI1_IO3, IP3SR3_11_8)
131 #define GPSR3_25 F_(QSPI1_SSL, IP3SR3_7_4)
132 #define GPSR3_24 F_(QSPI1_IO2, IP3SR3_3_0)
133 #define GPSR3_23 F_(QSPI1_MISO_IO1, IP2SR3_31_28)
134 #define GPSR3_22 F_(QSPI1_SPCLK, IP2SR3_27_24)
135 #define GPSR3_21 F_(QSPI1_MOSI_IO0, IP2SR3_23_20)
136 #define GPSR3_20 F_(QSPI0_SPCLK, IP2SR3_19_16)
137 #define GPSR3_19 F_(QSPI0_MOSI_IO0, IP2SR3_15_12)
138 #define GPSR3_18 F_(QSPI0_MISO_IO1, IP2SR3_11_8)
139 #define GPSR3_17 F_(QSPI0_IO2, IP2SR3_7_4)
140 #define GPSR3_16 F_(QSPI0_IO3, IP2SR3_3_0)
141 #define GPSR3_15 F_(QSPI0_SSL, IP1SR3_31_28)
142 #define GPSR3_14 F_(IPC_CLKOUT, IP1SR3_27_24)
143 #define GPSR3_13 F_(IPC_CLKIN, IP1SR3_23_20)
144 #define GPSR3_12 F_(SD_WP, IP1SR3_19_16)
145 #define GPSR3_11 F_(SD_CD, IP1SR3_15_12)
146 #define GPSR3_10 F_(MMC_SD_CMD, IP1SR3_11_8)
147 #define GPSR3_9 F_(MMC_D6, IP1SR3_7_4)
148 #define GPSR3_8 F_(MMC_D7, IP1SR3_3_0)
149 #define GPSR3_7 F_(MMC_D4, IP0SR3_31_28)
150 #define GPSR3_6 F_(MMC_D5, IP0SR3_27_24)
151 #define GPSR3_5 F_(MMC_SD_D3, IP0SR3_23_20)
152 #define GPSR3_4 F_(MMC_DS, IP0SR3_19_16)
153 #define GPSR3_3 F_(MMC_SD_CLK, IP0SR3_15_12)
154 #define GPSR3_2 F_(MMC_SD_D2, IP0SR3_11_8)
155 #define GPSR3_1 F_(MMC_SD_D0, IP0SR3_7_4)
156 #define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0)
157
158 /* GPSR4 */
159 #define GPSR4_24 F_(AVS1, IP3SR4_3_0)
160 #define GPSR4_23 F_(AVS0, IP2SR4_31_28)
161 #define GPSR4_22 F_(PCIE1_CLKREQ_N, IP2SR4_27_24)
162 #define GPSR4_21 F_(PCIE0_CLKREQ_N, IP2SR4_23_20)
163 #define GPSR4_20 F_(TSN0_TXCREFCLK, IP2SR4_19_16)
164 #define GPSR4_19 F_(TSN0_TD2, IP2SR4_15_12)
165 #define GPSR4_18 F_(TSN0_TD3, IP2SR4_11_8)
166 #define GPSR4_17 F_(TSN0_RD2, IP2SR4_7_4)
167 #define GPSR4_16 F_(TSN0_RD3, IP2SR4_3_0)
168 #define GPSR4_15 F_(TSN0_TD0, IP1SR4_31_28)
169 #define GPSR4_14 F_(TSN0_TD1, IP1SR4_27_24)
170 #define GPSR4_13 F_(TSN0_RD1, IP1SR4_23_20)
171 #define GPSR4_12 F_(TSN0_TXC, IP1SR4_19_16)
172 #define GPSR4_11 F_(TSN0_RXC, IP1SR4_15_12)
173 #define GPSR4_10 F_(TSN0_RD0, IP1SR4_11_8)
174 #define GPSR4_9 F_(TSN0_TX_CTL, IP1SR4_7_4)
175 #define GPSR4_8 F_(TSN0_AVTP_PPS0, IP1SR4_3_0)
176 #define GPSR4_7 F_(TSN0_RX_CTL, IP0SR4_31_28)
177 #define GPSR4_6 F_(TSN0_AVTP_CAPTURE, IP0SR4_27_24)
178 #define GPSR4_5 F_(TSN0_AVTP_MATCH, IP0SR4_23_20)
179 #define GPSR4_4 F_(TSN0_LINK, IP0SR4_19_16)
180 #define GPSR4_3 F_(TSN0_PHY_INT, IP0SR4_15_12)
181 #define GPSR4_2 F_(TSN0_AVTP_PPS1, IP0SR4_11_8)
182 #define GPSR4_1 F_(TSN0_MDC, IP0SR4_7_4)
183 #define GPSR4_0 F_(TSN0_MDIO, IP0SR4_3_0)
184
185 /* GPSR 5 */
186 #define GPSR5_20 F_(AVB2_RX_CTL, IP2SR5_19_16)
187 #define GPSR5_19 F_(AVB2_TX_CTL, IP2SR5_15_12)
188 #define GPSR5_18 F_(AVB2_RXC, IP2SR5_11_8)
189 #define GPSR5_17 F_(AVB2_RD0, IP2SR5_7_4)
190 #define GPSR5_16 F_(AVB2_TXC, IP2SR5_3_0)
191 #define GPSR5_15 F_(AVB2_TD0, IP1SR5_31_28)
192 #define GPSR5_14 F_(AVB2_RD1, IP1SR5_27_24)
193 #define GPSR5_13 F_(AVB2_RD2, IP1SR5_23_20)
194 #define GPSR5_12 F_(AVB2_TD1, IP1SR5_19_16)
195 #define GPSR5_11 F_(AVB2_TD2, IP1SR5_15_12)
196 #define GPSR5_10 F_(AVB2_MDIO, IP1SR5_11_8)
197 #define GPSR5_9 F_(AVB2_RD3, IP1SR5_7_4)
198 #define GPSR5_8 F_(AVB2_TD3, IP1SR5_3_0)
199 #define GPSR5_7 F_(AVB2_TXCREFCLK, IP0SR5_31_28)
200 #define GPSR5_6 F_(AVB2_MDC, IP0SR5_27_24)
201 #define GPSR5_5 F_(AVB2_MAGIC, IP0SR5_23_20)
202 #define GPSR5_4 F_(AVB2_PHY_INT, IP0SR5_19_16)
203 #define GPSR5_3 F_(AVB2_LINK, IP0SR5_15_12)
204 #define GPSR5_2 F_(AVB2_AVTP_MATCH, IP0SR5_11_8)
205 #define GPSR5_1 F_(AVB2_AVTP_CAPTURE, IP0SR5_7_4)
206 #define GPSR5_0 F_(AVB2_AVTP_PPS, IP0SR5_3_0)
207
208 /* GPSR 6 */
209 #define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16)
210 #define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12)
211 #define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8)
212 #define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4)
213 #define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0)
214 #define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28)
215 #define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24)
216 #define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20)
217 #define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16)
218 #define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12)
219 #define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8)
220 #define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4)
221 #define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0)
222 #define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28)
223 #define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24)
224 #define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20)
225 #define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16)
226 #define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12)
227 #define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8)
228 #define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4)
229 #define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0)
230
231 /* GPSR7 */
232 #define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16)
233 #define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12)
234 #define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8)
235 #define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4)
236 #define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0)
237 #define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28)
238 #define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24)
239 #define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20)
240 #define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16)
241 #define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12)
242 #define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8)
243 #define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4)
244 #define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0)
245 #define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28)
246 #define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24)
247 #define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20)
248 #define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16)
249 #define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12)
250 #define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8)
251 #define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)
252 #define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)
253
254 /* GPSR8 */
255 #define GPSR8_13 F_(GP8_13, IP1SR8_23_20)
256 #define GPSR8_12 F_(GP8_12, IP1SR8_19_16)
257 #define GPSR8_11 F_(SDA5, IP1SR8_15_12)
258 #define GPSR8_10 F_(SCL5, IP1SR8_11_8)
259 #define GPSR8_9 F_(SDA4, IP1SR8_7_4)
260 #define GPSR8_8 F_(SCL4, IP1SR8_3_0)
261 #define GPSR8_7 F_(SDA3, IP0SR8_31_28)
262 #define GPSR8_6 F_(SCL3, IP0SR8_27_24)
263 #define GPSR8_5 F_(SDA2, IP0SR8_23_20)
264 #define GPSR8_4 F_(SCL2, IP0SR8_19_16)
265 #define GPSR8_3 F_(SDA1, IP0SR8_15_12)
266 #define GPSR8_2 F_(SCL1, IP0SR8_11_8)
267 #define GPSR8_1 F_(SDA0, IP0SR8_7_4)
268 #define GPSR8_0 F_(SCL0, IP0SR8_3_0)
269
270 /* SR0 */
271 /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
272 #define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280
281 /* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
282 #define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290
291 /* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
292 #define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295
296 /* SR1 */
297 /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
298 #define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) FM(TX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_A) FM(RX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_A) FM(RTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) FM(TX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) FM(RX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306
307 /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
308 #define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_X) FM(CTS1_N_X) FM(CANFD5_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_X) FM(RTS1_N_X) FM(CANFD5_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316
317 /* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
318 #define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326
327 /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
328 #define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333
334 /* SR2 */
335 /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
336 #define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP0SR2_23_20 FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344
345 /* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
346 #define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354
355 /* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
356 #define IP2SR2_3_0 FM(CANFD4_TX) F_(0, 0) FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP2SR2_7_4 FM(CANFD4_RX) F_(0, 0) FM(PWM5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP2SR2_11_8 FM(CANFD7_TX) F_(0, 0) FM(PWM6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP2SR2_15_12 FM(CANFD7_RX) F_(0, 0) FM(PWM7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360
361 /* SR3 */
362 /* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
363 #define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371
372 /* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
373 #define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_N_A) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381
382 /* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
383 #define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 #define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385 #define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391
392 /* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
393 #define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399
400 /* SR4 */
401 /* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
402 #define IP0SR4_3_0 FM(TSN0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403 #define IP0SR4_7_4 FM(TSN0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 #define IP0SR4_11_8 FM(TSN0_AVTP_PPS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
405 #define IP0SR4_15_12 FM(TSN0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
406 #define IP0SR4_19_16 FM(TSN0_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
407 #define IP0SR4_23_20 FM(TSN0_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
408 #define IP0SR4_27_24 FM(TSN0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
409 #define IP0SR4_31_28 FM(TSN0_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410
411 /* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
412 #define IP1SR4_3_0 FM(TSN0_AVTP_PPS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
413 #define IP1SR4_7_4 FM(TSN0_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
414 #define IP1SR4_11_8 FM(TSN0_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
415 #define IP1SR4_15_12 FM(TSN0_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
416 #define IP1SR4_19_16 FM(TSN0_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
417 #define IP1SR4_23_20 FM(TSN0_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
418 #define IP1SR4_27_24 FM(TSN0_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
419 #define IP1SR4_31_28 FM(TSN0_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
420
421 /* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
422 #define IP2SR4_3_0 FM(TSN0_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
423 #define IP2SR4_7_4 FM(TSN0_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
424 #define IP2SR4_11_8 FM(TSN0_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
425 #define IP2SR4_15_12 FM(TSN0_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
426 #define IP2SR4_19_16 FM(TSN0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
427 #define IP2SR4_23_20 FM(PCIE0_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
428 #define IP2SR4_27_24 FM(PCIE1_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
429 #define IP2SR4_31_28 FM(AVS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
430
431 /* IP3SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
432 #define IP3SR4_3_0 FM(AVS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
433
434 /* SR5 */
435 /* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
436 #define IP0SR5_3_0 FM(AVB2_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
437 #define IP0SR5_7_4 FM(AVB2_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
438 #define IP0SR5_11_8 FM(AVB2_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
439 #define IP0SR5_15_12 FM(AVB2_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
440 #define IP0SR5_19_16 FM(AVB2_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
441 #define IP0SR5_23_20 FM(AVB2_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
442 #define IP0SR5_27_24 FM(AVB2_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
443 #define IP0SR5_31_28 FM(AVB2_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
444
445 /* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
446 #define IP1SR5_3_0 FM(AVB2_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
447 #define IP1SR5_7_4 FM(AVB2_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
448 #define IP1SR5_11_8 FM(AVB2_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
449 #define IP1SR5_15_12 FM(AVB2_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
450 #define IP1SR5_19_16 FM(AVB2_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
451 #define IP1SR5_23_20 FM(AVB2_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
452 #define IP1SR5_27_24 FM(AVB2_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
453 #define IP1SR5_31_28 FM(AVB2_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
454
455 /* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
456 #define IP2SR5_3_0 FM(AVB2_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
457 #define IP2SR5_7_4 FM(AVB2_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
458 #define IP2SR5_11_8 FM(AVB2_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
459 #define IP2SR5_15_12 FM(AVB2_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
460 #define IP2SR5_19_16 FM(AVB2_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
461
462 /* SR6 */
463 /* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
464 #define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
465 #define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
466 #define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
467 #define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
468 #define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
469 #define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
470 #define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
471 #define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
472
473 /* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
474 #define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
475 #define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
476 #define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
477 #define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
478 #define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
479 #define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
480 #define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
481 #define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
482
483 /* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
484 #define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
485 #define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
486 #define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
487 #define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
488 #define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
489
490 /* SR7 */
491 /* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
492 #define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
493 #define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
494 #define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
495 #define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
496 #define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
497 #define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
498 #define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
499 #define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
500
501 /* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
502 #define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
503 #define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
504 #define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
505 #define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
506 #define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
507 #define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
508 #define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
509 #define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
510
511 /* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
512 #define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
513 #define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
514 #define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
515 #define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
516 #define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
517
518 /* SR8 */
519 /* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
520 #define IP0SR8_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
521 #define IP0SR8_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
522 #define IP0SR8_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
523 #define IP0SR8_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
524 #define IP0SR8_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
525 #define IP0SR8_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
526 #define IP0SR8_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
527 #define IP0SR8_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
528
529 /* IP1SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
530 #define IP1SR8_3_0 FM(SCL4) FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
531 #define IP1SR8_7_4 FM(SDA4) FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
532 #define IP1SR8_11_8 FM(SCL5) FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
533 #define IP1SR8_15_12 FM(SDA5) FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
534 #define IP1SR8_19_16 F_(0, 0) FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
535 #define IP1SR8_23_20 F_(0, 0) FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
536
537 #define PINMUX_GPSR \
538 GPSR3_29 \
539 GPSR1_28 GPSR3_28 \
540 GPSR1_27 GPSR3_27 \
541 GPSR1_26 GPSR3_26 \
542 GPSR1_25 GPSR3_25 \
543 GPSR1_24 GPSR3_24 GPSR4_24 \
544 GPSR1_23 GPSR3_23 GPSR4_23 \
545 GPSR1_22 GPSR3_22 GPSR4_22 \
546 GPSR1_21 GPSR3_21 GPSR4_21 \
547 GPSR1_20 GPSR3_20 GPSR4_20 GPSR5_20 GPSR6_20 GPSR7_20 \
548 GPSR1_19 GPSR2_19 GPSR3_19 GPSR4_19 GPSR5_19 GPSR6_19 GPSR7_19 \
549 GPSR0_18 GPSR1_18 GPSR2_18 GPSR3_18 GPSR4_18 GPSR5_18 GPSR6_18 GPSR7_18 \
550 GPSR0_17 GPSR1_17 GPSR2_17 GPSR3_17 GPSR4_17 GPSR5_17 GPSR6_17 GPSR7_17 \
551 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 GPSR5_16 GPSR6_16 GPSR7_16 \
552 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 \
553 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 \
554 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 GPSR8_13 \
555 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 GPSR8_12 \
556 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 GPSR8_11 \
557 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 GPSR8_10 \
558 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 GPSR8_9 \
559 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 GPSR8_8 \
560 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 GPSR8_7 \
561 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 GPSR8_6 \
562 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 GPSR8_5 \
563 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 GPSR8_4 \
564 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 GPSR8_3 \
565 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 GPSR8_2 \
566 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 GPSR8_1 \
567 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0
568
569 #define PINMUX_IPSR \
570 \
571 FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \
572 FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \
573 FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \
574 FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 \
575 FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 \
576 FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \
577 FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \
578 FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \
579 \
580 FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \
581 FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \
582 FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \
583 FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
584 FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
585 FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 \
586 FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 \
587 FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \
588 \
589 FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \
590 FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
591 FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \
592 FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \
593 FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 \
594 FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 \
595 FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 \
596 FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 \
597 \
598 FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 FM(IP2SR3_3_0) IP2SR3_3_0 FM(IP3SR3_3_0) IP3SR3_3_0 \
599 FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 FM(IP2SR3_7_4) IP2SR3_7_4 FM(IP3SR3_7_4) IP3SR3_7_4 \
600 FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 FM(IP2SR3_11_8) IP2SR3_11_8 FM(IP3SR3_11_8) IP3SR3_11_8 \
601 FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 FM(IP2SR3_15_12) IP2SR3_15_12 FM(IP3SR3_15_12) IP3SR3_15_12 \
602 FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 FM(IP2SR3_19_16) IP2SR3_19_16 FM(IP3SR3_19_16) IP3SR3_19_16 \
603 FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 FM(IP2SR3_23_20) IP2SR3_23_20 FM(IP3SR3_23_20) IP3SR3_23_20 \
604 FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 \
605 FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 \
606 \
607 FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 FM(IP3SR4_3_0) IP3SR4_3_0 \
608 FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \
609 FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \
610 FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \
611 FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \
612 FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \
613 FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \
614 FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \
615 \
616 FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \
617 FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \
618 FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \
619 FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \
620 FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \
621 FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \
622 FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \
623 FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 \
624 \
625 FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \
626 FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \
627 FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \
628 FM(IP0SR6_15_12) IP0SR6_15_12 FM(IP1SR6_15_12) IP1SR6_15_12 FM(IP2SR6_15_12) IP2SR6_15_12 \
629 FM(IP0SR6_19_16) IP0SR6_19_16 FM(IP1SR6_19_16) IP1SR6_19_16 FM(IP2SR6_19_16) IP2SR6_19_16 \
630 FM(IP0SR6_23_20) IP0SR6_23_20 FM(IP1SR6_23_20) IP1SR6_23_20 \
631 FM(IP0SR6_27_24) IP0SR6_27_24 FM(IP1SR6_27_24) IP1SR6_27_24 \
632 FM(IP0SR6_31_28) IP0SR6_31_28 FM(IP1SR6_31_28) IP1SR6_31_28 \
633 \
634 FM(IP0SR7_3_0) IP0SR7_3_0 FM(IP1SR7_3_0) IP1SR7_3_0 FM(IP2SR7_3_0) IP2SR7_3_0 \
635 FM(IP0SR7_7_4) IP0SR7_7_4 FM(IP1SR7_7_4) IP1SR7_7_4 FM(IP2SR7_7_4) IP2SR7_7_4 \
636 FM(IP0SR7_11_8) IP0SR7_11_8 FM(IP1SR7_11_8) IP1SR7_11_8 FM(IP2SR7_11_8) IP2SR7_11_8 \
637 FM(IP0SR7_15_12) IP0SR7_15_12 FM(IP1SR7_15_12) IP1SR7_15_12 FM(IP2SR7_15_12) IP2SR7_15_12 \
638 FM(IP0SR7_19_16) IP0SR7_19_16 FM(IP1SR7_19_16) IP1SR7_19_16 FM(IP2SR7_19_16) IP2SR7_19_16 \
639 FM(IP0SR7_23_20) IP0SR7_23_20 FM(IP1SR7_23_20) IP1SR7_23_20 \
640 FM(IP0SR7_27_24) IP0SR7_27_24 FM(IP1SR7_27_24) IP1SR7_27_24 \
641 FM(IP0SR7_31_28) IP0SR7_31_28 FM(IP1SR7_31_28) IP1SR7_31_28 \
642 \
643 FM(IP0SR8_3_0) IP0SR8_3_0 FM(IP1SR8_3_0) IP1SR8_3_0 \
644 FM(IP0SR8_7_4) IP0SR8_7_4 FM(IP1SR8_7_4) IP1SR8_7_4 \
645 FM(IP0SR8_11_8) IP0SR8_11_8 FM(IP1SR8_11_8) IP1SR8_11_8 \
646 FM(IP0SR8_15_12) IP0SR8_15_12 FM(IP1SR8_15_12) IP1SR8_15_12 \
647 FM(IP0SR8_19_16) IP0SR8_19_16 FM(IP1SR8_19_16) IP1SR8_19_16 \
648 FM(IP0SR8_23_20) IP0SR8_23_20 FM(IP1SR8_23_20) IP1SR8_23_20 \
649 FM(IP0SR8_27_24) IP0SR8_27_24 \
650 FM(IP0SR8_31_28) IP0SR8_31_28
651
652 /* MOD_SEL8 */ /* 0 */ /* 1 */
653 #define MOD_SEL8_11 FM(SEL_SDA5_0) FM(SEL_SDA5_1)
654 #define MOD_SEL8_10 FM(SEL_SCL5_0) FM(SEL_SCL5_1)
655 #define MOD_SEL8_9 FM(SEL_SDA4_0) FM(SEL_SDA4_1)
656 #define MOD_SEL8_8 FM(SEL_SCL4_0) FM(SEL_SCL4_1)
657 #define MOD_SEL8_7 FM(SEL_SDA3_0) FM(SEL_SDA3_1)
658 #define MOD_SEL8_6 FM(SEL_SCL3_0) FM(SEL_SCL3_1)
659 #define MOD_SEL8_5 FM(SEL_SDA2_0) FM(SEL_SDA2_1)
660 #define MOD_SEL8_4 FM(SEL_SCL2_0) FM(SEL_SCL2_1)
661 #define MOD_SEL8_3 FM(SEL_SDA1_0) FM(SEL_SDA1_1)
662 #define MOD_SEL8_2 FM(SEL_SCL1_0) FM(SEL_SCL1_1)
663 #define MOD_SEL8_1 FM(SEL_SDA0_0) FM(SEL_SDA0_1)
664 #define MOD_SEL8_0 FM(SEL_SCL0_0) FM(SEL_SCL0_1)
665
666 #define PINMUX_MOD_SELS \
667 \
668 MOD_SEL8_11 \
669 MOD_SEL8_10 \
670 MOD_SEL8_9 \
671 MOD_SEL8_8 \
672 MOD_SEL8_7 \
673 MOD_SEL8_6 \
674 MOD_SEL8_5 \
675 MOD_SEL8_4 \
676 MOD_SEL8_3 \
677 MOD_SEL8_2 \
678 MOD_SEL8_1 \
679 MOD_SEL8_0
680
681 enum {
682 PINMUX_RESERVED = 0,
683
684 PINMUX_DATA_BEGIN,
685 GP_ALL(DATA),
686 PINMUX_DATA_END,
687
688 #define F_(x, y)
689 #define FM(x) FN_##x,
690 PINMUX_FUNCTION_BEGIN,
691 GP_ALL(FN),
692 PINMUX_GPSR
693 PINMUX_IPSR
694 PINMUX_MOD_SELS
695 PINMUX_FUNCTION_END,
696 #undef F_
697 #undef FM
698
699 #define F_(x, y)
700 #define FM(x) x##_MARK,
701 PINMUX_MARK_BEGIN,
702 PINMUX_GPSR
703 PINMUX_IPSR
704 PINMUX_MOD_SELS
705 PINMUX_MARK_END,
706 #undef F_
707 #undef FM
708 };
709
710 static const u16 pinmux_data[] = {
711 PINMUX_DATA_GP_ALL(),
712
713 /* IP0SR0 */
714 PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B),
715 PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_A),
716
717 PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1),
718
719 PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2),
720
721 PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3),
722 PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK),
723
724 PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2),
725 PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD),
726
727 PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1),
728 PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD),
729
730 PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0),
731 PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC),
732
733 PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2),
734
735 /* IP1SR0 */
736 PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF5_SS1),
737
738 PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF5_SYNC),
739
740 PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF5_TXD),
741
742 PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF5_SCK),
743
744 PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD),
745
746 PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2),
747 PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1),
748 PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_A),
749
750 PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1),
751 PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1),
752 PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1),
753
754 PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC),
755 PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1),
756 PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1),
757
758 /* IP2SR0 */
759 PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD),
760 PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N),
761 PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N),
762
763 PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK),
764 PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N),
765 PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N),
766
767 PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD),
768 PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1),
769 PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1),
770
771 /* IP0SR1 */
772 PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
773 PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_A),
774 PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3),
775
776 PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),
777 PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_A),
778 PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3),
779
780 PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),
781 PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_A),
782 PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N),
783
784 PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
785 PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_A),
786 PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N),
787
788 PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),
789 PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A),
790 PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3),
791
792 PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
793
794 PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),
795 PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_X),
796 PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_X),
797
798 PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),
799 PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_X),
800 PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_X),
801
802 /* IP1SR1 */
803 PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),
804 PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_X),
805 PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_X),
806 PINMUX_IPSR_GPSR(IP1SR1_3_0, CANFD5_TX_B),
807
808 PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),
809 PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_X),
810 PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_X),
811 PINMUX_IPSR_GPSR(IP1SR1_7_4, CANFD5_RX_B),
812
813 PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),
814 PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_X),
815 PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_X),
816
817 PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD),
818
819 PINMUX_IPSR_GPSR(IP1SR1_19_16, HTX0),
820 PINMUX_IPSR_GPSR(IP1SR1_19_16, TX0),
821
822 PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N),
823 PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N),
824 PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8_A),
825
826 PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N),
827 PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N),
828 PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9_A),
829
830 PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),
831 PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),
832 PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A),
833
834 /* IP2SR1 */
835 PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0),
836 PINMUX_IPSR_GPSR(IP2SR1_3_0, RX0),
837
838 PINMUX_IPSR_GPSR(IP2SR1_7_4, SCIF_CLK),
839 PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A),
840
841 PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK),
842 PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3),
843
844 PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS),
845 PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4),
846
847 PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD),
848 PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_A),
849
850 PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT),
851 PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_A),
852
853 PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN),
854 PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_A),
855
856 PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2),
857 PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1),
858 PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B),
859
860 /* IP3SR1 */
861 PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3),
862 PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A),
863 PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),
864
865 PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3),
866 PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A),
867 PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
868 PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_A),
869
870 PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N),
871 PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A),
872 PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
873 PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_A),
874
875 PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N),
876 PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
877 PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),
878
879 PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3),
880 PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A),
881 PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),
882
883 /* IP0SR2 */
884 PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA),
885 PINMUX_IPSR_GPSR(IP0SR2_3_0, CANFD1_TX),
886 PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_A),
887
888 PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N),
889 PINMUX_IPSR_GPSR(IP0SR2_7_4, CANFD1_RX),
890 PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_A),
891
892 PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR),
893 PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX),
894 PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5),
895
896 PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR),
897 PINMUX_IPSR_GPSR(IP0SR2_15_12, CANFD5_RX),
898 PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B),
899
900 PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR),
901
902 PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N),
903
904 PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB),
905
906 PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1),
907 PINMUX_IPSR_GPSR(IP0SR2_31_28, CANFD6_TX),
908 PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_B),
909
910 /* IP1SR2 */
911 PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0),
912 PINMUX_IPSR_GPSR(IP1SR2_3_0, CANFD6_RX),
913 PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_A),
914
915 PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK),
916 PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_X),
917
918 PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX),
919 PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_X),
920
921 PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX),
922 PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),
923
924 PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX),
925 PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2),
926 PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_A),
927
928 PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX),
929 PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3),
930 PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B),
931 PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_A),
932
933 PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),
934 PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2_B),
935
936 PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX),
937 PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B),
938
939 /* IP2SR2 */
940 PINMUX_IPSR_GPSR(IP2SR2_3_0, CANFD4_TX),
941 PINMUX_IPSR_GPSR(IP2SR2_3_0, PWM4),
942
943 PINMUX_IPSR_GPSR(IP2SR2_7_4, CANFD4_RX),
944 PINMUX_IPSR_GPSR(IP2SR2_7_4, PWM5),
945
946 PINMUX_IPSR_GPSR(IP2SR2_11_8, CANFD7_TX),
947 PINMUX_IPSR_GPSR(IP2SR2_11_8, PWM6),
948
949 PINMUX_IPSR_GPSR(IP2SR2_15_12, CANFD7_RX),
950 PINMUX_IPSR_GPSR(IP2SR2_15_12, PWM7),
951
952 /* IP0SR3 */
953 PINMUX_IPSR_GPSR(IP0SR3_3_0, MMC_SD_D1),
954 PINMUX_IPSR_GPSR(IP0SR3_7_4, MMC_SD_D0),
955 PINMUX_IPSR_GPSR(IP0SR3_11_8, MMC_SD_D2),
956 PINMUX_IPSR_GPSR(IP0SR3_15_12, MMC_SD_CLK),
957 PINMUX_IPSR_GPSR(IP0SR3_19_16, MMC_DS),
958 PINMUX_IPSR_GPSR(IP0SR3_23_20, MMC_SD_D3),
959 PINMUX_IPSR_GPSR(IP0SR3_27_24, MMC_D5),
960 PINMUX_IPSR_GPSR(IP0SR3_31_28, MMC_D4),
961
962 /* IP1SR3 */
963 PINMUX_IPSR_GPSR(IP1SR3_3_0, MMC_D7),
964
965 PINMUX_IPSR_GPSR(IP1SR3_7_4, MMC_D6),
966
967 PINMUX_IPSR_GPSR(IP1SR3_11_8, MMC_SD_CMD),
968
969 PINMUX_IPSR_GPSR(IP1SR3_15_12, SD_CD),
970
971 PINMUX_IPSR_GPSR(IP1SR3_19_16, SD_WP),
972
973 PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKIN),
974 PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKEN_IN),
975 PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A),
976 PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_X),
977
978 PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT),
979 PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKEN_OUT),
980 PINMUX_IPSR_GPSR(IP1SR3_27_24, ERROROUTC_N_A),
981 PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_X),
982
983 PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL),
984
985 /* IP2SR3 */
986 PINMUX_IPSR_GPSR(IP2SR3_3_0, QSPI0_IO3),
987 PINMUX_IPSR_GPSR(IP2SR3_7_4, QSPI0_IO2),
988 PINMUX_IPSR_GPSR(IP2SR3_11_8, QSPI0_MISO_IO1),
989 PINMUX_IPSR_GPSR(IP2SR3_15_12, QSPI0_MOSI_IO0),
990 PINMUX_IPSR_GPSR(IP2SR3_19_16, QSPI0_SPCLK),
991 PINMUX_IPSR_GPSR(IP2SR3_23_20, QSPI1_MOSI_IO0),
992 PINMUX_IPSR_GPSR(IP2SR3_27_24, QSPI1_SPCLK),
993 PINMUX_IPSR_GPSR(IP2SR3_31_28, QSPI1_MISO_IO1),
994
995 /* IP3SR3 */
996 PINMUX_IPSR_GPSR(IP3SR3_3_0, QSPI1_IO2),
997 PINMUX_IPSR_GPSR(IP3SR3_7_4, QSPI1_SSL),
998 PINMUX_IPSR_GPSR(IP3SR3_11_8, QSPI1_IO3),
999 PINMUX_IPSR_GPSR(IP3SR3_15_12, RPC_RESET_N),
1000 PINMUX_IPSR_GPSR(IP3SR3_19_16, RPC_WP_N),
1001 PINMUX_IPSR_GPSR(IP3SR3_23_20, RPC_INT_N),
1002
1003 /* IP0SR4 */
1004 PINMUX_IPSR_GPSR(IP0SR4_3_0, TSN0_MDIO),
1005 PINMUX_IPSR_GPSR(IP0SR4_7_4, TSN0_MDC),
1006 PINMUX_IPSR_GPSR(IP0SR4_11_8, TSN0_AVTP_PPS1),
1007 PINMUX_IPSR_GPSR(IP0SR4_15_12, TSN0_PHY_INT),
1008 PINMUX_IPSR_GPSR(IP0SR4_19_16, TSN0_LINK),
1009 PINMUX_IPSR_GPSR(IP0SR4_23_20, TSN0_AVTP_MATCH),
1010 PINMUX_IPSR_GPSR(IP0SR4_27_24, TSN0_AVTP_CAPTURE),
1011 PINMUX_IPSR_GPSR(IP0SR4_31_28, TSN0_RX_CTL),
1012
1013 /* IP1SR4 */
1014 PINMUX_IPSR_GPSR(IP1SR4_3_0, TSN0_AVTP_PPS0),
1015 PINMUX_IPSR_GPSR(IP1SR4_7_4, TSN0_TX_CTL),
1016 PINMUX_IPSR_GPSR(IP1SR4_11_8, TSN0_RD0),
1017 PINMUX_IPSR_GPSR(IP1SR4_15_12, TSN0_RXC),
1018 PINMUX_IPSR_GPSR(IP1SR4_19_16, TSN0_TXC),
1019 PINMUX_IPSR_GPSR(IP1SR4_23_20, TSN0_RD1),
1020 PINMUX_IPSR_GPSR(IP1SR4_27_24, TSN0_TD1),
1021 PINMUX_IPSR_GPSR(IP1SR4_31_28, TSN0_TD0),
1022
1023 /* IP2SR4 */
1024 PINMUX_IPSR_GPSR(IP2SR4_3_0, TSN0_RD3),
1025 PINMUX_IPSR_GPSR(IP2SR4_7_4, TSN0_RD2),
1026 PINMUX_IPSR_GPSR(IP2SR4_11_8, TSN0_TD3),
1027 PINMUX_IPSR_GPSR(IP2SR4_15_12, TSN0_TD2),
1028 PINMUX_IPSR_GPSR(IP2SR4_19_16, TSN0_TXCREFCLK),
1029 PINMUX_IPSR_GPSR(IP2SR4_23_20, PCIE0_CLKREQ_N),
1030 PINMUX_IPSR_GPSR(IP2SR4_27_24, PCIE1_CLKREQ_N),
1031 PINMUX_IPSR_GPSR(IP2SR4_31_28, AVS0),
1032
1033 /* IP3SR4 */
1034 PINMUX_IPSR_GPSR(IP3SR4_3_0, AVS1),
1035
1036 /* IP0SR5 */
1037 PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB2_AVTP_PPS),
1038 PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB2_AVTP_CAPTURE),
1039 PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB2_AVTP_MATCH),
1040 PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB2_LINK),
1041 PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB2_PHY_INT),
1042 PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB2_MAGIC),
1043 PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB2_MDC),
1044 PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB2_TXCREFCLK),
1045
1046 /* IP1SR5 */
1047 PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB2_TD3),
1048 PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB2_RD3),
1049 PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB2_MDIO),
1050 PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB2_TD2),
1051 PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB2_TD1),
1052 PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB2_RD2),
1053 PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB2_RD1),
1054 PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB2_TD0),
1055
1056 /* IP2SR5 */
1057 PINMUX_IPSR_GPSR(IP2SR5_3_0, AVB2_TXC),
1058 PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB2_RD0),
1059 PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB2_RXC),
1060 PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB2_TX_CTL),
1061 PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB2_RX_CTL),
1062
1063 /* IP0SR6 */
1064 PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO),
1065
1066 PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC),
1067
1068 PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC),
1069
1070 PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),
1071
1072 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),
1073 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),
1074
1075 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),
1076 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),
1077
1078 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),
1079 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),
1080
1081 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),
1082 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),
1083
1084 /* IP1SR6 */
1085 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),
1086 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC),
1087
1088 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),
1089 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),
1090
1091 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),
1092 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),
1093
1094 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),
1095 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),
1096
1097 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),
1098 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),
1099
1100 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),
1101 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),
1102
1103 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),
1104 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),
1105
1106 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0),
1107 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),
1108
1109 /* IP2SR6 */
1110 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),
1111 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),
1112
1113 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),
1114 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),
1115
1116 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),
1117 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),
1118
1119 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),
1120 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),
1121
1122 PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK),
1123
1124 /* IP0SR7 */
1125 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS),
1126 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL),
1127
1128 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE),
1129 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS),
1130
1131 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH),
1132 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER),
1133 PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT),
1134
1135 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3),
1136 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3),
1137
1138 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK),
1139 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER),
1140
1141 PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT),
1142
1143 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2),
1144 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2),
1145
1146 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1),
1147 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1),
1148
1149 /* IP1SR7 */
1150 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3),
1151 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3),
1152
1153 PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK),
1154
1155 PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC),
1156
1157 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0),
1158 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0),
1159
1160 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2),
1161 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2),
1162
1163 PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC),
1164
1165 PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO),
1166
1167 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC),
1168 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC),
1169
1170 /* IP2SR7 */
1171 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL),
1172 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN),
1173
1174 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1),
1175 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1),
1176
1177 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0),
1178 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0),
1179
1180 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC),
1181 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC),
1182
1183 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL),
1184 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV),
1185
1186 /* IP0SR8 */
1187 PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_0),
1188 PINMUX_IPSR_MSEL(IP0SR8_7_4, SDA0, SEL_SDA0_0),
1189 PINMUX_IPSR_MSEL(IP0SR8_11_8, SCL1, SEL_SCL1_0),
1190 PINMUX_IPSR_MSEL(IP0SR8_15_12, SDA1, SEL_SDA1_0),
1191 PINMUX_IPSR_MSEL(IP0SR8_19_16, SCL2, SEL_SCL2_0),
1192 PINMUX_IPSR_MSEL(IP0SR8_23_20, SDA2, SEL_SDA2_0),
1193 PINMUX_IPSR_MSEL(IP0SR8_27_24, SCL3, SEL_SCL3_0),
1194 PINMUX_IPSR_MSEL(IP0SR8_31_28, SDA3, SEL_SDA3_0),
1195
1196 /* IP1SR8 */
1197 PINMUX_IPSR_MSEL(IP1SR8_3_0, SCL4, SEL_SCL4_0),
1198 PINMUX_IPSR_MSEL(IP1SR8_3_0, HRX2, SEL_SCL4_0),
1199 PINMUX_IPSR_MSEL(IP1SR8_3_0, SCK4, SEL_SCL4_0),
1200
1201 PINMUX_IPSR_MSEL(IP1SR8_7_4, SDA4, SEL_SDA4_0),
1202 PINMUX_IPSR_MSEL(IP1SR8_7_4, HTX2, SEL_SDA4_0),
1203 PINMUX_IPSR_MSEL(IP1SR8_7_4, CTS4_N, SEL_SDA4_0),
1204
1205 PINMUX_IPSR_MSEL(IP1SR8_11_8, SCL5, SEL_SCL5_0),
1206 PINMUX_IPSR_MSEL(IP1SR8_11_8, HRTS2_N, SEL_SCL5_0),
1207 PINMUX_IPSR_MSEL(IP1SR8_11_8, RTS4_N, SEL_SCL5_0),
1208
1209 PINMUX_IPSR_MSEL(IP1SR8_15_12, SDA5, SEL_SDA5_0),
1210 PINMUX_IPSR_MSEL(IP1SR8_15_12, SCIF_CLK2, SEL_SDA5_0),
1211
1212 PINMUX_IPSR_GPSR(IP1SR8_19_16, HCTS2_N),
1213 PINMUX_IPSR_GPSR(IP1SR8_19_16, TX4),
1214
1215 PINMUX_IPSR_GPSR(IP1SR8_23_20, HSCK2),
1216 PINMUX_IPSR_GPSR(IP1SR8_23_20, RX4),
1217 };
1218
1219 /*
1220 * Pins not associated with a GPIO port.
1221 */
1222 enum {
1223 GP_ASSIGN_LAST(),
1224 };
1225
1226 static const struct sh_pfc_pin pinmux_pins[] = {
1227 PINMUX_GPIO_GP_ALL(),
1228 };
1229
1230 /* - AVB0 ------------------------------------------------ */
1231 static const unsigned int avb0_link_pins[] = {
1232 /* AVB0_LINK */
1233 RCAR_GP_PIN(7, 4),
1234 };
1235 static const unsigned int avb0_link_mux[] = {
1236 AVB0_LINK_MARK,
1237 };
1238 static const unsigned int avb0_magic_pins[] = {
1239 /* AVB0_MAGIC */
1240 RCAR_GP_PIN(7, 10),
1241 };
1242 static const unsigned int avb0_magic_mux[] = {
1243 AVB0_MAGIC_MARK,
1244 };
1245 static const unsigned int avb0_phy_int_pins[] = {
1246 /* AVB0_PHY_INT */
1247 RCAR_GP_PIN(7, 5),
1248 };
1249 static const unsigned int avb0_phy_int_mux[] = {
1250 AVB0_PHY_INT_MARK,
1251 };
1252 static const unsigned int avb0_mdio_pins[] = {
1253 /* AVB0_MDC, AVB0_MDIO */
1254 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1255 };
1256 static const unsigned int avb0_mdio_mux[] = {
1257 AVB0_MDC_MARK, AVB0_MDIO_MARK,
1258 };
1259 static const unsigned int avb0_rgmii_pins[] = {
1260 /*
1261 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
1262 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
1263 */
1264 RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),
1265 RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7),
1266 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3),
1267 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),
1268 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
1269 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8),
1270 };
1271 static const unsigned int avb0_rgmii_mux[] = {
1272 AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
1273 AVB0_TD0_MARK, AVB0_TD1_MARK,
1274 AVB0_TD2_MARK, AVB0_TD3_MARK,
1275 AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
1276 AVB0_RD0_MARK, AVB0_RD1_MARK,
1277 AVB0_RD2_MARK, AVB0_RD3_MARK,
1278 };
1279 static const unsigned int avb0_txcrefclk_pins[] = {
1280 /* AVB0_TXCREFCLK */
1281 RCAR_GP_PIN(7, 9),
1282 };
1283 static const unsigned int avb0_txcrefclk_mux[] = {
1284 AVB0_TXCREFCLK_MARK,
1285 };
1286 static const unsigned int avb0_avtp_pps_pins[] = {
1287 /* AVB0_AVTP_PPS */
1288 RCAR_GP_PIN(7, 0),
1289 };
1290 static const unsigned int avb0_avtp_pps_mux[] = {
1291 AVB0_AVTP_PPS_MARK,
1292 };
1293 static const unsigned int avb0_avtp_capture_pins[] = {
1294 /* AVB0_AVTP_CAPTURE */
1295 RCAR_GP_PIN(7, 1),
1296 };
1297 static const unsigned int avb0_avtp_capture_mux[] = {
1298 AVB0_AVTP_CAPTURE_MARK,
1299 };
1300 static const unsigned int avb0_avtp_match_pins[] = {
1301 /* AVB0_AVTP_MATCH */
1302 RCAR_GP_PIN(7, 2),
1303 };
1304 static const unsigned int avb0_avtp_match_mux[] = {
1305 AVB0_AVTP_MATCH_MARK,
1306 };
1307
1308 /* - AVB1 ------------------------------------------------ */
1309 static const unsigned int avb1_link_pins[] = {
1310 /* AVB1_LINK */
1311 RCAR_GP_PIN(6, 4),
1312 };
1313 static const unsigned int avb1_link_mux[] = {
1314 AVB1_LINK_MARK,
1315 };
1316 static const unsigned int avb1_magic_pins[] = {
1317 /* AVB1_MAGIC */
1318 RCAR_GP_PIN(6, 1),
1319 };
1320 static const unsigned int avb1_magic_mux[] = {
1321 AVB1_MAGIC_MARK,
1322 };
1323 static const unsigned int avb1_phy_int_pins[] = {
1324 /* AVB1_PHY_INT */
1325 RCAR_GP_PIN(6, 3),
1326 };
1327 static const unsigned int avb1_phy_int_mux[] = {
1328 AVB1_PHY_INT_MARK,
1329 };
1330 static const unsigned int avb1_mdio_pins[] = {
1331 /* AVB1_MDC, AVB1_MDIO */
1332 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
1333 };
1334 static const unsigned int avb1_mdio_mux[] = {
1335 AVB1_MDC_MARK, AVB1_MDIO_MARK,
1336 };
1337 static const unsigned int avb1_rgmii_pins[] = {
1338 /*
1339 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
1340 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
1341 */
1342 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1343 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),
1344 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),
1345 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8),
1346 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1347 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),
1348 };
1349 static const unsigned int avb1_rgmii_mux[] = {
1350 AVB1_TX_CTL_MARK, AVB1_TXC_MARK,
1351 AVB1_TD0_MARK, AVB1_TD1_MARK,
1352 AVB1_TD2_MARK, AVB1_TD3_MARK,
1353 AVB1_RX_CTL_MARK, AVB1_RXC_MARK,
1354 AVB1_RD0_MARK, AVB1_RD1_MARK,
1355 AVB1_RD2_MARK, AVB1_RD3_MARK,
1356 };
1357 static const unsigned int avb1_txcrefclk_pins[] = {
1358 /* AVB1_TXCREFCLK */
1359 RCAR_GP_PIN(6, 20),
1360 };
1361 static const unsigned int avb1_txcrefclk_mux[] = {
1362 AVB1_TXCREFCLK_MARK,
1363 };
1364 static const unsigned int avb1_avtp_pps_pins[] = {
1365 /* AVB1_AVTP_PPS */
1366 RCAR_GP_PIN(6, 10),
1367 };
1368 static const unsigned int avb1_avtp_pps_mux[] = {
1369 AVB1_AVTP_PPS_MARK,
1370 };
1371 static const unsigned int avb1_avtp_capture_pins[] = {
1372 /* AVB1_AVTP_CAPTURE */
1373 RCAR_GP_PIN(6, 11),
1374 };
1375 static const unsigned int avb1_avtp_capture_mux[] = {
1376 AVB1_AVTP_CAPTURE_MARK,
1377 };
1378 static const unsigned int avb1_avtp_match_pins[] = {
1379 /* AVB1_AVTP_MATCH */
1380 RCAR_GP_PIN(6, 5),
1381 };
1382 static const unsigned int avb1_avtp_match_mux[] = {
1383 AVB1_AVTP_MATCH_MARK,
1384 };
1385
1386 /* - AVB2 ------------------------------------------------ */
1387 static const unsigned int avb2_link_pins[] = {
1388 /* AVB2_LINK */
1389 RCAR_GP_PIN(5, 3),
1390 };
1391 static const unsigned int avb2_link_mux[] = {
1392 AVB2_LINK_MARK,
1393 };
1394 static const unsigned int avb2_magic_pins[] = {
1395 /* AVB2_MAGIC */
1396 RCAR_GP_PIN(5, 5),
1397 };
1398 static const unsigned int avb2_magic_mux[] = {
1399 AVB2_MAGIC_MARK,
1400 };
1401 static const unsigned int avb2_phy_int_pins[] = {
1402 /* AVB2_PHY_INT */
1403 RCAR_GP_PIN(5, 4),
1404 };
1405 static const unsigned int avb2_phy_int_mux[] = {
1406 AVB2_PHY_INT_MARK,
1407 };
1408 static const unsigned int avb2_mdio_pins[] = {
1409 /* AVB2_MDC, AVB2_MDIO */
1410 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),
1411 };
1412 static const unsigned int avb2_mdio_mux[] = {
1413 AVB2_MDC_MARK, AVB2_MDIO_MARK,
1414 };
1415 static const unsigned int avb2_rgmii_pins[] = {
1416 /*
1417 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
1418 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
1419 */
1420 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),
1421 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),
1422 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8),
1423 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),
1424 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),
1425 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9),
1426 };
1427 static const unsigned int avb2_rgmii_mux[] = {
1428 AVB2_TX_CTL_MARK, AVB2_TXC_MARK,
1429 AVB2_TD0_MARK, AVB2_TD1_MARK,
1430 AVB2_TD2_MARK, AVB2_TD3_MARK,
1431 AVB2_RX_CTL_MARK, AVB2_RXC_MARK,
1432 AVB2_RD0_MARK, AVB2_RD1_MARK,
1433 AVB2_RD2_MARK, AVB2_RD3_MARK,
1434 };
1435 static const unsigned int avb2_txcrefclk_pins[] = {
1436 /* AVB2_TXCREFCLK */
1437 RCAR_GP_PIN(5, 7),
1438 };
1439 static const unsigned int avb2_txcrefclk_mux[] = {
1440 AVB2_TXCREFCLK_MARK,
1441 };
1442 static const unsigned int avb2_avtp_pps_pins[] = {
1443 /* AVB2_AVTP_PPS */
1444 RCAR_GP_PIN(5, 0),
1445 };
1446 static const unsigned int avb2_avtp_pps_mux[] = {
1447 AVB2_AVTP_PPS_MARK,
1448 };
1449 static const unsigned int avb2_avtp_capture_pins[] = {
1450 /* AVB2_AVTP_CAPTURE */
1451 RCAR_GP_PIN(5, 1),
1452 };
1453 static const unsigned int avb2_avtp_capture_mux[] = {
1454 AVB2_AVTP_CAPTURE_MARK,
1455 };
1456 static const unsigned int avb2_avtp_match_pins[] = {
1457 /* AVB2_AVTP_MATCH */
1458 RCAR_GP_PIN(5, 2),
1459 };
1460 static const unsigned int avb2_avtp_match_mux[] = {
1461 AVB2_AVTP_MATCH_MARK,
1462 };
1463
1464 /* - CANFD0 ----------------------------------------------------------------- */
1465 static const unsigned int canfd0_data_pins[] = {
1466 /* CANFD0_TX, CANFD0_RX */
1467 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1468 };
1469 static const unsigned int canfd0_data_mux[] = {
1470 CANFD0_TX_MARK, CANFD0_RX_MARK,
1471 };
1472
1473 /* - CANFD1 ----------------------------------------------------------------- */
1474 static const unsigned int canfd1_data_pins[] = {
1475 /* CANFD1_TX, CANFD1_RX */
1476 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1477 };
1478 static const unsigned int canfd1_data_mux[] = {
1479 CANFD1_TX_MARK, CANFD1_RX_MARK,
1480 };
1481
1482 /* - CANFD2 ----------------------------------------------------------------- */
1483 static const unsigned int canfd2_data_pins[] = {
1484 /* CANFD2_TX, CANFD2_RX */
1485 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1486 };
1487 static const unsigned int canfd2_data_mux[] = {
1488 CANFD2_TX_MARK, CANFD2_RX_MARK,
1489 };
1490
1491 /* - CANFD3 ----------------------------------------------------------------- */
1492 static const unsigned int canfd3_data_pins[] = {
1493 /* CANFD3_TX, CANFD3_RX */
1494 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1495 };
1496 static const unsigned int canfd3_data_mux[] = {
1497 CANFD3_TX_MARK, CANFD3_RX_MARK,
1498 };
1499
1500 /* - CANFD4 ----------------------------------------------------------------- */
1501 static const unsigned int canfd4_data_pins[] = {
1502 /* CANFD4_TX, CANFD4_RX */
1503 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1504 };
1505 static const unsigned int canfd4_data_mux[] = {
1506 CANFD4_TX_MARK, CANFD4_RX_MARK,
1507 };
1508
1509 /* - CANFD5 ----------------------------------------------------------------- */
1510 static const unsigned int canfd5_data_pins[] = {
1511 /* CANFD5_TX, CANFD5_RX */
1512 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1513 };
1514 static const unsigned int canfd5_data_mux[] = {
1515 CANFD5_TX_MARK, CANFD5_RX_MARK,
1516 };
1517
1518 /* - CANFD5_B ----------------------------------------------------------------- */
1519 static const unsigned int canfd5_data_b_pins[] = {
1520 /* CANFD5_TX_B, CANFD5_RX_B */
1521 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1522 };
1523 static const unsigned int canfd5_data_b_mux[] = {
1524 CANFD5_TX_B_MARK, CANFD5_RX_B_MARK,
1525 };
1526
1527 /* - CANFD6 ----------------------------------------------------------------- */
1528 static const unsigned int canfd6_data_pins[] = {
1529 /* CANFD6_TX, CANFD6_RX */
1530 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1531 };
1532 static const unsigned int canfd6_data_mux[] = {
1533 CANFD6_TX_MARK, CANFD6_RX_MARK,
1534 };
1535
1536 /* - CANFD7 ----------------------------------------------------------------- */
1537 static const unsigned int canfd7_data_pins[] = {
1538 /* CANFD7_TX, CANFD7_RX */
1539 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1540 };
1541 static const unsigned int canfd7_data_mux[] = {
1542 CANFD7_TX_MARK, CANFD7_RX_MARK,
1543 };
1544
1545 /* - CANFD Clock ------------------------------------------------------------ */
1546 static const unsigned int can_clk_pins[] = {
1547 /* CAN_CLK */
1548 RCAR_GP_PIN(2, 9),
1549 };
1550 static const unsigned int can_clk_mux[] = {
1551 CAN_CLK_MARK,
1552 };
1553
1554 /* - HSCIF0 ----------------------------------------------------------------- */
1555 static const unsigned int hscif0_data_pins[] = {
1556 /* HRX0, HTX0 */
1557 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
1558 };
1559 static const unsigned int hscif0_data_mux[] = {
1560 HRX0_MARK, HTX0_MARK,
1561 };
1562 static const unsigned int hscif0_clk_pins[] = {
1563 /* HSCK0 */
1564 RCAR_GP_PIN(1, 15),
1565 };
1566 static const unsigned int hscif0_clk_mux[] = {
1567 HSCK0_MARK,
1568 };
1569 static const unsigned int hscif0_ctrl_pins[] = {
1570 /* HRTS0_N, HCTS0_N */
1571 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1572 };
1573 static const unsigned int hscif0_ctrl_mux[] = {
1574 HRTS0_N_MARK, HCTS0_N_MARK,
1575 };
1576
1577 /* - HSCIF1 ----------------------------------------------------------------- */
1578 static const unsigned int hscif1_data_pins[] = {
1579 /* HRX1, HTX1 */
1580 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1581 };
1582 static const unsigned int hscif1_data_mux[] = {
1583 HRX1_MARK, HTX1_MARK,
1584 };
1585 static const unsigned int hscif1_clk_pins[] = {
1586 /* HSCK1 */
1587 RCAR_GP_PIN(0, 18),
1588 };
1589 static const unsigned int hscif1_clk_mux[] = {
1590 HSCK1_MARK,
1591 };
1592 static const unsigned int hscif1_ctrl_pins[] = {
1593 /* HRTS1_N, HCTS1_N */
1594 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
1595 };
1596 static const unsigned int hscif1_ctrl_mux[] = {
1597 HRTS1_N_MARK, HCTS1_N_MARK,
1598 };
1599
1600 /* - HSCIF1_X---------------------------------------------------------------- */
1601 static const unsigned int hscif1_data_x_pins[] = {
1602 /* HRX1_X, HTX1_X */
1603 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1604 };
1605 static const unsigned int hscif1_data_x_mux[] = {
1606 HRX1_X_MARK, HTX1_X_MARK,
1607 };
1608 static const unsigned int hscif1_clk_x_pins[] = {
1609 /* HSCK1_X */
1610 RCAR_GP_PIN(1, 10),
1611 };
1612 static const unsigned int hscif1_clk_x_mux[] = {
1613 HSCK1_X_MARK,
1614 };
1615 static const unsigned int hscif1_ctrl_x_pins[] = {
1616 /* HRTS1_N_X, HCTS1_N_X */
1617 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1618 };
1619 static const unsigned int hscif1_ctrl_x_mux[] = {
1620 HRTS1_N_X_MARK, HCTS1_N_X_MARK,
1621 };
1622
1623 /* - HSCIF2 ----------------------------------------------------------------- */
1624 static const unsigned int hscif2_data_pins[] = {
1625 /* HRX2, HTX2 */
1626 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1627 };
1628 static const unsigned int hscif2_data_mux[] = {
1629 HRX2_MARK, HTX2_MARK,
1630 };
1631 static const unsigned int hscif2_clk_pins[] = {
1632 /* HSCK2 */
1633 RCAR_GP_PIN(8, 13),
1634 };
1635 static const unsigned int hscif2_clk_mux[] = {
1636 HSCK2_MARK,
1637 };
1638 static const unsigned int hscif2_ctrl_pins[] = {
1639 /* HRTS2_N, HCTS2_N */
1640 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12),
1641 };
1642 static const unsigned int hscif2_ctrl_mux[] = {
1643 HRTS2_N_MARK, HCTS2_N_MARK,
1644 };
1645
1646 /* - HSCIF3 ----------------------------------------------------------------- */
1647 static const unsigned int hscif3_data_pins[] = {
1648 /* HRX3, HTX3 */
1649 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
1650 };
1651 static const unsigned int hscif3_data_mux[] = {
1652 HRX3_MARK, HTX3_MARK,
1653 };
1654 static const unsigned int hscif3_clk_pins[] = {
1655 /* HSCK3 */
1656 RCAR_GP_PIN(1, 25),
1657 };
1658 static const unsigned int hscif3_clk_mux[] = {
1659 HSCK3_MARK,
1660 };
1661 static const unsigned int hscif3_ctrl_pins[] = {
1662 /* HRTS3_N, HCTS3_N */
1663 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1664 };
1665 static const unsigned int hscif3_ctrl_mux[] = {
1666 HRTS3_N_MARK, HCTS3_N_MARK,
1667 };
1668
1669 /* - HSCIF3_A ----------------------------------------------------------------- */
1670 static const unsigned int hscif3_data_a_pins[] = {
1671 /* HRX3_A, HTX3_A */
1672 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1673 };
1674 static const unsigned int hscif3_data_a_mux[] = {
1675 HRX3_A_MARK, HTX3_A_MARK,
1676 };
1677 static const unsigned int hscif3_clk_a_pins[] = {
1678 /* HSCK3_A */
1679 RCAR_GP_PIN(1, 3),
1680 };
1681 static const unsigned int hscif3_clk_a_mux[] = {
1682 HSCK3_A_MARK,
1683 };
1684 static const unsigned int hscif3_ctrl_a_pins[] = {
1685 /* HRTS3_N_A, HCTS3_N_A */
1686 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1687 };
1688 static const unsigned int hscif3_ctrl_a_mux[] = {
1689 HRTS3_N_A_MARK, HCTS3_N_A_MARK,
1690 };
1691
1692 /* - I2C0 ------------------------------------------------------------------- */
1693 static const unsigned int i2c0_pins[] = {
1694 /* SDA0, SCL0 */
1695 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0),
1696 };
1697 static const unsigned int i2c0_mux[] = {
1698 SDA0_MARK, SCL0_MARK,
1699 };
1700
1701 /* - I2C1 ------------------------------------------------------------------- */
1702 static const unsigned int i2c1_pins[] = {
1703 /* SDA1, SCL1 */
1704 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2),
1705 };
1706 static const unsigned int i2c1_mux[] = {
1707 SDA1_MARK, SCL1_MARK,
1708 };
1709
1710 /* - I2C2 ------------------------------------------------------------------- */
1711 static const unsigned int i2c2_pins[] = {
1712 /* SDA2, SCL2 */
1713 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4),
1714 };
1715 static const unsigned int i2c2_mux[] = {
1716 SDA2_MARK, SCL2_MARK,
1717 };
1718
1719 /* - I2C3 ------------------------------------------------------------------- */
1720 static const unsigned int i2c3_pins[] = {
1721 /* SDA3, SCL3 */
1722 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6),
1723 };
1724 static const unsigned int i2c3_mux[] = {
1725 SDA3_MARK, SCL3_MARK,
1726 };
1727
1728 /* - I2C4 ------------------------------------------------------------------- */
1729 static const unsigned int i2c4_pins[] = {
1730 /* SDA4, SCL4 */
1731 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8),
1732 };
1733 static const unsigned int i2c4_mux[] = {
1734 SDA4_MARK, SCL4_MARK,
1735 };
1736
1737 /* - I2C5 ------------------------------------------------------------------- */
1738 static const unsigned int i2c5_pins[] = {
1739 /* SDA5, SCL5 */
1740 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10),
1741 };
1742 static const unsigned int i2c5_mux[] = {
1743 SDA5_MARK, SCL5_MARK,
1744 };
1745
1746 /* - MMC -------------------------------------------------------------------- */
1747 static const unsigned int mmc_data_pins[] = {
1748 /* MMC_SD_D[0:3], MMC_D[4:7] */
1749 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1750 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),
1751 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),
1752 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1753 };
1754 static const unsigned int mmc_data_mux[] = {
1755 MMC_SD_D0_MARK, MMC_SD_D1_MARK,
1756 MMC_SD_D2_MARK, MMC_SD_D3_MARK,
1757 MMC_D4_MARK, MMC_D5_MARK,
1758 MMC_D6_MARK, MMC_D7_MARK,
1759 };
1760 static const unsigned int mmc_ctrl_pins[] = {
1761 /* MMC_SD_CLK, MMC_SD_CMD */
1762 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),
1763 };
1764 static const unsigned int mmc_ctrl_mux[] = {
1765 MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
1766 };
1767 static const unsigned int mmc_cd_pins[] = {
1768 /* SD_CD */
1769 RCAR_GP_PIN(3, 11),
1770 };
1771 static const unsigned int mmc_cd_mux[] = {
1772 SD_CD_MARK,
1773 };
1774 static const unsigned int mmc_wp_pins[] = {
1775 /* SD_WP */
1776 RCAR_GP_PIN(3, 12),
1777 };
1778 static const unsigned int mmc_wp_mux[] = {
1779 SD_WP_MARK,
1780 };
1781 static const unsigned int mmc_ds_pins[] = {
1782 /* MMC_DS */
1783 RCAR_GP_PIN(3, 4),
1784 };
1785 static const unsigned int mmc_ds_mux[] = {
1786 MMC_DS_MARK,
1787 };
1788
1789 /* - MSIOF0 ----------------------------------------------------------------- */
1790 static const unsigned int msiof0_clk_pins[] = {
1791 /* MSIOF0_SCK */
1792 RCAR_GP_PIN(1, 10),
1793 };
1794 static const unsigned int msiof0_clk_mux[] = {
1795 MSIOF0_SCK_MARK,
1796 };
1797 static const unsigned int msiof0_sync_pins[] = {
1798 /* MSIOF0_SYNC */
1799 RCAR_GP_PIN(1, 8),
1800 };
1801 static const unsigned int msiof0_sync_mux[] = {
1802 MSIOF0_SYNC_MARK,
1803 };
1804 static const unsigned int msiof0_ss1_pins[] = {
1805 /* MSIOF0_SS1 */
1806 RCAR_GP_PIN(1, 7),
1807 };
1808 static const unsigned int msiof0_ss1_mux[] = {
1809 MSIOF0_SS1_MARK,
1810 };
1811 static const unsigned int msiof0_ss2_pins[] = {
1812 /* MSIOF0_SS2 */
1813 RCAR_GP_PIN(1, 6),
1814 };
1815 static const unsigned int msiof0_ss2_mux[] = {
1816 MSIOF0_SS2_MARK,
1817 };
1818 static const unsigned int msiof0_txd_pins[] = {
1819 /* MSIOF0_TXD */
1820 RCAR_GP_PIN(1, 9),
1821 };
1822 static const unsigned int msiof0_txd_mux[] = {
1823 MSIOF0_TXD_MARK,
1824 };
1825 static const unsigned int msiof0_rxd_pins[] = {
1826 /* MSIOF0_RXD */
1827 RCAR_GP_PIN(1, 11),
1828 };
1829 static const unsigned int msiof0_rxd_mux[] = {
1830 MSIOF0_RXD_MARK,
1831 };
1832
1833 /* - MSIOF1 ----------------------------------------------------------------- */
1834 static const unsigned int msiof1_clk_pins[] = {
1835 /* MSIOF1_SCK */
1836 RCAR_GP_PIN(1, 3),
1837 };
1838 static const unsigned int msiof1_clk_mux[] = {
1839 MSIOF1_SCK_MARK,
1840 };
1841 static const unsigned int msiof1_sync_pins[] = {
1842 /* MSIOF1_SYNC */
1843 RCAR_GP_PIN(1, 2),
1844 };
1845 static const unsigned int msiof1_sync_mux[] = {
1846 MSIOF1_SYNC_MARK,
1847 };
1848 static const unsigned int msiof1_ss1_pins[] = {
1849 /* MSIOF1_SS1 */
1850 RCAR_GP_PIN(1, 1),
1851 };
1852 static const unsigned int msiof1_ss1_mux[] = {
1853 MSIOF1_SS1_MARK,
1854 };
1855 static const unsigned int msiof1_ss2_pins[] = {
1856 /* MSIOF1_SS2 */
1857 RCAR_GP_PIN(1, 0),
1858 };
1859 static const unsigned int msiof1_ss2_mux[] = {
1860 MSIOF1_SS2_MARK,
1861 };
1862 static const unsigned int msiof1_txd_pins[] = {
1863 /* MSIOF1_TXD */
1864 RCAR_GP_PIN(1, 4),
1865 };
1866 static const unsigned int msiof1_txd_mux[] = {
1867 MSIOF1_TXD_MARK,
1868 };
1869 static const unsigned int msiof1_rxd_pins[] = {
1870 /* MSIOF1_RXD */
1871 RCAR_GP_PIN(1, 5),
1872 };
1873 static const unsigned int msiof1_rxd_mux[] = {
1874 MSIOF1_RXD_MARK,
1875 };
1876
1877 /* - MSIOF2 ----------------------------------------------------------------- */
1878 static const unsigned int msiof2_clk_pins[] = {
1879 /* MSIOF2_SCK */
1880 RCAR_GP_PIN(0, 17),
1881 };
1882 static const unsigned int msiof2_clk_mux[] = {
1883 MSIOF2_SCK_MARK,
1884 };
1885 static const unsigned int msiof2_sync_pins[] = {
1886 /* MSIOF2_SYNC */
1887 RCAR_GP_PIN(0, 15),
1888 };
1889 static const unsigned int msiof2_sync_mux[] = {
1890 MSIOF2_SYNC_MARK,
1891 };
1892 static const unsigned int msiof2_ss1_pins[] = {
1893 /* MSIOF2_SS1 */
1894 RCAR_GP_PIN(0, 14),
1895 };
1896 static const unsigned int msiof2_ss1_mux[] = {
1897 MSIOF2_SS1_MARK,
1898 };
1899 static const unsigned int msiof2_ss2_pins[] = {
1900 /* MSIOF2_SS2 */
1901 RCAR_GP_PIN(0, 13),
1902 };
1903 static const unsigned int msiof2_ss2_mux[] = {
1904 MSIOF2_SS2_MARK,
1905 };
1906 static const unsigned int msiof2_txd_pins[] = {
1907 /* MSIOF2_TXD */
1908 RCAR_GP_PIN(0, 16),
1909 };
1910 static const unsigned int msiof2_txd_mux[] = {
1911 MSIOF2_TXD_MARK,
1912 };
1913 static const unsigned int msiof2_rxd_pins[] = {
1914 /* MSIOF2_RXD */
1915 RCAR_GP_PIN(0, 18),
1916 };
1917 static const unsigned int msiof2_rxd_mux[] = {
1918 MSIOF2_RXD_MARK,
1919 };
1920
1921 /* - MSIOF3 ----------------------------------------------------------------- */
1922 static const unsigned int msiof3_clk_pins[] = {
1923 /* MSIOF3_SCK */
1924 RCAR_GP_PIN(0, 3),
1925 };
1926 static const unsigned int msiof3_clk_mux[] = {
1927 MSIOF3_SCK_MARK,
1928 };
1929 static const unsigned int msiof3_sync_pins[] = {
1930 /* MSIOF3_SYNC */
1931 RCAR_GP_PIN(0, 6),
1932 };
1933 static const unsigned int msiof3_sync_mux[] = {
1934 MSIOF3_SYNC_MARK,
1935 };
1936 static const unsigned int msiof3_ss1_pins[] = {
1937 /* MSIOF3_SS1 */
1938 RCAR_GP_PIN(0, 1),
1939 };
1940 static const unsigned int msiof3_ss1_mux[] = {
1941 MSIOF3_SS1_MARK,
1942 };
1943 static const unsigned int msiof3_ss2_pins[] = {
1944 /* MSIOF3_SS2 */
1945 RCAR_GP_PIN(0, 2),
1946 };
1947 static const unsigned int msiof3_ss2_mux[] = {
1948 MSIOF3_SS2_MARK,
1949 };
1950 static const unsigned int msiof3_txd_pins[] = {
1951 /* MSIOF3_TXD */
1952 RCAR_GP_PIN(0, 4),
1953 };
1954 static const unsigned int msiof3_txd_mux[] = {
1955 MSIOF3_TXD_MARK,
1956 };
1957 static const unsigned int msiof3_rxd_pins[] = {
1958 /* MSIOF3_RXD */
1959 RCAR_GP_PIN(0, 5),
1960 };
1961 static const unsigned int msiof3_rxd_mux[] = {
1962 MSIOF3_RXD_MARK,
1963 };
1964
1965 /* - MSIOF4 ----------------------------------------------------------------- */
1966 static const unsigned int msiof4_clk_pins[] = {
1967 /* MSIOF4_SCK */
1968 RCAR_GP_PIN(1, 25),
1969 };
1970 static const unsigned int msiof4_clk_mux[] = {
1971 MSIOF4_SCK_MARK,
1972 };
1973 static const unsigned int msiof4_sync_pins[] = {
1974 /* MSIOF4_SYNC */
1975 RCAR_GP_PIN(1, 28),
1976 };
1977 static const unsigned int msiof4_sync_mux[] = {
1978 MSIOF4_SYNC_MARK,
1979 };
1980 static const unsigned int msiof4_ss1_pins[] = {
1981 /* MSIOF4_SS1 */
1982 RCAR_GP_PIN(1, 23),
1983 };
1984 static const unsigned int msiof4_ss1_mux[] = {
1985 MSIOF4_SS1_MARK,
1986 };
1987 static const unsigned int msiof4_ss2_pins[] = {
1988 /* MSIOF4_SS2 */
1989 RCAR_GP_PIN(1, 24),
1990 };
1991 static const unsigned int msiof4_ss2_mux[] = {
1992 MSIOF4_SS2_MARK,
1993 };
1994 static const unsigned int msiof4_txd_pins[] = {
1995 /* MSIOF4_TXD */
1996 RCAR_GP_PIN(1, 26),
1997 };
1998 static const unsigned int msiof4_txd_mux[] = {
1999 MSIOF4_TXD_MARK,
2000 };
2001 static const unsigned int msiof4_rxd_pins[] = {
2002 /* MSIOF4_RXD */
2003 RCAR_GP_PIN(1, 27),
2004 };
2005 static const unsigned int msiof4_rxd_mux[] = {
2006 MSIOF4_RXD_MARK,
2007 };
2008
2009 /* - MSIOF5 ----------------------------------------------------------------- */
2010 static const unsigned int msiof5_clk_pins[] = {
2011 /* MSIOF5_SCK */
2012 RCAR_GP_PIN(0, 11),
2013 };
2014 static const unsigned int msiof5_clk_mux[] = {
2015 MSIOF5_SCK_MARK,
2016 };
2017 static const unsigned int msiof5_sync_pins[] = {
2018 /* MSIOF5_SYNC */
2019 RCAR_GP_PIN(0, 9),
2020 };
2021 static const unsigned int msiof5_sync_mux[] = {
2022 MSIOF5_SYNC_MARK,
2023 };
2024 static const unsigned int msiof5_ss1_pins[] = {
2025 /* MSIOF5_SS1 */
2026 RCAR_GP_PIN(0, 8),
2027 };
2028 static const unsigned int msiof5_ss1_mux[] = {
2029 MSIOF5_SS1_MARK,
2030 };
2031 static const unsigned int msiof5_ss2_pins[] = {
2032 /* MSIOF5_SS2 */
2033 RCAR_GP_PIN(0, 7),
2034 };
2035 static const unsigned int msiof5_ss2_mux[] = {
2036 MSIOF5_SS2_MARK,
2037 };
2038 static const unsigned int msiof5_txd_pins[] = {
2039 /* MSIOF5_TXD */
2040 RCAR_GP_PIN(0, 10),
2041 };
2042 static const unsigned int msiof5_txd_mux[] = {
2043 MSIOF5_TXD_MARK,
2044 };
2045 static const unsigned int msiof5_rxd_pins[] = {
2046 /* MSIOF5_RXD */
2047 RCAR_GP_PIN(0, 12),
2048 };
2049 static const unsigned int msiof5_rxd_mux[] = {
2050 MSIOF5_RXD_MARK,
2051 };
2052
2053 /* - PCIE ------------------------------------------------------------------- */
2054 static const unsigned int pcie0_clkreq_n_pins[] = {
2055 /* PCIE0_CLKREQ_N */
2056 RCAR_GP_PIN(4, 21),
2057 };
2058
2059 static const unsigned int pcie0_clkreq_n_mux[] = {
2060 PCIE0_CLKREQ_N_MARK,
2061 };
2062
2063 static const unsigned int pcie1_clkreq_n_pins[] = {
2064 /* PCIE1_CLKREQ_N */
2065 RCAR_GP_PIN(4, 22),
2066 };
2067
2068 static const unsigned int pcie1_clkreq_n_mux[] = {
2069 PCIE1_CLKREQ_N_MARK,
2070 };
2071
2072 /* - PWM0_A ------------------------------------------------------------------- */
2073 static const unsigned int pwm0_a_pins[] = {
2074 /* PWM0_A */
2075 RCAR_GP_PIN(1, 15),
2076 };
2077 static const unsigned int pwm0_a_mux[] = {
2078 PWM0_A_MARK,
2079 };
2080
2081 /* - PWM1_A ------------------------------------------------------------------- */
2082 static const unsigned int pwm1_a_pins[] = {
2083 /* PWM1_A */
2084 RCAR_GP_PIN(3, 13),
2085 };
2086 static const unsigned int pwm1_a_mux[] = {
2087 PWM1_A_MARK,
2088 };
2089
2090 /* - PWM1_B ------------------------------------------------------------------- */
2091 static const unsigned int pwm1_b_pins[] = {
2092 /* PWM1_B */
2093 RCAR_GP_PIN(2, 13),
2094 };
2095 static const unsigned int pwm1_b_mux[] = {
2096 PWM1_B_MARK,
2097 };
2098
2099 /* - PWM2_B ------------------------------------------------------------------- */
2100 static const unsigned int pwm2_b_pins[] = {
2101 /* PWM2_B */
2102 RCAR_GP_PIN(2, 14),
2103 };
2104 static const unsigned int pwm2_b_mux[] = {
2105 PWM2_B_MARK,
2106 };
2107
2108 /* - PWM3_A ------------------------------------------------------------------- */
2109 static const unsigned int pwm3_a_pins[] = {
2110 /* PWM3_A */
2111 RCAR_GP_PIN(1, 22),
2112 };
2113 static const unsigned int pwm3_a_mux[] = {
2114 PWM3_A_MARK,
2115 };
2116
2117 /* - PWM3_B ------------------------------------------------------------------- */
2118 static const unsigned int pwm3_b_pins[] = {
2119 /* PWM3_B */
2120 RCAR_GP_PIN(2, 15),
2121 };
2122 static const unsigned int pwm3_b_mux[] = {
2123 PWM3_B_MARK,
2124 };
2125
2126 /* - PWM4 ------------------------------------------------------------------- */
2127 static const unsigned int pwm4_pins[] = {
2128 /* PWM4 */
2129 RCAR_GP_PIN(2, 16),
2130 };
2131 static const unsigned int pwm4_mux[] = {
2132 PWM4_MARK,
2133 };
2134
2135 /* - PWM5 ------------------------------------------------------------------- */
2136 static const unsigned int pwm5_pins[] = {
2137 /* PWM5 */
2138 RCAR_GP_PIN(2, 17),
2139 };
2140 static const unsigned int pwm5_mux[] = {
2141 PWM5_MARK,
2142 };
2143
2144 /* - PWM6 ------------------------------------------------------------------- */
2145 static const unsigned int pwm6_pins[] = {
2146 /* PWM6 */
2147 RCAR_GP_PIN(2, 18),
2148 };
2149 static const unsigned int pwm6_mux[] = {
2150 PWM6_MARK,
2151 };
2152
2153 /* - PWM7 ------------------------------------------------------------------- */
2154 static const unsigned int pwm7_pins[] = {
2155 /* PWM7 */
2156 RCAR_GP_PIN(2, 19),
2157 };
2158 static const unsigned int pwm7_mux[] = {
2159 PWM7_MARK,
2160 };
2161
2162 /* - PWM8_A ------------------------------------------------------------------- */
2163 static const unsigned int pwm8_a_pins[] = {
2164 /* PWM8_A */
2165 RCAR_GP_PIN(1, 13),
2166 };
2167 static const unsigned int pwm8_a_mux[] = {
2168 PWM8_A_MARK,
2169 };
2170
2171 /* - PWM9_A ------------------------------------------------------------------- */
2172 static const unsigned int pwm9_a_pins[] = {
2173 /* PWM9_A */
2174 RCAR_GP_PIN(1, 14),
2175 };
2176 static const unsigned int pwm9_a_mux[] = {
2177 PWM9_A_MARK,
2178 };
2179
2180 /* - QSPI0 ------------------------------------------------------------------ */
2181 static const unsigned int qspi0_ctrl_pins[] = {
2182 /* SPCLK, SSL */
2183 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),
2184 };
2185 static const unsigned int qspi0_ctrl_mux[] = {
2186 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
2187 };
2188 static const unsigned int qspi0_data_pins[] = {
2189 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2190 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2191 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2192 };
2193 static const unsigned int qspi0_data_mux[] = {
2194 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2195 QSPI0_IO2_MARK, QSPI0_IO3_MARK
2196 };
2197
2198 /* - QSPI1 ------------------------------------------------------------------ */
2199 static const unsigned int qspi1_ctrl_pins[] = {
2200 /* SPCLK, SSL */
2201 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),
2202 };
2203 static const unsigned int qspi1_ctrl_mux[] = {
2204 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
2205 };
2206 static const unsigned int qspi1_data_pins[] = {
2207 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2208 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),
2209 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),
2210 };
2211 static const unsigned int qspi1_data_mux[] = {
2212 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2213 QSPI1_IO2_MARK, QSPI1_IO3_MARK
2214 };
2215
2216 /* - SCIF0 ------------------------------------------------------------------ */
2217 static const unsigned int scif0_data_pins[] = {
2218 /* RX0, TX0 */
2219 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
2220 };
2221 static const unsigned int scif0_data_mux[] = {
2222 RX0_MARK, TX0_MARK,
2223 };
2224 static const unsigned int scif0_clk_pins[] = {
2225 /* SCK0 */
2226 RCAR_GP_PIN(1, 15),
2227 };
2228 static const unsigned int scif0_clk_mux[] = {
2229 SCK0_MARK,
2230 };
2231 static const unsigned int scif0_ctrl_pins[] = {
2232 /* RTS0_N, CTS0_N */
2233 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2234 };
2235 static const unsigned int scif0_ctrl_mux[] = {
2236 RTS0_N_MARK, CTS0_N_MARK,
2237 };
2238
2239 /* - SCIF1 ------------------------------------------------------------------ */
2240 static const unsigned int scif1_data_pins[] = {
2241 /* RX1, TX1 */
2242 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2243 };
2244 static const unsigned int scif1_data_mux[] = {
2245 RX1_MARK, TX1_MARK,
2246 };
2247 static const unsigned int scif1_clk_pins[] = {
2248 /* SCK1 */
2249 RCAR_GP_PIN(0, 18),
2250 };
2251 static const unsigned int scif1_clk_mux[] = {
2252 SCK1_MARK,
2253 };
2254 static const unsigned int scif1_ctrl_pins[] = {
2255 /* RTS1_N, CTS1_N */
2256 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
2257 };
2258 static const unsigned int scif1_ctrl_mux[] = {
2259 RTS1_N_MARK, CTS1_N_MARK,
2260 };
2261
2262 /* - SCIF1_X ------------------------------------------------------------------ */
2263 static const unsigned int scif1_data_x_pins[] = {
2264 /* RX1_X, TX1_X */
2265 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2266 };
2267 static const unsigned int scif1_data_x_mux[] = {
2268 RX1_X_MARK, TX1_X_MARK,
2269 };
2270 static const unsigned int scif1_clk_x_pins[] = {
2271 /* SCK1_X */
2272 RCAR_GP_PIN(1, 10),
2273 };
2274 static const unsigned int scif1_clk_x_mux[] = {
2275 SCK1_X_MARK,
2276 };
2277 static const unsigned int scif1_ctrl_x_pins[] = {
2278 /* RTS1_N_X, CTS1_N_X */
2279 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2280 };
2281 static const unsigned int scif1_ctrl_x_mux[] = {
2282 RTS1_N_X_MARK, CTS1_N_X_MARK,
2283 };
2284
2285 /* - SCIF3 ------------------------------------------------------------------ */
2286 static const unsigned int scif3_data_pins[] = {
2287 /* RX3, TX3 */
2288 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2289 };
2290 static const unsigned int scif3_data_mux[] = {
2291 RX3_MARK, TX3_MARK,
2292 };
2293 static const unsigned int scif3_clk_pins[] = {
2294 /* SCK3 */
2295 RCAR_GP_PIN(1, 4),
2296 };
2297 static const unsigned int scif3_clk_mux[] = {
2298 SCK3_MARK,
2299 };
2300 static const unsigned int scif3_ctrl_pins[] = {
2301 /* RTS3_N, CTS3_N */
2302 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2303 };
2304 static const unsigned int scif3_ctrl_mux[] = {
2305 RTS3_N_MARK, CTS3_N_MARK,
2306 };
2307
2308 /* - SCIF3_A ------------------------------------------------------------------ */
2309 static const unsigned int scif3_data_a_pins[] = {
2310 /* RX3_A, TX3_A */
2311 RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
2312 };
2313 static const unsigned int scif3_data_a_mux[] = {
2314 RX3_A_MARK, TX3_A_MARK,
2315 };
2316 static const unsigned int scif3_clk_a_pins[] = {
2317 /* SCK3_A */
2318 RCAR_GP_PIN(1, 24),
2319 };
2320 static const unsigned int scif3_clk_a_mux[] = {
2321 SCK3_A_MARK,
2322 };
2323 static const unsigned int scif3_ctrl_a_pins[] = {
2324 /* RTS3_N_A, CTS3_N_A */
2325 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2326 };
2327 static const unsigned int scif3_ctrl_a_mux[] = {
2328 RTS3_N_A_MARK, CTS3_N_A_MARK,
2329 };
2330
2331 /* - SCIF4 ------------------------------------------------------------------ */
2332 static const unsigned int scif4_data_pins[] = {
2333 /* RX4, TX4 */
2334 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),
2335 };
2336 static const unsigned int scif4_data_mux[] = {
2337 RX4_MARK, TX4_MARK,
2338 };
2339 static const unsigned int scif4_clk_pins[] = {
2340 /* SCK4 */
2341 RCAR_GP_PIN(8, 8),
2342 };
2343 static const unsigned int scif4_clk_mux[] = {
2344 SCK4_MARK,
2345 };
2346 static const unsigned int scif4_ctrl_pins[] = {
2347 /* RTS4_N, CTS4_N */
2348 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),
2349 };
2350 static const unsigned int scif4_ctrl_mux[] = {
2351 RTS4_N_MARK, CTS4_N_MARK,
2352 };
2353
2354 /* - SCIF Clock ------------------------------------------------------------- */
2355 static const unsigned int scif_clk_pins[] = {
2356 /* SCIF_CLK */
2357 RCAR_GP_PIN(1, 17),
2358 };
2359 static const unsigned int scif_clk_mux[] = {
2360 SCIF_CLK_MARK,
2361 };
2362
2363 /* - TPU ------------------------------------------------------------------- */
2364 static const unsigned int tpu_to0_pins[] = {
2365 /* TPU0TO0 */
2366 RCAR_GP_PIN(2, 8),
2367 };
2368 static const unsigned int tpu_to0_mux[] = {
2369 TPU0TO0_MARK,
2370 };
2371 static const unsigned int tpu_to1_pins[] = {
2372 /* TPU0TO1 */
2373 RCAR_GP_PIN(2, 7),
2374 };
2375 static const unsigned int tpu_to1_mux[] = {
2376 TPU0TO1_MARK,
2377 };
2378 static const unsigned int tpu_to2_pins[] = {
2379 /* TPU0TO2 */
2380 RCAR_GP_PIN(2, 12),
2381 };
2382 static const unsigned int tpu_to2_mux[] = {
2383 TPU0TO2_MARK,
2384 };
2385 static const unsigned int tpu_to3_pins[] = {
2386 /* TPU0TO3 */
2387 RCAR_GP_PIN(2, 13),
2388 };
2389 static const unsigned int tpu_to3_mux[] = {
2390 TPU0TO3_MARK,
2391 };
2392
2393 /* - TPU_A ------------------------------------------------------------------- */
2394 static const unsigned int tpu_to0_a_pins[] = {
2395 /* TPU0TO0_A */
2396 RCAR_GP_PIN(1, 25),
2397 };
2398 static const unsigned int tpu_to0_a_mux[] = {
2399 TPU0TO0_A_MARK,
2400 };
2401 static const unsigned int tpu_to1_a_pins[] = {
2402 /* TPU0TO1_A */
2403 RCAR_GP_PIN(1, 26),
2404 };
2405 static const unsigned int tpu_to1_a_mux[] = {
2406 TPU0TO1_A_MARK,
2407 };
2408 static const unsigned int tpu_to2_a_pins[] = {
2409 /* TPU0TO2_A */
2410 RCAR_GP_PIN(2, 0),
2411 };
2412 static const unsigned int tpu_to2_a_mux[] = {
2413 TPU0TO2_A_MARK,
2414 };
2415 static const unsigned int tpu_to3_a_pins[] = {
2416 /* TPU0TO3_A */
2417 RCAR_GP_PIN(2, 1),
2418 };
2419 static const unsigned int tpu_to3_a_mux[] = {
2420 TPU0TO3_A_MARK,
2421 };
2422
2423 /* - TSN0 ------------------------------------------------ */
2424 static const unsigned int tsn0_link_pins[] = {
2425 /* TSN0_LINK */
2426 RCAR_GP_PIN(4, 4),
2427 };
2428 static const unsigned int tsn0_link_mux[] = {
2429 TSN0_LINK_MARK,
2430 };
2431 static const unsigned int tsn0_phy_int_pins[] = {
2432 /* TSN0_PHY_INT */
2433 RCAR_GP_PIN(4, 3),
2434 };
2435 static const unsigned int tsn0_phy_int_mux[] = {
2436 TSN0_PHY_INT_MARK,
2437 };
2438 static const unsigned int tsn0_mdio_pins[] = {
2439 /* TSN0_MDC, TSN0_MDIO */
2440 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
2441 };
2442 static const unsigned int tsn0_mdio_mux[] = {
2443 TSN0_MDC_MARK, TSN0_MDIO_MARK,
2444 };
2445 static const unsigned int tsn0_rgmii_pins[] = {
2446 /*
2447 * TSN0_TX_CTL, TSN0_TXC, TSN0_TD0, TSN0_TD1, TSN0_TD2, TSN0_TD3,
2448 * TSN0_RX_CTL, TSN0_RXC, TSN0_RD0, TSN0_RD1, TSN0_RD2, TSN0_RD3,
2449 */
2450 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 12),
2451 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14),
2452 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2453 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 11),
2454 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13),
2455 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
2456 };
2457 static const unsigned int tsn0_rgmii_mux[] = {
2458 TSN0_TX_CTL_MARK, TSN0_TXC_MARK,
2459 TSN0_TD0_MARK, TSN0_TD1_MARK,
2460 TSN0_TD2_MARK, TSN0_TD3_MARK,
2461 TSN0_RX_CTL_MARK, TSN0_RXC_MARK,
2462 TSN0_RD0_MARK, TSN0_RD1_MARK,
2463 TSN0_RD2_MARK, TSN0_RD3_MARK,
2464 };
2465 static const unsigned int tsn0_txcrefclk_pins[] = {
2466 /* TSN0_TXCREFCLK */
2467 RCAR_GP_PIN(4, 20),
2468 };
2469 static const unsigned int tsn0_txcrefclk_mux[] = {
2470 TSN0_TXCREFCLK_MARK,
2471 };
2472 static const unsigned int tsn0_avtp_pps_pins[] = {
2473 /* TSN0_AVTP_PPS0, TSN0_AVTP_PPS1 */
2474 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2),
2475 };
2476 static const unsigned int tsn0_avtp_pps_mux[] = {
2477 TSN0_AVTP_PPS0_MARK, TSN0_AVTP_PPS1_MARK,
2478 };
2479 static const unsigned int tsn0_avtp_capture_pins[] = {
2480 /* TSN0_AVTP_CAPTURE */
2481 RCAR_GP_PIN(4, 6),
2482 };
2483 static const unsigned int tsn0_avtp_capture_mux[] = {
2484 TSN0_AVTP_CAPTURE_MARK,
2485 };
2486 static const unsigned int tsn0_avtp_match_pins[] = {
2487 /* TSN0_AVTP_MATCH */
2488 RCAR_GP_PIN(4, 5),
2489 };
2490 static const unsigned int tsn0_avtp_match_mux[] = {
2491 TSN0_AVTP_MATCH_MARK,
2492 };
2493
2494 static const struct sh_pfc_pin_group pinmux_groups[] = {
2495 SH_PFC_PIN_GROUP(avb0_link),
2496 SH_PFC_PIN_GROUP(avb0_magic),
2497 SH_PFC_PIN_GROUP(avb0_phy_int),
2498 SH_PFC_PIN_GROUP(avb0_mdio),
2499 SH_PFC_PIN_GROUP(avb0_rgmii),
2500 SH_PFC_PIN_GROUP(avb0_txcrefclk),
2501 SH_PFC_PIN_GROUP(avb0_avtp_pps),
2502 SH_PFC_PIN_GROUP(avb0_avtp_capture),
2503 SH_PFC_PIN_GROUP(avb0_avtp_match),
2504
2505 SH_PFC_PIN_GROUP(avb1_link),
2506 SH_PFC_PIN_GROUP(avb1_magic),
2507 SH_PFC_PIN_GROUP(avb1_phy_int),
2508 SH_PFC_PIN_GROUP(avb1_mdio),
2509 SH_PFC_PIN_GROUP(avb1_rgmii),
2510 SH_PFC_PIN_GROUP(avb1_txcrefclk),
2511 SH_PFC_PIN_GROUP(avb1_avtp_pps),
2512 SH_PFC_PIN_GROUP(avb1_avtp_capture),
2513 SH_PFC_PIN_GROUP(avb1_avtp_match),
2514
2515 SH_PFC_PIN_GROUP(avb2_link),
2516 SH_PFC_PIN_GROUP(avb2_magic),
2517 SH_PFC_PIN_GROUP(avb2_phy_int),
2518 SH_PFC_PIN_GROUP(avb2_mdio),
2519 SH_PFC_PIN_GROUP(avb2_rgmii),
2520 SH_PFC_PIN_GROUP(avb2_txcrefclk),
2521 SH_PFC_PIN_GROUP(avb2_avtp_pps),
2522 SH_PFC_PIN_GROUP(avb2_avtp_capture),
2523 SH_PFC_PIN_GROUP(avb2_avtp_match),
2524
2525 SH_PFC_PIN_GROUP(canfd0_data),
2526 SH_PFC_PIN_GROUP(canfd1_data),
2527 SH_PFC_PIN_GROUP(canfd2_data),
2528 SH_PFC_PIN_GROUP(canfd3_data),
2529 SH_PFC_PIN_GROUP(canfd4_data),
2530 SH_PFC_PIN_GROUP(canfd5_data), /* suffix might be updated */
2531 SH_PFC_PIN_GROUP(canfd5_data_b), /* suffix might be updated */
2532 SH_PFC_PIN_GROUP(canfd6_data),
2533 SH_PFC_PIN_GROUP(canfd7_data),
2534 SH_PFC_PIN_GROUP(can_clk),
2535
2536 SH_PFC_PIN_GROUP(hscif0_data),
2537 SH_PFC_PIN_GROUP(hscif0_clk),
2538 SH_PFC_PIN_GROUP(hscif0_ctrl),
2539 SH_PFC_PIN_GROUP(hscif1_data), /* suffix might be updated */
2540 SH_PFC_PIN_GROUP(hscif1_clk), /* suffix might be updated */
2541 SH_PFC_PIN_GROUP(hscif1_ctrl), /* suffix might be updated */
2542 SH_PFC_PIN_GROUP(hscif1_data_x), /* suffix might be updated */
2543 SH_PFC_PIN_GROUP(hscif1_clk_x), /* suffix might be updated */
2544 SH_PFC_PIN_GROUP(hscif1_ctrl_x), /* suffix might be updated */
2545 SH_PFC_PIN_GROUP(hscif2_data),
2546 SH_PFC_PIN_GROUP(hscif2_clk),
2547 SH_PFC_PIN_GROUP(hscif2_ctrl),
2548 SH_PFC_PIN_GROUP(hscif3_data), /* suffix might be updated */
2549 SH_PFC_PIN_GROUP(hscif3_clk), /* suffix might be updated */
2550 SH_PFC_PIN_GROUP(hscif3_ctrl), /* suffix might be updated */
2551 SH_PFC_PIN_GROUP(hscif3_data_a), /* suffix might be updated */
2552 SH_PFC_PIN_GROUP(hscif3_clk_a), /* suffix might be updated */
2553 SH_PFC_PIN_GROUP(hscif3_ctrl_a), /* suffix might be updated */
2554
2555 SH_PFC_PIN_GROUP(i2c0),
2556 SH_PFC_PIN_GROUP(i2c1),
2557 SH_PFC_PIN_GROUP(i2c2),
2558 SH_PFC_PIN_GROUP(i2c3),
2559 SH_PFC_PIN_GROUP(i2c4),
2560 SH_PFC_PIN_GROUP(i2c5),
2561
2562 BUS_DATA_PIN_GROUP(mmc_data, 1),
2563 BUS_DATA_PIN_GROUP(mmc_data, 4),
2564 BUS_DATA_PIN_GROUP(mmc_data, 8),
2565 SH_PFC_PIN_GROUP(mmc_ctrl),
2566 SH_PFC_PIN_GROUP(mmc_cd),
2567 SH_PFC_PIN_GROUP(mmc_wp),
2568 SH_PFC_PIN_GROUP(mmc_ds),
2569
2570 SH_PFC_PIN_GROUP(msiof0_clk),
2571 SH_PFC_PIN_GROUP(msiof0_sync),
2572 SH_PFC_PIN_GROUP(msiof0_ss1),
2573 SH_PFC_PIN_GROUP(msiof0_ss2),
2574 SH_PFC_PIN_GROUP(msiof0_txd),
2575 SH_PFC_PIN_GROUP(msiof0_rxd),
2576
2577 SH_PFC_PIN_GROUP(msiof1_clk),
2578 SH_PFC_PIN_GROUP(msiof1_sync),
2579 SH_PFC_PIN_GROUP(msiof1_ss1),
2580 SH_PFC_PIN_GROUP(msiof1_ss2),
2581 SH_PFC_PIN_GROUP(msiof1_txd),
2582 SH_PFC_PIN_GROUP(msiof1_rxd),
2583
2584 SH_PFC_PIN_GROUP(msiof2_clk),
2585 SH_PFC_PIN_GROUP(msiof2_sync),
2586 SH_PFC_PIN_GROUP(msiof2_ss1),
2587 SH_PFC_PIN_GROUP(msiof2_ss2),
2588 SH_PFC_PIN_GROUP(msiof2_txd),
2589 SH_PFC_PIN_GROUP(msiof2_rxd),
2590
2591 SH_PFC_PIN_GROUP(msiof3_clk),
2592 SH_PFC_PIN_GROUP(msiof3_sync),
2593 SH_PFC_PIN_GROUP(msiof3_ss1),
2594 SH_PFC_PIN_GROUP(msiof3_ss2),
2595 SH_PFC_PIN_GROUP(msiof3_txd),
2596 SH_PFC_PIN_GROUP(msiof3_rxd),
2597
2598 SH_PFC_PIN_GROUP(msiof4_clk),
2599 SH_PFC_PIN_GROUP(msiof4_sync),
2600 SH_PFC_PIN_GROUP(msiof4_ss1),
2601 SH_PFC_PIN_GROUP(msiof4_ss2),
2602 SH_PFC_PIN_GROUP(msiof4_txd),
2603 SH_PFC_PIN_GROUP(msiof4_rxd),
2604
2605 SH_PFC_PIN_GROUP(msiof5_clk),
2606 SH_PFC_PIN_GROUP(msiof5_sync),
2607 SH_PFC_PIN_GROUP(msiof5_ss1),
2608 SH_PFC_PIN_GROUP(msiof5_ss2),
2609 SH_PFC_PIN_GROUP(msiof5_txd),
2610 SH_PFC_PIN_GROUP(msiof5_rxd),
2611
2612 SH_PFC_PIN_GROUP(pcie0_clkreq_n),
2613 SH_PFC_PIN_GROUP(pcie1_clkreq_n),
2614
2615 SH_PFC_PIN_GROUP(pwm0_a), /* suffix might be updated */
2616 SH_PFC_PIN_GROUP(pwm1_a),
2617 SH_PFC_PIN_GROUP(pwm1_b),
2618 SH_PFC_PIN_GROUP(pwm2_b), /* suffix might be updated */
2619 SH_PFC_PIN_GROUP(pwm3_a),
2620 SH_PFC_PIN_GROUP(pwm3_b),
2621 SH_PFC_PIN_GROUP(pwm4),
2622 SH_PFC_PIN_GROUP(pwm5),
2623 SH_PFC_PIN_GROUP(pwm6),
2624 SH_PFC_PIN_GROUP(pwm7),
2625 SH_PFC_PIN_GROUP(pwm8_a), /* suffix might be updated */
2626 SH_PFC_PIN_GROUP(pwm9_a), /* suffix might be updated */
2627
2628 SH_PFC_PIN_GROUP(qspi0_ctrl),
2629 BUS_DATA_PIN_GROUP(qspi0_data, 2),
2630 BUS_DATA_PIN_GROUP(qspi0_data, 4),
2631 SH_PFC_PIN_GROUP(qspi1_ctrl),
2632 BUS_DATA_PIN_GROUP(qspi1_data, 2),
2633 BUS_DATA_PIN_GROUP(qspi1_data, 4),
2634
2635 SH_PFC_PIN_GROUP(scif0_data),
2636 SH_PFC_PIN_GROUP(scif0_clk),
2637 SH_PFC_PIN_GROUP(scif0_ctrl),
2638 SH_PFC_PIN_GROUP(scif1_data), /* suffix might be updated */
2639 SH_PFC_PIN_GROUP(scif1_clk), /* suffix might be updated */
2640 SH_PFC_PIN_GROUP(scif1_ctrl), /* suffix might be updated */
2641 SH_PFC_PIN_GROUP(scif1_data_x), /* suffix might be updated */
2642 SH_PFC_PIN_GROUP(scif1_clk_x), /* suffix might be updated */
2643 SH_PFC_PIN_GROUP(scif1_ctrl_x), /* suffix might be updated */
2644 SH_PFC_PIN_GROUP(scif3_data), /* suffix might be updated */
2645 SH_PFC_PIN_GROUP(scif3_clk), /* suffix might be updated */
2646 SH_PFC_PIN_GROUP(scif3_ctrl), /* suffix might be updated */
2647 SH_PFC_PIN_GROUP(scif3_data_a), /* suffix might be updated */
2648 SH_PFC_PIN_GROUP(scif3_clk_a), /* suffix might be updated */
2649 SH_PFC_PIN_GROUP(scif3_ctrl_a), /* suffix might be updated */
2650 SH_PFC_PIN_GROUP(scif4_data),
2651 SH_PFC_PIN_GROUP(scif4_clk),
2652 SH_PFC_PIN_GROUP(scif4_ctrl),
2653 SH_PFC_PIN_GROUP(scif_clk),
2654
2655 SH_PFC_PIN_GROUP(tpu_to0), /* suffix might be updated */
2656 SH_PFC_PIN_GROUP(tpu_to0_a), /* suffix might be updated */
2657 SH_PFC_PIN_GROUP(tpu_to1), /* suffix might be updated */
2658 SH_PFC_PIN_GROUP(tpu_to1_a), /* suffix might be updated */
2659 SH_PFC_PIN_GROUP(tpu_to2), /* suffix might be updated */
2660 SH_PFC_PIN_GROUP(tpu_to2_a), /* suffix might be updated */
2661 SH_PFC_PIN_GROUP(tpu_to3), /* suffix might be updated */
2662 SH_PFC_PIN_GROUP(tpu_to3_a), /* suffix might be updated */
2663
2664 SH_PFC_PIN_GROUP(tsn0_link),
2665 SH_PFC_PIN_GROUP(tsn0_phy_int),
2666 SH_PFC_PIN_GROUP(tsn0_mdio),
2667 SH_PFC_PIN_GROUP(tsn0_rgmii),
2668 SH_PFC_PIN_GROUP(tsn0_txcrefclk),
2669 SH_PFC_PIN_GROUP(tsn0_avtp_pps),
2670 SH_PFC_PIN_GROUP(tsn0_avtp_capture),
2671 SH_PFC_PIN_GROUP(tsn0_avtp_match),
2672 };
2673
2674 static const char * const avb0_groups[] = {
2675 "avb0_link",
2676 "avb0_magic",
2677 "avb0_phy_int",
2678 "avb0_mdio",
2679 "avb0_rgmii",
2680 "avb0_txcrefclk",
2681 "avb0_avtp_pps",
2682 "avb0_avtp_capture",
2683 "avb0_avtp_match",
2684 };
2685
2686 static const char * const avb1_groups[] = {
2687 "avb1_link",
2688 "avb1_magic",
2689 "avb1_phy_int",
2690 "avb1_mdio",
2691 "avb1_rgmii",
2692 "avb1_txcrefclk",
2693 "avb1_avtp_pps",
2694 "avb1_avtp_capture",
2695 "avb1_avtp_match",
2696 };
2697
2698 static const char * const avb2_groups[] = {
2699 "avb2_link",
2700 "avb2_magic",
2701 "avb2_phy_int",
2702 "avb2_mdio",
2703 "avb2_rgmii",
2704 "avb2_txcrefclk",
2705 "avb2_avtp_pps",
2706 "avb2_avtp_capture",
2707 "avb2_avtp_match",
2708 };
2709
2710 static const char * const canfd0_groups[] = {
2711 "canfd0_data",
2712 };
2713
2714 static const char * const canfd1_groups[] = {
2715 "canfd1_data",
2716 };
2717
2718 static const char * const canfd2_groups[] = {
2719 "canfd2_data",
2720 };
2721
2722 static const char * const canfd3_groups[] = {
2723 "canfd3_data",
2724 };
2725
2726 static const char * const canfd4_groups[] = {
2727 "canfd4_data",
2728 };
2729
2730 static const char * const canfd5_groups[] = {
2731 /* suffix might be updated */
2732 "canfd5_data",
2733 "canfd5_data_b",
2734 };
2735
2736 static const char * const canfd6_groups[] = {
2737 "canfd6_data",
2738 };
2739
2740 static const char * const canfd7_groups[] = {
2741 "canfd7_data",
2742 };
2743
2744 static const char * const can_clk_groups[] = {
2745 "can_clk",
2746 };
2747
2748 static const char * const hscif0_groups[] = {
2749 "hscif0_data",
2750 "hscif0_clk",
2751 "hscif0_ctrl",
2752 };
2753
2754 static const char * const hscif1_groups[] = {
2755 /* suffix might be updated */
2756 "hscif1_data",
2757 "hscif1_clk",
2758 "hscif1_ctrl",
2759 "hscif1_data_x",
2760 "hscif1_clk_x",
2761 "hscif1_ctrl_x",
2762 };
2763
2764 static const char * const hscif2_groups[] = {
2765 "hscif2_data",
2766 "hscif2_clk",
2767 "hscif2_ctrl",
2768 };
2769
2770 static const char * const hscif3_groups[] = {
2771 /* suffix might be updated */
2772 "hscif3_data",
2773 "hscif3_clk",
2774 "hscif3_ctrl",
2775 "hscif3_data_a",
2776 "hscif3_clk_a",
2777 "hscif3_ctrl_a",
2778 };
2779
2780 static const char * const i2c0_groups[] = {
2781 "i2c0",
2782 };
2783
2784 static const char * const i2c1_groups[] = {
2785 "i2c1",
2786 };
2787
2788 static const char * const i2c2_groups[] = {
2789 "i2c2",
2790 };
2791
2792 static const char * const i2c3_groups[] = {
2793 "i2c3",
2794 };
2795
2796 static const char * const i2c4_groups[] = {
2797 "i2c4",
2798 };
2799
2800 static const char * const i2c5_groups[] = {
2801 "i2c5",
2802 };
2803
2804 static const char * const mmc_groups[] = {
2805 "mmc_data1",
2806 "mmc_data4",
2807 "mmc_data8",
2808 "mmc_ctrl",
2809 "mmc_cd",
2810 "mmc_wp",
2811 "mmc_ds",
2812 };
2813
2814 static const char * const msiof0_groups[] = {
2815 "msiof0_clk",
2816 "msiof0_sync",
2817 "msiof0_ss1",
2818 "msiof0_ss2",
2819 "msiof0_txd",
2820 "msiof0_rxd",
2821 };
2822
2823 static const char * const msiof1_groups[] = {
2824 "msiof1_clk",
2825 "msiof1_sync",
2826 "msiof1_ss1",
2827 "msiof1_ss2",
2828 "msiof1_txd",
2829 "msiof1_rxd",
2830 };
2831
2832 static const char * const msiof2_groups[] = {
2833 "msiof2_clk",
2834 "msiof2_sync",
2835 "msiof2_ss1",
2836 "msiof2_ss2",
2837 "msiof2_txd",
2838 "msiof2_rxd",
2839 };
2840
2841 static const char * const msiof3_groups[] = {
2842 "msiof3_clk",
2843 "msiof3_sync",
2844 "msiof3_ss1",
2845 "msiof3_ss2",
2846 "msiof3_txd",
2847 "msiof3_rxd",
2848 };
2849
2850 static const char * const msiof4_groups[] = {
2851 "msiof4_clk",
2852 "msiof4_sync",
2853 "msiof4_ss1",
2854 "msiof4_ss2",
2855 "msiof4_txd",
2856 "msiof4_rxd",
2857 };
2858
2859 static const char * const msiof5_groups[] = {
2860 "msiof5_clk",
2861 "msiof5_sync",
2862 "msiof5_ss1",
2863 "msiof5_ss2",
2864 "msiof5_txd",
2865 "msiof5_rxd",
2866 };
2867
2868 static const char * const pcie_groups[] = {
2869 "pcie0_clkreq_n",
2870 "pcie1_clkreq_n",
2871 };
2872
2873 static const char * const pwm0_groups[] = {
2874 /* suffix might be updated */
2875 "pwm0_a",
2876 };
2877
2878 static const char * const pwm1_groups[] = {
2879 "pwm1_a",
2880 "pwm1_b",
2881 };
2882
2883 static const char * const pwm2_groups[] = {
2884 /* suffix might be updated */
2885 "pwm2_b",
2886 };
2887
2888 static const char * const pwm3_groups[] = {
2889 "pwm3_a",
2890 "pwm3_b",
2891 };
2892
2893 static const char * const pwm4_groups[] = {
2894 "pwm4",
2895 };
2896
2897 static const char * const pwm5_groups[] = {
2898 "pwm5",
2899 };
2900
2901 static const char * const pwm6_groups[] = {
2902 "pwm6",
2903 };
2904
2905 static const char * const pwm7_groups[] = {
2906 "pwm7",
2907 };
2908
2909 static const char * const pwm8_groups[] = {
2910 /* suffix might be updated */
2911 "pwm8_a",
2912 };
2913
2914 static const char * const pwm9_groups[] = {
2915 /* suffix might be updated */
2916 "pwm9_a",
2917 };
2918
2919 static const char * const qspi0_groups[] = {
2920 "qspi0_ctrl",
2921 "qspi0_data2",
2922 "qspi0_data4",
2923 };
2924
2925 static const char * const qspi1_groups[] = {
2926 "qspi1_ctrl",
2927 "qspi1_data2",
2928 "qspi1_data4",
2929 };
2930
2931 static const char * const scif0_groups[] = {
2932 "scif0_data",
2933 "scif0_clk",
2934 "scif0_ctrl",
2935 };
2936
2937 static const char * const scif1_groups[] = {
2938 /* suffix might be updated */
2939 "scif1_data",
2940 "scif1_clk",
2941 "scif1_ctrl",
2942 "scif1_data_x",
2943 "scif1_clk_x",
2944 "scif1_ctrl_x",
2945 };
2946
2947 static const char * const scif3_groups[] = {
2948 /* suffix might be updated */
2949 "scif3_data",
2950 "scif3_clk",
2951 "scif3_ctrl",
2952 "scif3_data_a",
2953 "scif3_clk_a",
2954 "scif3_ctrl_a",
2955 };
2956
2957 static const char * const scif4_groups[] = {
2958 "scif4_data",
2959 "scif4_clk",
2960 "scif4_ctrl",
2961 };
2962
2963 static const char * const scif_clk_groups[] = {
2964 "scif_clk",
2965 };
2966
2967 static const char * const tpu_groups[] = {
2968 /* suffix might be updated */
2969 "tpu_to0",
2970 "tpu_to0_a",
2971 "tpu_to1",
2972 "tpu_to1_a",
2973 "tpu_to2",
2974 "tpu_to2_a",
2975 "tpu_to3",
2976 "tpu_to3_a",
2977 };
2978
2979 static const char * const tsn0_groups[] = {
2980 "tsn0_link",
2981 "tsn0_phy_int",
2982 "tsn0_mdio",
2983 "tsn0_rgmii",
2984 "tsn0_txcrefclk",
2985 "tsn0_avtp_pps",
2986 "tsn0_avtp_capture",
2987 "tsn0_avtp_match",
2988 };
2989
2990 static const struct sh_pfc_function pinmux_functions[] = {
2991 SH_PFC_FUNCTION(avb0),
2992 SH_PFC_FUNCTION(avb1),
2993 SH_PFC_FUNCTION(avb2),
2994
2995 SH_PFC_FUNCTION(canfd0),
2996 SH_PFC_FUNCTION(canfd1),
2997 SH_PFC_FUNCTION(canfd2),
2998 SH_PFC_FUNCTION(canfd3),
2999 SH_PFC_FUNCTION(canfd4),
3000 SH_PFC_FUNCTION(canfd5),
3001 SH_PFC_FUNCTION(canfd6),
3002 SH_PFC_FUNCTION(canfd7),
3003 SH_PFC_FUNCTION(can_clk),
3004
3005 SH_PFC_FUNCTION(hscif0),
3006 SH_PFC_FUNCTION(hscif1),
3007 SH_PFC_FUNCTION(hscif2),
3008 SH_PFC_FUNCTION(hscif3),
3009
3010 SH_PFC_FUNCTION(i2c0),
3011 SH_PFC_FUNCTION(i2c1),
3012 SH_PFC_FUNCTION(i2c2),
3013 SH_PFC_FUNCTION(i2c3),
3014 SH_PFC_FUNCTION(i2c4),
3015 SH_PFC_FUNCTION(i2c5),
3016
3017 SH_PFC_FUNCTION(mmc),
3018
3019 SH_PFC_FUNCTION(msiof0),
3020 SH_PFC_FUNCTION(msiof1),
3021 SH_PFC_FUNCTION(msiof2),
3022 SH_PFC_FUNCTION(msiof3),
3023 SH_PFC_FUNCTION(msiof4),
3024 SH_PFC_FUNCTION(msiof5),
3025
3026 SH_PFC_FUNCTION(pcie),
3027
3028 SH_PFC_FUNCTION(pwm0),
3029 SH_PFC_FUNCTION(pwm1),
3030 SH_PFC_FUNCTION(pwm2),
3031 SH_PFC_FUNCTION(pwm3),
3032 SH_PFC_FUNCTION(pwm4),
3033 SH_PFC_FUNCTION(pwm5),
3034 SH_PFC_FUNCTION(pwm6),
3035 SH_PFC_FUNCTION(pwm7),
3036 SH_PFC_FUNCTION(pwm8),
3037 SH_PFC_FUNCTION(pwm9),
3038
3039 SH_PFC_FUNCTION(qspi0),
3040 SH_PFC_FUNCTION(qspi1),
3041
3042 SH_PFC_FUNCTION(scif0),
3043 SH_PFC_FUNCTION(scif1),
3044 SH_PFC_FUNCTION(scif3),
3045 SH_PFC_FUNCTION(scif4),
3046 SH_PFC_FUNCTION(scif_clk),
3047
3048 SH_PFC_FUNCTION(tpu),
3049
3050 SH_PFC_FUNCTION(tsn0),
3051 };
3052
3053 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3054 #define F_(x, y) FN_##y
3055 #define FM(x) FN_##x
3056 { PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32,
3057 GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3058 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3059 GROUP(
3060 /* GP0_31_19 RESERVED */
3061 GP_0_18_FN, GPSR0_18,
3062 GP_0_17_FN, GPSR0_17,
3063 GP_0_16_FN, GPSR0_16,
3064 GP_0_15_FN, GPSR0_15,
3065 GP_0_14_FN, GPSR0_14,
3066 GP_0_13_FN, GPSR0_13,
3067 GP_0_12_FN, GPSR0_12,
3068 GP_0_11_FN, GPSR0_11,
3069 GP_0_10_FN, GPSR0_10,
3070 GP_0_9_FN, GPSR0_9,
3071 GP_0_8_FN, GPSR0_8,
3072 GP_0_7_FN, GPSR0_7,
3073 GP_0_6_FN, GPSR0_6,
3074 GP_0_5_FN, GPSR0_5,
3075 GP_0_4_FN, GPSR0_4,
3076 GP_0_3_FN, GPSR0_3,
3077 GP_0_2_FN, GPSR0_2,
3078 GP_0_1_FN, GPSR0_1,
3079 GP_0_0_FN, GPSR0_0, ))
3080 },
3081 { PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP(
3082 0, 0,
3083 0, 0,
3084 0, 0,
3085 GP_1_28_FN, GPSR1_28,
3086 GP_1_27_FN, GPSR1_27,
3087 GP_1_26_FN, GPSR1_26,
3088 GP_1_25_FN, GPSR1_25,
3089 GP_1_24_FN, GPSR1_24,
3090 GP_1_23_FN, GPSR1_23,
3091 GP_1_22_FN, GPSR1_22,
3092 GP_1_21_FN, GPSR1_21,
3093 GP_1_20_FN, GPSR1_20,
3094 GP_1_19_FN, GPSR1_19,
3095 GP_1_18_FN, GPSR1_18,
3096 GP_1_17_FN, GPSR1_17,
3097 GP_1_16_FN, GPSR1_16,
3098 GP_1_15_FN, GPSR1_15,
3099 GP_1_14_FN, GPSR1_14,
3100 GP_1_13_FN, GPSR1_13,
3101 GP_1_12_FN, GPSR1_12,
3102 GP_1_11_FN, GPSR1_11,
3103 GP_1_10_FN, GPSR1_10,
3104 GP_1_9_FN, GPSR1_9,
3105 GP_1_8_FN, GPSR1_8,
3106 GP_1_7_FN, GPSR1_7,
3107 GP_1_6_FN, GPSR1_6,
3108 GP_1_5_FN, GPSR1_5,
3109 GP_1_4_FN, GPSR1_4,
3110 GP_1_3_FN, GPSR1_3,
3111 GP_1_2_FN, GPSR1_2,
3112 GP_1_1_FN, GPSR1_1,
3113 GP_1_0_FN, GPSR1_0, ))
3114 },
3115 { PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32,
3116 GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3117 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3118 GROUP(
3119 /* GP2_31_20 RESERVED */
3120 GP_2_19_FN, GPSR2_19,
3121 GP_2_18_FN, GPSR2_18,
3122 GP_2_17_FN, GPSR2_17,
3123 GP_2_16_FN, GPSR2_16,
3124 GP_2_15_FN, GPSR2_15,
3125 GP_2_14_FN, GPSR2_14,
3126 GP_2_13_FN, GPSR2_13,
3127 GP_2_12_FN, GPSR2_12,
3128 GP_2_11_FN, GPSR2_11,
3129 GP_2_10_FN, GPSR2_10,
3130 GP_2_9_FN, GPSR2_9,
3131 GP_2_8_FN, GPSR2_8,
3132 GP_2_7_FN, GPSR2_7,
3133 GP_2_6_FN, GPSR2_6,
3134 GP_2_5_FN, GPSR2_5,
3135 GP_2_4_FN, GPSR2_4,
3136 GP_2_3_FN, GPSR2_3,
3137 GP_2_2_FN, GPSR2_2,
3138 GP_2_1_FN, GPSR2_1,
3139 GP_2_0_FN, GPSR2_0, ))
3140 },
3141 { PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP(
3142 0, 0,
3143 0, 0,
3144 GP_3_29_FN, GPSR3_29,
3145 GP_3_28_FN, GPSR3_28,
3146 GP_3_27_FN, GPSR3_27,
3147 GP_3_26_FN, GPSR3_26,
3148 GP_3_25_FN, GPSR3_25,
3149 GP_3_24_FN, GPSR3_24,
3150 GP_3_23_FN, GPSR3_23,
3151 GP_3_22_FN, GPSR3_22,
3152 GP_3_21_FN, GPSR3_21,
3153 GP_3_20_FN, GPSR3_20,
3154 GP_3_19_FN, GPSR3_19,
3155 GP_3_18_FN, GPSR3_18,
3156 GP_3_17_FN, GPSR3_17,
3157 GP_3_16_FN, GPSR3_16,
3158 GP_3_15_FN, GPSR3_15,
3159 GP_3_14_FN, GPSR3_14,
3160 GP_3_13_FN, GPSR3_13,
3161 GP_3_12_FN, GPSR3_12,
3162 GP_3_11_FN, GPSR3_11,
3163 GP_3_10_FN, GPSR3_10,
3164 GP_3_9_FN, GPSR3_9,
3165 GP_3_8_FN, GPSR3_8,
3166 GP_3_7_FN, GPSR3_7,
3167 GP_3_6_FN, GPSR3_6,
3168 GP_3_5_FN, GPSR3_5,
3169 GP_3_4_FN, GPSR3_4,
3170 GP_3_3_FN, GPSR3_3,
3171 GP_3_2_FN, GPSR3_2,
3172 GP_3_1_FN, GPSR3_1,
3173 GP_3_0_FN, GPSR3_0, ))
3174 },
3175 { PINMUX_CFG_REG("GPSR4", 0xE6060040, 32, 1, GROUP(
3176 0, 0,
3177 0, 0,
3178 0, 0,
3179 0, 0,
3180 0, 0,
3181 0, 0,
3182 0, 0,
3183 GP_4_24_FN, GPSR4_24,
3184 GP_4_23_FN, GPSR4_23,
3185 GP_4_22_FN, GPSR4_22,
3186 GP_4_21_FN, GPSR4_21,
3187 GP_4_20_FN, GPSR4_20,
3188 GP_4_19_FN, GPSR4_19,
3189 GP_4_18_FN, GPSR4_18,
3190 GP_4_17_FN, GPSR4_17,
3191 GP_4_16_FN, GPSR4_16,
3192 GP_4_15_FN, GPSR4_15,
3193 GP_4_14_FN, GPSR4_14,
3194 GP_4_13_FN, GPSR4_13,
3195 GP_4_12_FN, GPSR4_12,
3196 GP_4_11_FN, GPSR4_11,
3197 GP_4_10_FN, GPSR4_10,
3198 GP_4_9_FN, GPSR4_9,
3199 GP_4_8_FN, GPSR4_8,
3200 GP_4_7_FN, GPSR4_7,
3201 GP_4_6_FN, GPSR4_6,
3202 GP_4_5_FN, GPSR4_5,
3203 GP_4_4_FN, GPSR4_4,
3204 GP_4_3_FN, GPSR4_3,
3205 GP_4_2_FN, GPSR4_2,
3206 GP_4_1_FN, GPSR4_1,
3207 GP_4_0_FN, GPSR4_0, ))
3208 },
3209 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32,
3210 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3211 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3212 GROUP(
3213 /* GP5_31_21 RESERVED */
3214 GP_5_20_FN, GPSR5_20,
3215 GP_5_19_FN, GPSR5_19,
3216 GP_5_18_FN, GPSR5_18,
3217 GP_5_17_FN, GPSR5_17,
3218 GP_5_16_FN, GPSR5_16,
3219 GP_5_15_FN, GPSR5_15,
3220 GP_5_14_FN, GPSR5_14,
3221 GP_5_13_FN, GPSR5_13,
3222 GP_5_12_FN, GPSR5_12,
3223 GP_5_11_FN, GPSR5_11,
3224 GP_5_10_FN, GPSR5_10,
3225 GP_5_9_FN, GPSR5_9,
3226 GP_5_8_FN, GPSR5_8,
3227 GP_5_7_FN, GPSR5_7,
3228 GP_5_6_FN, GPSR5_6,
3229 GP_5_5_FN, GPSR5_5,
3230 GP_5_4_FN, GPSR5_4,
3231 GP_5_3_FN, GPSR5_3,
3232 GP_5_2_FN, GPSR5_2,
3233 GP_5_1_FN, GPSR5_1,
3234 GP_5_0_FN, GPSR5_0, ))
3235 },
3236 { PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32,
3237 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3238 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3239 GROUP(
3240 /* GP6_31_21 RESERVED */
3241 GP_6_20_FN, GPSR6_20,
3242 GP_6_19_FN, GPSR6_19,
3243 GP_6_18_FN, GPSR6_18,
3244 GP_6_17_FN, GPSR6_17,
3245 GP_6_16_FN, GPSR6_16,
3246 GP_6_15_FN, GPSR6_15,
3247 GP_6_14_FN, GPSR6_14,
3248 GP_6_13_FN, GPSR6_13,
3249 GP_6_12_FN, GPSR6_12,
3250 GP_6_11_FN, GPSR6_11,
3251 GP_6_10_FN, GPSR6_10,
3252 GP_6_9_FN, GPSR6_9,
3253 GP_6_8_FN, GPSR6_8,
3254 GP_6_7_FN, GPSR6_7,
3255 GP_6_6_FN, GPSR6_6,
3256 GP_6_5_FN, GPSR6_5,
3257 GP_6_4_FN, GPSR6_4,
3258 GP_6_3_FN, GPSR6_3,
3259 GP_6_2_FN, GPSR6_2,
3260 GP_6_1_FN, GPSR6_1,
3261 GP_6_0_FN, GPSR6_0, ))
3262 },
3263 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32,
3264 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3265 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3266 GROUP(
3267 /* GP7_31_21 RESERVED */
3268 GP_7_20_FN, GPSR7_20,
3269 GP_7_19_FN, GPSR7_19,
3270 GP_7_18_FN, GPSR7_18,
3271 GP_7_17_FN, GPSR7_17,
3272 GP_7_16_FN, GPSR7_16,
3273 GP_7_15_FN, GPSR7_15,
3274 GP_7_14_FN, GPSR7_14,
3275 GP_7_13_FN, GPSR7_13,
3276 GP_7_12_FN, GPSR7_12,
3277 GP_7_11_FN, GPSR7_11,
3278 GP_7_10_FN, GPSR7_10,
3279 GP_7_9_FN, GPSR7_9,
3280 GP_7_8_FN, GPSR7_8,
3281 GP_7_7_FN, GPSR7_7,
3282 GP_7_6_FN, GPSR7_6,
3283 GP_7_5_FN, GPSR7_5,
3284 GP_7_4_FN, GPSR7_4,
3285 GP_7_3_FN, GPSR7_3,
3286 GP_7_2_FN, GPSR7_2,
3287 GP_7_1_FN, GPSR7_1,
3288 GP_7_0_FN, GPSR7_0, ))
3289 },
3290 { PINMUX_CFG_REG_VAR("GPSR8", 0xE6068040, 32,
3291 GROUP(-18, 1, 1, 1, 1,
3292 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3293 GROUP(
3294 /* GP8_31_14 RESERVED */
3295 GP_8_13_FN, GPSR8_13,
3296 GP_8_12_FN, GPSR8_12,
3297 GP_8_11_FN, GPSR8_11,
3298 GP_8_10_FN, GPSR8_10,
3299 GP_8_9_FN, GPSR8_9,
3300 GP_8_8_FN, GPSR8_8,
3301 GP_8_7_FN, GPSR8_7,
3302 GP_8_6_FN, GPSR8_6,
3303 GP_8_5_FN, GPSR8_5,
3304 GP_8_4_FN, GPSR8_4,
3305 GP_8_3_FN, GPSR8_3,
3306 GP_8_2_FN, GPSR8_2,
3307 GP_8_1_FN, GPSR8_1,
3308 GP_8_0_FN, GPSR8_0, ))
3309 },
3310 #undef F_
3311 #undef FM
3312
3313 #define F_(x, y) x,
3314 #define FM(x) FN_##x,
3315 { PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP(
3316 IP0SR0_31_28
3317 IP0SR0_27_24
3318 IP0SR0_23_20
3319 IP0SR0_19_16
3320 IP0SR0_15_12
3321 IP0SR0_11_8
3322 IP0SR0_7_4
3323 IP0SR0_3_0))
3324 },
3325 { PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP(
3326 IP1SR0_31_28
3327 IP1SR0_27_24
3328 IP1SR0_23_20
3329 IP1SR0_19_16
3330 IP1SR0_15_12
3331 IP1SR0_11_8
3332 IP1SR0_7_4
3333 IP1SR0_3_0))
3334 },
3335 { PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32,
3336 GROUP(-20, 4, 4, 4),
3337 GROUP(
3338 /* IP2SR0_31_12 RESERVED */
3339 IP2SR0_11_8
3340 IP2SR0_7_4
3341 IP2SR0_3_0))
3342 },
3343 { PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP(
3344 IP0SR1_31_28
3345 IP0SR1_27_24
3346 IP0SR1_23_20
3347 IP0SR1_19_16
3348 IP0SR1_15_12
3349 IP0SR1_11_8
3350 IP0SR1_7_4
3351 IP0SR1_3_0))
3352 },
3353 { PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP(
3354 IP1SR1_31_28
3355 IP1SR1_27_24
3356 IP1SR1_23_20
3357 IP1SR1_19_16
3358 IP1SR1_15_12
3359 IP1SR1_11_8
3360 IP1SR1_7_4
3361 IP1SR1_3_0))
3362 },
3363 { PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP(
3364 IP2SR1_31_28
3365 IP2SR1_27_24
3366 IP2SR1_23_20
3367 IP2SR1_19_16
3368 IP2SR1_15_12
3369 IP2SR1_11_8
3370 IP2SR1_7_4
3371 IP2SR1_3_0))
3372 },
3373 { PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32,
3374 GROUP(-12, 4, 4, 4, 4, 4),
3375 GROUP(
3376 /* IP3SR1_31_20 RESERVED */
3377 IP3SR1_19_16
3378 IP3SR1_15_12
3379 IP3SR1_11_8
3380 IP3SR1_7_4
3381 IP3SR1_3_0))
3382 },
3383 { PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP(
3384 IP0SR2_31_28
3385 IP0SR2_27_24
3386 IP0SR2_23_20
3387 IP0SR2_19_16
3388 IP0SR2_15_12
3389 IP0SR2_11_8
3390 IP0SR2_7_4
3391 IP0SR2_3_0))
3392 },
3393 { PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP(
3394 IP1SR2_31_28
3395 IP1SR2_27_24
3396 IP1SR2_23_20
3397 IP1SR2_19_16
3398 IP1SR2_15_12
3399 IP1SR2_11_8
3400 IP1SR2_7_4
3401 IP1SR2_3_0))
3402 },
3403 { PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32,
3404 GROUP(-16, 4, 4, 4, 4),
3405 GROUP(
3406 /* IP2SR2_31_16 RESERVED */
3407 IP2SR2_15_12
3408 IP2SR2_11_8
3409 IP2SR2_7_4
3410 IP2SR2_3_0))
3411 },
3412 { PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP(
3413 IP0SR3_31_28
3414 IP0SR3_27_24
3415 IP0SR3_23_20
3416 IP0SR3_19_16
3417 IP0SR3_15_12
3418 IP0SR3_11_8
3419 IP0SR3_7_4
3420 IP0SR3_3_0))
3421 },
3422 { PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP(
3423 IP1SR3_31_28
3424 IP1SR3_27_24
3425 IP1SR3_23_20
3426 IP1SR3_19_16
3427 IP1SR3_15_12
3428 IP1SR3_11_8
3429 IP1SR3_7_4
3430 IP1SR3_3_0))
3431 },
3432 { PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP(
3433 IP2SR3_31_28
3434 IP2SR3_27_24
3435 IP2SR3_23_20
3436 IP2SR3_19_16
3437 IP2SR3_15_12
3438 IP2SR3_11_8
3439 IP2SR3_7_4
3440 IP2SR3_3_0))
3441 },
3442 { PINMUX_CFG_REG_VAR("IP3SR3", 0xE605886C, 32,
3443 GROUP(-8, 4, 4, 4, 4, 4, 4),
3444 GROUP(
3445 /* IP3SR3_31_24 RESERVED */
3446 IP3SR3_23_20
3447 IP3SR3_19_16
3448 IP3SR3_15_12
3449 IP3SR3_11_8
3450 IP3SR3_7_4
3451 IP3SR3_3_0))
3452 },
3453 { PINMUX_CFG_REG_VAR("IP0SR4", 0xE6060060, 32,
3454 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3455 GROUP(
3456 IP0SR4_31_28
3457 IP0SR4_27_24
3458 IP0SR4_23_20
3459 IP0SR4_19_16
3460 IP0SR4_15_12
3461 IP0SR4_11_8
3462 IP0SR4_7_4
3463 IP0SR4_3_0))
3464 },
3465 { PINMUX_CFG_REG_VAR("IP1SR4", 0xE6060064, 32,
3466 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3467 GROUP(
3468 IP1SR4_31_28
3469 IP1SR4_27_24
3470 IP1SR4_23_20
3471 IP1SR4_19_16
3472 IP1SR4_15_12
3473 IP1SR4_11_8
3474 IP1SR4_7_4
3475 IP1SR4_3_0))
3476 },
3477 { PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32,
3478 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3479 GROUP(
3480 IP2SR4_31_28
3481 IP2SR4_27_24
3482 IP2SR4_23_20
3483 IP2SR4_19_16
3484 IP2SR4_15_12
3485 IP2SR4_11_8
3486 IP2SR4_7_4
3487 IP2SR4_3_0))
3488 },
3489 { PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32,
3490 GROUP(-28, 4),
3491 GROUP(
3492 /* IP3SR4_31_4 RESERVED */
3493 IP3SR4_3_0))
3494 },
3495 { PINMUX_CFG_REG_VAR("IP0SR5", 0xE6060860, 32,
3496 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3497 GROUP(
3498 IP0SR5_31_28
3499 IP0SR5_27_24
3500 IP0SR5_23_20
3501 IP0SR5_19_16
3502 IP0SR5_15_12
3503 IP0SR5_11_8
3504 IP0SR5_7_4
3505 IP0SR5_3_0))
3506 },
3507 { PINMUX_CFG_REG_VAR("IP1SR5", 0xE6060864, 32,
3508 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3509 GROUP(
3510 IP1SR5_31_28
3511 IP1SR5_27_24
3512 IP1SR5_23_20
3513 IP1SR5_19_16
3514 IP1SR5_15_12
3515 IP1SR5_11_8
3516 IP1SR5_7_4
3517 IP1SR5_3_0))
3518 },
3519 { PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32,
3520 GROUP(-12, 4, 4, 4, 4, 4),
3521 GROUP(
3522 /* IP2SR5_31_20 RESERVED */
3523 IP2SR5_19_16
3524 IP2SR5_15_12
3525 IP2SR5_11_8
3526 IP2SR5_7_4
3527 IP2SR5_3_0))
3528 },
3529 { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(
3530 IP0SR6_31_28
3531 IP0SR6_27_24
3532 IP0SR6_23_20
3533 IP0SR6_19_16
3534 IP0SR6_15_12
3535 IP0SR6_11_8
3536 IP0SR6_7_4
3537 IP0SR6_3_0))
3538 },
3539 { PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP(
3540 IP1SR6_31_28
3541 IP1SR6_27_24
3542 IP1SR6_23_20
3543 IP1SR6_19_16
3544 IP1SR6_15_12
3545 IP1SR6_11_8
3546 IP1SR6_7_4
3547 IP1SR6_3_0))
3548 },
3549 { PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32,
3550 GROUP(-12, 4, 4, 4, 4, 4),
3551 GROUP(
3552 /* IP2SR6_31_20 RESERVED */
3553 IP2SR6_19_16
3554 IP2SR6_15_12
3555 IP2SR6_11_8
3556 IP2SR6_7_4
3557 IP2SR6_3_0))
3558 },
3559 { PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP(
3560 IP0SR7_31_28
3561 IP0SR7_27_24
3562 IP0SR7_23_20
3563 IP0SR7_19_16
3564 IP0SR7_15_12
3565 IP0SR7_11_8
3566 IP0SR7_7_4
3567 IP0SR7_3_0))
3568 },
3569 { PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP(
3570 IP1SR7_31_28
3571 IP1SR7_27_24
3572 IP1SR7_23_20
3573 IP1SR7_19_16
3574 IP1SR7_15_12
3575 IP1SR7_11_8
3576 IP1SR7_7_4
3577 IP1SR7_3_0))
3578 },
3579 { PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32,
3580 GROUP(-12, 4, 4, 4, 4, 4),
3581 GROUP(
3582 /* IP2SR7_31_20 RESERVED */
3583 IP2SR7_19_16
3584 IP2SR7_15_12
3585 IP2SR7_11_8
3586 IP2SR7_7_4
3587 IP2SR7_3_0))
3588 },
3589 { PINMUX_CFG_REG("IP0SR8", 0xE6068060, 32, 4, GROUP(
3590 IP0SR8_31_28
3591 IP0SR8_27_24
3592 IP0SR8_23_20
3593 IP0SR8_19_16
3594 IP0SR8_15_12
3595 IP0SR8_11_8
3596 IP0SR8_7_4
3597 IP0SR8_3_0))
3598 },
3599 { PINMUX_CFG_REG_VAR("IP1SR8", 0xE6068064, 32,
3600 GROUP(-8, 4, 4, 4, 4, 4, 4),
3601 GROUP(
3602 /* IP1SR8_31_24 RESERVED */
3603 IP1SR8_23_20
3604 IP1SR8_19_16
3605 IP1SR8_15_12
3606 IP1SR8_11_8
3607 IP1SR8_7_4
3608 IP1SR8_3_0))
3609 },
3610 #undef F_
3611 #undef FM
3612
3613 #define F_(x, y) x,
3614 #define FM(x) FN_##x,
3615 { PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32,
3616 GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3617 GROUP(
3618 /* RESERVED 31-12 */
3619 MOD_SEL8_11
3620 MOD_SEL8_10
3621 MOD_SEL8_9
3622 MOD_SEL8_8
3623 MOD_SEL8_7
3624 MOD_SEL8_6
3625 MOD_SEL8_5
3626 MOD_SEL8_4
3627 MOD_SEL8_3
3628 MOD_SEL8_2
3629 MOD_SEL8_1
3630 MOD_SEL8_0))
3631 },
3632 { },
3633 };
3634
3635 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
3636 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) {
3637 { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */
3638 { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */
3639 { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */
3640 { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */
3641 { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */
3642 { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */
3643 { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */
3644 { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */
3645 } },
3646 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) {
3647 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */
3648 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */
3649 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */
3650 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */
3651 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */
3652 { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */
3653 { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */
3654 { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */
3655 } },
3656 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) {
3657 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */
3658 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */
3659 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */
3660 } },
3661 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) {
3662 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */
3663 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */
3664 { RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */
3665 { RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */
3666 { RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */
3667 { RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */
3668 { RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */
3669 { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */
3670 } },
3671 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) {
3672 { RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */
3673 { RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */
3674 { RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */
3675 { RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */
3676 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */
3677 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */
3678 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */
3679 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */
3680 } },
3681 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) {
3682 { RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */
3683 { RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */
3684 { RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */
3685 { RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */
3686 { RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */
3687 { RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */
3688 { RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */
3689 { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */
3690 } },
3691 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) {
3692 { RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */
3693 { RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */
3694 { RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */
3695 { RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */
3696 { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */
3697 } },
3698 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) {
3699 { RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */
3700 { RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */
3701 { RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */
3702 { RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */
3703 { RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */
3704 { RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */
3705 { RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */
3706 { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */
3707 } },
3708 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) {
3709 { RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */
3710 { RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */
3711 { RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */
3712 { RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */
3713 { RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */
3714 { RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */
3715 { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */
3716 { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */
3717 } },
3718 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) {
3719 { RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD7_RX */
3720 { RCAR_GP_PIN(2, 18), 8, 3 }, /* CANFD7_TX */
3721 { RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD4_RX */
3722 { RCAR_GP_PIN(2, 16), 0, 3 }, /* CANFD4_TX */
3723 } },
3724 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) {
3725 { RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */
3726 { RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */
3727 { RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */
3728 { RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */
3729 { RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */
3730 { RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */
3731 { RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */
3732 { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */
3733 } },
3734 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) {
3735 { RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */
3736 { RCAR_GP_PIN(3, 14), 24, 2 }, /* IPC_CLKOUT */
3737 { RCAR_GP_PIN(3, 13), 20, 2 }, /* IPC_CLKIN */
3738 { RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */
3739 { RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */
3740 { RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */
3741 { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/
3742 { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */
3743 } },
3744 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) {
3745 { RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */
3746 { RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */
3747 { RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */
3748 { RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */
3749 { RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */
3750 { RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */
3751 { RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */
3752 { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */
3753 } },
3754 { PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) {
3755 { RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */
3756 { RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */
3757 { RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */
3758 { RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */
3759 { RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */
3760 { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */
3761 } },
3762 { PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) {
3763 { RCAR_GP_PIN(4, 7), 28, 3 }, /* TSN0_RX_CTL */
3764 { RCAR_GP_PIN(4, 6), 24, 3 }, /* TSN0_AVTP_CAPTURE */
3765 { RCAR_GP_PIN(4, 5), 20, 3 }, /* TSN0_AVTP_MATCH */
3766 { RCAR_GP_PIN(4, 4), 16, 3 }, /* TSN0_LINK */
3767 { RCAR_GP_PIN(4, 3), 12, 3 }, /* TSN0_PHY_INT */
3768 { RCAR_GP_PIN(4, 2), 8, 3 }, /* TSN0_AVTP_PPS1 */
3769 { RCAR_GP_PIN(4, 1), 4, 3 }, /* TSN0_MDC */
3770 { RCAR_GP_PIN(4, 0), 0, 3 }, /* TSN0_MDIO */
3771 } },
3772 { PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) {
3773 { RCAR_GP_PIN(4, 15), 28, 3 }, /* TSN0_TD0 */
3774 { RCAR_GP_PIN(4, 14), 24, 3 }, /* TSN0_TD1 */
3775 { RCAR_GP_PIN(4, 13), 20, 3 }, /* TSN0_RD1 */
3776 { RCAR_GP_PIN(4, 12), 16, 3 }, /* TSN0_TXC */
3777 { RCAR_GP_PIN(4, 11), 12, 3 }, /* TSN0_RXC */
3778 { RCAR_GP_PIN(4, 10), 8, 3 }, /* TSN0_RD0 */
3779 { RCAR_GP_PIN(4, 9), 4, 3 }, /* TSN0_TX_CTL */
3780 { RCAR_GP_PIN(4, 8), 0, 3 }, /* TSN0_AVTP_PPS0 */
3781 } },
3782 { PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) {
3783 { RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */
3784 { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */
3785 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */
3786 { RCAR_GP_PIN(4, 20), 16, 3 }, /* TSN0_TXCREFCLK */
3787 { RCAR_GP_PIN(4, 19), 12, 3 }, /* TSN0_TD2 */
3788 { RCAR_GP_PIN(4, 18), 8, 3 }, /* TSN0_TD3 */
3789 { RCAR_GP_PIN(4, 17), 4, 3 }, /* TSN0_RD2 */
3790 { RCAR_GP_PIN(4, 16), 0, 3 }, /* TSN0_RD3 */
3791 } },
3792 { PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) {
3793 { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */
3794 } },
3795 { PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) {
3796 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */
3797 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */
3798 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */
3799 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */
3800 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */
3801 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */
3802 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */
3803 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */
3804 } },
3805 { PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) {
3806 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */
3807 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */
3808 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */
3809 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */
3810 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */
3811 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */
3812 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */
3813 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */
3814 } },
3815 { PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) {
3816 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */
3817 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */
3818 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */
3819 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */
3820 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */
3821 } },
3822 { PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) {
3823 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */
3824 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */
3825 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */
3826 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */
3827 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */
3828 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */
3829 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */
3830 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */
3831 } },
3832 { PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) {
3833 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */
3834 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */
3835 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */
3836 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */
3837 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */
3838 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */
3839 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */
3840 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */
3841 } },
3842 { PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) {
3843 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */
3844 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */
3845 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */
3846 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */
3847 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */
3848 } },
3849 { PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) {
3850 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */
3851 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */
3852 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */
3853 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */
3854 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */
3855 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */
3856 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */
3857 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */
3858 } },
3859 { PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) {
3860 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */
3861 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */
3862 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */
3863 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */
3864 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */
3865 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */
3866 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */
3867 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */
3868 } },
3869 { PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) {
3870 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */
3871 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */
3872 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */
3873 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */
3874 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */
3875 } },
3876 { PINMUX_DRIVE_REG("DRV0CTRL8", 0xE6068080) {
3877 { RCAR_GP_PIN(8, 7), 28, 3 }, /* SDA3 */
3878 { RCAR_GP_PIN(8, 6), 24, 3 }, /* SCL3 */
3879 { RCAR_GP_PIN(8, 5), 20, 3 }, /* SDA2 */
3880 { RCAR_GP_PIN(8, 4), 16, 3 }, /* SCL2 */
3881 { RCAR_GP_PIN(8, 3), 12, 3 }, /* SDA1 */
3882 { RCAR_GP_PIN(8, 2), 8, 3 }, /* SCL1 */
3883 { RCAR_GP_PIN(8, 1), 4, 3 }, /* SDA0 */
3884 { RCAR_GP_PIN(8, 0), 0, 3 }, /* SCL0 */
3885 } },
3886 { PINMUX_DRIVE_REG("DRV1CTRL8", 0xE6068084) {
3887 { RCAR_GP_PIN(8, 13), 20, 3 }, /* GP8_13 */
3888 { RCAR_GP_PIN(8, 12), 16, 3 }, /* GP8_12 */
3889 { RCAR_GP_PIN(8, 11), 12, 3 }, /* SDA5 */
3890 { RCAR_GP_PIN(8, 10), 8, 3 }, /* SCL5 */
3891 { RCAR_GP_PIN(8, 9), 4, 3 }, /* SDA4 */
3892 { RCAR_GP_PIN(8, 8), 0, 3 }, /* SCL4 */
3893 } },
3894 { },
3895 };
3896
3897 enum ioctrl_regs {
3898 POC0,
3899 POC1,
3900 POC3,
3901 POC4,
3902 POC5,
3903 POC6,
3904 POC7,
3905 POC8,
3906 };
3907
3908 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
3909 [POC0] = { 0xE60500A0, },
3910 [POC1] = { 0xE60508A0, },
3911 [POC3] = { 0xE60588A0, },
3912 [POC4] = { 0xE60600A0, },
3913 [POC5] = { 0xE60608A0, },
3914 [POC6] = { 0xE60610A0, },
3915 [POC7] = { 0xE60618A0, },
3916 [POC8] = { 0xE60680A0, },
3917 { /* sentinel */ },
3918 };
3919
r8a779g0_pin_to_pocctrl(unsigned int pin,u32 * pocctrl)3920 static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
3921 {
3922 int bit = pin & 0x1f;
3923
3924 *pocctrl = pinmux_ioctrl_regs[POC0].reg;
3925 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 18))
3926 return bit;
3927
3928 *pocctrl = pinmux_ioctrl_regs[POC1].reg;
3929 if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 22))
3930 return bit;
3931
3932 *pocctrl = pinmux_ioctrl_regs[POC3].reg;
3933 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 12))
3934 return bit;
3935
3936 *pocctrl = pinmux_ioctrl_regs[POC8].reg;
3937 if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 13))
3938 return bit;
3939
3940 return -EINVAL;
3941 }
3942
3943 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
3944 { PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) {
3945 [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */
3946 [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */
3947 [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */
3948 [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */
3949 [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */
3950 [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */
3951 [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */
3952 [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */
3953 [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */
3954 [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */
3955 [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */
3956 [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */
3957 [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */
3958 [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */
3959 [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */
3960 [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */
3961 [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */
3962 [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */
3963 [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */
3964 [19] = SH_PFC_PIN_NONE,
3965 [20] = SH_PFC_PIN_NONE,
3966 [21] = SH_PFC_PIN_NONE,
3967 [22] = SH_PFC_PIN_NONE,
3968 [23] = SH_PFC_PIN_NONE,
3969 [24] = SH_PFC_PIN_NONE,
3970 [25] = SH_PFC_PIN_NONE,
3971 [26] = SH_PFC_PIN_NONE,
3972 [27] = SH_PFC_PIN_NONE,
3973 [28] = SH_PFC_PIN_NONE,
3974 [29] = SH_PFC_PIN_NONE,
3975 [30] = SH_PFC_PIN_NONE,
3976 [31] = SH_PFC_PIN_NONE,
3977 } },
3978 { PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) {
3979 [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */
3980 [ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */
3981 [ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */
3982 [ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */
3983 [ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */
3984 [ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */
3985 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */
3986 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */
3987 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */
3988 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */
3989 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */
3990 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */
3991 [12] = RCAR_GP_PIN(1, 12), /* HTX0 */
3992 [13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */
3993 [14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */
3994 [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */
3995 [16] = RCAR_GP_PIN(1, 16), /* HRX0 */
3996 [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */
3997 [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */
3998 [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */
3999 [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */
4000 [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */
4001 [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */
4002 [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */
4003 [24] = RCAR_GP_PIN(1, 24), /* HRX3 */
4004 [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */
4005 [26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */
4006 [27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */
4007 [28] = RCAR_GP_PIN(1, 28), /* HTX3 */
4008 [29] = SH_PFC_PIN_NONE,
4009 [30] = SH_PFC_PIN_NONE,
4010 [31] = SH_PFC_PIN_NONE,
4011 } },
4012 { PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) {
4013 [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */
4014 [ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */
4015 [ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */
4016 [ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */
4017 [ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */
4018 [ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */
4019 [ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */
4020 [ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */
4021 [ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */
4022 [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */
4023 [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */
4024 [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */
4025 [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */
4026 [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */
4027 [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */
4028 [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */
4029 [16] = RCAR_GP_PIN(2, 16), /* CANFD4_TX */
4030 [17] = RCAR_GP_PIN(2, 17), /* CANFD4_RX */
4031 [18] = RCAR_GP_PIN(2, 18), /* CANFD7_TX */
4032 [19] = RCAR_GP_PIN(2, 19), /* CANFD7_RX */
4033 [20] = SH_PFC_PIN_NONE,
4034 [21] = SH_PFC_PIN_NONE,
4035 [22] = SH_PFC_PIN_NONE,
4036 [23] = SH_PFC_PIN_NONE,
4037 [24] = SH_PFC_PIN_NONE,
4038 [25] = SH_PFC_PIN_NONE,
4039 [26] = SH_PFC_PIN_NONE,
4040 [27] = SH_PFC_PIN_NONE,
4041 [28] = SH_PFC_PIN_NONE,
4042 [29] = SH_PFC_PIN_NONE,
4043 [30] = SH_PFC_PIN_NONE,
4044 [31] = SH_PFC_PIN_NONE,
4045 } },
4046 { PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) {
4047 [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */
4048 [ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */
4049 [ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */
4050 [ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */
4051 [ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */
4052 [ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */
4053 [ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */
4054 [ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */
4055 [ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */
4056 [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */
4057 [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */
4058 [11] = RCAR_GP_PIN(3, 11), /* SD_CD */
4059 [12] = RCAR_GP_PIN(3, 12), /* SD_WP */
4060 [13] = RCAR_GP_PIN(3, 13), /* IPC_CLKIN */
4061 [14] = RCAR_GP_PIN(3, 14), /* IPC_CLKOUT */
4062 [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */
4063 [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */
4064 [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */
4065 [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */
4066 [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */
4067 [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */
4068 [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */
4069 [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */
4070 [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */
4071 [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */
4072 [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */
4073 [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */
4074 [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */
4075 [28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */
4076 [29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */
4077 [30] = SH_PFC_PIN_NONE,
4078 [31] = SH_PFC_PIN_NONE,
4079 } },
4080 { PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) {
4081 [ 0] = RCAR_GP_PIN(4, 0), /* TSN0_MDIO */
4082 [ 1] = RCAR_GP_PIN(4, 1), /* TSN0_MDC */
4083 [ 2] = RCAR_GP_PIN(4, 2), /* TSN0_AVTP_PPS1 */
4084 [ 3] = RCAR_GP_PIN(4, 3), /* TSN0_PHY_INT */
4085 [ 4] = RCAR_GP_PIN(4, 4), /* TSN0_LINK */
4086 [ 5] = RCAR_GP_PIN(4, 5), /* TSN0_AVTP_MATCH */
4087 [ 6] = RCAR_GP_PIN(4, 6), /* TSN0_AVTP_CAPTURE */
4088 [ 7] = RCAR_GP_PIN(4, 7), /* TSN0_RX_CTL */
4089 [ 8] = RCAR_GP_PIN(4, 8), /* TSN0_AVTP_PPS0 */
4090 [ 9] = RCAR_GP_PIN(4, 9), /* TSN0_TX_CTL */
4091 [10] = RCAR_GP_PIN(4, 10), /* TSN0_RD0 */
4092 [11] = RCAR_GP_PIN(4, 11), /* TSN0_RXC */
4093 [12] = RCAR_GP_PIN(4, 12), /* TSN0_TXC */
4094 [13] = RCAR_GP_PIN(4, 13), /* TSN0_RD1 */
4095 [14] = RCAR_GP_PIN(4, 14), /* TSN0_TD1 */
4096 [15] = RCAR_GP_PIN(4, 15), /* TSN0_TD0 */
4097 [16] = RCAR_GP_PIN(4, 16), /* TSN0_RD3 */
4098 [17] = RCAR_GP_PIN(4, 17), /* TSN0_RD2 */
4099 [18] = RCAR_GP_PIN(4, 18), /* TSN0_TD3 */
4100 [19] = RCAR_GP_PIN(4, 19), /* TSN0_TD2 */
4101 [20] = RCAR_GP_PIN(4, 20), /* TSN0_TXCREFCLK */
4102 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */
4103 [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */
4104 [23] = RCAR_GP_PIN(4, 23), /* AVS0 */
4105 [24] = RCAR_GP_PIN(4, 24), /* AVS1 */
4106 [25] = SH_PFC_PIN_NONE,
4107 [26] = SH_PFC_PIN_NONE,
4108 [27] = SH_PFC_PIN_NONE,
4109 [28] = SH_PFC_PIN_NONE,
4110 [29] = SH_PFC_PIN_NONE,
4111 [30] = SH_PFC_PIN_NONE,
4112 [31] = SH_PFC_PIN_NONE,
4113 } },
4114 { PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) {
4115 [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */
4116 [ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */
4117 [ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */
4118 [ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */
4119 [ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */
4120 [ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */
4121 [ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */
4122 [ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */
4123 [ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */
4124 [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */
4125 [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */
4126 [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */
4127 [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */
4128 [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */
4129 [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */
4130 [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */
4131 [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */
4132 [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */
4133 [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */
4134 [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */
4135 [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */
4136 [21] = SH_PFC_PIN_NONE,
4137 [22] = SH_PFC_PIN_NONE,
4138 [23] = SH_PFC_PIN_NONE,
4139 [24] = SH_PFC_PIN_NONE,
4140 [25] = SH_PFC_PIN_NONE,
4141 [26] = SH_PFC_PIN_NONE,
4142 [27] = SH_PFC_PIN_NONE,
4143 [28] = SH_PFC_PIN_NONE,
4144 [29] = SH_PFC_PIN_NONE,
4145 [30] = SH_PFC_PIN_NONE,
4146 [31] = SH_PFC_PIN_NONE,
4147 } },
4148 { PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) {
4149 [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */
4150 [ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */
4151 [ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */
4152 [ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */
4153 [ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */
4154 [ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */
4155 [ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */
4156 [ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */
4157 [ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */
4158 [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */
4159 [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */
4160 [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */
4161 [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */
4162 [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */
4163 [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/
4164 [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */
4165 [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */
4166 [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */
4167 [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */
4168 [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */
4169 [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */
4170 [21] = SH_PFC_PIN_NONE,
4171 [22] = SH_PFC_PIN_NONE,
4172 [23] = SH_PFC_PIN_NONE,
4173 [24] = SH_PFC_PIN_NONE,
4174 [25] = SH_PFC_PIN_NONE,
4175 [26] = SH_PFC_PIN_NONE,
4176 [27] = SH_PFC_PIN_NONE,
4177 [28] = SH_PFC_PIN_NONE,
4178 [29] = SH_PFC_PIN_NONE,
4179 [30] = SH_PFC_PIN_NONE,
4180 [31] = SH_PFC_PIN_NONE,
4181 } },
4182 { PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) {
4183 [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */
4184 [ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */
4185 [ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */
4186 [ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */
4187 [ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */
4188 [ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */
4189 [ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */
4190 [ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */
4191 [ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */
4192 [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */
4193 [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */
4194 [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */
4195 [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */
4196 [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */
4197 [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */
4198 [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */
4199 [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */
4200 [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */
4201 [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */
4202 [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */
4203 [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */
4204 [21] = SH_PFC_PIN_NONE,
4205 [22] = SH_PFC_PIN_NONE,
4206 [23] = SH_PFC_PIN_NONE,
4207 [24] = SH_PFC_PIN_NONE,
4208 [25] = SH_PFC_PIN_NONE,
4209 [26] = SH_PFC_PIN_NONE,
4210 [27] = SH_PFC_PIN_NONE,
4211 [28] = SH_PFC_PIN_NONE,
4212 [29] = SH_PFC_PIN_NONE,
4213 [30] = SH_PFC_PIN_NONE,
4214 [31] = SH_PFC_PIN_NONE,
4215 } },
4216 { PINMUX_BIAS_REG("PUEN8", 0xE60680C0, "PUD8", 0xE60680E0) {
4217 [ 0] = RCAR_GP_PIN(8, 0), /* SCL0 */
4218 [ 1] = RCAR_GP_PIN(8, 1), /* SDA0 */
4219 [ 2] = RCAR_GP_PIN(8, 2), /* SCL1 */
4220 [ 3] = RCAR_GP_PIN(8, 3), /* SDA1 */
4221 [ 4] = RCAR_GP_PIN(8, 4), /* SCL2 */
4222 [ 5] = RCAR_GP_PIN(8, 5), /* SDA2 */
4223 [ 6] = RCAR_GP_PIN(8, 6), /* SCL3 */
4224 [ 7] = RCAR_GP_PIN(8, 7), /* SDA3 */
4225 [ 8] = RCAR_GP_PIN(8, 8), /* SCL4 */
4226 [ 9] = RCAR_GP_PIN(8, 9), /* SDA4 */
4227 [10] = RCAR_GP_PIN(8, 10), /* SCL5 */
4228 [11] = RCAR_GP_PIN(8, 11), /* SDA5 */
4229 [12] = RCAR_GP_PIN(8, 12), /* GP8_12 */
4230 [13] = RCAR_GP_PIN(8, 13), /* GP8_13 */
4231 [14] = SH_PFC_PIN_NONE,
4232 [15] = SH_PFC_PIN_NONE,
4233 [16] = SH_PFC_PIN_NONE,
4234 [17] = SH_PFC_PIN_NONE,
4235 [18] = SH_PFC_PIN_NONE,
4236 [19] = SH_PFC_PIN_NONE,
4237 [20] = SH_PFC_PIN_NONE,
4238 [21] = SH_PFC_PIN_NONE,
4239 [22] = SH_PFC_PIN_NONE,
4240 [23] = SH_PFC_PIN_NONE,
4241 [24] = SH_PFC_PIN_NONE,
4242 [25] = SH_PFC_PIN_NONE,
4243 [26] = SH_PFC_PIN_NONE,
4244 [27] = SH_PFC_PIN_NONE,
4245 [28] = SH_PFC_PIN_NONE,
4246 [29] = SH_PFC_PIN_NONE,
4247 [30] = SH_PFC_PIN_NONE,
4248 [31] = SH_PFC_PIN_NONE,
4249 } },
4250 { /* sentinel */ },
4251 };
4252
4253 static const struct sh_pfc_soc_operations r8a779g0_pin_ops = {
4254 .pin_to_pocctrl = r8a779g0_pin_to_pocctrl,
4255 .get_bias = rcar_pinmux_get_bias,
4256 .set_bias = rcar_pinmux_set_bias,
4257 };
4258
4259 const struct sh_pfc_soc_info r8a779g0_pinmux_info = {
4260 .name = "r8a779g0_pfc",
4261 .ops = &r8a779g0_pin_ops,
4262 .unlock_reg = 0x1ff, /* PMMRn mask */
4263
4264 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4265
4266 .pins = pinmux_pins,
4267 .nr_pins = ARRAY_SIZE(pinmux_pins),
4268 .groups = pinmux_groups,
4269 .nr_groups = ARRAY_SIZE(pinmux_groups),
4270 .functions = pinmux_functions,
4271 .nr_functions = ARRAY_SIZE(pinmux_functions),
4272
4273 .cfg_regs = pinmux_config_regs,
4274 .drive_regs = pinmux_drive_regs,
4275 .bias_regs = pinmux_bias_regs,
4276 .ioctrl_regs = pinmux_ioctrl_regs,
4277
4278 .pinmux_data = pinmux_data,
4279 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
4280 };
4281