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Searched refs:APBC_TWSI0 (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/mmp/
Dclk-of-pxa168.c30 #define APBC_TWSI0 0x2c macro
161 …{0, "twsi0_mux", twsi_parent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI0
180 …{PXA168_CLK_TWSI0, "twsi0_clk", "twsi0_mux", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &t…
Dclk-pxa910.c21 #define APBC_TWSI0 0x2c macro
167 apbc_base + APBC_TWSI0, 10, 0, &clk_lock); in pxa910_clk_init()
Dclk-of-pxa910.c23 #define APBC_TWSI0 0x2c macro
139 …{PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, …
Dclk-pxa168.c21 #define APBC_TWSI0 0x2c macro
162 apbc_base + APBC_TWSI0, 10, 0, &clk_lock); in pxa168_clk_init()
Dclk-mmp2.c21 #define APBC_TWSI0 0x4 macro
191 apbc_base + APBC_TWSI0, 10, 0, &clk_lock); in mmp2_clk_init()
Dclk-of-mmp2.c26 #define APBC_TWSI0 0x4 macro
249 …{MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_…