1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * pxa168 clock framework source file
4 *
5 * Copyright (C) 2012 Marvell
6 * Chao Xie <xiechao.mail@gmail.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk/mmp.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/spinlock.h>
14 #include <linux/io.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17
18 #include "clk.h"
19
20 #define APBC_RTC 0x28
21 #define APBC_TWSI0 0x2c
22 #define APBC_KPC 0x30
23 #define APBC_UART0 0x0
24 #define APBC_UART1 0x4
25 #define APBC_GPIO 0x8
26 #define APBC_PWM0 0xc
27 #define APBC_PWM1 0x10
28 #define APBC_PWM2 0x14
29 #define APBC_PWM3 0x18
30 #define APBC_SSP0 0x81c
31 #define APBC_SSP1 0x820
32 #define APBC_SSP2 0x84c
33 #define APBC_SSP3 0x858
34 #define APBC_SSP4 0x85c
35 #define APBC_TWSI1 0x6c
36 #define APBC_UART2 0x70
37 #define APMU_SDH0 0x54
38 #define APMU_SDH1 0x58
39 #define APMU_USB 0x5c
40 #define APMU_DISP0 0x4c
41 #define APMU_CCIC0 0x50
42 #define APMU_DFC 0x60
43 #define MPMU_UART_PLL 0x14
44
45 static DEFINE_SPINLOCK(clk_lock);
46
47 static struct mmp_clk_factor_masks uart_factor_masks = {
48 .factor = 2,
49 .num_mask = 0x1fff,
50 .den_mask = 0x1fff,
51 .num_shift = 16,
52 .den_shift = 0,
53 };
54
55 static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
56 {.num = 8125, .den = 1536}, /*14.745MHZ */
57 };
58
59 static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
60 static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
61 static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
62 static const char *disp_parent[] = {"pll1_2", "pll1_12"};
63 static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
64 static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
65
pxa168_clk_init(phys_addr_t mpmu_phys,phys_addr_t apmu_phys,phys_addr_t apbc_phys)66 void __init pxa168_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
67 phys_addr_t apbc_phys)
68 {
69 struct clk *clk;
70 struct clk *uart_pll;
71 void __iomem *mpmu_base;
72 void __iomem *apmu_base;
73 void __iomem *apbc_base;
74
75 mpmu_base = ioremap(mpmu_phys, SZ_4K);
76 if (!mpmu_base) {
77 pr_err("error to ioremap MPMU base\n");
78 return;
79 }
80
81 apmu_base = ioremap(apmu_phys, SZ_4K);
82 if (!apmu_base) {
83 pr_err("error to ioremap APMU base\n");
84 return;
85 }
86
87 apbc_base = ioremap(apbc_phys, SZ_4K);
88 if (!apbc_base) {
89 pr_err("error to ioremap APBC base\n");
90 return;
91 }
92
93 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
94 clk_register_clkdev(clk, "clk32", NULL);
95
96 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
97 clk_register_clkdev(clk, "vctcxo", NULL);
98
99 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000);
100 clk_register_clkdev(clk, "pll1", NULL);
101
102 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
103 CLK_SET_RATE_PARENT, 1, 2);
104 clk_register_clkdev(clk, "pll1_2", NULL);
105
106 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
107 CLK_SET_RATE_PARENT, 1, 2);
108 clk_register_clkdev(clk, "pll1_4", NULL);
109
110 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
111 CLK_SET_RATE_PARENT, 1, 2);
112 clk_register_clkdev(clk, "pll1_8", NULL);
113
114 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
115 CLK_SET_RATE_PARENT, 1, 2);
116 clk_register_clkdev(clk, "pll1_16", NULL);
117
118 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
119 CLK_SET_RATE_PARENT, 1, 3);
120 clk_register_clkdev(clk, "pll1_6", NULL);
121
122 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
123 CLK_SET_RATE_PARENT, 1, 2);
124 clk_register_clkdev(clk, "pll1_12", NULL);
125
126 clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
127 CLK_SET_RATE_PARENT, 1, 2);
128 clk_register_clkdev(clk, "pll1_24", NULL);
129
130 clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
131 CLK_SET_RATE_PARENT, 1, 2);
132 clk_register_clkdev(clk, "pll1_48", NULL);
133
134 clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
135 CLK_SET_RATE_PARENT, 1, 2);
136 clk_register_clkdev(clk, "pll1_96", NULL);
137
138 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
139 CLK_SET_RATE_PARENT, 1, 13);
140 clk_register_clkdev(clk, "pll1_13", NULL);
141
142 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
143 CLK_SET_RATE_PARENT, 2, 3);
144 clk_register_clkdev(clk, "pll1_13_1_5", NULL);
145
146 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
147 CLK_SET_RATE_PARENT, 2, 3);
148 clk_register_clkdev(clk, "pll1_2_1_5", NULL);
149
150 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
151 CLK_SET_RATE_PARENT, 3, 16);
152 clk_register_clkdev(clk, "pll1_3_16", NULL);
153
154 uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
155 mpmu_base + MPMU_UART_PLL,
156 &uart_factor_masks, uart_factor_tbl,
157 ARRAY_SIZE(uart_factor_tbl), &clk_lock);
158 clk_set_rate(uart_pll, 14745600);
159 clk_register_clkdev(uart_pll, "uart_pll", NULL);
160
161 clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
162 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
163 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
164
165 clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
166 apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
167 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
168
169 clk = mmp_clk_register_apbc("gpio", "vctcxo",
170 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
171 clk_register_clkdev(clk, NULL, "mmp-gpio");
172
173 clk = mmp_clk_register_apbc("kpc", "clk32",
174 apbc_base + APBC_KPC, 10, 0, &clk_lock);
175 clk_register_clkdev(clk, NULL, "pxa27x-keypad");
176
177 clk = mmp_clk_register_apbc("rtc", "clk32",
178 apbc_base + APBC_RTC, 10, 0, &clk_lock);
179 clk_register_clkdev(clk, NULL, "sa1100-rtc");
180
181 clk = mmp_clk_register_apbc("pwm0", "pll1_48",
182 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
183 clk_register_clkdev(clk, NULL, "pxa168-pwm.0");
184
185 clk = mmp_clk_register_apbc("pwm1", "pll1_48",
186 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
187 clk_register_clkdev(clk, NULL, "pxa168-pwm.1");
188
189 clk = mmp_clk_register_apbc("pwm2", "pll1_48",
190 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
191 clk_register_clkdev(clk, NULL, "pxa168-pwm.2");
192
193 clk = mmp_clk_register_apbc("pwm3", "pll1_48",
194 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
195 clk_register_clkdev(clk, NULL, "pxa168-pwm.3");
196
197 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
198 ARRAY_SIZE(uart_parent),
199 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
200 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
201 clk_set_parent(clk, uart_pll);
202 clk_register_clkdev(clk, "uart_mux.0", NULL);
203
204 clk = mmp_clk_register_apbc("uart0", "uart0_mux",
205 apbc_base + APBC_UART0, 10, 0, &clk_lock);
206 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
207
208 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
209 ARRAY_SIZE(uart_parent),
210 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
211 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
212 clk_set_parent(clk, uart_pll);
213 clk_register_clkdev(clk, "uart_mux.1", NULL);
214
215 clk = mmp_clk_register_apbc("uart1", "uart1_mux",
216 apbc_base + APBC_UART1, 10, 0, &clk_lock);
217 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
218
219 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
220 ARRAY_SIZE(uart_parent),
221 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
222 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
223 clk_set_parent(clk, uart_pll);
224 clk_register_clkdev(clk, "uart_mux.2", NULL);
225
226 clk = mmp_clk_register_apbc("uart2", "uart2_mux",
227 apbc_base + APBC_UART2, 10, 0, &clk_lock);
228 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
229
230 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
231 ARRAY_SIZE(ssp_parent),
232 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
233 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
234 clk_register_clkdev(clk, "uart_mux.0", NULL);
235
236 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0,
237 10, 0, &clk_lock);
238 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
239
240 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
241 ARRAY_SIZE(ssp_parent),
242 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
243 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
244 clk_register_clkdev(clk, "ssp_mux.1", NULL);
245
246 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1,
247 10, 0, &clk_lock);
248 clk_register_clkdev(clk, NULL, "mmp-ssp.1");
249
250 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
251 ARRAY_SIZE(ssp_parent),
252 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
253 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
254 clk_register_clkdev(clk, "ssp_mux.2", NULL);
255
256 clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2,
257 10, 0, &clk_lock);
258 clk_register_clkdev(clk, NULL, "mmp-ssp.2");
259
260 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
261 ARRAY_SIZE(ssp_parent),
262 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
263 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
264 clk_register_clkdev(clk, "ssp_mux.3", NULL);
265
266 clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3,
267 10, 0, &clk_lock);
268 clk_register_clkdev(clk, NULL, "mmp-ssp.3");
269
270 clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent,
271 ARRAY_SIZE(ssp_parent),
272 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
273 apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
274 clk_register_clkdev(clk, "ssp_mux.4", NULL);
275
276 clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4,
277 10, 0, &clk_lock);
278 clk_register_clkdev(clk, NULL, "mmp-ssp.4");
279
280 clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC,
281 0x19b, &clk_lock);
282 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
283
284 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
285 ARRAY_SIZE(sdh_parent),
286 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
287 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
288 clk_register_clkdev(clk, "sdh0_mux", NULL);
289
290 clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0,
291 0x1b, &clk_lock);
292 clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
293
294 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
295 ARRAY_SIZE(sdh_parent),
296 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
297 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
298 clk_register_clkdev(clk, "sdh1_mux", NULL);
299
300 clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1,
301 0x1b, &clk_lock);
302 clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
303
304 clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
305 0x9, &clk_lock);
306 clk_register_clkdev(clk, "usb_clk", NULL);
307
308 clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB,
309 0x12, &clk_lock);
310 clk_register_clkdev(clk, "sph_clk", NULL);
311
312 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
313 ARRAY_SIZE(disp_parent),
314 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
315 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
316 clk_register_clkdev(clk, "disp_mux.0", NULL);
317
318 clk = mmp_clk_register_apmu("disp0", "disp0_mux",
319 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
320 clk_register_clkdev(clk, "fnclk", "mmp-disp.0");
321
322 clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux",
323 apmu_base + APMU_DISP0, 0x24, &clk_lock);
324 clk_register_clkdev(clk, "hclk", "mmp-disp.0");
325
326 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
327 ARRAY_SIZE(ccic_parent),
328 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
329 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
330 clk_register_clkdev(clk, "ccic_mux.0", NULL);
331
332 clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
333 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
334 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
335
336 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
337 ARRAY_SIZE(ccic_phy_parent),
338 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
339 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
340 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
341
342 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
343 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
344 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
345
346 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
347 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
348 10, 5, 0, &clk_lock);
349 clk_register_clkdev(clk, "sphyclk_div", NULL);
350
351 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
352 apmu_base + APMU_CCIC0, 0x300, &clk_lock);
353 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
354 }
355