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Searched refs:APBC_UART0 (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/mmp/
Dclk-pxa910.c23 #define APBC_UART0 0x0 macro
205 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); in pxa910_clk_init()
210 apbc_base + APBC_UART0, 10, 0, &clk_lock); in pxa910_clk_init()
Dclk-of-pxa910.c25 #define APBC_UART0 0x0 macro
126 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0
148 …{PXA910_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &u…
Dclk-of-pxa168.c22 #define APBC_UART0 0x0 macro
168 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0
189 …{PXA168_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &u…
Dclk-pxa168.c23 #define APBC_UART0 0x0 macro
200 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); in pxa168_clk_init()
205 apbc_base + APBC_UART0, 10, 0, &clk_lock); in pxa168_clk_init()
Dclk-mmp2.c28 #define APBC_UART0 0x2c macro
245 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); in mmp2_clk_init()
250 apbc_base + APBC_UART0, 10, 0, &clk_lock); in mmp2_clk_init()
Dclk-of-mmp2.c34 #define APBC_UART0 0x2c macro
237 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0
263 …{MMP2_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 0x3, 0x0, 0, &uar…