Searched refs:APBC_UART2 (Results 1 – 4 of 4) sorted by relevance
| /drivers/clk/mmp/ |
| D | clk-of-pxa168.c | 37 #define APBC_UART2 0x70 macro
170 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2…
191 …{PXA168_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x3, 0x3, 0x0, 0, &u…
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| D | clk-pxa168.c | 36 #define APBC_UART2 0x70 macro
222 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); in pxa168_clk_init()
227 apbc_base + APBC_UART2, 10, 0, &clk_lock); in pxa168_clk_init()
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| D | clk-mmp2.c | 30 #define APBC_UART2 0x34 macro
267 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); in mmp2_clk_init()
272 apbc_base + APBC_UART2, 10, 0, &clk_lock); in mmp2_clk_init()
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| D | clk-of-mmp2.c | 36 #define APBC_UART2 0x34 macro
239 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2…
265 …{MMP2_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x7, 0x3, 0x0, 0, &uar…
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