| /drivers/clk/mmp/ |
| D | clk-pxa910.c | 39 #define APMU_CCIC0 0x50 macro
300 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); in pxa910_clk_init()
304 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); in pxa910_clk_init()
310 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); in pxa910_clk_init()
314 apmu_base + APMU_CCIC0, 0x24, &clk_lock); in pxa910_clk_init()
318 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in pxa910_clk_init()
323 apmu_base + APMU_CCIC0, 0x300, &clk_lock); in pxa910_clk_init()
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| D | clk-of-pxa910.c | 43 #define APMU_CCIC0 0x50 macro
196 …{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0…
197 …_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0…
201 {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
212 …{PXA910_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, …
213 …{PXA910_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x…
214 …{PXA910_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300…
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| D | clk-of-pxa168.c | 45 #define APMU_CCIC0 0x50 macro
237 …{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0…
238 …_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0…
242 {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
257 …{PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, …
258 …{PXA168_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x…
259 …{PXA168_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300…
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| D | clk-pxa168.c | 41 #define APMU_CCIC0 0x50 macro
329 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); in pxa168_clk_init()
333 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); in pxa168_clk_init()
339 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); in pxa168_clk_init()
343 apmu_base + APMU_CCIC0, 0x24, &clk_lock); in pxa168_clk_init()
347 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in pxa168_clk_init()
352 apmu_base + APMU_CCIC0, 0x300, &clk_lock); in pxa168_clk_init()
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| D | clk-mmp2.c | 48 #define APMU_CCIC0 0x50 macro
396 apmu_base + APMU_CCIC0, 0x1800, &clk_lock); in mmp2_clk_init()
402 apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock); in mmp2_clk_init()
406 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in mmp2_clk_init()
411 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); in mmp2_clk_init()
415 apmu_base + APMU_CCIC0, 0x24, &clk_lock); in mmp2_clk_init()
419 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in mmp2_clk_init()
424 apmu_base + APMU_CCIC0, 0x300, &clk_lock); in mmp2_clk_init()
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| D | clk-of-mmp2.c | 59 #define APMU_CCIC0 0x50 macro
350 {0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
372 …{MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800,…
373 …{MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0…
374 …{MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24…
375 …{MMP2_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, …
404 ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0; in mmp2_axi_periph_clk_init()
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