Searched refs:APMU_DISP0 (Results 1 – 6 of 6) sorted by relevance
| /drivers/clk/mmp/ |
| D | clk-mmp2.c | 46 #define APMU_DISP0 0x4c macro
360 apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock); in mmp2_clk_init()
364 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0, in mmp2_clk_init()
369 apmu_base + APMU_DISP0, 0x1b, &clk_lock); in mmp2_clk_init()
373 apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock); in mmp2_clk_init()
377 apmu_base + APMU_DISP0, 0x1024, &clk_lock); in mmp2_clk_init()
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| D | clk-of-mmp2.c | 57 #define APMU_DISP0 0x4c macro
333 …disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0…
347 …{0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, CLK_DIVIDER_ONE_BASED, &disp0…
348 {0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock},
368 …{MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x12, 0x12, 0x0, 0, &d…
369 …{MMP2_CLK_DISP0_LCDC, "disp0_lcdc_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x09, 0x09, …
370 …{MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024,…
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| D | clk-pxa168.c | 40 #define APMU_DISP0 0x4c macro
315 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); in pxa168_clk_init()
319 apmu_base + APMU_DISP0, 0x1b, &clk_lock); in pxa168_clk_init()
323 apmu_base + APMU_DISP0, 0x24, &clk_lock); in pxa168_clk_init()
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| D | clk-pxa910.c | 38 #define APMU_DISP0 0x4c macro
290 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); in pxa910_clk_init()
294 apmu_base + APMU_DISP0, 0x1b, &clk_lock); in pxa910_clk_init()
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| D | clk-of-pxa910.c | 42 #define APMU_DISP0 0x4c macro
195 …{0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0…
211 …{PXA910_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, …
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| D | clk-of-pxa168.c | 44 #define APMU_DISP0 0x4c macro
236 …{0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0…
256 …{PXA168_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, …
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