Home
last modified time | relevance | path

Searched refs:MUX_GATE_CLR_SET_UPD (Results 1 – 10 of 10) sorted by relevance

/drivers/clk/mediatek/
Dclk-mt8195-topckgen.c873 MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
875 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
877 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
879 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
882 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
884 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
886 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
888 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
891 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
893 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2",
[all …]
Dclk-mt8186-topckgen.c511 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "top_mfg",
513 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
516 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1, "top_camtg1",
518 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
520 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
522 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "top_camtg4",
525 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "top_camtg5",
527 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6, "top_camtg6",
529 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
531 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
[all …]
Dclk-mt7986-topckgen.c177 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
179 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
181 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
183 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
186 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
188 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
190 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
192 MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
196 MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
199 MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
[all …]
Dclk-mt6779.c644 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
646 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
649 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents,
651 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents,
653 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents,
655 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents,
658 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents,
660 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents,
662 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents,
664 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "dsp2_sel", dsp2_parents,
[all …]
Dclk-mt8192.c560 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel",
566 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel",
568 MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel",
570 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel",
572 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel",
575 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel",
577 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel",
579 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel",
581 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel",
584 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel",
[all …]
Dclk-mt8183.c526 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
529 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
532 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
536 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel",
539 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel",
542 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel",
545 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel",
549 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel",
552 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel",
555 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel",
[all …]
Dclk-mt8365.c421 MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040,
423 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044,
425 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x040,
428 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050,
430 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x050,
432 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
434 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
437 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060,
439 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060,
441 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HC_SEL, "msdc50_0_hc_sel",
[all …]
Dclk-mt6765.c374 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
377 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0,
381 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, CLK_CFG_1,
384 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, CLK_CFG_1,
387 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
390 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
394 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
397 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", camtg_parents,
400 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
403 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, CLK_CFG_2,
[all …]
Dclk-mt7986-infracfg.c42 MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
45 MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
48 MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
51 MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
54 MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
57 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
60 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
63 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
67 MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
Dclk-mux.h70 #define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ macro