1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright (c) 2018 MediaTek Inc.
4 // Author: Weiyi Lu <weiyi.lu@mediatek.com>
5
6 #include <linux/delay.h>
7 #include <linux/mfd/syscon.h>
8 #include <linux/of.h>
9 #include <linux/of_address.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/slab.h>
13
14 #include "clk-gate.h"
15 #include "clk-mtk.h"
16 #include "clk-mux.h"
17 #include "clk-pll.h"
18
19 #include <dt-bindings/clock/mt8183-clk.h>
20
21 static DEFINE_SPINLOCK(mt8183_clk_lock);
22
23 static const struct mtk_fixed_clk top_fixed_clks[] = {
24 FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
25 FIXED_CLK(CLK_TOP_ULPOSC, "osc", NULL, 250000),
26 FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000),
27 };
28
29 static const struct mtk_fixed_factor top_early_divs[] = {
30 FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
31 };
32
33 static const struct mtk_fixed_factor top_divs[] = {
34 FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1,
35 2),
36 FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1,
37 1),
38 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
39 2),
40 FACTOR(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1,
41 2),
42 FACTOR(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1,
43 4),
44 FACTOR(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1,
45 8),
46 FACTOR(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1,
47 16),
48 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1,
49 3),
50 FACTOR(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1,
51 2),
52 FACTOR(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1,
53 4),
54 FACTOR(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1,
55 8),
56 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1,
57 5),
58 FACTOR(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1,
59 2),
60 FACTOR(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1,
61 4),
62 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1,
63 7),
64 FACTOR(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1,
65 2),
66 FACTOR(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1,
67 4),
68 FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1,
69 1),
70 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
71 2),
72 FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1,
73 2),
74 FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1,
75 4),
76 FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1,
77 8),
78 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1,
79 3),
80 FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1,
81 2),
82 FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1,
83 4),
84 FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1,
85 8),
86 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1,
87 5),
88 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1,
89 2),
90 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1,
91 4),
92 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1,
93 8),
94 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1,
95 7),
96 FACTOR(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1,
97 1),
98 FACTOR(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1,
99 2),
100 FACTOR(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1,
101 4),
102 FACTOR(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1,
103 8),
104 FACTOR(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1,
105 16),
106 FACTOR(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1,
107 32),
108 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1,
109 1),
110 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1,
111 2),
112 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1,
113 4),
114 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1,
115 8),
116 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1,
117 1),
118 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1,
119 2),
120 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1,
121 4),
122 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1,
123 8),
124 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1,
125 1),
126 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
127 2),
128 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1,
129 4),
130 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1,
131 8),
132 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1,
133 16),
134 FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1,
135 1),
136 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1,
137 4),
138 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1,
139 2),
140 FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1,
141 4),
142 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1,
143 5),
144 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1,
145 2),
146 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1,
147 4),
148 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1,
149 6),
150 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1,
151 7),
152 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1,
153 1),
154 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1,
155 1),
156 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1,
157 2),
158 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1,
159 4),
160 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1,
161 8),
162 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1,
163 16),
164 FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1,
165 1),
166 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1,
167 2),
168 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1,
169 4),
170 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1,
171 8),
172 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1,
173 16),
174 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1,
175 2),
176 FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1,
177 16),
178 };
179
180 static const char * const axi_parents[] = {
181 "clk26m",
182 "syspll_d2_d4",
183 "syspll_d7",
184 "osc_d4"
185 };
186
187 static const char * const mm_parents[] = {
188 "clk26m",
189 "mmpll_d7",
190 "syspll_d3",
191 "univpll_d2_d2",
192 "syspll_d2_d2",
193 "syspll_d3_d2"
194 };
195
196 static const char * const img_parents[] = {
197 "clk26m",
198 "mmpll_d6",
199 "univpll_d3",
200 "syspll_d3",
201 "univpll_d2_d2",
202 "syspll_d2_d2",
203 "univpll_d3_d2",
204 "syspll_d3_d2"
205 };
206
207 static const char * const cam_parents[] = {
208 "clk26m",
209 "syspll_d2",
210 "mmpll_d6",
211 "syspll_d3",
212 "mmpll_d7",
213 "univpll_d3",
214 "univpll_d2_d2",
215 "syspll_d2_d2",
216 "syspll_d3_d2",
217 "univpll_d3_d2"
218 };
219
220 static const char * const dsp_parents[] = {
221 "clk26m",
222 "mmpll_d6",
223 "mmpll_d7",
224 "univpll_d3",
225 "syspll_d3",
226 "univpll_d2_d2",
227 "syspll_d2_d2",
228 "univpll_d3_d2",
229 "syspll_d3_d2"
230 };
231
232 static const char * const dsp1_parents[] = {
233 "clk26m",
234 "mmpll_d6",
235 "mmpll_d7",
236 "univpll_d3",
237 "syspll_d3",
238 "univpll_d2_d2",
239 "syspll_d2_d2",
240 "univpll_d3_d2",
241 "syspll_d3_d2"
242 };
243
244 static const char * const dsp2_parents[] = {
245 "clk26m",
246 "mmpll_d6",
247 "mmpll_d7",
248 "univpll_d3",
249 "syspll_d3",
250 "univpll_d2_d2",
251 "syspll_d2_d2",
252 "univpll_d3_d2",
253 "syspll_d3_d2"
254 };
255
256 static const char * const ipu_if_parents[] = {
257 "clk26m",
258 "mmpll_d6",
259 "mmpll_d7",
260 "univpll_d3",
261 "syspll_d3",
262 "univpll_d2_d2",
263 "syspll_d2_d2",
264 "univpll_d3_d2",
265 "syspll_d3_d2"
266 };
267
268 static const char * const mfg_parents[] = {
269 "clk26m",
270 "mfgpll_ck",
271 "univpll_d3",
272 "syspll_d3"
273 };
274
275 static const char * const f52m_mfg_parents[] = {
276 "clk26m",
277 "univpll_d3_d2",
278 "univpll_d3_d4",
279 "univpll_d3_d8"
280 };
281
282 static const char * const camtg_parents[] = {
283 "clk26m",
284 "univ_192m_d8",
285 "univpll_d3_d8",
286 "univ_192m_d4",
287 "univpll_d3_d16",
288 "csw_f26m_ck_d2",
289 "univ_192m_d16",
290 "univ_192m_d32"
291 };
292
293 static const char * const camtg2_parents[] = {
294 "clk26m",
295 "univ_192m_d8",
296 "univpll_d3_d8",
297 "univ_192m_d4",
298 "univpll_d3_d16",
299 "csw_f26m_ck_d2",
300 "univ_192m_d16",
301 "univ_192m_d32"
302 };
303
304 static const char * const camtg3_parents[] = {
305 "clk26m",
306 "univ_192m_d8",
307 "univpll_d3_d8",
308 "univ_192m_d4",
309 "univpll_d3_d16",
310 "csw_f26m_ck_d2",
311 "univ_192m_d16",
312 "univ_192m_d32"
313 };
314
315 static const char * const camtg4_parents[] = {
316 "clk26m",
317 "univ_192m_d8",
318 "univpll_d3_d8",
319 "univ_192m_d4",
320 "univpll_d3_d16",
321 "csw_f26m_ck_d2",
322 "univ_192m_d16",
323 "univ_192m_d32"
324 };
325
326 static const char * const uart_parents[] = {
327 "clk26m",
328 "univpll_d3_d8"
329 };
330
331 static const char * const spi_parents[] = {
332 "clk26m",
333 "syspll_d5_d2",
334 "syspll_d3_d4",
335 "msdcpll_d4"
336 };
337
338 static const char * const msdc50_hclk_parents[] = {
339 "clk26m",
340 "syspll_d2_d2",
341 "syspll_d3_d2"
342 };
343
344 static const char * const msdc50_0_parents[] = {
345 "clk26m",
346 "msdcpll_ck",
347 "msdcpll_d2",
348 "univpll_d2_d4",
349 "syspll_d3_d2",
350 "univpll_d2_d2"
351 };
352
353 static const char * const msdc30_1_parents[] = {
354 "clk26m",
355 "univpll_d3_d2",
356 "syspll_d3_d2",
357 "syspll_d7",
358 "msdcpll_d2"
359 };
360
361 static const char * const msdc30_2_parents[] = {
362 "clk26m",
363 "univpll_d3_d2",
364 "syspll_d3_d2",
365 "syspll_d7",
366 "msdcpll_d2"
367 };
368
369 static const char * const audio_parents[] = {
370 "clk26m",
371 "syspll_d5_d4",
372 "syspll_d7_d4",
373 "syspll_d2_d16"
374 };
375
376 static const char * const aud_intbus_parents[] = {
377 "clk26m",
378 "syspll_d2_d4",
379 "syspll_d7_d2"
380 };
381
382 static const char * const pmicspi_parents[] = {
383 "clk26m",
384 "syspll_d2_d8",
385 "osc_d8"
386 };
387
388 static const char * const fpwrap_ulposc_parents[] = {
389 "clk26m",
390 "osc_d16",
391 "osc_d4",
392 "osc_d8"
393 };
394
395 static const char * const atb_parents[] = {
396 "clk26m",
397 "syspll_d2_d2",
398 "syspll_d5"
399 };
400
401 static const char * const dpi0_parents[] = {
402 "clk26m",
403 "tvdpll_d2",
404 "tvdpll_d4",
405 "tvdpll_d8",
406 "tvdpll_d16",
407 "univpll_d5_d2",
408 "univpll_d3_d4",
409 "syspll_d3_d4",
410 "univpll_d3_d8"
411 };
412
413 static const char * const scam_parents[] = {
414 "clk26m",
415 "syspll_d5_d2"
416 };
417
418 static const char * const disppwm_parents[] = {
419 "clk26m",
420 "univpll_d3_d4",
421 "osc_d2",
422 "osc_d4",
423 "osc_d16"
424 };
425
426 static const char * const usb_top_parents[] = {
427 "clk26m",
428 "univpll_d5_d4",
429 "univpll_d3_d4",
430 "univpll_d5_d2"
431 };
432
433
434 static const char * const ssusb_top_xhci_parents[] = {
435 "clk26m",
436 "univpll_d5_d4",
437 "univpll_d3_d4",
438 "univpll_d5_d2"
439 };
440
441 static const char * const spm_parents[] = {
442 "clk26m",
443 "syspll_d2_d8"
444 };
445
446 static const char * const i2c_parents[] = {
447 "clk26m",
448 "syspll_d2_d8",
449 "univpll_d5_d2"
450 };
451
452 static const char * const scp_parents[] = {
453 "clk26m",
454 "univpll_d2_d8",
455 "syspll_d5",
456 "syspll_d2_d2",
457 "univpll_d2_d2",
458 "syspll_d3",
459 "univpll_d3"
460 };
461
462 static const char * const seninf_parents[] = {
463 "clk26m",
464 "univpll_d2_d2",
465 "univpll_d3_d2",
466 "univpll_d2_d4"
467 };
468
469 static const char * const dxcc_parents[] = {
470 "clk26m",
471 "syspll_d2_d2",
472 "syspll_d2_d4",
473 "syspll_d2_d8"
474 };
475
476 static const char * const aud_engen1_parents[] = {
477 "clk26m",
478 "apll1_d2",
479 "apll1_d4",
480 "apll1_d8"
481 };
482
483 static const char * const aud_engen2_parents[] = {
484 "clk26m",
485 "apll2_d2",
486 "apll2_d4",
487 "apll2_d8"
488 };
489
490 static const char * const faes_ufsfde_parents[] = {
491 "clk26m",
492 "syspll_d2",
493 "syspll_d2_d2",
494 "syspll_d3",
495 "syspll_d2_d4",
496 "univpll_d3"
497 };
498
499 static const char * const fufs_parents[] = {
500 "clk26m",
501 "syspll_d2_d4",
502 "syspll_d2_d8",
503 "syspll_d2_d16"
504 };
505
506 static const char * const aud_1_parents[] = {
507 "clk26m",
508 "apll1_ck"
509 };
510
511 static const char * const aud_2_parents[] = {
512 "clk26m",
513 "apll2_ck"
514 };
515
516 /*
517 * CRITICAL CLOCK:
518 * axi_sel is the main bus clock of whole SOC.
519 * spm_sel is the clock of the always-on co-processor.
520 */
521 static const struct mtk_mux top_muxes[] = {
522 /* CLK_CFG_0 */
523 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel",
524 axi_parents, 0x40,
525 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL),
526 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
527 mm_parents, 0x40,
528 0x44, 0x48, 8, 3, 15, 0x004, 1),
529 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
530 img_parents, 0x40,
531 0x44, 0x48, 16, 3, 23, 0x004, 2),
532 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
533 cam_parents, 0x40,
534 0x44, 0x48, 24, 4, 31, 0x004, 3),
535 /* CLK_CFG_1 */
536 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP, "dsp_sel",
537 dsp_parents, 0x50,
538 0x54, 0x58, 0, 4, 7, 0x004, 4),
539 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP1, "dsp1_sel",
540 dsp1_parents, 0x50,
541 0x54, 0x58, 8, 4, 15, 0x004, 5),
542 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DSP2, "dsp2_sel",
543 dsp2_parents, 0x50,
544 0x54, 0x58, 16, 4, 23, 0x004, 6),
545 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IPU_IF, "ipu_if_sel",
546 ipu_if_parents, 0x50,
547 0x54, 0x58, 24, 4, 31, 0x004, 7),
548 /* CLK_CFG_2 */
549 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MFG, "mfg_sel",
550 mfg_parents, 0x60,
551 0x64, 0x68, 0, 2, 7, 0x004, 8),
552 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_F52M_MFG, "f52m_mfg_sel",
553 f52m_mfg_parents, 0x60,
554 0x64, 0x68, 8, 2, 15, 0x004, 9),
555 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG, "camtg_sel",
556 camtg_parents, 0x60,
557 0x64, 0x68, 16, 3, 23, 0x004, 10),
558 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG2, "camtg2_sel",
559 camtg2_parents, 0x60,
560 0x64, 0x68, 24, 3, 31, 0x004, 11),
561 /* CLK_CFG_3 */
562 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG3, "camtg3_sel",
563 camtg3_parents, 0x70,
564 0x74, 0x78, 0, 3, 7, 0x004, 12),
565 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAMTG4, "camtg4_sel",
566 camtg4_parents, 0x70,
567 0x74, 0x78, 8, 3, 15, 0x004, 13),
568 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",
569 uart_parents, 0x70,
570 0x74, 0x78, 16, 1, 23, 0x004, 14),
571 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SPI, "spi_sel",
572 spi_parents, 0x70,
573 0x74, 0x78, 24, 2, 31, 0x004, 15),
574 /* CLK_CFG_4 */
575 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_hclk_sel",
576 msdc50_hclk_parents, 0x80,
577 0x84, 0x88, 0, 2, 7, 0x004, 16),
578 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel",
579 msdc50_0_parents, 0x80,
580 0x84, 0x88, 8, 3, 15, 0x004, 17),
581 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel",
582 msdc30_1_parents, 0x80,
583 0x84, 0x88, 16, 3, 23, 0x004, 18),
584 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel",
585 msdc30_2_parents, 0x80,
586 0x84, 0x88, 24, 3, 31, 0x004, 19),
587 /* CLK_CFG_5 */
588 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUDIO, "audio_sel",
589 audio_parents, 0x90,
590 0x94, 0x98, 0, 2, 7, 0x004, 20),
591 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel",
592 aud_intbus_parents, 0x90,
593 0x94, 0x98, 8, 2, 15, 0x004, 21),
594 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_PMICSPI, "pmicspi_sel",
595 pmicspi_parents, 0x90,
596 0x94, 0x98, 16, 2, 23, 0x004, 22),
597 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
598 fpwrap_ulposc_parents, 0x90,
599 0x94, 0x98, 24, 2, 31, 0x004, 23),
600 /* CLK_CFG_6 */
601 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_ATB, "atb_sel",
602 atb_parents, 0xa0,
603 0xa4, 0xa8, 0, 2, 7, 0x004, 24),
604 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DPI0, "dpi0_sel",
605 dpi0_parents, 0xa0,
606 0xa4, 0xa8, 16, 4, 23, 0x004, 26),
607 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCAM, "scam_sel",
608 scam_parents, 0xa0,
609 0xa4, 0xa8, 24, 1, 31, 0x004, 27),
610 /* CLK_CFG_7 */
611 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DISP_PWM, "disppwm_sel",
612 disppwm_parents, 0xb0,
613 0xb4, 0xb8, 0, 3, 7, 0x004, 28),
614 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_USB_TOP, "usb_top_sel",
615 usb_top_parents, 0xb0,
616 0xb4, 0xb8, 8, 2, 15, 0x004, 29),
617 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
618 ssusb_top_xhci_parents, 0xb0,
619 0xb4, 0xb8, 16, 2, 23, 0x004, 30),
620 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel",
621 spm_parents, 0xb0,
622 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL),
623 /* CLK_CFG_8 */
624 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel",
625 i2c_parents, 0xc0,
626 0xc4, 0xc8, 0, 2, 7, 0x008, 1),
627 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SCP, "scp_sel",
628 scp_parents, 0xc0,
629 0xc4, 0xc8, 8, 3, 15, 0x008, 2),
630 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SENINF, "seninf_sel",
631 seninf_parents, 0xc0,
632 0xc4, 0xc8, 16, 2, 23, 0x008, 3),
633 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_DXCC, "dxcc_sel",
634 dxcc_parents, 0xc0,
635 0xc4, 0xc8, 24, 2, 31, 0x008, 4),
636 /* CLK_CFG_9 */
637 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG1, "aud_eng1_sel",
638 aud_engen1_parents, 0xd0,
639 0xd4, 0xd8, 0, 2, 7, 0x008, 5),
640 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_ENG2, "aud_eng2_sel",
641 aud_engen2_parents, 0xd0,
642 0xd4, 0xd8, 8, 2, 15, 0x008, 6),
643 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FAES_UFSFDE, "faes_ufsfde_sel",
644 faes_ufsfde_parents, 0xd0,
645 0xd4, 0xd8, 16, 3, 23, 0x008, 7),
646 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_FUFS, "fufs_sel",
647 fufs_parents, 0xd0,
648 0xd4, 0xd8, 24, 2, 31, 0x008, 8),
649 /* CLK_CFG_10 */
650 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel",
651 aud_1_parents, 0xe0,
652 0xe4, 0xe8, 0, 1, 7, 0x008, 9),
653 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_2, "aud_2_sel",
654 aud_2_parents, 0xe0,
655 0xe4, 0xe8, 8, 1, 15, 0x008, 10),
656 };
657
658 static const char * const apll_i2s0_parents[] = {
659 "aud_1_sel",
660 "aud_2_sel"
661 };
662
663 static const char * const apll_i2s1_parents[] = {
664 "aud_1_sel",
665 "aud_2_sel"
666 };
667
668 static const char * const apll_i2s2_parents[] = {
669 "aud_1_sel",
670 "aud_2_sel"
671 };
672
673 static const char * const apll_i2s3_parents[] = {
674 "aud_1_sel",
675 "aud_2_sel"
676 };
677
678 static const char * const apll_i2s4_parents[] = {
679 "aud_1_sel",
680 "aud_2_sel"
681 };
682
683 static const char * const apll_i2s5_parents[] = {
684 "aud_1_sel",
685 "aud_2_sel"
686 };
687
688 static struct mtk_composite top_aud_muxes[] = {
689 MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents,
690 0x320, 8, 1),
691 MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents,
692 0x320, 9, 1),
693 MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents,
694 0x320, 10, 1),
695 MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents,
696 0x320, 11, 1),
697 MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents,
698 0x320, 12, 1),
699 MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents,
700 0x328, 20, 1),
701 };
702
703 static const char * const mcu_mp0_parents[] = {
704 "clk26m",
705 "armpll_ll",
706 "armpll_div_pll1",
707 "armpll_div_pll2"
708 };
709
710 static const char * const mcu_mp2_parents[] = {
711 "clk26m",
712 "armpll_l",
713 "armpll_div_pll1",
714 "armpll_div_pll2"
715 };
716
717 static const char * const mcu_bus_parents[] = {
718 "clk26m",
719 "ccipll",
720 "armpll_div_pll1",
721 "armpll_div_pll2"
722 };
723
724 static struct mtk_composite mcu_muxes[] = {
725 /* mp0_pll_divider_cfg */
726 MUX(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 9, 2),
727 /* mp2_pll_divider_cfg */
728 MUX(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 9, 2),
729 /* bus_pll_divider_cfg */
730 MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2),
731 };
732
733 static struct mtk_composite top_aud_divs[] = {
734 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel",
735 0x320, 2, 0x324, 8, 0),
736 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel",
737 0x320, 3, 0x324, 8, 8),
738 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_sel",
739 0x320, 4, 0x324, 8, 16),
740 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_sel",
741 0x320, 5, 0x324, 8, 24),
742 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_sel",
743 0x320, 6, 0x328, 8, 0),
744 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
745 0x320, 7, 0x328, 8, 8),
746 };
747
748 static const struct mtk_gate_regs top_cg_regs = {
749 .set_ofs = 0x104,
750 .clr_ofs = 0x104,
751 .sta_ofs = 0x104,
752 };
753
754 #define GATE_TOP(_id, _name, _parent, _shift) \
755 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, \
756 &mtk_clk_gate_ops_no_setclr_inv)
757
758 static const struct mtk_gate top_clks[] = {
759 /* TOP */
760 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL1, "armpll_div_pll1", "mainpll", 4),
761 GATE_TOP(CLK_TOP_ARMPLL_DIV_PLL2, "armpll_div_pll2", "univpll", 5),
762 };
763
764 static const struct mtk_gate_regs infra0_cg_regs = {
765 .set_ofs = 0x80,
766 .clr_ofs = 0x84,
767 .sta_ofs = 0x90,
768 };
769
770 static const struct mtk_gate_regs infra1_cg_regs = {
771 .set_ofs = 0x88,
772 .clr_ofs = 0x8c,
773 .sta_ofs = 0x94,
774 };
775
776 static const struct mtk_gate_regs infra2_cg_regs = {
777 .set_ofs = 0xa4,
778 .clr_ofs = 0xa8,
779 .sta_ofs = 0xac,
780 };
781
782 static const struct mtk_gate_regs infra3_cg_regs = {
783 .set_ofs = 0xc0,
784 .clr_ofs = 0xc4,
785 .sta_ofs = 0xc8,
786 };
787
788 #define GATE_INFRA0(_id, _name, _parent, _shift) \
789 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
790 &mtk_clk_gate_ops_setclr)
791
792 #define GATE_INFRA1(_id, _name, _parent, _shift) \
793 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \
794 &mtk_clk_gate_ops_setclr)
795
796 #define GATE_INFRA2(_id, _name, _parent, _shift) \
797 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
798 &mtk_clk_gate_ops_setclr)
799
800 #define GATE_INFRA3(_id, _name, _parent, _shift) \
801 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
802 &mtk_clk_gate_ops_setclr)
803
804 static const struct mtk_gate infra_clks[] = {
805 /* INFRA0 */
806 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
807 "axi_sel", 0),
808 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
809 "axi_sel", 1),
810 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
811 "axi_sel", 2),
812 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
813 "axi_sel", 3),
814 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp",
815 "scp_sel", 4),
816 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
817 "f_f26m_ck", 5),
818 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
819 "axi_sel", 6),
820 GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
821 "axi_sel", 8),
822 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
823 "axi_sel", 9),
824 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
825 "axi_sel", 10),
826 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
827 "i2c_sel", 11),
828 GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
829 "i2c_sel", 12),
830 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
831 "i2c_sel", 13),
832 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
833 "i2c_sel", 14),
834 GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
835 "axi_sel", 15),
836 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
837 "i2c_sel", 16),
838 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
839 "i2c_sel", 17),
840 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
841 "i2c_sel", 18),
842 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
843 "i2c_sel", 19),
844 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
845 "i2c_sel", 21),
846 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
847 "uart_sel", 22),
848 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
849 "uart_sel", 23),
850 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
851 "uart_sel", 24),
852 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
853 "uart_sel", 25),
854 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
855 "axi_sel", 27),
856 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
857 "axi_sel", 28),
858 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
859 "axi_sel", 31),
860 /* INFRA1 */
861 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
862 "spi_sel", 1),
863 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
864 "msdc50_hclk_sel", 2),
865 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
866 "axi_sel", 4),
867 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
868 "axi_sel", 5),
869 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
870 "msdc50_0_sel", 6),
871 GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc",
872 "f_f26m_ck", 7),
873 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
874 "axi_sel", 8),
875 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
876 "axi_sel", 9),
877 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
878 "f_f26m_ck", 10),
879 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
880 "axi_sel", 11),
881 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
882 "axi_sel", 12),
883 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
884 "axi_sel", 13),
885 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
886 "f_f26m_ck", 14),
887 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
888 "msdc30_1_sel", 16),
889 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
890 "msdc30_2_sel", 17),
891 GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
892 "axi_sel", 18),
893 GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
894 "axi_sel", 19),
895 GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
896 "axi_sel", 20),
897 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
898 "axi_sel", 23),
899 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",
900 "axi_sel", 24),
901 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio",
902 "axi_sel", 25),
903 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
904 "axi_sel", 26),
905 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
906 "dxcc_sel", 27),
907 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
908 "dxcc_sel", 28),
909 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
910 "axi_sel", 30),
911 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
912 "f_f26m_ck", 31),
913 /* INFRA2 */
914 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
915 "f_f26m_ck", 0),
916 GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
917 "usb_top_sel", 1),
918 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
919 "axi_sel", 2),
920 GATE_INFRA2(CLK_INFRA_CLDMA_BCLK, "infra_cldma_bclk",
921 "axi_sel", 3),
922 GATE_INFRA2(CLK_INFRA_AUDIO_26M_BCLK, "infra_audio_26m_bclk",
923 "f_f26m_ck", 4),
924 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
925 "spi_sel", 6),
926 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
927 "i2c_sel", 7),
928 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
929 "f_f26m_ck", 8),
930 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
931 "spi_sel", 9),
932 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
933 "spi_sel", 10),
934 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
935 "ssusb_top_xhci_sel", 11),
936 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
937 "fufs_sel", 12),
938 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
939 "fufs_sel", 13),
940 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
941 "axi_sel", 14),
942 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
943 "axi_sel", 16),
944 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
945 "i2c_sel", 18),
946 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
947 "i2c_sel", 19),
948 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
949 "i2c_sel", 20),
950 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
951 "i2c_sel", 21),
952 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
953 "i2c_sel", 22),
954 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
955 "i2c_sel", 23),
956 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
957 "i2c_sel", 24),
958 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
959 "spi_sel", 25),
960 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
961 "spi_sel", 26),
962 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
963 "axi_sel", 27),
964 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
965 "fufs_sel", 28),
966 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
967 "faes_ufsfde_sel", 29),
968 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
969 "fufs_sel", 30),
970 /* INFRA3 */
971 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
972 "msdc50_0_sel", 0),
973 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
974 "msdc50_0_sel", 1),
975 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
976 "msdc50_0_sel", 2),
977 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
978 "axi_sel", 5),
979 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
980 "i2c_sel", 6),
981 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
982 "msdc50_hclk_sel", 7),
983 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
984 "msdc50_hclk_sel", 8),
985 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
986 "axi_sel", 16),
987 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
988 "axi_sel", 17),
989 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
990 "axi_sel", 18),
991 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
992 "axi_sel", 19),
993 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
994 "f_f26m_ck", 20),
995 GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
996 "axi_sel", 21),
997 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
998 "i2c_sel", 22),
999 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
1000 "i2c_sel", 23),
1001 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
1002 "msdc50_0_sel", 24),
1003 };
1004
1005 static const struct mtk_gate_regs peri_cg_regs = {
1006 .set_ofs = 0x20c,
1007 .clr_ofs = 0x20c,
1008 .sta_ofs = 0x20c,
1009 };
1010
1011 #define GATE_PERI(_id, _name, _parent, _shift) \
1012 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \
1013 &mtk_clk_gate_ops_no_setclr_inv)
1014
1015 static const struct mtk_gate peri_clks[] = {
1016 GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31),
1017 };
1018
1019 static const struct mtk_gate_regs apmixed_cg_regs = {
1020 .set_ofs = 0x20,
1021 .clr_ofs = 0x20,
1022 .sta_ofs = 0x20,
1023 };
1024
1025 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
1026 GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
1027 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
1028
1029 #define GATE_APMIXED(_id, _name, _parent, _shift) \
1030 GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
1031
1032 /*
1033 * CRITICAL CLOCK:
1034 * apmixed_appll26m is the toppest clock gate of all PLLs.
1035 */
1036 static const struct mtk_gate apmixed_clks[] = {
1037 /* AUDIO0 */
1038 GATE_APMIXED(CLK_APMIXED_SSUSB_26M, "apmixed_ssusb26m",
1039 "f_f26m_ck", 4),
1040 GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL_26M, "apmixed_appll26m",
1041 "f_f26m_ck", 5, CLK_IS_CRITICAL),
1042 GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
1043 "f_f26m_ck", 6),
1044 GATE_APMIXED(CLK_APMIXED_MDPLLGP_26M, "apmixed_mdpll26m",
1045 "f_f26m_ck", 7),
1046 GATE_APMIXED(CLK_APMIXED_MMSYS_26M, "apmixed_mmsys26m",
1047 "f_f26m_ck", 8),
1048 GATE_APMIXED(CLK_APMIXED_UFS_26M, "apmixed_ufs26m",
1049 "f_f26m_ck", 9),
1050 GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
1051 "f_f26m_ck", 11),
1052 GATE_APMIXED(CLK_APMIXED_MEMPLL_26M, "apmixed_mempll26m",
1053 "f_f26m_ck", 13),
1054 GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
1055 "f_f26m_ck", 14),
1056 GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
1057 "f_f26m_ck", 16),
1058 GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
1059 "f_f26m_ck", 17),
1060 };
1061
1062 #define MT8183_PLL_FMAX (3800UL * MHZ)
1063 #define MT8183_PLL_FMIN (1500UL * MHZ)
1064
1065 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1066 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1067 _pd_shift, _tuner_reg, _tuner_en_reg, \
1068 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1069 _pcw_chg_reg, _div_table) { \
1070 .id = _id, \
1071 .name = _name, \
1072 .reg = _reg, \
1073 .pwr_reg = _pwr_reg, \
1074 .en_mask = _en_mask, \
1075 .flags = _flags, \
1076 .rst_bar_mask = _rst_bar_mask, \
1077 .fmax = MT8183_PLL_FMAX, \
1078 .fmin = MT8183_PLL_FMIN, \
1079 .pcwbits = _pcwbits, \
1080 .pcwibits = _pcwibits, \
1081 .pd_reg = _pd_reg, \
1082 .pd_shift = _pd_shift, \
1083 .tuner_reg = _tuner_reg, \
1084 .tuner_en_reg = _tuner_en_reg, \
1085 .tuner_en_bit = _tuner_en_bit, \
1086 .pcw_reg = _pcw_reg, \
1087 .pcw_shift = _pcw_shift, \
1088 .pcw_chg_reg = _pcw_chg_reg, \
1089 .div_table = _div_table, \
1090 }
1091
1092 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1093 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1094 _pd_shift, _tuner_reg, _tuner_en_reg, \
1095 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1096 _pcw_chg_reg) \
1097 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1098 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1099 _pd_shift, _tuner_reg, _tuner_en_reg, \
1100 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1101 _pcw_chg_reg, NULL)
1102
1103 static const struct mtk_pll_div_table armpll_div_table[] = {
1104 { .div = 0, .freq = MT8183_PLL_FMAX },
1105 { .div = 1, .freq = 1500 * MHZ },
1106 { .div = 2, .freq = 750 * MHZ },
1107 { .div = 3, .freq = 375 * MHZ },
1108 { .div = 4, .freq = 187500000 },
1109 { } /* sentinel */
1110 };
1111
1112 static const struct mtk_pll_div_table mfgpll_div_table[] = {
1113 { .div = 0, .freq = MT8183_PLL_FMAX },
1114 { .div = 1, .freq = 1600 * MHZ },
1115 { .div = 2, .freq = 800 * MHZ },
1116 { .div = 3, .freq = 400 * MHZ },
1117 { .div = 4, .freq = 200 * MHZ },
1118 { } /* sentinel */
1119 };
1120
1121 static const struct mtk_pll_data plls[] = {
1122 PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
1123 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
1124 0x0204, 0, 0, armpll_div_table),
1125 PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0,
1126 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0,
1127 0x0214, 0, 0, armpll_div_table),
1128 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0,
1129 HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0,
1130 0x0294, 0, 0),
1131 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0,
1132 HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0,
1133 0x0224, 0, 0),
1134 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0,
1135 HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0,
1136 0x0234, 0, 0),
1137 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0,
1138 0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0,
1139 mfgpll_div_table),
1140 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0,
1141 0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0),
1142 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0,
1143 0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0),
1144 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0,
1145 HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0,
1146 0x0274, 0, 0),
1147 PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0,
1148 0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0),
1149 PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0,
1150 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
1151 };
1152
1153 static u16 infra_rst_ofs[] = {
1154 INFRA_RST0_SET_OFFSET,
1155 INFRA_RST1_SET_OFFSET,
1156 INFRA_RST2_SET_OFFSET,
1157 INFRA_RST3_SET_OFFSET,
1158 };
1159
1160 static const struct mtk_clk_rst_desc clk_rst_desc = {
1161 .version = MTK_RST_SET_CLR,
1162 .rst_bank_ofs = infra_rst_ofs,
1163 .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
1164 };
1165
clk_mt8183_apmixed_probe(struct platform_device * pdev)1166 static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
1167 {
1168 struct clk_hw_onecell_data *clk_data;
1169 struct device_node *node = pdev->dev.of_node;
1170
1171 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1172
1173 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1174
1175 mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks),
1176 clk_data);
1177
1178 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1179 }
1180
1181 static struct clk_hw_onecell_data *top_clk_data;
1182
clk_mt8183_top_init_early(struct device_node * node)1183 static void clk_mt8183_top_init_early(struct device_node *node)
1184 {
1185 int i;
1186
1187 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1188
1189 for (i = 0; i < CLK_TOP_NR_CLK; i++)
1190 top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
1191
1192 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1193 top_clk_data);
1194
1195 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
1196 }
1197
1198 CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen",
1199 clk_mt8183_top_init_early);
1200
1201 /* Register mux notifier for MFG mux */
clk_mt8183_reg_mfg_mux_notifier(struct device * dev,struct clk * clk)1202 static int clk_mt8183_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
1203 {
1204 struct mtk_mux_nb *mfg_mux_nb;
1205 int i;
1206
1207 mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
1208 if (!mfg_mux_nb)
1209 return -ENOMEM;
1210
1211 for (i = 0; i < ARRAY_SIZE(top_muxes); i++)
1212 if (top_muxes[i].id == CLK_TOP_MUX_MFG)
1213 break;
1214 if (i == ARRAY_SIZE(top_muxes))
1215 return -EINVAL;
1216
1217 mfg_mux_nb->ops = top_muxes[i].ops;
1218 mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */
1219
1220 return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
1221 }
1222
clk_mt8183_top_probe(struct platform_device * pdev)1223 static int clk_mt8183_top_probe(struct platform_device *pdev)
1224 {
1225 void __iomem *base;
1226 struct device_node *node = pdev->dev.of_node;
1227 int ret;
1228
1229 base = devm_platform_ioremap_resource(pdev, 0);
1230 if (IS_ERR(base))
1231 return PTR_ERR(base);
1232
1233 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1234 top_clk_data);
1235
1236 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1237 top_clk_data);
1238
1239 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1240
1241 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
1242 node, &mt8183_clk_lock, top_clk_data);
1243
1244 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
1245 base, &mt8183_clk_lock, top_clk_data);
1246
1247 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
1248 base, &mt8183_clk_lock, top_clk_data);
1249
1250 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
1251 top_clk_data);
1252
1253 ret = clk_mt8183_reg_mfg_mux_notifier(&pdev->dev,
1254 top_clk_data->hws[CLK_TOP_MUX_MFG]->clk);
1255 if (ret)
1256 return ret;
1257
1258 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
1259 top_clk_data);
1260 }
1261
clk_mt8183_infra_probe(struct platform_device * pdev)1262 static int clk_mt8183_infra_probe(struct platform_device *pdev)
1263 {
1264 struct clk_hw_onecell_data *clk_data;
1265 struct device_node *node = pdev->dev.of_node;
1266 int r;
1267
1268 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1269
1270 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1271 clk_data);
1272
1273 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1274 if (r) {
1275 dev_err(&pdev->dev,
1276 "%s(): could not register clock provider: %d\n",
1277 __func__, r);
1278 return r;
1279 }
1280
1281 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
1282
1283 return r;
1284 }
1285
clk_mt8183_peri_probe(struct platform_device * pdev)1286 static int clk_mt8183_peri_probe(struct platform_device *pdev)
1287 {
1288 struct clk_hw_onecell_data *clk_data;
1289 struct device_node *node = pdev->dev.of_node;
1290
1291 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1292
1293 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
1294 clk_data);
1295
1296 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1297 }
1298
clk_mt8183_mcu_probe(struct platform_device * pdev)1299 static int clk_mt8183_mcu_probe(struct platform_device *pdev)
1300 {
1301 struct clk_hw_onecell_data *clk_data;
1302 struct device_node *node = pdev->dev.of_node;
1303 void __iomem *base;
1304
1305 base = devm_platform_ioremap_resource(pdev, 0);
1306 if (IS_ERR(base))
1307 return PTR_ERR(base);
1308
1309 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
1310
1311 mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
1312 &mt8183_clk_lock, clk_data);
1313
1314 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1315 }
1316
1317 static const struct of_device_id of_match_clk_mt8183[] = {
1318 {
1319 .compatible = "mediatek,mt8183-apmixedsys",
1320 .data = clk_mt8183_apmixed_probe,
1321 }, {
1322 .compatible = "mediatek,mt8183-topckgen",
1323 .data = clk_mt8183_top_probe,
1324 }, {
1325 .compatible = "mediatek,mt8183-infracfg",
1326 .data = clk_mt8183_infra_probe,
1327 }, {
1328 .compatible = "mediatek,mt8183-pericfg",
1329 .data = clk_mt8183_peri_probe,
1330 }, {
1331 .compatible = "mediatek,mt8183-mcucfg",
1332 .data = clk_mt8183_mcu_probe,
1333 }, {
1334 /* sentinel */
1335 }
1336 };
1337
clk_mt8183_probe(struct platform_device * pdev)1338 static int clk_mt8183_probe(struct platform_device *pdev)
1339 {
1340 int (*clk_probe)(struct platform_device *pdev);
1341 int r;
1342
1343 clk_probe = of_device_get_match_data(&pdev->dev);
1344 if (!clk_probe)
1345 return -EINVAL;
1346
1347 r = clk_probe(pdev);
1348 if (r)
1349 dev_err(&pdev->dev,
1350 "could not register clock provider: %s: %d\n",
1351 pdev->name, r);
1352
1353 return r;
1354 }
1355
1356 static struct platform_driver clk_mt8183_drv = {
1357 .probe = clk_mt8183_probe,
1358 .driver = {
1359 .name = "clk-mt8183",
1360 .of_match_table = of_match_clk_mt8183,
1361 },
1362 };
1363
clk_mt8183_init(void)1364 static int __init clk_mt8183_init(void)
1365 {
1366 return platform_driver_register(&clk_mt8183_drv);
1367 }
1368
1369 arch_initcall(clk_mt8183_init);
1370