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/drivers/infiniband/core/
Duverbs_marshall.c63 struct ib_uverbs_ah_attr *dst, in ib_copy_ah_attr_to_user() argument
69 memset(&dst->grh, 0, sizeof(dst->grh)); in ib_copy_ah_attr_to_user()
76 dst->dlid = rdma_ah_get_dlid(src); in ib_copy_ah_attr_to_user()
77 dst->sl = rdma_ah_get_sl(src); in ib_copy_ah_attr_to_user()
78 dst->src_path_bits = rdma_ah_get_path_bits(src); in ib_copy_ah_attr_to_user()
79 dst->static_rate = rdma_ah_get_static_rate(src); in ib_copy_ah_attr_to_user()
80 dst->is_global = rdma_ah_get_ah_flags(src) & in ib_copy_ah_attr_to_user()
82 if (dst->is_global) { in ib_copy_ah_attr_to_user()
85 memcpy(dst->grh.dgid, grh->dgid.raw, sizeof(grh->dgid)); in ib_copy_ah_attr_to_user()
86 dst->grh.flow_label = grh->flow_label; in ib_copy_ah_attr_to_user()
[all …]
/drivers/video/fbdev/core/
Dcfbfillrect.c35 bitfill_aligned(struct fb_info *p, unsigned long __iomem *dst, int dst_idx, in bitfill_aligned() argument
50 FB_WRITEL(comp(pat, FB_READL(dst), first), dst); in bitfill_aligned()
56 FB_WRITEL(comp(pat, FB_READL(dst), first), dst); in bitfill_aligned()
57 dst++; in bitfill_aligned()
64 FB_WRITEL(pat, dst++); in bitfill_aligned()
65 FB_WRITEL(pat, dst++); in bitfill_aligned()
66 FB_WRITEL(pat, dst++); in bitfill_aligned()
67 FB_WRITEL(pat, dst++); in bitfill_aligned()
68 FB_WRITEL(pat, dst++); in bitfill_aligned()
69 FB_WRITEL(pat, dst++); in bitfill_aligned()
[all …]
Dsyscopyarea.c28 bitcpy(struct fb_info *p, unsigned long *dst, unsigned dst_idx, in bitcpy() argument
44 *dst = comp(*src, *dst, first); in bitcpy()
49 *dst = comp(*src, *dst, first); in bitcpy()
50 dst++; in bitcpy()
58 *dst++ = *src++; in bitcpy()
59 *dst++ = *src++; in bitcpy()
60 *dst++ = *src++; in bitcpy()
61 *dst++ = *src++; in bitcpy()
62 *dst++ = *src++; in bitcpy()
63 *dst++ = *src++; in bitcpy()
[all …]
Dsysfillrect.c25 bitfill_aligned(struct fb_info *p, unsigned long *dst, int dst_idx, in bitfill_aligned() argument
40 *dst = comp(pat, *dst, first); in bitfill_aligned()
46 *dst = comp(pat, *dst, first); in bitfill_aligned()
47 dst++; in bitfill_aligned()
53 memset_l(dst, pat, n); in bitfill_aligned()
54 dst += n; in bitfill_aligned()
58 *dst = comp(pat, *dst, last); in bitfill_aligned()
71 bitfill_unaligned(struct fb_info *p, unsigned long *dst, int dst_idx, in bitfill_unaligned() argument
86 *dst = comp(pat, *dst, first); in bitfill_unaligned()
91 *dst = comp(pat, *dst, first); in bitfill_unaligned()
[all …]
Dcfbcopyarea.c46 bitcpy(struct fb_info *p, unsigned long __iomem *dst, unsigned dst_idx, in bitcpy() argument
58 memmove((char *)dst + ((dst_idx & (bits - 1))) / 8, in bitcpy()
73 FB_WRITEL( comp( FB_READL(src), FB_READL(dst), first), dst); in bitcpy()
79 FB_WRITEL( comp( FB_READL(src), FB_READL(dst), first), dst); in bitcpy()
80 dst++; in bitcpy()
88 FB_WRITEL(FB_READL(src++), dst++); in bitcpy()
89 FB_WRITEL(FB_READL(src++), dst++); in bitcpy()
90 FB_WRITEL(FB_READL(src++), dst++); in bitcpy()
91 FB_WRITEL(FB_READL(src++), dst++); in bitcpy()
92 FB_WRITEL(FB_READL(src++), dst++); in bitcpy()
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Dsysimgblt.c56 u32 *dst, *dst2; in color_imageblit() local
66 dst = dst1; in color_imageblit()
73 val = *dst & start_mask; in color_imageblit()
85 *dst++ = val; in color_imageblit()
97 *dst &= end_mask; in color_imageblit()
98 *dst |= val; in color_imageblit()
116 u32 *dst, *dst2; in slow_imageblit() local
131 dst = dst1; in slow_imageblit()
138 val = *dst & start_mask; in slow_imageblit()
149 *dst++ = val; in slow_imageblit()
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Dcfbimgblt.c81 u32 __iomem *dst, *dst2; in color_imageblit() local
92 dst = (u32 __iomem *) dst1; in color_imageblit()
99 val = FB_READL(dst) & start_mask; in color_imageblit()
111 FB_WRITEL(val, dst++); in color_imageblit()
124 FB_WRITEL((FB_READL(dst) & end_mask) | val, dst); in color_imageblit()
144 u32 __iomem *dst, *dst2; in slow_imageblit() local
160 dst = (u32 __iomem *) dst1; in slow_imageblit()
167 val = FB_READL(dst) & start_mask; in slow_imageblit()
178 FB_WRITEL(val, dst++); in slow_imageblit()
192 FB_WRITEL((FB_READL(dst) & end_mask) | val, dst); in slow_imageblit()
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/drivers/media/platform/verisilicon/
Dhantro_vp8.c54 u8 *dst; in hantro_vp8_prob_update() local
57 dst = ctx->vp8_dec.prob_tbl.cpu; in hantro_vp8_prob_update()
59 dst[0] = hdr->prob_skip_false; in hantro_vp8_prob_update()
60 dst[1] = hdr->prob_intra; in hantro_vp8_prob_update()
61 dst[2] = hdr->prob_last; in hantro_vp8_prob_update()
62 dst[3] = hdr->prob_gf; in hantro_vp8_prob_update()
63 dst[4] = hdr->segment.segment_probs[0]; in hantro_vp8_prob_update()
64 dst[5] = hdr->segment.segment_probs[1]; in hantro_vp8_prob_update()
65 dst[6] = hdr->segment.segment_probs[2]; in hantro_vp8_prob_update()
66 dst[7] = 0; in hantro_vp8_prob_update()
[all …]
/drivers/gpu/drm/tests/
Ddrm_rect_test.c14 struct drm_rect src, dst, clip; in drm_test_rect_clip_scaled_div_by_zero() local
22 drm_rect_init(&dst, 0, 0, 0, 0); in drm_test_rect_clip_scaled_div_by_zero()
24 visible = drm_rect_clip_scaled(&src, &dst, &clip); in drm_test_rect_clip_scaled_div_by_zero()
30 drm_rect_init(&dst, 3, 3, 0, 0); in drm_test_rect_clip_scaled_div_by_zero()
32 visible = drm_rect_clip_scaled(&src, &dst, &clip); in drm_test_rect_clip_scaled_div_by_zero()
40 struct drm_rect src, dst, clip; in drm_test_rect_clip_scaled_not_clipped() local
45 drm_rect_init(&dst, 0, 0, 1, 1); in drm_test_rect_clip_scaled_not_clipped()
48 visible = drm_rect_clip_scaled(&src, &dst, &clip); in drm_test_rect_clip_scaled_not_clipped()
52 KUNIT_EXPECT_FALSE_MSG(test, dst.x1 != 0 || dst.x2 != 1 || in drm_test_rect_clip_scaled_not_clipped()
53 dst.y1 != 0 || dst.y2 != 1, "Destination badly clipped\n"); in drm_test_rect_clip_scaled_not_clipped()
[all …]
/drivers/media/platform/allegro-dvt/
Dallegro-mail.c44 allegro_enc_init(u32 *dst, struct mcu_msg_init_request *msg) in allegro_enc_init() argument
49 dst[i++] = msg->reserved0; in allegro_enc_init()
50 dst[i++] = msg->suballoc_dma; in allegro_enc_init()
51 dst[i++] = msg->suballoc_size; in allegro_enc_init()
52 dst[i++] = msg->encoder_buffer_size; in allegro_enc_init()
53 dst[i++] = msg->encoder_buffer_color_depth; in allegro_enc_init()
54 dst[i++] = msg->num_cores; in allegro_enc_init()
56 dst[i++] = msg->clk_rate; in allegro_enc_init()
57 dst[i++] = 0; in allegro_enc_init()
60 return i * sizeof(*dst); in allegro_enc_init()
[all …]
/drivers/phy/
Dphy-xgene.c94 #define REGSPEC_CFG_I_TX_WORDMODE0_SET(dst, src) \ argument
95 (((dst) & ~0x00070000) | (((u32) (src) << 16) & 0x00070000))
96 #define REGSPEC_CFG_I_RX_WORDMODE0_SET(dst, src) \ argument
97 (((dst) & ~0x00e00000) | (((u32) (src) << 21) & 0x00e00000))
99 #define REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(dst, src) \ argument
100 (((dst) & ~0x00007fff) | (((u32) (src)) & 0x00007fff))
102 #define CFG_I_SPD_SEL_CDR_OVR1_SET(dst, src) \ argument
103 (((dst) & ~0x0000000f) | (((u32) (src)) & 0x0000000f))
109 #define CFG_IND_ADDR_SET(dst, src) \ argument
110 (((dst) & ~0x003ffff0) | (((u32) (src) << 4) & 0x003ffff0))
[all …]
/drivers/infiniband/hw/vmw_pvrdma/
Dpvrdma_misc.c224 void pvrdma_qp_cap_to_ib(struct ib_qp_cap *dst, const struct pvrdma_qp_cap *src) in pvrdma_qp_cap_to_ib() argument
226 dst->max_send_wr = src->max_send_wr; in pvrdma_qp_cap_to_ib()
227 dst->max_recv_wr = src->max_recv_wr; in pvrdma_qp_cap_to_ib()
228 dst->max_send_sge = src->max_send_sge; in pvrdma_qp_cap_to_ib()
229 dst->max_recv_sge = src->max_recv_sge; in pvrdma_qp_cap_to_ib()
230 dst->max_inline_data = src->max_inline_data; in pvrdma_qp_cap_to_ib()
233 void ib_qp_cap_to_pvrdma(struct pvrdma_qp_cap *dst, const struct ib_qp_cap *src) in ib_qp_cap_to_pvrdma() argument
235 dst->max_send_wr = src->max_send_wr; in ib_qp_cap_to_pvrdma()
236 dst->max_recv_wr = src->max_recv_wr; in ib_qp_cap_to_pvrdma()
237 dst->max_send_sge = src->max_send_sge; in ib_qp_cap_to_pvrdma()
[all …]
/drivers/video/fbdev/
Datafb_utils.h220 static inline void fast_memmove(char *dst, const char *src, size_t size) in fast_memmove() argument
224 if (dst < src) in fast_memmove()
232 : "=a" (src), "=a" (dst), "=d" (size) in fast_memmove()
233 : "0" (src), "1" (dst), "2" (size / 16 - 1) in fast_memmove()
243 : "=a" (src), "=a" (dst), "=d" (size) in fast_memmove()
244 : "0" (src + size), "1" (dst + size), "2" (size / 16 - 1) in fast_memmove()
280 static inline void fill8_col(u8 *dst, u32 m[]) in fill8_col() argument
283 dst[0] = tmp; in fill8_col()
284 dst[2] = (tmp >>= 8); in fill8_col()
286 dst[4] = (tmp >>= 8); in fill8_col()
[all …]
Damifb.c2591 static void bitcpy(unsigned long *dst, int dst_idx, const unsigned long *src, in bitcpy() argument
2613 *dst = comp(*src, *dst, first); in bitcpy()
2618 *dst = comp(*src, *dst, first); in bitcpy()
2619 dst++; in bitcpy()
2627 *dst++ = *src++; in bitcpy()
2628 *dst++ = *src++; in bitcpy()
2629 *dst++ = *src++; in bitcpy()
2630 *dst++ = *src++; in bitcpy()
2631 *dst++ = *src++; in bitcpy()
2632 *dst++ = *src++; in bitcpy()
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/drivers/gpu/drm/gud/
Dgud_internal.h126 static inline void gud_from_display_mode(struct gud_display_mode_req *dst, in gud_from_display_mode() argument
134 dst->clock = cpu_to_le32(src->clock); in gud_from_display_mode()
135 dst->hdisplay = cpu_to_le16(src->hdisplay); in gud_from_display_mode()
136 dst->hsync_start = cpu_to_le16(src->hsync_start); in gud_from_display_mode()
137 dst->hsync_end = cpu_to_le16(src->hsync_end); in gud_from_display_mode()
138 dst->htotal = cpu_to_le16(src->htotal); in gud_from_display_mode()
139 dst->vdisplay = cpu_to_le16(src->vdisplay); in gud_from_display_mode()
140 dst->vsync_start = cpu_to_le16(src->vsync_start); in gud_from_display_mode()
141 dst->vsync_end = cpu_to_le16(src->vsync_end); in gud_from_display_mode()
142 dst->vtotal = cpu_to_le16(src->vtotal); in gud_from_display_mode()
[all …]
/drivers/block/xen-blkback/
Dcommon.h398 static inline void blkif_get_x86_32_req(struct blkif_request *dst, in blkif_get_x86_32_req() argument
402 dst->operation = READ_ONCE(src->operation); in blkif_get_x86_32_req()
403 switch (dst->operation) { in blkif_get_x86_32_req()
408 dst->u.rw.nr_segments = src->u.rw.nr_segments; in blkif_get_x86_32_req()
409 dst->u.rw.handle = src->u.rw.handle; in blkif_get_x86_32_req()
410 dst->u.rw.id = src->u.rw.id; in blkif_get_x86_32_req()
411 dst->u.rw.sector_number = src->u.rw.sector_number; in blkif_get_x86_32_req()
413 if (n > dst->u.rw.nr_segments) in blkif_get_x86_32_req()
414 n = dst->u.rw.nr_segments; in blkif_get_x86_32_req()
416 dst->u.rw.seg[i] = src->u.rw.seg[i]; in blkif_get_x86_32_req()
[all …]
/drivers/gpu/drm/i915/
Di915_memcpy.c38 static void __memcpy_ntdqa(void *dst, const void *src, unsigned long len) in __memcpy_ntdqa() argument
51 :: "r" (src), "r" (dst) : "memory"); in __memcpy_ntdqa()
53 dst += 64; in __memcpy_ntdqa()
59 :: "r" (src), "r" (dst) : "memory"); in __memcpy_ntdqa()
61 dst += 16; in __memcpy_ntdqa()
67 static void __memcpy_ntdqu(void *dst, const void *src, unsigned long len) in __memcpy_ntdqu() argument
80 :: "r" (src), "r" (dst) : "memory"); in __memcpy_ntdqu()
82 dst += 64; in __memcpy_ntdqu()
88 :: "r" (src), "r" (dst) : "memory"); in __memcpy_ntdqu()
90 dst += 16; in __memcpy_ntdqu()
[all …]
/drivers/gpu/drm/
Ddrm_rect.c55 static u32 clip_scaled(int src, int dst, int *clip) in clip_scaled() argument
59 if (dst == 0) in clip_scaled()
63 *clip = min(*clip, dst); in clip_scaled()
65 tmp = mul_u32_u32(src, dst - *clip); in clip_scaled()
71 if (src < (dst << 16)) in clip_scaled()
72 return DIV_ROUND_UP_ULL(tmp, dst); in clip_scaled()
74 return DIV_ROUND_DOWN_ULL(tmp, dst); in clip_scaled()
92 bool drm_rect_clip_scaled(struct drm_rect *src, struct drm_rect *dst, in drm_rect_clip_scaled() argument
97 diff = clip->x1 - dst->x1; in drm_rect_clip_scaled()
100 drm_rect_width(dst), &diff); in drm_rect_clip_scaled()
[all …]
Ddrm_cache.c214 static void memcpy_fallback(struct iosys_map *dst, in memcpy_fallback() argument
218 if (!dst->is_iomem && !src->is_iomem) { in memcpy_fallback()
219 memcpy(dst->vaddr, src->vaddr, len); in memcpy_fallback()
221 iosys_map_memcpy_to(dst, 0, src->vaddr, len); in memcpy_fallback()
222 } else if (!dst->is_iomem) { in memcpy_fallback()
223 memcpy_fromio(dst->vaddr, src->vaddr_iomem, len); in memcpy_fallback()
232 void __iomem *_dst = dst->vaddr_iomem; in memcpy_fallback()
252 static void __memcpy_ntdqa(void *dst, const void *src, unsigned long len) in __memcpy_ntdqa() argument
265 :: "r" (src), "r" (dst) : "memory"); in __memcpy_ntdqa()
267 dst += 64; in __memcpy_ntdqa()
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/drivers/infiniband/ulp/opa_vnic/
Dopa_vnic_vema_iface.c88 __be64 *dst; in opa_vnic_get_summary_counters() local
111 for (dst = &cntrs->tx_unicast, src = &vstats.tx_grp.unicast; in opa_vnic_get_summary_counters()
112 dst < &cntrs->reserved[0]; dst++, src++) { in opa_vnic_get_summary_counters()
113 *dst = cpu_to_be64(*src); in opa_vnic_get_summary_counters()
198 struct __opa_vesw_info *dst = &adapter->info.vesw; in opa_vnic_set_vesw_info() local
201 dst->fabric_id = be16_to_cpu(info->fabric_id); in opa_vnic_set_vesw_info()
202 dst->vesw_id = be16_to_cpu(info->vesw_id); in opa_vnic_set_vesw_info()
203 memcpy(dst->rsvd0, info->rsvd0, ARRAY_SIZE(info->rsvd0)); in opa_vnic_set_vesw_info()
204 dst->def_port_mask = be16_to_cpu(info->def_port_mask); in opa_vnic_set_vesw_info()
205 memcpy(dst->rsvd1, info->rsvd1, ARRAY_SIZE(info->rsvd1)); in opa_vnic_set_vesw_info()
[all …]
/drivers/net/ethernet/apm/xgene/
Dxgene_enet_hw.h20 static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len) in xgene_set_bits() argument
25 *dst &= ~mask; in xgene_set_bits()
26 *dst |= (val << start) & mask; in xgene_set_bits()
139 #define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16) argument
157 #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3) argument
158 #define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3) argument
160 #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2) argument
161 #define CFG_CLE_IP_HDR_LEN_SET(dst, val) xgene_set_bits(dst, val, 8, 5) argument
162 #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12) argument
163 #define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4) argument
[all …]
/drivers/gpu/drm/vmwgfx/
Dvmwgfx_blit.c38 (const _type * dst, const _type * src, size_t size)\
43 if (*dst++ != *src++) \
59 const _type * dst, const _type * src, size_t size) \
62 if (*--dst != *--src) \
105 unsigned int spill = SPILL(dst, _type); \
111 diff_offs = vmw_find_first_diff_u8(dst, src, spill); \
115 dst += spill; \
125 ((_type *) dst, (_type *) src, to_copy); \
129 dst += diff_offs; \
148 static size_t vmw_find_first_diff(const u8 *dst, const u8 *src, size_t size, in vmw_find_first_diff() argument
[all …]
/drivers/firmware/efi/
Dearlycon.c73 unsigned long *dst; in efi_earlycon_clear_scanline() local
77 dst = efi_earlycon_map(y*len, len); in efi_earlycon_clear_scanline()
78 if (!dst) in efi_earlycon_clear_scanline()
81 memset(dst, 0, len); in efi_earlycon_clear_scanline()
82 efi_earlycon_unmap(dst, len); in efi_earlycon_clear_scanline()
87 unsigned long *dst, *src; in efi_earlycon_scroll_up() local
95 dst = efi_earlycon_map(i*len, len); in efi_earlycon_scroll_up()
96 if (!dst) in efi_earlycon_scroll_up()
101 efi_earlycon_unmap(dst, len); in efi_earlycon_scroll_up()
105 memmove(dst, src, len); in efi_earlycon_scroll_up()
[all …]
/drivers/net/ethernet/netronome/nfp/bpf/
Djit.c294 emit_immed(struct nfp_prog *nfp_prog, swreg dst, u16 imm, in emit_immed() argument
300 if (swreg_type(dst) == NN_REG_IMM) { in emit_immed()
305 err = swreg_to_unrestricted(dst, dst, reg_imm(imm & 0xff), &reg); in emit_immed()
313 swreg_type(dst) == NN_REG_NONE ? reg.dst : reg.areg, in emit_immed()
319 __emit_shf(struct nfp_prog *nfp_prog, u16 dst, enum alu_dst_ab dst_ab, in __emit_shf() argument
351 FIELD_PREP(OP_SHF_DST, dst) | in __emit_shf()
363 emit_shf(struct nfp_prog *nfp_prog, swreg dst, in emit_shf() argument
369 err = swreg_to_restricted(dst, lreg, rreg, &reg, true); in emit_shf()
375 __emit_shf(nfp_prog, reg.dst, reg.dst_ab, sc, shift, in emit_shf()
381 emit_shf_indir(struct nfp_prog *nfp_prog, swreg dst, in emit_shf_indir() argument
[all …]
/drivers/char/hw_random/
Dxgene-rng.c53 #define MAX_REFILL_CYCLES_SET(dst, src) \ argument
54 ((dst & ~0xffff0000) | (((u32)src << 16) & 0xffff0000))
55 #define MIN_REFILL_CYCLES_SET(dst, src) \ argument
56 ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
57 #define ALARM_THRESHOLD_SET(dst, src) \ argument
58 ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
59 #define ENABLE_RNG_SET(dst, src) \ argument
60 ((dst & ~BIT(10)) | (((u32)src << 10) & BIT(10)))
61 #define REGSPEC_TEST_MODE_SET(dst, src) \ argument
62 ((dst & ~BIT(8)) | (((u32)src << 8) & BIT(8)))
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