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Searched refs:fcr (Results 1 – 24 of 24) sorted by relevance

/drivers/mtd/nand/raw/
Dtmio_nand.c112 void __iomem *fcr; member
154 tmio_iowrite8(mode, tmio->fcr + FCR_MODE); in tmio_nand_hwcontrol()
166 return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY); in tmio_nand_dev_ready()
174 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); in tmio_irq()
194 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR); in tmio_nand_wait()
196 tmio_iowrite8(0x81, tmio->fcr + FCR_IMR); in tmio_nand_wait()
203 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); in tmio_nand_wait()
207 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); in tmio_nand_wait()
231 data = tmio_ioread16(tmio->fcr + FCR_DATA); in tmio_nand_read_byte()
247 tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1); in tmio_nand_write_buf()
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Dfsl_elbc_nand.c217 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); in fsl_elbc_run_command()
241 in_be32(&lbc->fir), in_be32(&lbc->fcr), in fsl_elbc_run_command()
289 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | in fsl_elbc_do_read()
299 out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT); in fsl_elbc_do_read()
301 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); in fsl_elbc_do_read()
374 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT); in fsl_elbc_cmdfunc()
406 out_be32(&lbc->fcr, in fsl_elbc_cmdfunc()
420 __be32 fcr; in fsl_elbc_cmdfunc() local
438 fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) | in fsl_elbc_cmdfunc()
464 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT; in fsl_elbc_cmdfunc()
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/drivers/net/ethernet/freescale/
Dgianfar_ethtool.c605 u32 fcr = 0x0, fpr = FPR_FILER_MASK; in ethflow_to_filer_rules() local
608 fcr = RQFCR_PID_DAH | RQFCR_CMP_NOMATCH | in ethflow_to_filer_rules()
611 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr; in ethflow_to_filer_rules()
612 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr); in ethflow_to_filer_rules()
615 fcr = RQFCR_PID_DAL | RQFCR_CMP_NOMATCH | in ethflow_to_filer_rules()
618 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr; in ethflow_to_filer_rules()
619 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr); in ethflow_to_filer_rules()
624 fcr = RQFCR_PID_VID | RQFCR_CMP_NOMATCH | RQFCR_HASH | in ethflow_to_filer_rules()
626 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr); in ethflow_to_filer_rules()
628 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr; in ethflow_to_filer_rules()
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Dgianfar.h1236 unsigned int far, unsigned int fcr, unsigned int fpr) in gfar_write_filer() argument
1241 gfar_write(&regs->rqfcr, fcr); in gfar_write_filer()
1246 unsigned int far, unsigned int *fcr, unsigned int *fpr) in gfar_read_filer() argument
1251 *fcr = gfar_read(&regs->rqfcr); in gfar_read_filer()
/drivers/tty/serial/8250/
D8250_port.c82 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
101 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
110 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
124 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
133 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
142 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
149 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
156 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
170 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
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D8250_omap.c218 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | in omap_8250_mdr1_errataset()
316 serial_out(up, UART_FCR, up->fcr); in omap8250_restore_regs()
454 up->fcr = UART_FCR_ENABLE_FIFO; in omap_8250_set_termios()
455 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; in omap_8250_set_termios()
456 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; in omap_8250_set_termios()
D8250.h71 unsigned char fcr; member
D8250_dw.c95 if (up->fcr & UART_FCR_ENABLE_FIFO) { in dw8250_force_idle()
/drivers/net/ethernet/davicom/
Ddm9051.c260 u8 fcr = 0; in dm9051_set_fcr() local
263 fcr |= FCR_BKPM | FCR_FLCE; in dm9051_set_fcr()
265 fcr |= FCR_TXPEN; in dm9051_set_fcr()
267 return dm9051_set_reg(db, DM9051_FCR, fcr); in dm9051_set_fcr()
305 u8 fcr = 0; in dm9051_update_fcr() local
308 fcr |= FCR_BKPM | FCR_FLCE; in dm9051_update_fcr()
310 fcr |= FCR_TXPEN; in dm9051_update_fcr()
312 return dm9051_update_bits(db, DM9051_FCR, FCR_RXTX_BITS, fcr); in dm9051_update_fcr()
/drivers/tty/serial/
Dpch_uart.c221 unsigned int fcr; member
484 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
485 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, in pch_uart_hal_fifo_reset()
487 iowrite8(priv->fcr, priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
496 u8 fcr; in pch_uart_hal_set_fifo() local
534 fcr = in pch_uart_hal_set_fifo()
539 iowrite8(fcr, priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
540 priv->fcr = fcr; in pch_uart_hal_set_fifo()
1746 priv->fcr = 0; in pch_uart_init_port()
Dserial-tegra.c308 unsigned long fcr = tup->fcr_shadow; in tegra_uart_fifo_reset() local
315 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); in tegra_uart_fifo_reset()
316 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
318 fcr &= ~UART_FCR_ENABLE_FIFO; in tegra_uart_fifo_reset()
319 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
321 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); in tegra_uart_fifo_reset()
322 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
323 fcr |= UART_FCR_ENABLE_FIFO; in tegra_uart_fifo_reset()
324 tegra_uart_write(tup, fcr, UART_FCR); in tegra_uart_fifo_reset()
Dsunsu.c776 unsigned char cval, fcr = 0; in sunsu_change_speed() local
815 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; in sunsu_change_speed()
818 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14; in sunsu_change_speed()
821 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8; in sunsu_change_speed()
824 fcr |= UART_FCR7_64BYTE; in sunsu_change_speed()
882 serial_outp(up, UART_FCR, fcr); /* set fcr */ in sunsu_change_speed()
886 if (fcr & UART_FCR_ENABLE_FIFO) { in sunsu_change_speed()
890 serial_outp(up, UART_FCR, fcr); /* set fcr */ in sunsu_change_speed()
Dpxa.c429 unsigned char cval, fcr = 0; in serial_pxa_set_termios() local
450 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1; in serial_pxa_set_termios()
452 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8; in serial_pxa_set_termios()
454 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32; in serial_pxa_set_termios()
529 serial_out(up, UART_FCR, fcr); in serial_pxa_set_termios()
Domap-serial.c134 unsigned char fcr; member
840 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | in serial_omap_set_termios()
929 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; in serial_omap_set_termios()
930 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; in serial_omap_set_termios()
931 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | in serial_omap_set_termios()
934 serial_out(up, UART_FCR, up->fcr); in serial_omap_set_termios()
1723 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | in serial_omap_mdr1_errataset()
1759 serial_out(up, UART_FCR, up->fcr); in serial_omap_restore_context()
Dmilbeaut_usio.c123 u16 fcr = readw(port->membase + MLB_USIO_REG_FCR); in mlb_usio_start_tx() local
125 writew(fcr | MLB_USIO_FCR_FTIE, port->membase + MLB_USIO_REG_FCR); in mlb_usio_start_tx()
126 if (!(fcr & MLB_USIO_FCR_FDRQ)) in mlb_usio_start_tx()
Dserial_txx9.c599 unsigned int cval, fcr = 0; in serial_txx9_set_termios() local
645 fcr = TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1; in serial_txx9_set_termios()
699 sio_out(up, TXX9_SIFCR, fcr); in serial_txx9_set_termios()
/drivers/mmc/core/
Dsdio_uart.c251 unsigned char cval, fcr = 0; in sdio_uart_change_speed() local
283 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; in sdio_uart_change_speed()
285 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10; in sdio_uart_change_speed()
329 sdio_out(port, UART_FCR, fcr); in sdio_uart_change_speed()
/drivers/ata/
Dpata_macio.c871 u32 fcr = readl(priv->kauai_fcr); in pata_macio_do_suspend() local
872 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE); in pata_macio_do_suspend()
873 writel(fcr, priv->kauai_fcr); in pata_macio_do_suspend()
/drivers/net/ethernet/faraday/
Dftgmac100.c228 u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16); in ftgmac100_config_pause() local
232 fcr |= FTGMAC100_FCR_FC_EN; in ftgmac100_config_pause()
238 fcr |= FTGMAC100_FCR_FCTHR_EN; in ftgmac100_config_pause()
240 iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR); in ftgmac100_config_pause()
/drivers/net/ethernet/broadcom/genet/
Dbcmgenet.h104 u32 fcr; /* RO # of carrier sense error pkt */ member
Dbcmgenet.c1081 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
/drivers/net/ethernet/broadcom/
Dbcmsysport.h523 u32 fcr; /* RO # of carrier sense error pkt */ member
Dbcmsysport.c248 STAT_MIB_RX("rx_carrier", mib.rx.fcr),
/drivers/tty/
Dmxser.c717 u8 fcr = UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT; in mxser_disable_and_clear_FIFO() local
720 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; in mxser_disable_and_clear_FIFO()
722 outb(fcr, info->ioaddr + UART_FCR); in mxser_disable_and_clear_FIFO()