1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
4 *
5 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com).
6 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * This code is loosely based on the 1.8 moxa driver which is based on
9 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
10 * others.
11 *
12 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
13 * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on
14 * www.moxa.com.
15 * - Fixed x86_64 cleanness
16 */
17
18 #include <linux/module.h>
19 #include <linux/errno.h>
20 #include <linux/signal.h>
21 #include <linux/sched.h>
22 #include <linux/timer.h>
23 #include <linux/interrupt.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial.h>
27 #include <linux/serial_reg.h>
28 #include <linux/major.h>
29 #include <linux/string.h>
30 #include <linux/fcntl.h>
31 #include <linux/ptrace.h>
32 #include <linux/ioport.h>
33 #include <linux/mm.h>
34 #include <linux/delay.h>
35 #include <linux/pci.h>
36 #include <linux/bitops.h>
37 #include <linux/slab.h>
38 #include <linux/ratelimit.h>
39
40 #include <asm/io.h>
41 #include <asm/irq.h>
42 #include <linux/uaccess.h>
43
44 /*
45 * Semi-public control interfaces
46 */
47
48 /*
49 * MOXA ioctls
50 */
51
52 #define MOXA 0x400
53 #define MOXA_SET_OP_MODE (MOXA + 66)
54 #define MOXA_GET_OP_MODE (MOXA + 67)
55
56 #define RS232_MODE 0
57 #define RS485_2WIRE_MODE 1
58 #define RS422_MODE 2
59 #define RS485_4WIRE_MODE 3
60 #define OP_MODE_MASK 3
61
62 /* --------------------------------------------------- */
63
64 /*
65 * Follow just what Moxa Must chip defines.
66 *
67 * When LCR register (offset 0x03) is written the following value, the Must chip
68 * will enter enhanced mode. And a write to EFR (offset 0x02) bit 6,7 will
69 * change bank.
70 */
71 #define MOXA_MUST_ENTER_ENHANCED 0xBF
72
73 /* when enhanced mode is enabled, access to general bank register */
74 #define MOXA_MUST_GDL_REGISTER 0x07
75 #define MOXA_MUST_GDL_MASK 0x7F
76 #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
77
78 #define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
79 /* enhanced register bank select and enhanced mode setting register */
80 /* This works only when LCR register equals to 0xBF */
81 #define MOXA_MUST_EFR_REGISTER 0x02
82 #define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enhanced mode enable */
83 /* enhanced register bank set 0, 1, 2 */
84 #define MOXA_MUST_EFR_BANK0 0x00
85 #define MOXA_MUST_EFR_BANK1 0x40
86 #define MOXA_MUST_EFR_BANK2 0x80
87 #define MOXA_MUST_EFR_BANK3 0xC0
88 #define MOXA_MUST_EFR_BANK_MASK 0xC0
89
90 /* set XON1 value register, when LCR=0xBF and change to bank0 */
91 #define MOXA_MUST_XON1_REGISTER 0x04
92
93 /* set XON2 value register, when LCR=0xBF and change to bank0 */
94 #define MOXA_MUST_XON2_REGISTER 0x05
95
96 /* set XOFF1 value register, when LCR=0xBF and change to bank0 */
97 #define MOXA_MUST_XOFF1_REGISTER 0x06
98
99 /* set XOFF2 value register, when LCR=0xBF and change to bank0 */
100 #define MOXA_MUST_XOFF2_REGISTER 0x07
101
102 #define MOXA_MUST_RBRTL_REGISTER 0x04
103 #define MOXA_MUST_RBRTH_REGISTER 0x05
104 #define MOXA_MUST_RBRTI_REGISTER 0x06
105 #define MOXA_MUST_THRTL_REGISTER 0x07
106 #define MOXA_MUST_ENUM_REGISTER 0x04
107 #define MOXA_MUST_HWID_REGISTER 0x05
108 #define MOXA_MUST_ECR_REGISTER 0x06
109 #define MOXA_MUST_CSR_REGISTER 0x07
110
111 #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */
112 #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */
113
114 #define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */
115 #define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */
116 #define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */
117 #define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */
118
119 #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
120
121 /* GDA interrupt pending */
122 #define MOXA_MUST_IIR_GDA 0x1C
123 #define MOXA_MUST_IIR_RDA 0x04
124 #define MOXA_MUST_IIR_RTO 0x0C
125 #define MOXA_MUST_IIR_LSR 0x06
126
127 /* received Xon/Xoff or specical interrupt pending */
128 #define MOXA_MUST_IIR_XSC 0x10
129
130 /* RTS/CTS change state interrupt pending */
131 #define MOXA_MUST_IIR_RTSCTS 0x20
132 #define MOXA_MUST_IIR_MASK 0x3E
133
134 #define MOXA_MUST_MCR_XON_FLAG 0x40
135 #define MOXA_MUST_MCR_XON_ANY 0x80
136 #define MOXA_MUST_MCR_TX_XON 0x08
137
138 #define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */
139 #define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */
140 #define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */
141 #define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */
142 #define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */
143 #define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */
144 #define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */
145 #define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */
146 #define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */
147 #define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */
148 #define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */
149
150 #define MXSERMAJOR 174
151
152 #define MXSER_BOARDS 4 /* Max. boards */
153 #define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
154 #define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
155 #define MXSER_ISR_PASS_LIMIT 100
156
157 #define WAKEUP_CHARS 256
158
159 #define MXSER_BAUD_BASE 921600
160 #define MXSER_CUSTOM_DIVISOR (MXSER_BAUD_BASE * 16)
161
162 #define PCI_DEVICE_ID_MOXA_RC7000 0x0001
163 #define PCI_DEVICE_ID_MOXA_CP102 0x1020
164 #define PCI_DEVICE_ID_MOXA_CP102UL 0x1021
165 #define PCI_DEVICE_ID_MOXA_CP102U 0x1022
166 #define PCI_DEVICE_ID_MOXA_CP102UF 0x1023
167 #define PCI_DEVICE_ID_MOXA_C104 0x1040
168 #define PCI_DEVICE_ID_MOXA_CP104U 0x1041
169 #define PCI_DEVICE_ID_MOXA_CP104JU 0x1042
170 #define PCI_DEVICE_ID_MOXA_CP104EL 0x1043
171 #define PCI_DEVICE_ID_MOXA_POS104UL 0x1044
172 #define PCI_DEVICE_ID_MOXA_CB108 0x1080
173 #define PCI_DEVICE_ID_MOXA_CP112UL 0x1120
174 #define PCI_DEVICE_ID_MOXA_CT114 0x1140
175 #define PCI_DEVICE_ID_MOXA_CP114 0x1141
176 #define PCI_DEVICE_ID_MOXA_CB114 0x1142
177 #define PCI_DEVICE_ID_MOXA_CP114UL 0x1143
178 #define PCI_DEVICE_ID_MOXA_CP118U 0x1180
179 #define PCI_DEVICE_ID_MOXA_CP118EL 0x1181
180 #define PCI_DEVICE_ID_MOXA_CP132 0x1320
181 #define PCI_DEVICE_ID_MOXA_CP132U 0x1321
182 #define PCI_DEVICE_ID_MOXA_CP134U 0x1340
183 #define PCI_DEVICE_ID_MOXA_CB134I 0x1341
184 #define PCI_DEVICE_ID_MOXA_CP138U 0x1380
185 #define PCI_DEVICE_ID_MOXA_C168 0x1680
186 #define PCI_DEVICE_ID_MOXA_CP168U 0x1681
187 #define PCI_DEVICE_ID_MOXA_CP168EL 0x1682
188
189 #define MXSER_NPORTS(ddata) ((ddata) & 0xffU)
190 #define MXSER_HIGHBAUD 0x0100
191
192 enum mxser_must_hwid {
193 MOXA_OTHER_UART = 0x00,
194 MOXA_MUST_MU150_HWID = 0x01,
195 MOXA_MUST_MU860_HWID = 0x02,
196 };
197
198 static const struct {
199 u8 type;
200 u8 fifo_size;
201 u8 rx_high_water;
202 u8 rx_low_water;
203 speed_t max_baud;
204 } Gpci_uart_info[] = {
205 { MOXA_OTHER_UART, 16, 14, 1, 921600 },
206 { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 },
207 { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 }
208 };
209 #define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
210
211
212 /* driver_data correspond to the lines in the structure above
213 see also ISA probe function before you change something */
214 static const struct pci_device_id mxser_pcibrds[] = {
215 { PCI_DEVICE_DATA(MOXA, C168, 8) },
216 { PCI_DEVICE_DATA(MOXA, C104, 4) },
217 { PCI_DEVICE_DATA(MOXA, CP132, 2) },
218 { PCI_DEVICE_DATA(MOXA, CP114, 4) },
219 { PCI_DEVICE_DATA(MOXA, CT114, 4) },
220 { PCI_DEVICE_DATA(MOXA, CP102, 2 | MXSER_HIGHBAUD) },
221 { PCI_DEVICE_DATA(MOXA, CP104U, 4) },
222 { PCI_DEVICE_DATA(MOXA, CP168U, 8) },
223 { PCI_DEVICE_DATA(MOXA, CP132U, 2) },
224 { PCI_DEVICE_DATA(MOXA, CP134U, 4) },
225 { PCI_DEVICE_DATA(MOXA, CP104JU, 4) },
226 { PCI_DEVICE_DATA(MOXA, RC7000, 8) }, /* RC7000 */
227 { PCI_DEVICE_DATA(MOXA, CP118U, 8) },
228 { PCI_DEVICE_DATA(MOXA, CP102UL, 2) },
229 { PCI_DEVICE_DATA(MOXA, CP102U, 2) },
230 { PCI_DEVICE_DATA(MOXA, CP118EL, 8) },
231 { PCI_DEVICE_DATA(MOXA, CP168EL, 8) },
232 { PCI_DEVICE_DATA(MOXA, CP104EL, 4) },
233 { PCI_DEVICE_DATA(MOXA, CB108, 8) },
234 { PCI_DEVICE_DATA(MOXA, CB114, 4) },
235 { PCI_DEVICE_DATA(MOXA, CB134I, 4) },
236 { PCI_DEVICE_DATA(MOXA, CP138U, 8) },
237 { PCI_DEVICE_DATA(MOXA, POS104UL, 4) },
238 { PCI_DEVICE_DATA(MOXA, CP114UL, 4) },
239 { PCI_DEVICE_DATA(MOXA, CP102UF, 2) },
240 { PCI_DEVICE_DATA(MOXA, CP112UL, 2) },
241 { }
242 };
243 MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
244
245 static int ttymajor = MXSERMAJOR;
246
247 /* Variables for insmod */
248
249 MODULE_AUTHOR("Casper Yang");
250 MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
251 module_param(ttymajor, int, 0);
252 MODULE_LICENSE("GPL");
253
254 struct mxser_board;
255
256 struct mxser_port {
257 struct tty_port port;
258 struct mxser_board *board;
259
260 unsigned long ioaddr;
261 unsigned long opmode_ioaddr;
262
263 u8 rx_high_water;
264 u8 rx_low_water;
265 int type; /* UART type */
266
267 unsigned char x_char; /* xon/xoff character */
268 u8 IER; /* Interrupt Enable Register */
269 u8 MCR; /* Modem control register */
270 u8 FCR; /* FIFO control register */
271
272 struct async_icount icount; /* kernel counters for 4 input interrupts */
273 unsigned int timeout;
274
275 u8 read_status_mask;
276 u8 ignore_status_mask;
277 u8 xmit_fifo_size;
278
279 spinlock_t slock;
280 };
281
282 struct mxser_board {
283 unsigned int idx;
284 unsigned short nports;
285 int irq;
286 unsigned long vector;
287
288 enum mxser_must_hwid must_hwid;
289 speed_t max_baud;
290
291 struct mxser_port ports[];
292 };
293
294 static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS);
295 static struct tty_driver *mxvar_sdriver;
296
__mxser_must_set_EFR(unsigned long baseio,u8 clear,u8 set,bool restore_LCR)297 static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set,
298 bool restore_LCR)
299 {
300 u8 oldlcr, efr;
301
302 oldlcr = inb(baseio + UART_LCR);
303 outb(MOXA_MUST_ENTER_ENHANCED, baseio + UART_LCR);
304
305 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
306 efr &= ~clear;
307 efr |= set;
308
309 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
310
311 if (restore_LCR)
312 outb(oldlcr, baseio + UART_LCR);
313
314 return oldlcr;
315 }
316
mxser_must_select_bank(unsigned long baseio,u8 bank)317 static u8 mxser_must_select_bank(unsigned long baseio, u8 bank)
318 {
319 return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank,
320 false);
321 }
322
mxser_set_must_xon1_value(unsigned long baseio,u8 value)323 static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
324 {
325 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0);
326 outb(value, baseio + MOXA_MUST_XON1_REGISTER);
327 outb(oldlcr, baseio + UART_LCR);
328 }
329
mxser_set_must_xoff1_value(unsigned long baseio,u8 value)330 static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
331 {
332 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0);
333 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
334 outb(oldlcr, baseio + UART_LCR);
335 }
336
mxser_set_must_fifo_value(struct mxser_port * info)337 static void mxser_set_must_fifo_value(struct mxser_port *info)
338 {
339 u8 oldlcr = mxser_must_select_bank(info->ioaddr, MOXA_MUST_EFR_BANK1);
340 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
341 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
342 outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
343 outb(oldlcr, info->ioaddr + UART_LCR);
344 }
345
mxser_set_must_enum_value(unsigned long baseio,u8 value)346 static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
347 {
348 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2);
349 outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
350 outb(oldlcr, baseio + UART_LCR);
351 }
352
mxser_get_must_hardware_id(unsigned long baseio)353 static u8 mxser_get_must_hardware_id(unsigned long baseio)
354 {
355 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2);
356 u8 id = inb(baseio + MOXA_MUST_HWID_REGISTER);
357 outb(oldlcr, baseio + UART_LCR);
358
359 return id;
360 }
361
mxser_must_set_EFR(unsigned long baseio,u8 clear,u8 set)362 static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set)
363 {
364 __mxser_must_set_EFR(baseio, clear, set, true);
365 }
366
mxser_must_set_enhance_mode(unsigned long baseio,bool enable)367 static void mxser_must_set_enhance_mode(unsigned long baseio, bool enable)
368 {
369 mxser_must_set_EFR(baseio,
370 enable ? 0 : MOXA_MUST_EFR_EFRB_ENABLE,
371 enable ? MOXA_MUST_EFR_EFRB_ENABLE : 0);
372 }
373
mxser_must_no_sw_flow_control(unsigned long baseio)374 static void mxser_must_no_sw_flow_control(unsigned long baseio)
375 {
376 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_MASK, 0);
377 }
378
mxser_must_set_tx_sw_flow_control(unsigned long baseio,bool enable)379 static void mxser_must_set_tx_sw_flow_control(unsigned long baseio, bool enable)
380 {
381 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_TX_MASK,
382 enable ? MOXA_MUST_EFR_SF_TX1 : 0);
383 }
384
mxser_must_set_rx_sw_flow_control(unsigned long baseio,bool enable)385 static void mxser_must_set_rx_sw_flow_control(unsigned long baseio, bool enable)
386 {
387 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_RX_MASK,
388 enable ? MOXA_MUST_EFR_SF_RX1 : 0);
389 }
390
mxser_must_get_hwid(unsigned long io)391 static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io)
392 {
393 u8 oldmcr, hwid;
394 int i;
395
396 outb(0, io + UART_LCR);
397 mxser_must_set_enhance_mode(io, false);
398 oldmcr = inb(io + UART_MCR);
399 outb(0, io + UART_MCR);
400 mxser_set_must_xon1_value(io, 0x11);
401 if (inb(io + UART_MCR) != 0) {
402 outb(oldmcr, io + UART_MCR);
403 return MOXA_OTHER_UART;
404 }
405
406 hwid = mxser_get_must_hardware_id(io);
407 for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */
408 if (hwid == Gpci_uart_info[i].type)
409 return hwid;
410
411 return MOXA_OTHER_UART;
412 }
413
mxser_16550A_or_MUST(struct mxser_port * info)414 static bool mxser_16550A_or_MUST(struct mxser_port *info)
415 {
416 return info->type == PORT_16550A || info->board->must_hwid;
417 }
418
mxser_process_txrx_fifo(struct mxser_port * info)419 static void mxser_process_txrx_fifo(struct mxser_port *info)
420 {
421 unsigned int i;
422
423 if (info->type == PORT_16450 || info->type == PORT_8250) {
424 info->rx_high_water = 1;
425 info->rx_low_water = 1;
426 info->xmit_fifo_size = 1;
427 return;
428 }
429
430 for (i = 0; i < UART_INFO_NUM; i++)
431 if (info->board->must_hwid == Gpci_uart_info[i].type) {
432 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
433 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
434 info->xmit_fifo_size = Gpci_uart_info[i].fifo_size;
435 break;
436 }
437 }
438
__mxser_start_tx(struct mxser_port * info)439 static void __mxser_start_tx(struct mxser_port *info)
440 {
441 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
442 info->IER |= UART_IER_THRI;
443 outb(info->IER, info->ioaddr + UART_IER);
444 }
445
mxser_start_tx(struct mxser_port * info)446 static void mxser_start_tx(struct mxser_port *info)
447 {
448 unsigned long flags;
449
450 spin_lock_irqsave(&info->slock, flags);
451 __mxser_start_tx(info);
452 spin_unlock_irqrestore(&info->slock, flags);
453 }
454
__mxser_stop_tx(struct mxser_port * info)455 static void __mxser_stop_tx(struct mxser_port *info)
456 {
457 info->IER &= ~UART_IER_THRI;
458 outb(info->IER, info->ioaddr + UART_IER);
459 }
460
mxser_carrier_raised(struct tty_port * port)461 static int mxser_carrier_raised(struct tty_port *port)
462 {
463 struct mxser_port *mp = container_of(port, struct mxser_port, port);
464 return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0;
465 }
466
mxser_dtr_rts(struct tty_port * port,int on)467 static void mxser_dtr_rts(struct tty_port *port, int on)
468 {
469 struct mxser_port *mp = container_of(port, struct mxser_port, port);
470 unsigned long flags;
471 u8 mcr;
472
473 spin_lock_irqsave(&mp->slock, flags);
474 mcr = inb(mp->ioaddr + UART_MCR);
475 if (on)
476 mcr |= UART_MCR_DTR | UART_MCR_RTS;
477 else
478 mcr &= ~(UART_MCR_DTR | UART_MCR_RTS);
479 outb(mcr, mp->ioaddr + UART_MCR);
480 spin_unlock_irqrestore(&mp->slock, flags);
481 }
482
mxser_set_baud(struct tty_struct * tty,speed_t newspd)483 static int mxser_set_baud(struct tty_struct *tty, speed_t newspd)
484 {
485 struct mxser_port *info = tty->driver_data;
486 unsigned int quot = 0, baud;
487 unsigned char cval;
488 u64 timeout;
489
490 if (newspd > info->board->max_baud)
491 return -1;
492
493 if (newspd == 134) {
494 quot = 2 * MXSER_BAUD_BASE / 269;
495 tty_encode_baud_rate(tty, 134, 134);
496 } else if (newspd) {
497 quot = MXSER_BAUD_BASE / newspd;
498 if (quot == 0)
499 quot = 1;
500 baud = MXSER_BAUD_BASE / quot;
501 tty_encode_baud_rate(tty, baud, baud);
502 } else {
503 quot = 0;
504 }
505
506 /*
507 * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the
508 * u64 domain
509 */
510 timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot;
511 do_div(timeout, MXSER_BAUD_BASE);
512 info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */
513
514 if (quot) {
515 info->MCR |= UART_MCR_DTR;
516 outb(info->MCR, info->ioaddr + UART_MCR);
517 } else {
518 info->MCR &= ~UART_MCR_DTR;
519 outb(info->MCR, info->ioaddr + UART_MCR);
520 return 0;
521 }
522
523 cval = inb(info->ioaddr + UART_LCR);
524
525 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
526
527 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
528 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
529 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
530
531 if (C_BAUD(tty) == BOTHER) {
532 quot = MXSER_BAUD_BASE % newspd;
533 quot *= 8;
534 if (quot % newspd > newspd / 2) {
535 quot /= newspd;
536 quot++;
537 } else
538 quot /= newspd;
539
540 mxser_set_must_enum_value(info->ioaddr, quot);
541 } else {
542 mxser_set_must_enum_value(info->ioaddr, 0);
543 }
544
545 return 0;
546 }
547
mxser_handle_cts(struct tty_struct * tty,struct mxser_port * info,u8 msr)548 static void mxser_handle_cts(struct tty_struct *tty, struct mxser_port *info,
549 u8 msr)
550 {
551 bool cts = msr & UART_MSR_CTS;
552
553 if (tty->hw_stopped) {
554 if (cts) {
555 tty->hw_stopped = 0;
556
557 if (!mxser_16550A_or_MUST(info))
558 __mxser_start_tx(info);
559 tty_wakeup(tty);
560 }
561 return;
562 } else if (cts)
563 return;
564
565 tty->hw_stopped = 1;
566 if (!mxser_16550A_or_MUST(info))
567 __mxser_stop_tx(info);
568 }
569
570 /*
571 * This routine is called to set the UART divisor registers to match
572 * the specified baud rate for a serial port.
573 */
mxser_change_speed(struct tty_struct * tty,const struct ktermios * old_termios)574 static void mxser_change_speed(struct tty_struct *tty,
575 const struct ktermios *old_termios)
576 {
577 struct mxser_port *info = tty->driver_data;
578 unsigned cflag, cval;
579
580 cflag = tty->termios.c_cflag;
581
582 if (mxser_set_baud(tty, tty_get_baud_rate(tty))) {
583 /* Use previous rate on a failure */
584 if (old_termios) {
585 speed_t baud = tty_termios_baud_rate(old_termios);
586 tty_encode_baud_rate(tty, baud, baud);
587 }
588 }
589
590 /* byte size and parity */
591 cval = UART_LCR_WLEN(tty_get_char_size(tty->termios.c_cflag));
592
593 if (cflag & CSTOPB)
594 cval |= UART_LCR_STOP;
595 if (cflag & PARENB)
596 cval |= UART_LCR_PARITY;
597 if (!(cflag & PARODD))
598 cval |= UART_LCR_EPAR;
599 if (cflag & CMSPAR)
600 cval |= UART_LCR_SPAR;
601
602 info->FCR = 0;
603 if (info->board->must_hwid) {
604 info->FCR |= UART_FCR_ENABLE_FIFO |
605 MOXA_MUST_FCR_GDA_MODE_ENABLE;
606 mxser_set_must_fifo_value(info);
607 } else if (info->type != PORT_8250 && info->type != PORT_16450) {
608 info->FCR |= UART_FCR_ENABLE_FIFO;
609 switch (info->rx_high_water) {
610 case 1:
611 info->FCR |= UART_FCR_TRIGGER_1;
612 break;
613 case 4:
614 info->FCR |= UART_FCR_TRIGGER_4;
615 break;
616 case 8:
617 info->FCR |= UART_FCR_TRIGGER_8;
618 break;
619 default:
620 info->FCR |= UART_FCR_TRIGGER_14;
621 break;
622 }
623 }
624
625 /* CTS flow control flag and modem status interrupts */
626 info->IER &= ~UART_IER_MSI;
627 info->MCR &= ~UART_MCR_AFE;
628 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
629 if (cflag & CRTSCTS) {
630 info->IER |= UART_IER_MSI;
631 if (mxser_16550A_or_MUST(info)) {
632 info->MCR |= UART_MCR_AFE;
633 } else {
634 mxser_handle_cts(tty, info,
635 inb(info->ioaddr + UART_MSR));
636 }
637 }
638 outb(info->MCR, info->ioaddr + UART_MCR);
639 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
640 if (~cflag & CLOCAL)
641 info->IER |= UART_IER_MSI;
642 outb(info->IER, info->ioaddr + UART_IER);
643
644 /*
645 * Set up parity check flag
646 */
647 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
648 if (I_INPCK(tty))
649 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
650 if (I_BRKINT(tty) || I_PARMRK(tty))
651 info->read_status_mask |= UART_LSR_BI;
652
653 info->ignore_status_mask = 0;
654
655 if (I_IGNBRK(tty)) {
656 info->ignore_status_mask |= UART_LSR_BI;
657 info->read_status_mask |= UART_LSR_BI;
658 /*
659 * If we're ignore parity and break indicators, ignore
660 * overruns too. (For real raw support).
661 */
662 if (I_IGNPAR(tty)) {
663 info->ignore_status_mask |=
664 UART_LSR_OE |
665 UART_LSR_PE |
666 UART_LSR_FE;
667 info->read_status_mask |=
668 UART_LSR_OE |
669 UART_LSR_PE |
670 UART_LSR_FE;
671 }
672 }
673 if (info->board->must_hwid) {
674 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty));
675 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty));
676 mxser_must_set_rx_sw_flow_control(info->ioaddr, I_IXON(tty));
677 mxser_must_set_tx_sw_flow_control(info->ioaddr, I_IXOFF(tty));
678 }
679
680
681 outb(info->FCR, info->ioaddr + UART_FCR);
682 outb(cval, info->ioaddr + UART_LCR);
683 }
684
mxser_check_modem_status(struct tty_struct * tty,struct mxser_port * port)685 static u8 mxser_check_modem_status(struct tty_struct *tty,
686 struct mxser_port *port)
687 {
688 u8 msr = inb(port->ioaddr + UART_MSR);
689
690 if (!(msr & UART_MSR_ANY_DELTA))
691 return msr;
692
693 /* update input line counters */
694 if (msr & UART_MSR_TERI)
695 port->icount.rng++;
696 if (msr & UART_MSR_DDSR)
697 port->icount.dsr++;
698 if (msr & UART_MSR_DDCD)
699 port->icount.dcd++;
700 if (msr & UART_MSR_DCTS)
701 port->icount.cts++;
702 wake_up_interruptible(&port->port.delta_msr_wait);
703
704 if (tty_port_check_carrier(&port->port) && (msr & UART_MSR_DDCD)) {
705 if (msr & UART_MSR_DCD)
706 wake_up_interruptible(&port->port.open_wait);
707 }
708
709 if (tty_port_cts_enabled(&port->port))
710 mxser_handle_cts(tty, port, msr);
711
712 return msr;
713 }
714
mxser_disable_and_clear_FIFO(struct mxser_port * info)715 static void mxser_disable_and_clear_FIFO(struct mxser_port *info)
716 {
717 u8 fcr = UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT;
718
719 if (info->board->must_hwid)
720 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
721
722 outb(fcr, info->ioaddr + UART_FCR);
723 }
724
mxser_activate(struct tty_port * port,struct tty_struct * tty)725 static int mxser_activate(struct tty_port *port, struct tty_struct *tty)
726 {
727 struct mxser_port *info = container_of(port, struct mxser_port, port);
728 unsigned long flags;
729 int ret;
730
731 ret = tty_port_alloc_xmit_buf(port);
732 if (ret < 0)
733 return ret;
734
735 spin_lock_irqsave(&info->slock, flags);
736
737 if (!info->type) {
738 set_bit(TTY_IO_ERROR, &tty->flags);
739 spin_unlock_irqrestore(&info->slock, flags);
740 ret = 0;
741 goto err_free_xmit;
742 }
743
744 /*
745 * Clear the FIFO buffers and disable them
746 * (they will be reenabled in mxser_change_speed())
747 */
748 mxser_disable_and_clear_FIFO(info);
749
750 /*
751 * At this point there's no way the LSR could still be 0xFF;
752 * if it is, then bail out, because there's likely no UART
753 * here.
754 */
755 if (inb(info->ioaddr + UART_LSR) == 0xff) {
756 spin_unlock_irqrestore(&info->slock, flags);
757 if (capable(CAP_SYS_ADMIN)) {
758 set_bit(TTY_IO_ERROR, &tty->flags);
759 return 0;
760 }
761
762 ret = -ENODEV;
763 goto err_free_xmit;
764 }
765
766 /*
767 * Clear the interrupt registers.
768 */
769 (void) inb(info->ioaddr + UART_LSR);
770 (void) inb(info->ioaddr + UART_RX);
771 (void) inb(info->ioaddr + UART_IIR);
772 (void) inb(info->ioaddr + UART_MSR);
773
774 /*
775 * Now, initialize the UART
776 */
777 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
778 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
779 outb(info->MCR, info->ioaddr + UART_MCR);
780
781 /*
782 * Finally, enable interrupts
783 */
784 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
785
786 if (info->board->must_hwid)
787 info->IER |= MOXA_MUST_IER_EGDAI;
788 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
789
790 /*
791 * And clear the interrupt registers again for luck.
792 */
793 (void) inb(info->ioaddr + UART_LSR);
794 (void) inb(info->ioaddr + UART_RX);
795 (void) inb(info->ioaddr + UART_IIR);
796 (void) inb(info->ioaddr + UART_MSR);
797
798 clear_bit(TTY_IO_ERROR, &tty->flags);
799 kfifo_reset(&port->xmit_fifo);
800
801 /*
802 * and set the speed of the serial port
803 */
804 mxser_change_speed(tty, NULL);
805 spin_unlock_irqrestore(&info->slock, flags);
806
807 return 0;
808 err_free_xmit:
809 tty_port_free_xmit_buf(port);
810 return ret;
811 }
812
813 /*
814 * To stop accepting input, we disable the receive line status interrupts, and
815 * tell the interrupt driver to stop checking the data ready bit in the line
816 * status register.
817 */
mxser_stop_rx(struct mxser_port * info)818 static void mxser_stop_rx(struct mxser_port *info)
819 {
820 info->IER &= ~UART_IER_RLSI;
821 if (info->board->must_hwid)
822 info->IER &= ~MOXA_MUST_RECV_ISR;
823
824 outb(info->IER, info->ioaddr + UART_IER);
825 }
826
827 /*
828 * This routine will shutdown a serial port
829 */
mxser_shutdown_port(struct tty_port * port)830 static void mxser_shutdown_port(struct tty_port *port)
831 {
832 struct mxser_port *info = container_of(port, struct mxser_port, port);
833 unsigned long flags;
834
835 spin_lock_irqsave(&info->slock, flags);
836
837 mxser_stop_rx(info);
838
839 /*
840 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
841 * here so the queue might never be waken up
842 */
843 wake_up_interruptible(&info->port.delta_msr_wait);
844
845 info->IER = 0;
846 outb(0x00, info->ioaddr + UART_IER);
847
848 /* clear Rx/Tx FIFO's */
849 mxser_disable_and_clear_FIFO(info);
850
851 /* read data port to reset things */
852 (void) inb(info->ioaddr + UART_RX);
853
854
855 if (info->board->must_hwid)
856 mxser_must_no_sw_flow_control(info->ioaddr);
857
858 spin_unlock_irqrestore(&info->slock, flags);
859
860 /* make sure ISR is not running while we free the buffer */
861 synchronize_irq(info->board->irq);
862
863 tty_port_free_xmit_buf(port);
864 }
865
866 /*
867 * This routine is called whenever a serial port is opened. It
868 * enables interrupts for a serial port, linking in its async structure into
869 * the IRQ chain. It also performs the serial-specific
870 * initialization for the tty structure.
871 */
mxser_open(struct tty_struct * tty,struct file * filp)872 static int mxser_open(struct tty_struct *tty, struct file *filp)
873 {
874 struct tty_port *tport = tty->port;
875 struct mxser_port *port = container_of(tport, struct mxser_port, port);
876
877 tty->driver_data = port;
878
879 return tty_port_open(tport, tty, filp);
880 }
881
mxser_flush_buffer(struct tty_struct * tty)882 static void mxser_flush_buffer(struct tty_struct *tty)
883 {
884 struct mxser_port *info = tty->driver_data;
885 unsigned long flags;
886
887 spin_lock_irqsave(&info->slock, flags);
888 kfifo_reset(&info->port.xmit_fifo);
889
890 outb(info->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
891 info->ioaddr + UART_FCR);
892
893 spin_unlock_irqrestore(&info->slock, flags);
894
895 tty_wakeup(tty);
896 }
897
mxser_close(struct tty_struct * tty,struct file * filp)898 static void mxser_close(struct tty_struct *tty, struct file *filp)
899 {
900 tty_port_close(tty->port, tty, filp);
901 }
902
mxser_write(struct tty_struct * tty,const unsigned char * buf,int count)903 static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
904 {
905 struct mxser_port *info = tty->driver_data;
906 unsigned long flags;
907 int written;
908 bool is_empty;
909
910 spin_lock_irqsave(&info->slock, flags);
911 written = kfifo_in(&info->port.xmit_fifo, buf, count);
912 is_empty = kfifo_is_empty(&info->port.xmit_fifo);
913 spin_unlock_irqrestore(&info->slock, flags);
914
915 if (!is_empty && !tty->flow.stopped)
916 if (!tty->hw_stopped || mxser_16550A_or_MUST(info))
917 mxser_start_tx(info);
918
919 return written;
920 }
921
mxser_put_char(struct tty_struct * tty,unsigned char ch)922 static int mxser_put_char(struct tty_struct *tty, unsigned char ch)
923 {
924 struct mxser_port *info = tty->driver_data;
925 unsigned long flags;
926 int ret;
927
928 spin_lock_irqsave(&info->slock, flags);
929 ret = kfifo_put(&info->port.xmit_fifo, ch);
930 spin_unlock_irqrestore(&info->slock, flags);
931
932 return ret;
933 }
934
935
mxser_flush_chars(struct tty_struct * tty)936 static void mxser_flush_chars(struct tty_struct *tty)
937 {
938 struct mxser_port *info = tty->driver_data;
939
940 if (kfifo_is_empty(&info->port.xmit_fifo) || tty->flow.stopped ||
941 (tty->hw_stopped && !mxser_16550A_or_MUST(info)))
942 return;
943
944 mxser_start_tx(info);
945 }
946
mxser_write_room(struct tty_struct * tty)947 static unsigned int mxser_write_room(struct tty_struct *tty)
948 {
949 struct mxser_port *info = tty->driver_data;
950
951 return kfifo_avail(&info->port.xmit_fifo);
952 }
953
mxser_chars_in_buffer(struct tty_struct * tty)954 static unsigned int mxser_chars_in_buffer(struct tty_struct *tty)
955 {
956 struct mxser_port *info = tty->driver_data;
957
958 return kfifo_len(&info->port.xmit_fifo);
959 }
960
961 /*
962 * ------------------------------------------------------------
963 * friends of mxser_ioctl()
964 * ------------------------------------------------------------
965 */
mxser_get_serial_info(struct tty_struct * tty,struct serial_struct * ss)966 static int mxser_get_serial_info(struct tty_struct *tty,
967 struct serial_struct *ss)
968 {
969 struct mxser_port *info = tty->driver_data;
970 struct tty_port *port = &info->port;
971 unsigned int closing_wait, close_delay;
972
973 mutex_lock(&port->mutex);
974
975 close_delay = jiffies_to_msecs(info->port.close_delay) / 10;
976 closing_wait = info->port.closing_wait;
977 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
978 closing_wait = jiffies_to_msecs(closing_wait) / 10;
979
980 ss->type = info->type;
981 ss->line = tty->index;
982 ss->port = info->ioaddr;
983 ss->irq = info->board->irq;
984 ss->flags = info->port.flags;
985 ss->baud_base = MXSER_BAUD_BASE;
986 ss->close_delay = close_delay;
987 ss->closing_wait = closing_wait;
988 ss->custom_divisor = MXSER_CUSTOM_DIVISOR,
989 mutex_unlock(&port->mutex);
990 return 0;
991 }
992
mxser_set_serial_info(struct tty_struct * tty,struct serial_struct * ss)993 static int mxser_set_serial_info(struct tty_struct *tty,
994 struct serial_struct *ss)
995 {
996 struct mxser_port *info = tty->driver_data;
997 struct tty_port *port = &info->port;
998 speed_t baud;
999 unsigned long sl_flags;
1000 unsigned int old_speed, close_delay, closing_wait;
1001 int retval = 0;
1002
1003 if (tty_io_error(tty))
1004 return -EIO;
1005
1006 mutex_lock(&port->mutex);
1007
1008 if (ss->irq != info->board->irq ||
1009 ss->port != info->ioaddr) {
1010 mutex_unlock(&port->mutex);
1011 return -EINVAL;
1012 }
1013
1014 old_speed = port->flags & ASYNC_SPD_MASK;
1015
1016 close_delay = msecs_to_jiffies(ss->close_delay * 10);
1017 closing_wait = ss->closing_wait;
1018 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
1019 closing_wait = msecs_to_jiffies(closing_wait * 10);
1020
1021 if (!capable(CAP_SYS_ADMIN)) {
1022 if ((ss->baud_base != MXSER_BAUD_BASE) ||
1023 (close_delay != port->close_delay) ||
1024 (closing_wait != port->closing_wait) ||
1025 ((ss->flags & ~ASYNC_USR_MASK) != (port->flags & ~ASYNC_USR_MASK))) {
1026 mutex_unlock(&port->mutex);
1027 return -EPERM;
1028 }
1029 port->flags = (port->flags & ~ASYNC_USR_MASK) |
1030 (ss->flags & ASYNC_USR_MASK);
1031 } else {
1032 /*
1033 * OK, past this point, all the error checking has been done.
1034 * At this point, we start making changes.....
1035 */
1036 port->flags = ((port->flags & ~ASYNC_FLAGS) |
1037 (ss->flags & ASYNC_FLAGS));
1038 port->close_delay = close_delay;
1039 port->closing_wait = closing_wait;
1040 if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
1041 (ss->baud_base != MXSER_BAUD_BASE ||
1042 ss->custom_divisor !=
1043 MXSER_CUSTOM_DIVISOR)) {
1044 if (ss->custom_divisor == 0) {
1045 mutex_unlock(&port->mutex);
1046 return -EINVAL;
1047 }
1048 baud = ss->baud_base / ss->custom_divisor;
1049 tty_encode_baud_rate(tty, baud, baud);
1050 }
1051
1052 info->type = ss->type;
1053
1054 mxser_process_txrx_fifo(info);
1055 }
1056
1057 if (tty_port_initialized(port)) {
1058 if (old_speed != (port->flags & ASYNC_SPD_MASK)) {
1059 spin_lock_irqsave(&info->slock, sl_flags);
1060 mxser_change_speed(tty, NULL);
1061 spin_unlock_irqrestore(&info->slock, sl_flags);
1062 }
1063 } else {
1064 retval = mxser_activate(port, tty);
1065 if (retval == 0)
1066 tty_port_set_initialized(port, 1);
1067 }
1068 mutex_unlock(&port->mutex);
1069 return retval;
1070 }
1071
1072 /*
1073 * mxser_get_lsr_info - get line status register info
1074 *
1075 * Purpose: Let user call ioctl() to get info when the UART physically
1076 * is emptied. On bus types like RS485, the transmitter must
1077 * release the bus after transmitting. This must be done when
1078 * the transmit shift register is empty, not be done when the
1079 * transmit holding register is empty. This functionality
1080 * allows an RS485 driver to be written in user space.
1081 */
mxser_get_lsr_info(struct mxser_port * info,unsigned int __user * value)1082 static int mxser_get_lsr_info(struct mxser_port *info,
1083 unsigned int __user *value)
1084 {
1085 unsigned char status;
1086 unsigned int result;
1087 unsigned long flags;
1088
1089 spin_lock_irqsave(&info->slock, flags);
1090 status = inb(info->ioaddr + UART_LSR);
1091 spin_unlock_irqrestore(&info->slock, flags);
1092 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1093 return put_user(result, value);
1094 }
1095
mxser_tiocmget(struct tty_struct * tty)1096 static int mxser_tiocmget(struct tty_struct *tty)
1097 {
1098 struct mxser_port *info = tty->driver_data;
1099 unsigned char control;
1100 unsigned long flags;
1101 u8 msr;
1102
1103 if (tty_io_error(tty))
1104 return -EIO;
1105
1106 spin_lock_irqsave(&info->slock, flags);
1107 control = info->MCR;
1108 msr = mxser_check_modem_status(tty, info);
1109 spin_unlock_irqrestore(&info->slock, flags);
1110
1111 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1112 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1113 ((msr & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1114 ((msr & UART_MSR_RI) ? TIOCM_RNG : 0) |
1115 ((msr & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1116 ((msr & UART_MSR_CTS) ? TIOCM_CTS : 0);
1117 }
1118
mxser_tiocmset(struct tty_struct * tty,unsigned int set,unsigned int clear)1119 static int mxser_tiocmset(struct tty_struct *tty,
1120 unsigned int set, unsigned int clear)
1121 {
1122 struct mxser_port *info = tty->driver_data;
1123 unsigned long flags;
1124
1125 if (tty_io_error(tty))
1126 return -EIO;
1127
1128 spin_lock_irqsave(&info->slock, flags);
1129
1130 if (set & TIOCM_RTS)
1131 info->MCR |= UART_MCR_RTS;
1132 if (set & TIOCM_DTR)
1133 info->MCR |= UART_MCR_DTR;
1134
1135 if (clear & TIOCM_RTS)
1136 info->MCR &= ~UART_MCR_RTS;
1137 if (clear & TIOCM_DTR)
1138 info->MCR &= ~UART_MCR_DTR;
1139
1140 outb(info->MCR, info->ioaddr + UART_MCR);
1141 spin_unlock_irqrestore(&info->slock, flags);
1142 return 0;
1143 }
1144
mxser_cflags_changed(struct mxser_port * info,unsigned long arg,struct async_icount * cprev)1145 static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1146 struct async_icount *cprev)
1147 {
1148 struct async_icount cnow;
1149 unsigned long flags;
1150 int ret;
1151
1152 spin_lock_irqsave(&info->slock, flags);
1153 cnow = info->icount; /* atomic copy */
1154 spin_unlock_irqrestore(&info->slock, flags);
1155
1156 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1157 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1158 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
1159 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1160
1161 *cprev = cnow;
1162
1163 return ret;
1164 }
1165
1166 /* We should likely switch to TIOCGRS485/TIOCSRS485. */
mxser_ioctl_op_mode(struct mxser_port * port,int index,bool set,int __user * u_opmode)1167 static int mxser_ioctl_op_mode(struct mxser_port *port, int index, bool set,
1168 int __user *u_opmode)
1169 {
1170 int opmode, p = index % 4;
1171 int shiftbit = p * 2;
1172 u8 val;
1173
1174 if (port->board->must_hwid != MOXA_MUST_MU860_HWID)
1175 return -EFAULT;
1176
1177 if (set) {
1178 if (get_user(opmode, u_opmode))
1179 return -EFAULT;
1180
1181 if (opmode & ~OP_MODE_MASK)
1182 return -EINVAL;
1183
1184 spin_lock_irq(&port->slock);
1185 val = inb(port->opmode_ioaddr);
1186 val &= ~(OP_MODE_MASK << shiftbit);
1187 val |= (opmode << shiftbit);
1188 outb(val, port->opmode_ioaddr);
1189 spin_unlock_irq(&port->slock);
1190
1191 return 0;
1192 }
1193
1194 spin_lock_irq(&port->slock);
1195 opmode = inb(port->opmode_ioaddr) >> shiftbit;
1196 spin_unlock_irq(&port->slock);
1197
1198 return put_user(opmode & OP_MODE_MASK, u_opmode);
1199 }
1200
mxser_ioctl(struct tty_struct * tty,unsigned int cmd,unsigned long arg)1201 static int mxser_ioctl(struct tty_struct *tty,
1202 unsigned int cmd, unsigned long arg)
1203 {
1204 struct mxser_port *info = tty->driver_data;
1205 struct async_icount cnow;
1206 unsigned long flags;
1207 void __user *argp = (void __user *)arg;
1208
1209 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE)
1210 return mxser_ioctl_op_mode(info, tty->index,
1211 cmd == MOXA_SET_OP_MODE, argp);
1212
1213 if (cmd != TIOCMIWAIT && tty_io_error(tty))
1214 return -EIO;
1215
1216 switch (cmd) {
1217 case TIOCSERGETLSR: /* Get line status register */
1218 return mxser_get_lsr_info(info, argp);
1219 /*
1220 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1221 * - mask passed in arg for lines of interest
1222 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1223 * Caller should use TIOCGICOUNT to see which one it was
1224 */
1225 case TIOCMIWAIT:
1226 spin_lock_irqsave(&info->slock, flags);
1227 cnow = info->icount; /* note the counters on entry */
1228 spin_unlock_irqrestore(&info->slock, flags);
1229
1230 return wait_event_interruptible(info->port.delta_msr_wait,
1231 mxser_cflags_changed(info, arg, &cnow));
1232 default:
1233 return -ENOIOCTLCMD;
1234 }
1235 return 0;
1236 }
1237
1238 /*
1239 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1240 * Return: write counters to the user passed counter struct
1241 * NB: both 1->0 and 0->1 transitions are counted except for
1242 * RI where only 0->1 is counted.
1243 */
1244
mxser_get_icount(struct tty_struct * tty,struct serial_icounter_struct * icount)1245 static int mxser_get_icount(struct tty_struct *tty,
1246 struct serial_icounter_struct *icount)
1247
1248 {
1249 struct mxser_port *info = tty->driver_data;
1250 struct async_icount cnow;
1251 unsigned long flags;
1252
1253 spin_lock_irqsave(&info->slock, flags);
1254 cnow = info->icount;
1255 spin_unlock_irqrestore(&info->slock, flags);
1256
1257 icount->frame = cnow.frame;
1258 icount->brk = cnow.brk;
1259 icount->overrun = cnow.overrun;
1260 icount->buf_overrun = cnow.buf_overrun;
1261 icount->parity = cnow.parity;
1262 icount->rx = cnow.rx;
1263 icount->tx = cnow.tx;
1264 icount->cts = cnow.cts;
1265 icount->dsr = cnow.dsr;
1266 icount->rng = cnow.rng;
1267 icount->dcd = cnow.dcd;
1268 return 0;
1269 }
1270
1271 /*
1272 * This routine is called by the upper-layer tty layer to signal that
1273 * incoming characters should be throttled.
1274 */
mxser_throttle(struct tty_struct * tty)1275 static void mxser_throttle(struct tty_struct *tty)
1276 {
1277 struct mxser_port *info = tty->driver_data;
1278
1279 if (I_IXOFF(tty)) {
1280 if (info->board->must_hwid) {
1281 info->IER &= ~MOXA_MUST_RECV_ISR;
1282 outb(info->IER, info->ioaddr + UART_IER);
1283 } else {
1284 info->x_char = STOP_CHAR(tty);
1285 outb(0, info->ioaddr + UART_IER);
1286 info->IER |= UART_IER_THRI;
1287 outb(info->IER, info->ioaddr + UART_IER);
1288 }
1289 }
1290
1291 if (C_CRTSCTS(tty)) {
1292 info->MCR &= ~UART_MCR_RTS;
1293 outb(info->MCR, info->ioaddr + UART_MCR);
1294 }
1295 }
1296
mxser_unthrottle(struct tty_struct * tty)1297 static void mxser_unthrottle(struct tty_struct *tty)
1298 {
1299 struct mxser_port *info = tty->driver_data;
1300
1301 /* startrx */
1302 if (I_IXOFF(tty)) {
1303 if (info->x_char)
1304 info->x_char = 0;
1305 else {
1306 if (info->board->must_hwid) {
1307 info->IER |= MOXA_MUST_RECV_ISR;
1308 outb(info->IER, info->ioaddr + UART_IER);
1309 } else {
1310 info->x_char = START_CHAR(tty);
1311 outb(0, info->ioaddr + UART_IER);
1312 info->IER |= UART_IER_THRI;
1313 outb(info->IER, info->ioaddr + UART_IER);
1314 }
1315 }
1316 }
1317
1318 if (C_CRTSCTS(tty)) {
1319 info->MCR |= UART_MCR_RTS;
1320 outb(info->MCR, info->ioaddr + UART_MCR);
1321 }
1322 }
1323
1324 /*
1325 * mxser_stop() and mxser_start()
1326 *
1327 * This routines are called before setting or resetting tty->flow.stopped.
1328 * They enable or disable transmitter interrupts, as necessary.
1329 */
mxser_stop(struct tty_struct * tty)1330 static void mxser_stop(struct tty_struct *tty)
1331 {
1332 struct mxser_port *info = tty->driver_data;
1333 unsigned long flags;
1334
1335 spin_lock_irqsave(&info->slock, flags);
1336 if (info->IER & UART_IER_THRI)
1337 __mxser_stop_tx(info);
1338 spin_unlock_irqrestore(&info->slock, flags);
1339 }
1340
mxser_start(struct tty_struct * tty)1341 static void mxser_start(struct tty_struct *tty)
1342 {
1343 struct mxser_port *info = tty->driver_data;
1344 unsigned long flags;
1345
1346 spin_lock_irqsave(&info->slock, flags);
1347 if (!kfifo_is_empty(&info->port.xmit_fifo))
1348 __mxser_start_tx(info);
1349 spin_unlock_irqrestore(&info->slock, flags);
1350 }
1351
mxser_set_termios(struct tty_struct * tty,const struct ktermios * old_termios)1352 static void mxser_set_termios(struct tty_struct *tty,
1353 const struct ktermios *old_termios)
1354 {
1355 struct mxser_port *info = tty->driver_data;
1356 unsigned long flags;
1357
1358 spin_lock_irqsave(&info->slock, flags);
1359 mxser_change_speed(tty, old_termios);
1360 spin_unlock_irqrestore(&info->slock, flags);
1361
1362 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
1363 tty->hw_stopped = 0;
1364 mxser_start(tty);
1365 }
1366
1367 /* Handle sw stopped */
1368 if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) {
1369 tty->flow.stopped = 0;
1370
1371 if (info->board->must_hwid) {
1372 spin_lock_irqsave(&info->slock, flags);
1373 mxser_must_set_rx_sw_flow_control(info->ioaddr, false);
1374 spin_unlock_irqrestore(&info->slock, flags);
1375 }
1376
1377 mxser_start(tty);
1378 }
1379 }
1380
mxser_tx_empty(struct mxser_port * info)1381 static bool mxser_tx_empty(struct mxser_port *info)
1382 {
1383 unsigned long flags;
1384 u8 lsr;
1385
1386 spin_lock_irqsave(&info->slock, flags);
1387 lsr = inb(info->ioaddr + UART_LSR);
1388 spin_unlock_irqrestore(&info->slock, flags);
1389
1390 return !(lsr & UART_LSR_TEMT);
1391 }
1392
1393 /*
1394 * mxser_wait_until_sent() --- wait until the transmitter is empty
1395 */
mxser_wait_until_sent(struct tty_struct * tty,int timeout)1396 static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1397 {
1398 struct mxser_port *info = tty->driver_data;
1399 unsigned long expire, char_time;
1400
1401 if (info->type == PORT_UNKNOWN)
1402 return;
1403
1404 if (info->xmit_fifo_size == 0)
1405 return; /* Just in case.... */
1406
1407 /*
1408 * Set the check interval to be 1/5 of the estimated time to
1409 * send a single character, and make it at least 1. The check
1410 * interval should also be less than the timeout.
1411 *
1412 * Note: we have to use pretty tight timings here to satisfy
1413 * the NIST-PCTS.
1414 */
1415 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
1416 char_time = char_time / 5;
1417 if (char_time == 0)
1418 char_time = 1;
1419 if (timeout && timeout < char_time)
1420 char_time = timeout;
1421
1422 char_time = jiffies_to_msecs(char_time);
1423
1424 /*
1425 * If the transmitter hasn't cleared in twice the approximate
1426 * amount of time to send the entire FIFO, it probably won't
1427 * ever clear. This assumes the UART isn't doing flow
1428 * control, which is currently the case. Hence, if it ever
1429 * takes longer than info->timeout, this is probably due to a
1430 * UART bug of some kind. So, we clamp the timeout parameter at
1431 * 2*info->timeout.
1432 */
1433 if (!timeout || timeout > 2 * info->timeout)
1434 timeout = 2 * info->timeout;
1435
1436 expire = jiffies + timeout;
1437
1438 while (mxser_tx_empty(info)) {
1439 msleep_interruptible(char_time);
1440 if (signal_pending(current))
1441 break;
1442 if (time_after(jiffies, expire))
1443 break;
1444 }
1445 }
1446
1447 /*
1448 * This routine is called by tty_hangup() when a hangup is signaled.
1449 */
mxser_hangup(struct tty_struct * tty)1450 static void mxser_hangup(struct tty_struct *tty)
1451 {
1452 struct mxser_port *info = tty->driver_data;
1453
1454 mxser_flush_buffer(tty);
1455 tty_port_hangup(&info->port);
1456 }
1457
1458 /*
1459 * mxser_rs_break() --- routine which turns the break handling on or off
1460 */
mxser_rs_break(struct tty_struct * tty,int break_state)1461 static int mxser_rs_break(struct tty_struct *tty, int break_state)
1462 {
1463 struct mxser_port *info = tty->driver_data;
1464 unsigned long flags;
1465 u8 lcr;
1466
1467 spin_lock_irqsave(&info->slock, flags);
1468 lcr = inb(info->ioaddr + UART_LCR);
1469 if (break_state == -1)
1470 lcr |= UART_LCR_SBC;
1471 else
1472 lcr &= ~UART_LCR_SBC;
1473 outb(lcr, info->ioaddr + UART_LCR);
1474 spin_unlock_irqrestore(&info->slock, flags);
1475
1476 return 0;
1477 }
1478
mxser_receive_chars_new(struct mxser_port * port,u8 status)1479 static bool mxser_receive_chars_new(struct mxser_port *port, u8 status)
1480 {
1481 enum mxser_must_hwid hwid = port->board->must_hwid;
1482 u8 gdl;
1483
1484 if (hwid == MOXA_OTHER_UART)
1485 return false;
1486 if (status & (UART_LSR_BRK_ERROR_BITS | MOXA_MUST_LSR_RERR))
1487 return false;
1488
1489 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
1490 if (hwid == MOXA_MUST_MU150_HWID)
1491 gdl &= MOXA_MUST_GDL_MASK;
1492
1493 while (gdl--) {
1494 u8 ch = inb(port->ioaddr + UART_RX);
1495 if (!tty_insert_flip_char(&port->port, ch, 0))
1496 port->icount.buf_overrun++;
1497 }
1498
1499 return true;
1500 }
1501
mxser_receive_chars_old(struct tty_struct * tty,struct mxser_port * port,u8 status)1502 static u8 mxser_receive_chars_old(struct tty_struct *tty,
1503 struct mxser_port *port, u8 status)
1504 {
1505 enum mxser_must_hwid hwid = port->board->must_hwid;
1506 int ignored = 0;
1507 int max = 256;
1508 u8 ch;
1509
1510 do {
1511 if (max-- < 0)
1512 break;
1513
1514 ch = inb(port->ioaddr + UART_RX);
1515 if (hwid && (status & UART_LSR_OE))
1516 outb(port->FCR | UART_FCR_CLEAR_RCVR,
1517 port->ioaddr + UART_FCR);
1518 status &= port->read_status_mask;
1519 if (status & port->ignore_status_mask) {
1520 if (++ignored > 100)
1521 break;
1522 } else {
1523 char flag = 0;
1524 if (status & UART_LSR_BRK_ERROR_BITS) {
1525 if (status & UART_LSR_BI) {
1526 flag = TTY_BREAK;
1527 port->icount.brk++;
1528
1529 if (port->port.flags & ASYNC_SAK)
1530 do_SAK(tty);
1531 } else if (status & UART_LSR_PE) {
1532 flag = TTY_PARITY;
1533 port->icount.parity++;
1534 } else if (status & UART_LSR_FE) {
1535 flag = TTY_FRAME;
1536 port->icount.frame++;
1537 } else if (status & UART_LSR_OE) {
1538 flag = TTY_OVERRUN;
1539 port->icount.overrun++;
1540 }
1541 }
1542 if (!tty_insert_flip_char(&port->port, ch, flag)) {
1543 port->icount.buf_overrun++;
1544 break;
1545 }
1546 }
1547
1548 if (hwid)
1549 break;
1550
1551 status = inb(port->ioaddr + UART_LSR);
1552 } while (status & UART_LSR_DR);
1553
1554 return status;
1555 }
1556
mxser_receive_chars(struct tty_struct * tty,struct mxser_port * port,u8 status)1557 static u8 mxser_receive_chars(struct tty_struct *tty,
1558 struct mxser_port *port, u8 status)
1559 {
1560 if (!mxser_receive_chars_new(port, status))
1561 status = mxser_receive_chars_old(tty, port, status);
1562
1563 tty_flip_buffer_push(&port->port);
1564
1565 return status;
1566 }
1567
mxser_transmit_chars(struct tty_struct * tty,struct mxser_port * port)1568 static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port)
1569 {
1570 int count;
1571
1572 if (port->x_char) {
1573 outb(port->x_char, port->ioaddr + UART_TX);
1574 port->x_char = 0;
1575 port->icount.tx++;
1576 return;
1577 }
1578
1579 if (kfifo_is_empty(&port->port.xmit_fifo) || tty->flow.stopped ||
1580 (tty->hw_stopped && !mxser_16550A_or_MUST(port))) {
1581 __mxser_stop_tx(port);
1582 return;
1583 }
1584
1585 count = port->xmit_fifo_size;
1586 do {
1587 unsigned char c;
1588
1589 if (!kfifo_get(&port->port.xmit_fifo, &c))
1590 break;
1591
1592 outb(c, port->ioaddr + UART_TX);
1593 port->icount.tx++;
1594 } while (--count > 0);
1595
1596 if (kfifo_len(&port->port.xmit_fifo) < WAKEUP_CHARS)
1597 tty_wakeup(tty);
1598
1599 if (kfifo_is_empty(&port->port.xmit_fifo))
1600 __mxser_stop_tx(port);
1601 }
1602
mxser_port_isr(struct mxser_port * port)1603 static bool mxser_port_isr(struct mxser_port *port)
1604 {
1605 struct tty_struct *tty;
1606 u8 iir, status;
1607 bool error = false;
1608
1609 iir = inb(port->ioaddr + UART_IIR);
1610 if (iir & UART_IIR_NO_INT)
1611 return true;
1612
1613 iir &= MOXA_MUST_IIR_MASK;
1614 tty = tty_port_tty_get(&port->port);
1615 if (!tty) {
1616 status = inb(port->ioaddr + UART_LSR);
1617 outb(port->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1618 port->ioaddr + UART_FCR);
1619 inb(port->ioaddr + UART_MSR);
1620
1621 error = true;
1622 goto put_tty;
1623 }
1624
1625 status = inb(port->ioaddr + UART_LSR);
1626
1627 if (port->board->must_hwid) {
1628 if (iir == MOXA_MUST_IIR_GDA ||
1629 iir == MOXA_MUST_IIR_RDA ||
1630 iir == MOXA_MUST_IIR_RTO ||
1631 iir == MOXA_MUST_IIR_LSR)
1632 status = mxser_receive_chars(tty, port, status);
1633 } else {
1634 status &= port->read_status_mask;
1635 if (status & UART_LSR_DR)
1636 status = mxser_receive_chars(tty, port, status);
1637 }
1638
1639 mxser_check_modem_status(tty, port);
1640
1641 if (port->board->must_hwid) {
1642 if (iir == 0x02 && (status & UART_LSR_THRE))
1643 mxser_transmit_chars(tty, port);
1644 } else {
1645 if (status & UART_LSR_THRE)
1646 mxser_transmit_chars(tty, port);
1647 }
1648
1649 put_tty:
1650 tty_kref_put(tty);
1651
1652 return error;
1653 }
1654
1655 /*
1656 * This is the serial driver's generic interrupt routine
1657 */
mxser_interrupt(int irq,void * dev_id)1658 static irqreturn_t mxser_interrupt(int irq, void *dev_id)
1659 {
1660 struct mxser_board *brd = dev_id;
1661 struct mxser_port *port;
1662 unsigned int int_cnt, pass_counter = 0;
1663 unsigned int i, max = brd->nports;
1664 int handled = IRQ_NONE;
1665 u8 irqbits, bits, mask = BIT(max) - 1;
1666
1667 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
1668 irqbits = inb(brd->vector) & mask;
1669 if (irqbits == mask)
1670 break;
1671
1672 handled = IRQ_HANDLED;
1673 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
1674 if (irqbits == mask)
1675 break;
1676 if (bits & irqbits)
1677 continue;
1678 port = &brd->ports[i];
1679
1680 int_cnt = 0;
1681 spin_lock(&port->slock);
1682 do {
1683 if (mxser_port_isr(port))
1684 break;
1685 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
1686 spin_unlock(&port->slock);
1687 }
1688 }
1689
1690 return handled;
1691 }
1692
1693 static const struct tty_operations mxser_ops = {
1694 .open = mxser_open,
1695 .close = mxser_close,
1696 .write = mxser_write,
1697 .put_char = mxser_put_char,
1698 .flush_chars = mxser_flush_chars,
1699 .write_room = mxser_write_room,
1700 .chars_in_buffer = mxser_chars_in_buffer,
1701 .flush_buffer = mxser_flush_buffer,
1702 .ioctl = mxser_ioctl,
1703 .throttle = mxser_throttle,
1704 .unthrottle = mxser_unthrottle,
1705 .set_termios = mxser_set_termios,
1706 .stop = mxser_stop,
1707 .start = mxser_start,
1708 .hangup = mxser_hangup,
1709 .break_ctl = mxser_rs_break,
1710 .wait_until_sent = mxser_wait_until_sent,
1711 .tiocmget = mxser_tiocmget,
1712 .tiocmset = mxser_tiocmset,
1713 .set_serial = mxser_set_serial_info,
1714 .get_serial = mxser_get_serial_info,
1715 .get_icount = mxser_get_icount,
1716 };
1717
1718 static const struct tty_port_operations mxser_port_ops = {
1719 .carrier_raised = mxser_carrier_raised,
1720 .dtr_rts = mxser_dtr_rts,
1721 .activate = mxser_activate,
1722 .shutdown = mxser_shutdown_port,
1723 };
1724
1725 /*
1726 * The MOXA Smartio/Industio serial driver boot-time initialization code!
1727 */
1728
mxser_initbrd(struct mxser_board * brd,bool high_baud)1729 static void mxser_initbrd(struct mxser_board *brd, bool high_baud)
1730 {
1731 struct mxser_port *info;
1732 unsigned int i;
1733 bool is_mu860;
1734
1735 brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr);
1736 is_mu860 = brd->must_hwid == MOXA_MUST_MU860_HWID;
1737
1738 for (i = 0; i < UART_INFO_NUM; i++) {
1739 if (Gpci_uart_info[i].type == brd->must_hwid) {
1740 brd->max_baud = Gpci_uart_info[i].max_baud;
1741
1742 /* exception....CP-102 */
1743 if (high_baud)
1744 brd->max_baud = 921600;
1745 break;
1746 }
1747 }
1748
1749 if (is_mu860) {
1750 /* set to RS232 mode by default */
1751 outb(0, brd->vector + 4);
1752 outb(0, brd->vector + 0x0c);
1753 }
1754
1755 for (i = 0; i < brd->nports; i++) {
1756 info = &brd->ports[i];
1757 if (is_mu860) {
1758 if (i < 4)
1759 info->opmode_ioaddr = brd->vector + 4;
1760 else
1761 info->opmode_ioaddr = brd->vector + 0x0c;
1762 }
1763 tty_port_init(&info->port);
1764 info->port.ops = &mxser_port_ops;
1765 info->board = brd;
1766
1767 /* Enhance mode enabled here */
1768 if (brd->must_hwid != MOXA_OTHER_UART)
1769 mxser_must_set_enhance_mode(info->ioaddr, true);
1770
1771 info->type = PORT_16550A;
1772
1773 mxser_process_txrx_fifo(info);
1774
1775 info->port.close_delay = 5 * HZ / 10;
1776 info->port.closing_wait = 30 * HZ;
1777 spin_lock_init(&info->slock);
1778
1779 /* before set INT ISR, disable all int */
1780 outb(inb(info->ioaddr + UART_IER) & 0xf0,
1781 info->ioaddr + UART_IER);
1782 }
1783 }
1784
mxser_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1785 static int mxser_probe(struct pci_dev *pdev,
1786 const struct pci_device_id *ent)
1787 {
1788 struct mxser_board *brd;
1789 unsigned int i, base;
1790 unsigned long ioaddress;
1791 unsigned short nports = MXSER_NPORTS(ent->driver_data);
1792 struct device *tty_dev;
1793 int retval = -EINVAL;
1794
1795 i = find_first_zero_bit(mxser_boards, MXSER_BOARDS);
1796 if (i >= MXSER_BOARDS) {
1797 dev_err(&pdev->dev, "too many boards found (maximum %d), board "
1798 "not configured\n", MXSER_BOARDS);
1799 goto err;
1800 }
1801
1802 brd = devm_kzalloc(&pdev->dev, struct_size(brd, ports, nports),
1803 GFP_KERNEL);
1804 if (!brd)
1805 goto err;
1806
1807 brd->idx = i;
1808 __set_bit(brd->idx, mxser_boards);
1809 base = i * MXSER_PORTS_PER_BOARD;
1810
1811 retval = pcim_enable_device(pdev);
1812 if (retval) {
1813 dev_err(&pdev->dev, "PCI enable failed\n");
1814 goto err_zero;
1815 }
1816
1817 /* io address */
1818 ioaddress = pci_resource_start(pdev, 2);
1819 retval = pci_request_region(pdev, 2, "mxser(IO)");
1820 if (retval)
1821 goto err_zero;
1822
1823 brd->nports = nports;
1824 for (i = 0; i < nports; i++)
1825 brd->ports[i].ioaddr = ioaddress + 8 * i;
1826
1827 /* vector */
1828 ioaddress = pci_resource_start(pdev, 3);
1829 retval = pci_request_region(pdev, 3, "mxser(vector)");
1830 if (retval)
1831 goto err_zero;
1832 brd->vector = ioaddress;
1833
1834 /* irq */
1835 brd->irq = pdev->irq;
1836
1837 mxser_initbrd(brd, ent->driver_data & MXSER_HIGHBAUD);
1838
1839 retval = devm_request_irq(&pdev->dev, brd->irq, mxser_interrupt,
1840 IRQF_SHARED, "mxser", brd);
1841 if (retval) {
1842 dev_err(&pdev->dev, "request irq failed");
1843 goto err_relbrd;
1844 }
1845
1846 for (i = 0; i < nports; i++) {
1847 tty_dev = tty_port_register_device(&brd->ports[i].port,
1848 mxvar_sdriver, base + i, &pdev->dev);
1849 if (IS_ERR(tty_dev)) {
1850 retval = PTR_ERR(tty_dev);
1851 for (; i > 0; i--)
1852 tty_unregister_device(mxvar_sdriver,
1853 base + i - 1);
1854 goto err_relbrd;
1855 }
1856 }
1857
1858 pci_set_drvdata(pdev, brd);
1859
1860 return 0;
1861 err_relbrd:
1862 for (i = 0; i < nports; i++)
1863 tty_port_destroy(&brd->ports[i].port);
1864 err_zero:
1865 __clear_bit(brd->idx, mxser_boards);
1866 err:
1867 return retval;
1868 }
1869
mxser_remove(struct pci_dev * pdev)1870 static void mxser_remove(struct pci_dev *pdev)
1871 {
1872 struct mxser_board *brd = pci_get_drvdata(pdev);
1873 unsigned int i, base = brd->idx * MXSER_PORTS_PER_BOARD;
1874
1875 for (i = 0; i < brd->nports; i++) {
1876 tty_unregister_device(mxvar_sdriver, base + i);
1877 tty_port_destroy(&brd->ports[i].port);
1878 }
1879
1880 __clear_bit(brd->idx, mxser_boards);
1881 }
1882
1883 static struct pci_driver mxser_driver = {
1884 .name = "mxser",
1885 .id_table = mxser_pcibrds,
1886 .probe = mxser_probe,
1887 .remove = mxser_remove
1888 };
1889
mxser_module_init(void)1890 static int __init mxser_module_init(void)
1891 {
1892 int retval;
1893
1894 mxvar_sdriver = tty_alloc_driver(MXSER_PORTS, TTY_DRIVER_REAL_RAW |
1895 TTY_DRIVER_DYNAMIC_DEV);
1896 if (IS_ERR(mxvar_sdriver))
1897 return PTR_ERR(mxvar_sdriver);
1898
1899 /* Initialize the tty_driver structure */
1900 mxvar_sdriver->name = "ttyMI";
1901 mxvar_sdriver->major = ttymajor;
1902 mxvar_sdriver->minor_start = 0;
1903 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
1904 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
1905 mxvar_sdriver->init_termios = tty_std_termios;
1906 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
1907 tty_set_operations(mxvar_sdriver, &mxser_ops);
1908
1909 retval = tty_register_driver(mxvar_sdriver);
1910 if (retval) {
1911 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
1912 "tty driver !\n");
1913 goto err_put;
1914 }
1915
1916 retval = pci_register_driver(&mxser_driver);
1917 if (retval) {
1918 printk(KERN_ERR "mxser: can't register pci driver\n");
1919 goto err_unr;
1920 }
1921
1922 return 0;
1923 err_unr:
1924 tty_unregister_driver(mxvar_sdriver);
1925 err_put:
1926 tty_driver_kref_put(mxvar_sdriver);
1927 return retval;
1928 }
1929
mxser_module_exit(void)1930 static void __exit mxser_module_exit(void)
1931 {
1932 pci_unregister_driver(&mxser_driver);
1933 tty_unregister_driver(mxvar_sdriver);
1934 tty_driver_kref_put(mxvar_sdriver);
1935 }
1936
1937 module_init(mxser_module_init);
1938 module_exit(mxser_module_exit);
1939