| /drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_resource.h | 173 #define ABM_DCN32_REG_LIST_RI(id) \ argument
175 SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
176 SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
177 SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
178 SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id), \
179 SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
180 SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
181 SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
182 SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id), \
183 SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
[all …]
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| /drivers/i2c/busses/ |
| D | i2c-sh7760.c | 114 struct cami2c *id = ptr; in sh7760_i2c_irq() local
115 struct i2c_msg *msg = id->msg; in sh7760_i2c_irq()
119 msr = IN32(id, I2CMSR); in sh7760_i2c_irq()
120 fsr = IN32(id, I2CFSR); in sh7760_i2c_irq()
124 OUT32(id, I2CMCR, 0); in sh7760_i2c_irq()
125 OUT32(id, I2CSCR, 0); in sh7760_i2c_irq()
126 OUT32(id, I2CSAR, 0); in sh7760_i2c_irq()
127 id->status |= IDS_DONE | IDS_ARBLOST; in sh7760_i2c_irq()
139 OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST); in sh7760_i2c_irq()
140 OUT32(id, I2CMCR, MCR_MIE | MCR_FSB); in sh7760_i2c_irq()
[all …]
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| D | i2c-cadence.c | 135 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
136 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
233 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) in cdns_i2c_clear_bus_hold() argument
240 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround) in cdns_is_holdquirk() argument
243 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1)); in cdns_is_holdquirk()
247 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id) in cdns_i2c_set_mode() argument
256 id->dev_mode = mode; in cdns_i2c_set_mode()
257 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; in cdns_i2c_set_mode()
262 cdns_i2c_writereg(id->ctrl_reg_diva_divb | in cdns_i2c_set_mode()
275 cdns_i2c_writereg(id->ctrl_reg_diva_divb & in cdns_i2c_set_mode()
[all …]
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| /drivers/clk/at91/ |
| D | sam9x60.c | 78 u8 id; member
80 { .n = "ddrck", .p = "masterck_div", .id = 2 },
81 { .n = "uhpck", .p = "usbck", .id = 6 },
82 { .n = "pck0", .p = "prog0", .id = 8 },
83 { .n = "pck1", .p = "prog1", .id = 9 },
84 { .n = "qspick", .p = "masterck_div", .id = 19 },
89 u8 id; member
91 { .n = "pioA_clk", .id = 2, },
92 { .n = "pioB_clk", .id = 3, },
93 { .n = "pioC_clk", .id = 4, },
[all …]
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| D | sama5d4.c | 42 u8 id; member
44 { .n = "ddrck", .p = "masterck_div", .id = 2 },
45 { .n = "lcdck", .p = "masterck_div", .id = 3 },
46 { .n = "smdck", .p = "smdclk", .id = 4 },
47 { .n = "uhpck", .p = "usbck", .id = 6 },
48 { .n = "udpck", .p = "usbck", .id = 7 },
49 { .n = "pck0", .p = "prog0", .id = 8 },
50 { .n = "pck1", .p = "prog1", .id = 9 },
51 { .n = "pck2", .p = "prog2", .id = 10 },
56 u8 id; member
[all …]
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| D | at91sam9260.c | 13 u8 id; member
18 u8 id; member
76 { .n = "uhpck", .p = "usbck", .id = 6 },
77 { .n = "udpck", .p = "usbck", .id = 7 },
78 { .n = "pck0", .p = "prog0", .id = 8 },
79 { .n = "pck1", .p = "prog1", .id = 9 },
83 { .n = "pioA_clk", .id = 2 },
84 { .n = "pioB_clk", .id = 3 },
85 { .n = "pioC_clk", .id = 4 },
86 { .n = "adc_clk", .id = 5 },
[all …]
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| D | sama5d2.c | 43 u8 id; member
45 { .n = "ddrck", .p = "masterck_div", .id = 2 },
46 { .n = "lcdck", .p = "masterck_div", .id = 3 },
47 { .n = "uhpck", .p = "usbck", .id = 6 },
48 { .n = "udpck", .p = "usbck", .id = 7 },
49 { .n = "pck0", .p = "prog0", .id = 8 },
50 { .n = "pck1", .p = "prog1", .id = 9 },
51 { .n = "pck2", .p = "prog2", .id = 10 },
52 { .n = "iscck", .p = "masterck_div", .id = 18 },
57 u8 id; member
[all …]
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| D | sama5d3.c | 43 u8 id; member
45 { .n = "ddrck", .p = "masterck_div", .id = 2 },
46 { .n = "lcdck", .p = "masterck_div", .id = 3 },
47 { .n = "smdck", .p = "smdclk", .id = 4 },
48 { .n = "uhpck", .p = "usbck", .id = 6 },
49 { .n = "udpck", .p = "usbck", .id = 7 },
50 { .n = "pck0", .p = "prog0", .id = 8 },
51 { .n = "pck1", .p = "prog1", .id = 9 },
52 { .n = "pck2", .p = "prog2", .id = 10 },
57 u8 id; member
[all …]
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| D | sama7g5.c | 314 u8 id; member
319 .id = 1,
328 .id = 2,
336 .id = 3,
343 .id = 4,
360 u8 id; member
362 { .n = "pck0", .p = "prog0", .id = 8, },
363 { .n = "pck1", .p = "prog1", .id = 9, },
364 { .n = "pck2", .p = "prog2", .id = 10, },
365 { .n = "pck3", .p = "prog3", .id = 11, },
[all …]
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| D | at91sam9x5.c | 44 u8 id; member
46 { .n = "ddrck", .p = "masterck_div", .id = 2 },
47 { .n = "smdck", .p = "smdclk", .id = 4 },
48 { .n = "uhpck", .p = "usbck", .id = 6 },
49 { .n = "udpck", .p = "usbck", .id = 7 },
50 { .n = "pck0", .p = "prog0", .id = 8 },
51 { .n = "pck1", .p = "prog1", .id = 9 },
63 u8 id; member
67 { .n = "pioAB_clk", .id = 2, },
68 { .n = "pioCD_clk", .id = 3, },
[all …]
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| D | at91sam9g45.c | 43 u8 id; member
45 { .n = "ddrck", .p = "masterck_div", .id = 2 },
46 { .n = "uhpck", .p = "usbck", .id = 6 },
47 { .n = "pck0", .p = "prog0", .id = 8 },
48 { .n = "pck1", .p = "prog1", .id = 9 },
53 u8 id; member
57 { .n = "pioA_clk", .id = 2, },
58 { .n = "pioB_clk", .id = 3, },
59 { .n = "pioC_clk", .id = 4, },
60 { .n = "pioDE_clk", .id = 5, },
[all …]
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| /drivers/gpu/drm/amd/display/dc/bios/ |
| D | bios_parser_common.c | 63 enum object_enum_id id; in enum_id_from_bios_object_id() local
67 id = ENUM_ID_1; in enum_id_from_bios_object_id()
70 id = ENUM_ID_2; in enum_id_from_bios_object_id()
73 id = ENUM_ID_3; in enum_id_from_bios_object_id()
76 id = ENUM_ID_4; in enum_id_from_bios_object_id()
79 id = ENUM_ID_5; in enum_id_from_bios_object_id()
82 id = ENUM_ID_6; in enum_id_from_bios_object_id()
85 id = ENUM_ID_7; in enum_id_from_bios_object_id()
88 id = ENUM_ID_UNKNOWN; in enum_id_from_bios_object_id()
92 return id; in enum_id_from_bios_object_id()
[all …]
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| /drivers/memory/tegra/ |
| D | tegra194.c | 14 .id = TEGRA194_MEMORY_CLIENT_PTCR,
24 .id = TEGRA194_MEMORY_CLIENT_MIU7R,
34 .id = TEGRA194_MEMORY_CLIENT_MIU7W,
44 .id = TEGRA194_MEMORY_CLIENT_HDAR,
54 .id = TEGRA194_MEMORY_CLIENT_HOST1XDMAR,
64 .id = TEGRA194_MEMORY_CLIENT_NVENCSRD,
74 .id = TEGRA194_MEMORY_CLIENT_SATAR,
84 .id = TEGRA194_MEMORY_CLIENT_MPCORER,
94 .id = TEGRA194_MEMORY_CLIENT_NVENCSWR,
104 .id = TEGRA194_MEMORY_CLIENT_HDAW,
[all …]
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| D | tegra186.c | 123 if (client->id == args.args[0]) { in tegra186_mc_probe_device()
148 .id = TEGRA186_MEMORY_CLIENT_PTCR,
158 .id = TEGRA186_MEMORY_CLIENT_AFIR,
168 .id = TEGRA186_MEMORY_CLIENT_HDAR,
178 .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR,
188 .id = TEGRA186_MEMORY_CLIENT_NVENCSRD,
198 .id = TEGRA186_MEMORY_CLIENT_SATAR,
208 .id = TEGRA186_MEMORY_CLIENT_MPCORER,
218 .id = TEGRA186_MEMORY_CLIENT_NVENCSWR,
228 .id = TEGRA186_MEMORY_CLIENT_AFIW,
[all …]
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_link_encoder.h | 39 #define AUX_REG_LIST(id)\ argument
40 SRI(AUX_CONTROL, DP_AUX, id), \
41 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
42 SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
44 #define HPD_REG_LIST(id)\ argument
45 SRI(DC_HPD_CONTROL, HPD, id)
47 #define LE_COMMON_REG_LIST_BASE(id) \ argument
52 SRI(DIG_BE_CNTL, DIG, id), \
53 SRI(DIG_BE_EN_CNTL, DIG, id), \
54 SRI(DP_CONFIG, DP, id), \
[all …]
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| D | dce_abm.h | 53 #define ABM_DCN10_REG_LIST(id)\ argument
55 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
56 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
57 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
58 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
59 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
60 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
61 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
62 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
63 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
[all …]
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| /drivers/media/platform/samsung/s3c-camif/ |
| D | camif-regs.h | 65 #define CIGCTRL_IRQ_CLR(id) BIT(19 - (id)) argument
71 #define S3C_CAMIF_REG_CIYSA(id, n) (0x18 + (id) * 0x54 + (n) * 4) argument
73 #define S3C_CAMIF_REG_CICBSA(id, n) (0x28 + (id) * 0x54 + (n) * 4) argument
75 #define S3C_CAMIF_REG_CICRSA(id, n) (0x38 + (id) * 0x54 + (n) * 4) argument
78 #define S3C_CAMIF_REG_CITRGFMT(id, _offs) (0x48 + (id) * (0x34 + (_offs))) argument
98 #define S3C_CAMIF_REG_CICTRL(id, _offs) (0x4c + (id) * (0x34 + (_offs))) argument
111 #define S3C_CAMIF_REG_CISCPRERATIO(id, _offs) (0x50 + (id) * (0x34 + (_offs))) argument
114 #define S3C_CAMIF_REG_CISCPREDST(id, _offs) (0x54 + (id) * (0x34 + (_offs))) argument
117 #define S3C_CAMIF_REG_CISCCTRL(id, _offs) (0x58 + (id) * (0x34 + (_offs))) argument
147 #define S3C_CAMIF_REG_CITAREA(id, _offs) (0x5c + (id) * (0x34 + (_offs))) argument
[all …]
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| /drivers/macintosh/ |
| D | adbhid.c | 212 int id; member
237 static void init_trackpad(int id);
238 static void init_trackball(int id);
239 static void init_turbomouse(int id);
240 static void init_microspeed(int id);
241 static void init_ms_a3(int id);
268 int id = (data[0] >> 4) & 0x0f; in adbhid_keyboard_input() local
270 if (!adbhid[id]) { in adbhid_keyboard_input()
272 id, data[0], data[1], data[2], data[3]); in adbhid_keyboard_input()
279 adbhid_input_keycode(id, data[1], 0); in adbhid_keyboard_input()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_dpp.h | 33 #define DPP_REG_LIST_DCN30_COMMON(id)\ argument
34 SRI(CM_DEALPHA, CM, id),\
35 SRI(CM_MEM_PWR_STATUS, CM, id),\
36 SRI(CM_BIAS_CR_R, CM, id),\
37 SRI(CM_BIAS_Y_G_CB_B, CM, id),\
38 SRI(PRE_DEGAM, CNVC_CFG, id),\
39 SRI(CM_GAMCOR_CONTROL, CM, id),\
40 SRI(CM_GAMCOR_LUT_CONTROL, CM, id),\
41 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
42 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
[all …]
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| /drivers/interconnect/qcom/ |
| D | sc8280xp.c | 20 .id = SC8280XP_MASTER_QSPI_0,
29 .id = SC8280XP_MASTER_QUP_1,
38 .id = SC8280XP_MASTER_QUP_2,
47 .id = SC8280XP_MASTER_A1NOC_CFG,
55 .id = SC8280XP_MASTER_IPA,
64 .id = SC8280XP_MASTER_EMAC_1,
73 .id = SC8280XP_MASTER_SDCC_4,
82 .id = SC8280XP_MASTER_UFS_MEM,
91 .id = SC8280XP_MASTER_USB3_0,
100 .id = SC8280XP_MASTER_USB3_1,
[all …]
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| D | sc8180x.c | 20 .id = SC8180X_MASTER_A1NOC_CFG,
29 .id = SC8180X_MASTER_UFS_CARD,
38 .id = SC8180X_MASTER_UFS_GEN4,
47 .id = SC8180X_MASTER_UFS_MEM,
56 .id = SC8180X_MASTER_USB3,
65 .id = SC8180X_MASTER_USB3_1,
74 .id = SC8180X_MASTER_USB3_2,
83 .id = SC8180X_MASTER_A2NOC_CFG,
92 .id = SC8180X_MASTER_QDSS_BAM,
101 .id = SC8180X_MASTER_QSPI_0,
[all …]
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| D | sm8450.c | 21 .id = SM8450_MASTER_QSPI_0,
30 .id = SM8450_MASTER_QUP_1,
39 .id = SM8450_MASTER_A1NOC_CFG,
48 .id = SM8450_MASTER_SDCC_4,
57 .id = SM8450_MASTER_UFS_MEM,
66 .id = SM8450_MASTER_USB3_0,
75 .id = SM8450_MASTER_QDSS_BAM,
84 .id = SM8450_MASTER_QUP_0,
93 .id = SM8450_MASTER_QUP_2,
102 .id = SM8450_MASTER_A2NOC_CFG,
[all …]
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| /drivers/soundwire/ |
| D | slave.c | 26 struct sdw_slave_id *id, struct fwnode_handle *fwnode) in sdw_slave_add() argument
37 memcpy(&slave->id, id, sizeof(*id)); in sdw_slave_add()
41 if (id->unique_id == SDW_IGNORED_UNIQUE_ID) { in sdw_slave_add()
44 bus->link_id, id->mfg_id, id->part_id, in sdw_slave_add()
45 id->class_id); in sdw_slave_add()
49 bus->link_id, id->mfg_id, id->part_id, in sdw_slave_add()
50 id->class_id, id->unique_id); in sdw_slave_add()
98 struct sdw_slave_id *id) in find_slave() argument
126 sdw_extract_slave_id(bus, addr, id); in find_slave()
134 struct sdw_slave_id id; member
[all …]
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| /drivers/gpu/drm/msm/dsi/ |
| D | dsi_manager.c | 35 #define IS_MASTER_DSI_LINK(id) (msm_dsim_glb.master_dsi_link_id == id) argument
63 static inline struct msm_dsi *dsi_mgr_get_dsi(int id) in dsi_mgr_get_dsi() argument
65 return msm_dsim_glb.dsi[id]; in dsi_mgr_get_dsi()
68 static inline struct msm_dsi *dsi_mgr_get_other_dsi(int id) in dsi_mgr_get_other_dsi() argument
70 return msm_dsim_glb.dsi[(id + 1) % DSI_MAX]; in dsi_mgr_get_other_dsi()
73 static int dsi_mgr_parse_of(struct device_node *np, int id) in dsi_mgr_parse_of() argument
85 msm_dsim->master_dsi_link_id = id; in dsi_mgr_parse_of()
94 static int dsi_mgr_setup_components(int id) in dsi_mgr_setup_components() argument
96 struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); in dsi_mgr_setup_components()
97 struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id); in dsi_mgr_setup_components()
[all …]
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| /drivers/gpu/drm/amd/display/include/ |
| D | grph_object_id.h | 228 uint32_t id:8; member
237 uint32_t id, in dal_graphics_object_id_init() argument
242 id, enum_id, type, 0 in dal_graphics_object_id_init()
250 struct graphics_object_id id) in dal_graphics_object_id_to_uint() argument
252 return id.id + (id.enum_id << 0x8) + (id.type << 0xc); in dal_graphics_object_id_to_uint()
256 struct graphics_object_id id) in dal_graphics_object_id_get_controller_id() argument
258 if (id.type == OBJECT_TYPE_CONTROLLER) in dal_graphics_object_id_get_controller_id()
259 return (enum controller_id) id.id; in dal_graphics_object_id_get_controller_id()
264 struct graphics_object_id id) in dal_graphics_object_id_get_clock_source_id() argument
266 if (id.type == OBJECT_TYPE_CLOCK_SOURCE) in dal_graphics_object_id_get_clock_source_id()
[all …]
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