1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * I2C bus driver for the Cadence I2C controller.
4 *
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/i2c.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/iopoll.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/of.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/pinctrl/consumer.h>
19
20 /* Register offsets for the I2C device. */
21 #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */
22 #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */
23 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */
24 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */
25 #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */
26 #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */
27 #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */
28 #define CDNS_I2C_IMR_OFFSET 0x20 /* IRQ Mask Register, RO */
29 #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */
30 #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */
31
32 /* Control Register Bit mask definitions */
33 #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */
34 #define CDNS_I2C_CR_ACK_EN BIT(3)
35 #define CDNS_I2C_CR_NEA BIT(2)
36 #define CDNS_I2C_CR_MS BIT(1)
37 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
38 #define CDNS_I2C_CR_RW BIT(0)
39 /* 1 = Auto init FIFO to zeroes */
40 #define CDNS_I2C_CR_CLR_FIFO BIT(6)
41 #define CDNS_I2C_CR_DIVA_SHIFT 14
42 #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT)
43 #define CDNS_I2C_CR_DIVB_SHIFT 8
44 #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT)
45
46 #define CDNS_I2C_CR_MASTER_EN_MASK (CDNS_I2C_CR_NEA | \
47 CDNS_I2C_CR_ACK_EN | \
48 CDNS_I2C_CR_MS)
49
50 #define CDNS_I2C_CR_SLAVE_EN_MASK ~CDNS_I2C_CR_MASTER_EN_MASK
51
52 /* Status Register Bit mask definitions */
53 #define CDNS_I2C_SR_BA BIT(8)
54 #define CDNS_I2C_SR_TXDV BIT(6)
55 #define CDNS_I2C_SR_RXDV BIT(5)
56 #define CDNS_I2C_SR_RXRW BIT(3)
57
58 /*
59 * I2C Address Register Bit mask definitions
60 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
61 * bits. A write access to this register always initiates a transfer if the I2C
62 * is in master mode.
63 */
64 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */
65
66 /*
67 * I2C Interrupt Registers Bit mask definitions
68 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
69 * bit definitions.
70 */
71 #define CDNS_I2C_IXR_ARB_LOST BIT(9)
72 #define CDNS_I2C_IXR_RX_UNF BIT(7)
73 #define CDNS_I2C_IXR_TX_OVF BIT(6)
74 #define CDNS_I2C_IXR_RX_OVF BIT(5)
75 #define CDNS_I2C_IXR_SLV_RDY BIT(4)
76 #define CDNS_I2C_IXR_TO BIT(3)
77 #define CDNS_I2C_IXR_NACK BIT(2)
78 #define CDNS_I2C_IXR_DATA BIT(1)
79 #define CDNS_I2C_IXR_COMP BIT(0)
80
81 #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
82 CDNS_I2C_IXR_RX_UNF | \
83 CDNS_I2C_IXR_TX_OVF | \
84 CDNS_I2C_IXR_RX_OVF | \
85 CDNS_I2C_IXR_SLV_RDY | \
86 CDNS_I2C_IXR_TO | \
87 CDNS_I2C_IXR_NACK | \
88 CDNS_I2C_IXR_DATA | \
89 CDNS_I2C_IXR_COMP)
90
91 #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
92 CDNS_I2C_IXR_RX_UNF | \
93 CDNS_I2C_IXR_TX_OVF | \
94 CDNS_I2C_IXR_RX_OVF | \
95 CDNS_I2C_IXR_NACK)
96
97 #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \
98 CDNS_I2C_IXR_RX_UNF | \
99 CDNS_I2C_IXR_TX_OVF | \
100 CDNS_I2C_IXR_RX_OVF | \
101 CDNS_I2C_IXR_NACK | \
102 CDNS_I2C_IXR_DATA | \
103 CDNS_I2C_IXR_COMP)
104
105 #define CDNS_I2C_IXR_SLAVE_INTR_MASK (CDNS_I2C_IXR_RX_UNF | \
106 CDNS_I2C_IXR_TX_OVF | \
107 CDNS_I2C_IXR_RX_OVF | \
108 CDNS_I2C_IXR_TO | \
109 CDNS_I2C_IXR_NACK | \
110 CDNS_I2C_IXR_DATA | \
111 CDNS_I2C_IXR_COMP)
112
113 #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000)
114 /* timeout for pm runtime autosuspend */
115 #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */
116
117 #define CDNS_I2C_FIFO_DEPTH 16
118 /* FIFO depth at which the DATA interrupt occurs */
119 #define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2)
120 #define CDNS_I2C_MAX_TRANSFER_SIZE 255
121 /* Transfer size in multiples of data interrupt depth */
122 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3)
123
124 #define DRIVER_NAME "cdns-i2c"
125
126 #define CDNS_I2C_DIVA_MAX 4
127 #define CDNS_I2C_DIVB_MAX 64
128
129 #define CDNS_I2C_TIMEOUT_MAX 0xFF
130
131 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
132 #define CDNS_I2C_POLL_US 100000
133 #define CDNS_I2C_TIMEOUT_US 500000
134
135 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
136 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
137
138 #if IS_ENABLED(CONFIG_I2C_SLAVE)
139 /**
140 * enum cdns_i2c_mode - I2C Controller current operating mode
141 *
142 * @CDNS_I2C_MODE_SLAVE: I2C controller operating in slave mode
143 * @CDNS_I2C_MODE_MASTER: I2C Controller operating in master mode
144 */
145 enum cdns_i2c_mode {
146 CDNS_I2C_MODE_SLAVE,
147 CDNS_I2C_MODE_MASTER,
148 };
149
150 /**
151 * enum cdns_i2c_slave_state - Slave state when I2C is operating in slave mode
152 *
153 * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle
154 * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master
155 * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master
156 */
157 enum cdns_i2c_slave_state {
158 CDNS_I2C_SLAVE_STATE_IDLE,
159 CDNS_I2C_SLAVE_STATE_SEND,
160 CDNS_I2C_SLAVE_STATE_RECV,
161 };
162 #endif
163
164 /**
165 * struct cdns_i2c - I2C device private data structure
166 *
167 * @dev: Pointer to device structure
168 * @membase: Base address of the I2C device
169 * @adap: I2C adapter instance
170 * @p_msg: Message pointer
171 * @err_status: Error status in Interrupt Status Register
172 * @xfer_done: Transfer complete status
173 * @p_send_buf: Pointer to transmit buffer
174 * @p_recv_buf: Pointer to receive buffer
175 * @send_count: Number of bytes still expected to send
176 * @recv_count: Number of bytes still expected to receive
177 * @curr_recv_count: Number of bytes to be received in current transfer
178 * @irq: IRQ number
179 * @input_clk: Input clock to I2C controller
180 * @i2c_clk: Maximum I2C clock speed
181 * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit
182 * @clk: Pointer to struct clk
183 * @clk_rate_change_nb: Notifier block for clock rate changes
184 * @quirks: flag for broken hold bit usage in r1p10
185 * @ctrl_reg: Cached value of the control register.
186 * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register
187 * @slave: Registered slave instance.
188 * @dev_mode: I2C operating role(master/slave).
189 * @slave_state: I2C Slave state(idle/read/write).
190 */
191 struct cdns_i2c {
192 struct device *dev;
193 void __iomem *membase;
194 struct i2c_adapter adap;
195 struct i2c_msg *p_msg;
196 int err_status;
197 struct completion xfer_done;
198 unsigned char *p_send_buf;
199 unsigned char *p_recv_buf;
200 unsigned int send_count;
201 unsigned int recv_count;
202 unsigned int curr_recv_count;
203 int irq;
204 unsigned long input_clk;
205 unsigned int i2c_clk;
206 unsigned int bus_hold_flag;
207 struct clk *clk;
208 struct notifier_block clk_rate_change_nb;
209 u32 quirks;
210 u32 ctrl_reg;
211 struct i2c_bus_recovery_info rinfo;
212 #if IS_ENABLED(CONFIG_I2C_SLAVE)
213 u16 ctrl_reg_diva_divb;
214 struct i2c_client *slave;
215 enum cdns_i2c_mode dev_mode;
216 enum cdns_i2c_slave_state slave_state;
217 #endif
218 };
219
220 struct cdns_platform_data {
221 u32 quirks;
222 };
223
224 #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \
225 clk_rate_change_nb)
226
227 /**
228 * cdns_i2c_clear_bus_hold - Clear bus hold bit
229 * @id: Pointer to driver data struct
230 *
231 * Helper to clear the controller's bus hold bit.
232 */
cdns_i2c_clear_bus_hold(struct cdns_i2c * id)233 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id)
234 {
235 u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
236 if (reg & CDNS_I2C_CR_HOLD)
237 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
238 }
239
cdns_is_holdquirk(struct cdns_i2c * id,bool hold_wrkaround)240 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround)
241 {
242 return (hold_wrkaround &&
243 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1));
244 }
245
246 #if IS_ENABLED(CONFIG_I2C_SLAVE)
cdns_i2c_set_mode(enum cdns_i2c_mode mode,struct cdns_i2c * id)247 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id)
248 {
249 /* Disable all interrupts */
250 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
251
252 /* Clear FIFO and transfer size */
253 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
254
255 /* Update device mode and state */
256 id->dev_mode = mode;
257 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
258
259 switch (mode) {
260 case CDNS_I2C_MODE_MASTER:
261 /* Enable i2c master */
262 cdns_i2c_writereg(id->ctrl_reg_diva_divb |
263 CDNS_I2C_CR_MASTER_EN_MASK,
264 CDNS_I2C_CR_OFFSET);
265 /*
266 * This delay is needed to give the IP some time to switch to
267 * the master mode. With lower values(like 110 us) i2cdetect
268 * will not detect any slave and without this delay, the IP will
269 * trigger a timeout interrupt.
270 */
271 usleep_range(115, 125);
272 break;
273 case CDNS_I2C_MODE_SLAVE:
274 /* Enable i2c slave */
275 cdns_i2c_writereg(id->ctrl_reg_diva_divb &
276 CDNS_I2C_CR_SLAVE_EN_MASK,
277 CDNS_I2C_CR_OFFSET);
278
279 /* Setting slave address */
280 cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK,
281 CDNS_I2C_ADDR_OFFSET);
282
283 /* Enable slave send/receive interrupts */
284 cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK,
285 CDNS_I2C_IER_OFFSET);
286 break;
287 }
288 }
289
cdns_i2c_slave_rcv_data(struct cdns_i2c * id)290 static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id)
291 {
292 u8 bytes;
293 unsigned char data;
294
295 /* Prepare backend for data reception */
296 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
297 id->slave_state = CDNS_I2C_SLAVE_STATE_RECV;
298 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL);
299 }
300
301 /* Fetch number of bytes to receive */
302 bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
303
304 /* Read data and send to backend */
305 while (bytes--) {
306 data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
307 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data);
308 }
309 }
310
cdns_i2c_slave_send_data(struct cdns_i2c * id)311 static void cdns_i2c_slave_send_data(struct cdns_i2c *id)
312 {
313 u8 data;
314
315 /* Prepare backend for data transmission */
316 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) {
317 id->slave_state = CDNS_I2C_SLAVE_STATE_SEND;
318 i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data);
319 } else {
320 i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data);
321 }
322
323 /* Send data over bus */
324 cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET);
325 }
326
327 /**
328 * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role
329 * @ptr: Pointer to I2C device private data
330 *
331 * This function handles the data interrupt and transfer complete interrupt of
332 * the I2C device in slave role.
333 *
334 * Return: IRQ_HANDLED always
335 */
cdns_i2c_slave_isr(void * ptr)336 static irqreturn_t cdns_i2c_slave_isr(void *ptr)
337 {
338 struct cdns_i2c *id = ptr;
339 unsigned int isr_status, i2c_status;
340
341 /* Fetch the interrupt status */
342 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
343 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
344
345 /* Ignore masked interrupts */
346 isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET);
347
348 /* Fetch transfer mode (send/receive) */
349 i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
350
351 /* Handle data send/receive */
352 if (i2c_status & CDNS_I2C_SR_RXRW) {
353 /* Send data to master */
354 if (isr_status & CDNS_I2C_IXR_DATA)
355 cdns_i2c_slave_send_data(id);
356
357 if (isr_status & CDNS_I2C_IXR_COMP) {
358 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
359 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
360 }
361 } else {
362 /* Receive data from master */
363 if (isr_status & CDNS_I2C_IXR_DATA)
364 cdns_i2c_slave_rcv_data(id);
365
366 if (isr_status & CDNS_I2C_IXR_COMP) {
367 cdns_i2c_slave_rcv_data(id);
368 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
369 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
370 }
371 }
372
373 /* Master indicated xfer stop or fifo underflow/overflow */
374 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF |
375 CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) {
376 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
377 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL);
378 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET);
379 }
380
381 return IRQ_HANDLED;
382 }
383 #endif
384
385 /**
386 * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role
387 * @ptr: Pointer to I2C device private data
388 *
389 * This function handles the data interrupt, transfer complete interrupt and
390 * the error interrupts of the I2C device in master role.
391 *
392 * Return: IRQ_HANDLED always
393 */
cdns_i2c_master_isr(void * ptr)394 static irqreturn_t cdns_i2c_master_isr(void *ptr)
395 {
396 unsigned int isr_status, avail_bytes;
397 unsigned int bytes_to_send;
398 bool updatetx;
399 struct cdns_i2c *id = ptr;
400 /* Signal completion only after everything is updated */
401 int done_flag = 0;
402 irqreturn_t status = IRQ_NONE;
403
404 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
405 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
406 id->err_status = 0;
407
408 /* Handling nack and arbitration lost interrupt */
409 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) {
410 done_flag = 1;
411 status = IRQ_HANDLED;
412 }
413
414 /*
415 * Check if transfer size register needs to be updated again for a
416 * large data receive operation.
417 */
418 updatetx = id->recv_count > id->curr_recv_count;
419
420 /* When receiving, handle data interrupt and completion interrupt */
421 if (id->p_recv_buf &&
422 ((isr_status & CDNS_I2C_IXR_COMP) ||
423 (isr_status & CDNS_I2C_IXR_DATA))) {
424 /* Read data if receive data valid is set */
425 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) &
426 CDNS_I2C_SR_RXDV) {
427 if (id->recv_count > 0) {
428 *(id->p_recv_buf)++ =
429 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET);
430 id->recv_count--;
431 id->curr_recv_count--;
432
433 /*
434 * Clear hold bit that was set for FIFO control
435 * if RX data left is less than or equal to
436 * FIFO DEPTH unless repeated start is selected
437 */
438 if (id->recv_count <= CDNS_I2C_FIFO_DEPTH &&
439 !id->bus_hold_flag)
440 cdns_i2c_clear_bus_hold(id);
441
442 } else {
443 dev_err(id->adap.dev.parent,
444 "xfer_size reg rollover. xfer aborted!\n");
445 id->err_status |= CDNS_I2C_IXR_TO;
446 break;
447 }
448
449 if (cdns_is_holdquirk(id, updatetx))
450 break;
451 }
452
453 /*
454 * The controller sends NACK to the slave when transfer size
455 * register reaches zero without considering the HOLD bit.
456 * This workaround is implemented for large data transfers to
457 * maintain transfer size non-zero while performing a large
458 * receive operation.
459 */
460 if (cdns_is_holdquirk(id, updatetx)) {
461 /* wait while fifo is full */
462 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) !=
463 (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH))
464 ;
465
466 /*
467 * Check number of bytes to be received against maximum
468 * transfer size and update register accordingly.
469 */
470 if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) >
471 CDNS_I2C_TRANSFER_SIZE) {
472 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
473 CDNS_I2C_XFER_SIZE_OFFSET);
474 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
475 CDNS_I2C_FIFO_DEPTH;
476 } else {
477 cdns_i2c_writereg(id->recv_count -
478 CDNS_I2C_FIFO_DEPTH,
479 CDNS_I2C_XFER_SIZE_OFFSET);
480 id->curr_recv_count = id->recv_count;
481 }
482 }
483
484 /* Clear hold (if not repeated start) and signal completion */
485 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) {
486 if (!id->bus_hold_flag)
487 cdns_i2c_clear_bus_hold(id);
488 done_flag = 1;
489 }
490
491 status = IRQ_HANDLED;
492 }
493
494 /* When sending, handle transfer complete interrupt */
495 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) {
496 /*
497 * If there is more data to be sent, calculate the
498 * space available in FIFO and fill with that many bytes.
499 */
500 if (id->send_count) {
501 avail_bytes = CDNS_I2C_FIFO_DEPTH -
502 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
503 if (id->send_count > avail_bytes)
504 bytes_to_send = avail_bytes;
505 else
506 bytes_to_send = id->send_count;
507
508 while (bytes_to_send--) {
509 cdns_i2c_writereg(
510 (*(id->p_send_buf)++),
511 CDNS_I2C_DATA_OFFSET);
512 id->send_count--;
513 }
514 } else {
515 /*
516 * Signal the completion of transaction and
517 * clear the hold bus bit if there are no
518 * further messages to be processed.
519 */
520 done_flag = 1;
521 }
522 if (!id->send_count && !id->bus_hold_flag)
523 cdns_i2c_clear_bus_hold(id);
524
525 status = IRQ_HANDLED;
526 }
527
528 /* Update the status for errors */
529 id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
530 if (id->err_status)
531 status = IRQ_HANDLED;
532
533 if (done_flag)
534 complete(&id->xfer_done);
535
536 return status;
537 }
538
539 /**
540 * cdns_i2c_isr - Interrupt handler for the I2C device
541 * @irq: irq number for the I2C device
542 * @ptr: void pointer to cdns_i2c structure
543 *
544 * This function passes the control to slave/master based on current role of
545 * i2c controller.
546 *
547 * Return: IRQ_HANDLED always
548 */
cdns_i2c_isr(int irq,void * ptr)549 static irqreturn_t cdns_i2c_isr(int irq, void *ptr)
550 {
551 #if IS_ENABLED(CONFIG_I2C_SLAVE)
552 struct cdns_i2c *id = ptr;
553
554 if (id->dev_mode == CDNS_I2C_MODE_SLAVE)
555 return cdns_i2c_slave_isr(ptr);
556 #endif
557 return cdns_i2c_master_isr(ptr);
558 }
559
560 /**
561 * cdns_i2c_mrecv - Prepare and start a master receive operation
562 * @id: pointer to the i2c device structure
563 */
cdns_i2c_mrecv(struct cdns_i2c * id)564 static void cdns_i2c_mrecv(struct cdns_i2c *id)
565 {
566 unsigned int ctrl_reg;
567 unsigned int isr_status;
568 unsigned long flags;
569 bool hold_clear = false;
570 bool irq_save = false;
571
572 u32 addr;
573
574 id->p_recv_buf = id->p_msg->buf;
575 id->recv_count = id->p_msg->len;
576
577 /* Put the controller in master receive mode and clear the FIFO */
578 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
579 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
580
581 /*
582 * Receive up to I2C_SMBUS_BLOCK_MAX data bytes, plus one message length
583 * byte, plus one checksum byte if PEC is enabled. p_msg->len will be 2 if
584 * PEC is enabled, otherwise 1.
585 */
586 if (id->p_msg->flags & I2C_M_RECV_LEN)
587 id->recv_count = I2C_SMBUS_BLOCK_MAX + id->p_msg->len;
588
589 id->curr_recv_count = id->recv_count;
590
591 /*
592 * Check for the message size against FIFO depth and set the
593 * 'hold bus' bit if it is greater than FIFO depth.
594 */
595 if (id->recv_count > CDNS_I2C_FIFO_DEPTH)
596 ctrl_reg |= CDNS_I2C_CR_HOLD;
597
598 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
599
600 /* Clear the interrupts in interrupt status register */
601 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
602 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
603
604 /*
605 * The no. of bytes to receive is checked against the limit of
606 * max transfer size. Set transfer size register with no of bytes
607 * receive if it is less than transfer size and transfer size if
608 * it is more. Enable the interrupts.
609 */
610 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) {
611 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE,
612 CDNS_I2C_XFER_SIZE_OFFSET);
613 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
614 } else {
615 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
616 }
617
618 /* Determine hold_clear based on number of bytes to receive and hold flag */
619 if (!id->bus_hold_flag &&
620 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) &&
621 (id->recv_count <= CDNS_I2C_FIFO_DEPTH)) {
622 if (cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & CDNS_I2C_CR_HOLD) {
623 hold_clear = true;
624 if (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT)
625 irq_save = true;
626 }
627 }
628
629 addr = id->p_msg->addr;
630 addr &= CDNS_I2C_ADDR_MASK;
631
632 if (hold_clear) {
633 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & ~CDNS_I2C_CR_HOLD;
634 /*
635 * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size
636 * register reaches '0'. This is an IP bug which causes transfer size
637 * register overflow to 0xFF. To satisfy this timing requirement,
638 * disable the interrupts on current processor core between register
639 * writes to slave address register and control register.
640 */
641 if (irq_save)
642 local_irq_save(flags);
643
644 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET);
645 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
646 /* Read it back to avoid bufferring and make sure write happens */
647 cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
648
649 if (irq_save)
650 local_irq_restore(flags);
651 } else {
652 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET);
653 }
654
655 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
656 }
657
658 /**
659 * cdns_i2c_msend - Prepare and start a master send operation
660 * @id: pointer to the i2c device
661 */
cdns_i2c_msend(struct cdns_i2c * id)662 static void cdns_i2c_msend(struct cdns_i2c *id)
663 {
664 unsigned int avail_bytes;
665 unsigned int bytes_to_send;
666 unsigned int ctrl_reg;
667 unsigned int isr_status;
668
669 id->p_recv_buf = NULL;
670 id->p_send_buf = id->p_msg->buf;
671 id->send_count = id->p_msg->len;
672
673 /* Set the controller in Master transmit mode and clear the FIFO. */
674 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
675 ctrl_reg &= ~CDNS_I2C_CR_RW;
676 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
677
678 /*
679 * Check for the message size against FIFO depth and set the
680 * 'hold bus' bit if it is greater than FIFO depth.
681 */
682 if (id->send_count > CDNS_I2C_FIFO_DEPTH)
683 ctrl_reg |= CDNS_I2C_CR_HOLD;
684 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
685
686 /* Clear the interrupts in interrupt status register. */
687 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
688 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET);
689
690 /*
691 * Calculate the space available in FIFO. Check the message length
692 * against the space available, and fill the FIFO accordingly.
693 * Enable the interrupts.
694 */
695 avail_bytes = CDNS_I2C_FIFO_DEPTH -
696 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET);
697
698 if (id->send_count > avail_bytes)
699 bytes_to_send = avail_bytes;
700 else
701 bytes_to_send = id->send_count;
702
703 while (bytes_to_send--) {
704 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET);
705 id->send_count--;
706 }
707
708 /*
709 * Clear the bus hold flag if there is no more data
710 * and if it is the last message.
711 */
712 if (!id->bus_hold_flag && !id->send_count)
713 cdns_i2c_clear_bus_hold(id);
714 /* Set the slave address in address register - triggers operation. */
715 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,
716 CDNS_I2C_ADDR_OFFSET);
717
718 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
719 }
720
721 /**
722 * cdns_i2c_master_reset - Reset the interface
723 * @adap: pointer to the i2c adapter driver instance
724 *
725 * This function cleanup the fifos, clear the hold bit and status
726 * and disable the interrupts.
727 */
cdns_i2c_master_reset(struct i2c_adapter * adap)728 static void cdns_i2c_master_reset(struct i2c_adapter *adap)
729 {
730 struct cdns_i2c *id = adap->algo_data;
731 u32 regval;
732
733 /* Disable the interrupts */
734 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
735 /* Clear the hold bit and fifos */
736 regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
737 regval &= ~CDNS_I2C_CR_HOLD;
738 regval |= CDNS_I2C_CR_CLR_FIFO;
739 cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET);
740 /* Update the transfercount register to zero */
741 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET);
742 /* Clear the interrupt status register */
743 regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET);
744 cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET);
745 /* Clear the status register */
746 regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET);
747 cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET);
748 }
749
cdns_i2c_process_msg(struct cdns_i2c * id,struct i2c_msg * msg,struct i2c_adapter * adap)750 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg,
751 struct i2c_adapter *adap)
752 {
753 unsigned long time_left, msg_timeout;
754 u32 reg;
755
756 id->p_msg = msg;
757 id->err_status = 0;
758 reinit_completion(&id->xfer_done);
759
760 /* Check for the TEN Bit mode on each msg */
761 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
762 if (msg->flags & I2C_M_TEN) {
763 if (reg & CDNS_I2C_CR_NEA)
764 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA,
765 CDNS_I2C_CR_OFFSET);
766 } else {
767 if (!(reg & CDNS_I2C_CR_NEA))
768 cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA,
769 CDNS_I2C_CR_OFFSET);
770 }
771
772 /* Check for the R/W flag on each msg */
773 if (msg->flags & I2C_M_RD)
774 cdns_i2c_mrecv(id);
775 else
776 cdns_i2c_msend(id);
777
778 /* Minimal time to execute this message */
779 msg_timeout = msecs_to_jiffies((1000 * msg->len * BITS_PER_BYTE) / id->i2c_clk);
780 /* Plus some wiggle room */
781 msg_timeout += msecs_to_jiffies(500);
782
783 if (msg_timeout < adap->timeout)
784 msg_timeout = adap->timeout;
785
786 /* Wait for the signal of completion */
787 time_left = wait_for_completion_timeout(&id->xfer_done, msg_timeout);
788 if (time_left == 0) {
789 cdns_i2c_master_reset(adap);
790 dev_err(id->adap.dev.parent,
791 "timeout waiting on completion\n");
792 return -ETIMEDOUT;
793 }
794
795 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK,
796 CDNS_I2C_IDR_OFFSET);
797
798 /* If it is bus arbitration error, try again */
799 if (id->err_status & CDNS_I2C_IXR_ARB_LOST)
800 return -EAGAIN;
801
802 if (msg->flags & I2C_M_RECV_LEN)
803 msg->len += min_t(unsigned int, msg->buf[0], I2C_SMBUS_BLOCK_MAX);
804
805 return 0;
806 }
807
808 /**
809 * cdns_i2c_master_xfer - The main i2c transfer function
810 * @adap: pointer to the i2c adapter driver instance
811 * @msgs: pointer to the i2c message structure
812 * @num: the number of messages to transfer
813 *
814 * Initiates the send/recv activity based on the transfer message received.
815 *
816 * Return: number of msgs processed on success, negative error otherwise
817 */
cdns_i2c_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)818 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
819 int num)
820 {
821 int ret, count;
822 u32 reg;
823 struct cdns_i2c *id = adap->algo_data;
824 bool hold_quirk;
825 #if IS_ENABLED(CONFIG_I2C_SLAVE)
826 bool change_role = false;
827 #endif
828
829 ret = pm_runtime_resume_and_get(id->dev);
830 if (ret < 0)
831 return ret;
832
833 #if IS_ENABLED(CONFIG_I2C_SLAVE)
834 /* Check i2c operating mode and switch if possible */
835 if (id->dev_mode == CDNS_I2C_MODE_SLAVE) {
836 if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE) {
837 ret = -EAGAIN;
838 goto out;
839 }
840
841 /* Set mode to master */
842 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
843
844 /* Mark flag to change role once xfer is completed */
845 change_role = true;
846 }
847 #endif
848
849 /* Check if the bus is free */
850
851 ret = readl_relaxed_poll_timeout(id->membase + CDNS_I2C_SR_OFFSET,
852 reg,
853 !(reg & CDNS_I2C_SR_BA),
854 CDNS_I2C_POLL_US, CDNS_I2C_TIMEOUT_US);
855 if (ret) {
856 ret = -EAGAIN;
857 if (id->adap.bus_recovery_info)
858 i2c_recover_bus(adap);
859 goto out;
860 }
861
862 hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
863 /*
864 * Set the flag to one when multiple messages are to be
865 * processed with a repeated start.
866 */
867 if (num > 1) {
868 /*
869 * This controller does not give completion interrupt after a
870 * master receive message if HOLD bit is set (repeated start),
871 * resulting in SW timeout. Hence, if a receive message is
872 * followed by any other message, an error is returned
873 * indicating that this sequence is not supported.
874 */
875 for (count = 0; (count < num - 1 && hold_quirk); count++) {
876 if (msgs[count].flags & I2C_M_RD) {
877 dev_warn(adap->dev.parent,
878 "Can't do repeated start after a receive message\n");
879 ret = -EOPNOTSUPP;
880 goto out;
881 }
882 }
883 id->bus_hold_flag = 1;
884 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
885 reg |= CDNS_I2C_CR_HOLD;
886 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET);
887 } else {
888 id->bus_hold_flag = 0;
889 }
890
891 /* Process the msg one by one */
892 for (count = 0; count < num; count++, msgs++) {
893 if (count == (num - 1))
894 id->bus_hold_flag = 0;
895
896 ret = cdns_i2c_process_msg(id, msgs, adap);
897 if (ret)
898 goto out;
899
900 /* Report the other error interrupts to application */
901 if (id->err_status) {
902 cdns_i2c_master_reset(adap);
903
904 if (id->err_status & CDNS_I2C_IXR_NACK) {
905 ret = -ENXIO;
906 goto out;
907 }
908 ret = -EIO;
909 goto out;
910 }
911 }
912
913 ret = num;
914
915 out:
916
917 #if IS_ENABLED(CONFIG_I2C_SLAVE)
918 /* Switch i2c mode to slave */
919 if (change_role)
920 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
921 #endif
922
923 pm_runtime_mark_last_busy(id->dev);
924 pm_runtime_put_autosuspend(id->dev);
925 return ret;
926 }
927
928 /**
929 * cdns_i2c_func - Returns the supported features of the I2C driver
930 * @adap: pointer to the i2c adapter structure
931 *
932 * Return: 32 bit value, each bit corresponding to a feature
933 */
cdns_i2c_func(struct i2c_adapter * adap)934 static u32 cdns_i2c_func(struct i2c_adapter *adap)
935 {
936 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
937 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
938 I2C_FUNC_SMBUS_BLOCK_DATA;
939
940 #if IS_ENABLED(CONFIG_I2C_SLAVE)
941 func |= I2C_FUNC_SLAVE;
942 #endif
943
944 return func;
945 }
946
947 #if IS_ENABLED(CONFIG_I2C_SLAVE)
cdns_reg_slave(struct i2c_client * slave)948 static int cdns_reg_slave(struct i2c_client *slave)
949 {
950 int ret;
951 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
952 adap);
953
954 if (id->slave)
955 return -EBUSY;
956
957 if (slave->flags & I2C_CLIENT_TEN)
958 return -EAFNOSUPPORT;
959
960 ret = pm_runtime_resume_and_get(id->dev);
961 if (ret < 0)
962 return ret;
963
964 /* Store slave information */
965 id->slave = slave;
966
967 /* Enable I2C slave */
968 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id);
969
970 return 0;
971 }
972
cdns_unreg_slave(struct i2c_client * slave)973 static int cdns_unreg_slave(struct i2c_client *slave)
974 {
975 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c,
976 adap);
977
978 pm_runtime_put(id->dev);
979
980 /* Remove slave information */
981 id->slave = NULL;
982
983 /* Enable I2C master */
984 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id);
985
986 return 0;
987 }
988 #endif
989
990 static const struct i2c_algorithm cdns_i2c_algo = {
991 .master_xfer = cdns_i2c_master_xfer,
992 .functionality = cdns_i2c_func,
993 #if IS_ENABLED(CONFIG_I2C_SLAVE)
994 .reg_slave = cdns_reg_slave,
995 .unreg_slave = cdns_unreg_slave,
996 #endif
997 };
998
999 /**
1000 * cdns_i2c_calc_divs - Calculate clock dividers
1001 * @f: I2C clock frequency
1002 * @input_clk: Input clock frequency
1003 * @a: First divider (return value)
1004 * @b: Second divider (return value)
1005 *
1006 * f is used as input and output variable. As input it is used as target I2C
1007 * frequency. On function exit f holds the actually resulting I2C frequency.
1008 *
1009 * Return: 0 on success, negative errno otherwise.
1010 */
cdns_i2c_calc_divs(unsigned long * f,unsigned long input_clk,unsigned int * a,unsigned int * b)1011 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
1012 unsigned int *a, unsigned int *b)
1013 {
1014 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
1015 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
1016 unsigned int last_error, current_error;
1017
1018 /* calculate (divisor_a+1) x (divisor_b+1) */
1019 temp = input_clk / (22 * fscl);
1020
1021 /*
1022 * If the calculated value is negative or 0, the fscl input is out of
1023 * range. Return error.
1024 */
1025 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
1026 return -EINVAL;
1027
1028 last_error = -1;
1029 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
1030 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
1031
1032 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
1033 continue;
1034 div_b--;
1035
1036 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
1037
1038 if (actual_fscl > fscl)
1039 continue;
1040
1041 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
1042 (fscl - actual_fscl));
1043
1044 if (last_error > current_error) {
1045 calc_div_a = div_a;
1046 calc_div_b = div_b;
1047 best_fscl = actual_fscl;
1048 last_error = current_error;
1049 }
1050 }
1051
1052 *a = calc_div_a;
1053 *b = calc_div_b;
1054 *f = best_fscl;
1055
1056 return 0;
1057 }
1058
1059 /**
1060 * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device
1061 * @clk_in: I2C clock input frequency in Hz
1062 * @id: Pointer to the I2C device structure
1063 *
1064 * The device must be idle rather than busy transferring data before setting
1065 * these device options.
1066 * The data rate is set by values in the control register.
1067 * The formula for determining the correct register values is
1068 * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
1069 * See the hardware data sheet for a full explanation of setting the serial
1070 * clock rate. The clock can not be faster than the input clock divide by 22.
1071 * The two most common clock rates are 100KHz and 400KHz.
1072 *
1073 * Return: 0 on success, negative error otherwise
1074 */
cdns_i2c_setclk(unsigned long clk_in,struct cdns_i2c * id)1075 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id)
1076 {
1077 unsigned int div_a, div_b;
1078 unsigned int ctrl_reg;
1079 int ret = 0;
1080 unsigned long fscl = id->i2c_clk;
1081
1082 ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b);
1083 if (ret)
1084 return ret;
1085
1086 ctrl_reg = id->ctrl_reg;
1087 ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
1088 ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
1089 (div_b << CDNS_I2C_CR_DIVB_SHIFT));
1090 id->ctrl_reg = ctrl_reg;
1091 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
1092 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1093 id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK |
1094 CDNS_I2C_CR_DIVB_MASK);
1095 #endif
1096 return 0;
1097 }
1098
1099 /**
1100 * cdns_i2c_clk_notifier_cb - Clock rate change callback
1101 * @nb: Pointer to notifier block
1102 * @event: Notification reason
1103 * @data: Pointer to notification data object
1104 *
1105 * This function is called when the cdns_i2c input clock frequency changes.
1106 * The callback checks whether a valid bus frequency can be generated after the
1107 * change. If so, the change is acknowledged, otherwise the change is aborted.
1108 * New dividers are written to the HW in the pre- or post change notification
1109 * depending on the scaling direction.
1110 *
1111 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
1112 * to acknowledge the change, NOTIFY_DONE if the notification is
1113 * considered irrelevant.
1114 */
cdns_i2c_clk_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)1115 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
1116 event, void *data)
1117 {
1118 struct clk_notifier_data *ndata = data;
1119 struct cdns_i2c *id = to_cdns_i2c(nb);
1120
1121 if (pm_runtime_suspended(id->dev))
1122 return NOTIFY_OK;
1123
1124 switch (event) {
1125 case PRE_RATE_CHANGE:
1126 {
1127 unsigned long input_clk = ndata->new_rate;
1128 unsigned long fscl = id->i2c_clk;
1129 unsigned int div_a, div_b;
1130 int ret;
1131
1132 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b);
1133 if (ret) {
1134 dev_warn(id->adap.dev.parent,
1135 "clock rate change rejected\n");
1136 return NOTIFY_STOP;
1137 }
1138
1139 /* scale up */
1140 if (ndata->new_rate > ndata->old_rate)
1141 cdns_i2c_setclk(ndata->new_rate, id);
1142
1143 return NOTIFY_OK;
1144 }
1145 case POST_RATE_CHANGE:
1146 id->input_clk = ndata->new_rate;
1147 /* scale down */
1148 if (ndata->new_rate < ndata->old_rate)
1149 cdns_i2c_setclk(ndata->new_rate, id);
1150 return NOTIFY_OK;
1151 case ABORT_RATE_CHANGE:
1152 /* scale up */
1153 if (ndata->new_rate > ndata->old_rate)
1154 cdns_i2c_setclk(ndata->old_rate, id);
1155 return NOTIFY_OK;
1156 default:
1157 return NOTIFY_DONE;
1158 }
1159 }
1160
1161 /**
1162 * cdns_i2c_runtime_suspend - Runtime suspend method for the driver
1163 * @dev: Address of the platform_device structure
1164 *
1165 * Put the driver into low power mode.
1166 *
1167 * Return: 0 always
1168 */
cdns_i2c_runtime_suspend(struct device * dev)1169 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev)
1170 {
1171 struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1172
1173 clk_disable(xi2c->clk);
1174
1175 return 0;
1176 }
1177
1178 /**
1179 * cdns_i2c_init - Controller initialisation
1180 * @id: Device private data structure
1181 *
1182 * Initialise the i2c controller.
1183 *
1184 */
cdns_i2c_init(struct cdns_i2c * id)1185 static void cdns_i2c_init(struct cdns_i2c *id)
1186 {
1187 cdns_i2c_writereg(id->ctrl_reg, CDNS_I2C_CR_OFFSET);
1188 /*
1189 * Cadence I2C controller has a bug wherein it generates
1190 * invalid read transaction after HW timeout in master receiver mode.
1191 * HW timeout is not used by this driver and the interrupt is disabled.
1192 * But the feature itself cannot be disabled. Hence maximum value
1193 * is written to this register to reduce the chances of error.
1194 */
1195 cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
1196 }
1197
1198 /**
1199 * cdns_i2c_runtime_resume - Runtime resume
1200 * @dev: Address of the platform_device structure
1201 *
1202 * Runtime resume callback.
1203 *
1204 * Return: 0 on success and error value on error
1205 */
cdns_i2c_runtime_resume(struct device * dev)1206 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev)
1207 {
1208 struct cdns_i2c *xi2c = dev_get_drvdata(dev);
1209 int ret;
1210
1211 ret = clk_enable(xi2c->clk);
1212 if (ret) {
1213 dev_err(dev, "Cannot enable clock.\n");
1214 return ret;
1215 }
1216 cdns_i2c_init(xi2c);
1217
1218 return 0;
1219 }
1220
1221 static const struct dev_pm_ops cdns_i2c_dev_pm_ops = {
1222 SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend,
1223 cdns_i2c_runtime_resume, NULL)
1224 };
1225
1226 static const struct cdns_platform_data r1p10_i2c_def = {
1227 .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
1228 };
1229
1230 static const struct of_device_id cdns_i2c_of_match[] = {
1231 { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def },
1232 { .compatible = "cdns,i2c-r1p14",},
1233 { /* end of table */ }
1234 };
1235 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match);
1236
1237 /**
1238 * cdns_i2c_probe - Platform registration call
1239 * @pdev: Handle to the platform device structure
1240 *
1241 * This function does all the memory allocation and registration for the i2c
1242 * device. User can modify the address mode to 10 bit address mode using the
1243 * ioctl call with option I2C_TENBIT.
1244 *
1245 * Return: 0 on success, negative error otherwise
1246 */
cdns_i2c_probe(struct platform_device * pdev)1247 static int cdns_i2c_probe(struct platform_device *pdev)
1248 {
1249 struct resource *r_mem;
1250 struct cdns_i2c *id;
1251 int ret;
1252 const struct of_device_id *match;
1253
1254 id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL);
1255 if (!id)
1256 return -ENOMEM;
1257
1258 id->dev = &pdev->dev;
1259 platform_set_drvdata(pdev, id);
1260
1261 match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node);
1262 if (match && match->data) {
1263 const struct cdns_platform_data *data = match->data;
1264 id->quirks = data->quirks;
1265 }
1266
1267 id->rinfo.pinctrl = devm_pinctrl_get(&pdev->dev);
1268 if (IS_ERR(id->rinfo.pinctrl)) {
1269 int err = PTR_ERR(id->rinfo.pinctrl);
1270
1271 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1272 if (err != -ENODEV)
1273 return err;
1274 } else {
1275 id->adap.bus_recovery_info = &id->rinfo;
1276 }
1277
1278 id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem);
1279 if (IS_ERR(id->membase))
1280 return PTR_ERR(id->membase);
1281
1282 ret = platform_get_irq(pdev, 0);
1283 if (ret < 0)
1284 return ret;
1285 id->irq = ret;
1286
1287 id->adap.owner = THIS_MODULE;
1288 id->adap.dev.of_node = pdev->dev.of_node;
1289 id->adap.algo = &cdns_i2c_algo;
1290 id->adap.timeout = CDNS_I2C_TIMEOUT;
1291 id->adap.retries = 3; /* Default retry value. */
1292 id->adap.algo_data = id;
1293 id->adap.dev.parent = &pdev->dev;
1294 init_completion(&id->xfer_done);
1295 snprintf(id->adap.name, sizeof(id->adap.name),
1296 "Cadence I2C at %08lx", (unsigned long)r_mem->start);
1297
1298 id->clk = devm_clk_get(&pdev->dev, NULL);
1299 if (IS_ERR(id->clk))
1300 return dev_err_probe(&pdev->dev, PTR_ERR(id->clk),
1301 "input clock not found.\n");
1302
1303 ret = clk_prepare_enable(id->clk);
1304 if (ret)
1305 dev_err(&pdev->dev, "Unable to enable clock.\n");
1306
1307 pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT);
1308 pm_runtime_use_autosuspend(id->dev);
1309 pm_runtime_set_active(id->dev);
1310 pm_runtime_enable(id->dev);
1311
1312 id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb;
1313 if (clk_notifier_register(id->clk, &id->clk_rate_change_nb))
1314 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1315 id->input_clk = clk_get_rate(id->clk);
1316
1317 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1318 &id->i2c_clk);
1319 if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ))
1320 id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ;
1321
1322 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1323 /* Set initial mode to master */
1324 id->dev_mode = CDNS_I2C_MODE_MASTER;
1325 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE;
1326 #endif
1327 id->ctrl_reg = CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS;
1328
1329 ret = cdns_i2c_setclk(id->input_clk, id);
1330 if (ret) {
1331 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk);
1332 ret = -EINVAL;
1333 goto err_clk_dis;
1334 }
1335
1336 ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0,
1337 DRIVER_NAME, id);
1338 if (ret) {
1339 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
1340 goto err_clk_dis;
1341 }
1342 cdns_i2c_init(id);
1343
1344 ret = i2c_add_adapter(&id->adap);
1345 if (ret < 0)
1346 goto err_clk_dis;
1347
1348 dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n",
1349 id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq);
1350
1351 return 0;
1352
1353 err_clk_dis:
1354 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
1355 clk_disable_unprepare(id->clk);
1356 pm_runtime_disable(&pdev->dev);
1357 pm_runtime_set_suspended(&pdev->dev);
1358 return ret;
1359 }
1360
1361 /**
1362 * cdns_i2c_remove - Unregister the device after releasing the resources
1363 * @pdev: Handle to the platform device structure
1364 *
1365 * This function frees all the resources allocated to the device.
1366 *
1367 * Return: 0 always
1368 */
cdns_i2c_remove(struct platform_device * pdev)1369 static int cdns_i2c_remove(struct platform_device *pdev)
1370 {
1371 struct cdns_i2c *id = platform_get_drvdata(pdev);
1372
1373 pm_runtime_disable(&pdev->dev);
1374 pm_runtime_set_suspended(&pdev->dev);
1375 pm_runtime_dont_use_autosuspend(&pdev->dev);
1376
1377 i2c_del_adapter(&id->adap);
1378 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
1379 clk_disable_unprepare(id->clk);
1380
1381 return 0;
1382 }
1383
1384 static struct platform_driver cdns_i2c_drv = {
1385 .driver = {
1386 .name = DRIVER_NAME,
1387 .of_match_table = cdns_i2c_of_match,
1388 .pm = &cdns_i2c_dev_pm_ops,
1389 },
1390 .probe = cdns_i2c_probe,
1391 .remove = cdns_i2c_remove,
1392 };
1393
1394 module_platform_driver(cdns_i2c_drv);
1395
1396 MODULE_AUTHOR("Xilinx Inc.");
1397 MODULE_DESCRIPTION("Cadence I2C bus driver");
1398 MODULE_LICENSE("GPL");
1399