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Searched refs:input_clk (Results 1 – 7 of 7) sorted by relevance

/drivers/i2c/busses/
Di2c-cadence.c204 unsigned long input_clk; member
1011 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, in cdns_i2c_calc_divs() argument
1019 temp = input_clk / (22 * fscl); in cdns_i2c_calc_divs()
1030 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); in cdns_i2c_calc_divs()
1036 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); in cdns_i2c_calc_divs()
1127 unsigned long input_clk = ndata->new_rate; in cdns_i2c_clk_notifier_cb() local
1132 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b); in cdns_i2c_clk_notifier_cb()
1146 id->input_clk = ndata->new_rate; in cdns_i2c_clk_notifier_cb()
1315 id->input_clk = clk_get_rate(id->clk); in cdns_i2c_probe()
1329 ret = cdns_i2c_setclk(id->input_clk, id); in cdns_i2c_probe()
/drivers/gpu/drm/nouveau/
Dnouveau_led.c60 u32 input_clk = 27e6; /* PDISPLAY.SOR[1].PWM is connected to the crystal */ in nouveau_led_set_brightness() local
64 div = input_clk / freq; in nouveau_led_set_brightness()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega20_hwmgr.c2958 int32_t input_clk, input_vol, i; in vega20_odn_edit_dpm_table() local
2982 input_clk = input[i + 1]; in vega20_odn_edit_dpm_table()
2990 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value || in vega20_odn_edit_dpm_table()
2991 input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) { in vega20_odn_edit_dpm_table()
2993 input_clk, in vega20_odn_edit_dpm_table()
2999 if ((input_index == 0 && od_table->GfxclkFmin != input_clk) || in vega20_odn_edit_dpm_table()
3000 (input_index == 1 && od_table->GfxclkFmax != input_clk)) in vega20_odn_edit_dpm_table()
3004 od_table->GfxclkFmin = input_clk; in vega20_odn_edit_dpm_table()
3006 od_table->GfxclkFmax = input_clk; in vega20_odn_edit_dpm_table()
3025 input_clk = input[i + 1]; in vega20_odn_edit_dpm_table()
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Dvega10_hwmgr.c5546 uint32_t input_clk; in vega10_odn_edit_dpm_table() local
5589 input_clk = input[i+1] * 100; in vega10_odn_edit_dpm_table()
5592 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { in vega10_odn_edit_dpm_table()
5593 dpm_table->dpm_levels[input_level].value = input_clk; in vega10_odn_edit_dpm_table()
5594 podn_vdd_dep_table->entries[input_level].clk = input_clk; in vega10_odn_edit_dpm_table()
Dsmu7_hwmgr.c5491 uint32_t input_clk; in smu7_odn_edit_dpm_table() local
5532 input_clk = input[i+1] * 100; in smu7_odn_edit_dpm_table()
5535 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { in smu7_odn_edit_dpm_table()
5536 podn_dpm_table_in_backend->entries[input_level].clock = input_clk; in smu7_odn_edit_dpm_table()
5537 podn_vdd_dep_in_backend->entries[input_level].clk = input_clk; in smu7_odn_edit_dpm_table()
/drivers/clk/
Dclk-si5341.c75 struct clk *input_clk[SI5341_NUM_INPUTS]; member
1412 m_den = clk_get_rate(data->input_clk[sel]) / 10; in si5341_initialize_pll()
1431 if (!data->input_clk[res]) { in si5341_clk_select_active_input()
1436 if (data->input_clk[i]) { in si5341_clk_select_active_input()
1453 err = clk_prepare_enable(data->input_clk[res]); in si5341_clk_select_active_input()
1579 data->input_clk[i] = input; in si5341_probe()
/drivers/media/i2c/
Dov5670.c2475 u32 input_clk = 0; in ov5670_probe() local
2479 device_property_read_u32(&client->dev, "clock-frequency", &input_clk); in ov5670_probe()
2480 if (input_clk != 19200000) in ov5670_probe()