Searched refs:pll_mux (Results 1 – 5 of 5) sorted by relevance
| /drivers/clk/rockchip/ |
| D | clk-pll.c | 29 struct clk_mux pll_mux; member
193 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3036_pll_set_params() local
207 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3036_pll_set_params()
209 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_set_params()
243 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
428 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3066_pll_set_params() local
440 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); in rockchip_rk3066_pll_set_params()
442 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3066_pll_set_params()
478 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3066_pll_set_params()
675 struct clk_mux *pll_mux = &pll->pll_mux; in rockchip_rk3399_pll_set_params() local
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| /drivers/clk/socfpga/ |
| D | clk-s10.c | 15 static const struct clk_parent_data pll_mux[] = { variable
186 { STRATIX10_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
188 { STRATIX10_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
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| D | clk-agilex.c | 15 static const struct clk_parent_data pll_mux[] = { variable
230 { AGILEX_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
232 { AGILEX_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
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| /drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy_10nm.c | 66 u8 pll_mux; member
500 cached->pll_mux = cmn_clk_cfg1 & 0x3; in dsi_10nm_pll_save_state()
504 cached->pix_clk_div, cached->pll_mux); in dsi_10nm_pll_save_state()
525 val |= cached->pll_mux; in dsi_10nm_pll_restore_state()
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| D | dsi_phy_7nm.c | 65 u8 pll_mux; member
514 cached->pll_mux = cmn_clk_cfg1 & 0x3; in dsi_7nm_pll_save_state()
518 cached->pix_clk_div, cached->pll_mux); in dsi_7nm_pll_save_state()
539 val |= cached->pll_mux; in dsi_7nm_pll_restore_state()
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