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Searched refs:rcg (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/qcom/
Dclk-rcg.c39 struct clk_rcg *rcg = to_clk_rcg(hw); in clk_rcg_get_parent() local
44 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_get_parent()
47 ns = ns_to_src(&rcg->s, ns); in clk_rcg_get_parent()
49 if (ns == rcg->s.parent_map[i].cfg) in clk_rcg_get_parent()
58 static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank) in reg_to_bank() argument
60 bank &= BIT(rcg->mux_sel_bit); in reg_to_bank()
66 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); in clk_dyn_rcg_get_parent() local
73 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in clk_dyn_rcg_get_parent()
76 bank = reg_to_bank(rcg, reg); in clk_dyn_rcg_get_parent()
77 s = &rcg->s[bank]; in clk_dyn_rcg_get_parent()
[all …]
Dclk-rcg2.c46 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG) argument
47 #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG) argument
48 #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG) argument
49 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG) argument
66 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_is_enabled() local
70 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); in clk_rcg2_is_enabled()
79 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in __clk_rcg2_get_parent() local
87 if (cfg == rcg->parent_map[i].cfg) in __clk_rcg2_get_parent()
97 struct clk_rcg2 *rcg = to_clk_rcg2(hw); in clk_rcg2_get_parent() local
101 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); in clk_rcg2_get_parent()
[all …]
Dclk-rcg.h161 struct clk_rcg2 rcg; member
166 container_of(to_clk_rcg2(_hw), struct clk_rcg2_gfx3d, rcg)
180 struct clk_rcg2 *rcg; member
185 { .rcg = &r, .init = &r##_init }
Dgpucc-sdm660.c107 .rcg = {
138 &gfx3d_clk_src.rcg.clkr.hw,
275 [GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,
DMakefile8 clk-qcom-y += clk-rcg.o
Dmmcc-msm8996.c566 .rcg = {
1685 &gfx3d_clk_src.rcg.clkr.hw
3355 [GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,