1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020, AngeloGioacchino Del Regno
5 * <angelogioacchino.delregno@somainline.org>
6 */
7
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/err.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <linux/regmap.h>
18 #include <linux/reset-controller.h>
19 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
20
21 #include "clk-alpha-pll.h"
22 #include "common.h"
23 #include "clk-regmap.h"
24 #include "clk-pll.h"
25 #include "clk-rcg.h"
26 #include "clk-branch.h"
27 #include "gdsc.h"
28 #include "reset.h"
29
30 enum {
31 P_GPU_XO,
32 P_GPLL0_OUT_MAIN,
33 P_GPLL0_OUT_MAIN_DIV,
34 P_GPU_PLL0_PLL_OUT_MAIN,
35 P_GPU_PLL1_PLL_OUT_MAIN,
36 };
37
38 static struct clk_branch gpucc_cxo_clk = {
39 .halt_reg = 0x1020,
40 .clkr = {
41 .enable_reg = 0x1020,
42 .enable_mask = BIT(0),
43 .hw.init = &(struct clk_init_data){
44 .name = "gpucc_cxo_clk",
45 .parent_data = &(const struct clk_parent_data){
46 .fw_name = "xo"
47 },
48 .num_parents = 1,
49 .ops = &clk_branch2_ops,
50 .flags = CLK_IS_CRITICAL,
51 },
52 },
53 };
54
55 static struct pll_vco gpu_vco[] = {
56 { 1000000000, 2000000000, 0 },
57 { 500000000, 1000000000, 2 },
58 { 250000000, 500000000, 3 },
59 };
60
61 static struct clk_alpha_pll gpu_pll0_pll_out_main = {
62 .offset = 0x0,
63 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
64 .vco_table = gpu_vco,
65 .num_vco = ARRAY_SIZE(gpu_vco),
66 .clkr.hw.init = &(struct clk_init_data){
67 .name = "gpu_pll0_pll_out_main",
68 .parent_hws = (const struct clk_hw*[]){
69 &gpucc_cxo_clk.clkr.hw,
70 },
71 .num_parents = 1,
72 .ops = &clk_alpha_pll_ops,
73 },
74 };
75
76 static struct clk_alpha_pll gpu_pll1_pll_out_main = {
77 .offset = 0x40,
78 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
79 .vco_table = gpu_vco,
80 .num_vco = ARRAY_SIZE(gpu_vco),
81 .clkr.hw.init = &(struct clk_init_data){
82 .name = "gpu_pll1_pll_out_main",
83 .parent_hws = (const struct clk_hw*[]){
84 &gpucc_cxo_clk.clkr.hw,
85 },
86 .num_parents = 1,
87 .ops = &clk_alpha_pll_ops,
88 },
89 };
90
91 static const struct parent_map gpucc_parent_map_1[] = {
92 { P_GPU_XO, 0 },
93 { P_GPU_PLL0_PLL_OUT_MAIN, 1 },
94 { P_GPU_PLL1_PLL_OUT_MAIN, 3 },
95 { P_GPLL0_OUT_MAIN, 5 },
96 };
97
98 static const struct clk_parent_data gpucc_parent_data_1[] = {
99 { .hw = &gpucc_cxo_clk.clkr.hw },
100 { .hw = &gpu_pll0_pll_out_main.clkr.hw },
101 { .hw = &gpu_pll1_pll_out_main.clkr.hw },
102 { .fw_name = "gcc_gpu_gpll0_clk" },
103 };
104
105 static struct clk_rcg2_gfx3d gfx3d_clk_src = {
106 .div = 2,
107 .rcg = {
108 .cmd_rcgr = 0x1070,
109 .mnd_width = 0,
110 .hid_width = 5,
111 .parent_map = gpucc_parent_map_1,
112 .clkr.hw.init = &(struct clk_init_data){
113 .name = "gfx3d_clk_src",
114 .parent_data = gpucc_parent_data_1,
115 .num_parents = ARRAY_SIZE(gpucc_parent_data_1),
116 .ops = &clk_gfx3d_ops,
117 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
118 },
119 },
120 .hws = (struct clk_hw*[]){
121 &gpucc_cxo_clk.clkr.hw,
122 &gpu_pll0_pll_out_main.clkr.hw,
123 &gpu_pll1_pll_out_main.clkr.hw,
124 }
125 };
126
127 static struct clk_branch gpucc_gfx3d_clk = {
128 .halt_reg = 0x1098,
129 .halt_check = BRANCH_HALT,
130 .hwcg_reg = 0x1098,
131 .hwcg_bit = 1,
132 .clkr = {
133 .enable_reg = 0x1098,
134 .enable_mask = BIT(0),
135 .hw.init = &(struct clk_init_data){
136 .name = "gpucc_gfx3d_clk",
137 .parent_hws = (const struct clk_hw*[]){
138 &gfx3d_clk_src.rcg.clkr.hw,
139 },
140 .num_parents = 1,
141 .ops = &clk_branch2_ops,
142 .flags = CLK_SET_RATE_PARENT,
143 },
144 },
145 };
146
147 static const struct parent_map gpucc_parent_map_0[] = {
148 { P_GPU_XO, 0 },
149 { P_GPLL0_OUT_MAIN, 5 },
150 { P_GPLL0_OUT_MAIN_DIV, 6 },
151 };
152
153 static const struct clk_parent_data gpucc_parent_data_0[] = {
154 { .hw = &gpucc_cxo_clk.clkr.hw },
155 { .fw_name = "gcc_gpu_gpll0_clk" },
156 { .fw_name = "gcc_gpu_gpll0_div_clk" },
157 };
158
159 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
160 F(19200000, P_GPU_XO, 1, 0, 0),
161 { }
162 };
163
164 static struct clk_rcg2 rbbmtimer_clk_src = {
165 .cmd_rcgr = 0x10b0,
166 .mnd_width = 0,
167 .hid_width = 5,
168 .parent_map = gpucc_parent_map_0,
169 .freq_tbl = ftbl_rbbmtimer_clk_src,
170 .clkr.hw.init = &(struct clk_init_data){
171 .name = "rbbmtimer_clk_src",
172 .parent_data = gpucc_parent_data_0,
173 .num_parents = ARRAY_SIZE(gpucc_parent_data_0),
174 .ops = &clk_rcg2_ops,
175 },
176 };
177
178 static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
179 F(19200000, P_GPU_XO, 1, 0, 0),
180 F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0),
181 { }
182 };
183
184 static struct clk_rcg2 rbcpr_clk_src = {
185 .cmd_rcgr = 0x1030,
186 .mnd_width = 0,
187 .hid_width = 5,
188 .parent_map = gpucc_parent_map_0,
189 .freq_tbl = ftbl_rbcpr_clk_src,
190 .clkr.hw.init = &(struct clk_init_data){
191 .name = "rbcpr_clk_src",
192 .parent_data = gpucc_parent_data_0,
193 .num_parents = ARRAY_SIZE(gpucc_parent_data_0),
194 .ops = &clk_rcg2_ops,
195 },
196 };
197
198 static struct clk_branch gpucc_rbbmtimer_clk = {
199 .halt_reg = 0x10d0,
200 .halt_check = BRANCH_HALT,
201 .clkr = {
202 .enable_reg = 0x10d0,
203 .enable_mask = BIT(0),
204 .hw.init = &(struct clk_init_data){
205 .name = "gpucc_rbbmtimer_clk",
206 .parent_hws = (const struct clk_hw*[]){
207 &rbbmtimer_clk_src.clkr.hw,
208 },
209 .num_parents = 1,
210 .flags = CLK_SET_RATE_PARENT,
211 .ops = &clk_branch2_ops,
212 },
213 },
214 };
215
216 static struct clk_branch gpucc_rbcpr_clk = {
217 .halt_reg = 0x1054,
218 .halt_check = BRANCH_HALT,
219 .clkr = {
220 .enable_reg = 0x1054,
221 .enable_mask = BIT(0),
222 .hw.init = &(struct clk_init_data){
223 .name = "gpucc_rbcpr_clk",
224 .parent_hws = (const struct clk_hw*[]){
225 &rbcpr_clk_src.clkr.hw,
226 },
227 .num_parents = 1,
228 .flags = CLK_SET_RATE_PARENT,
229 .ops = &clk_branch2_ops,
230 },
231 },
232 };
233
234 static struct gdsc gpu_cx_gdsc = {
235 .gdscr = 0x1004,
236 .gds_hw_ctrl = 0x1008,
237 .pd = {
238 .name = "gpu_cx",
239 },
240 .pwrsts = PWRSTS_OFF_ON,
241 .flags = VOTABLE,
242 };
243
244 static struct gdsc gpu_gx_gdsc = {
245 .gdscr = 0x1094,
246 .clamp_io_ctrl = 0x130,
247 .resets = (unsigned int []){ GPU_GX_BCR },
248 .reset_count = 1,
249 .cxcs = (unsigned int []){ 0x1098 },
250 .cxc_count = 1,
251 .pd = {
252 .name = "gpu_gx",
253 },
254 .parent = &gpu_cx_gdsc.pd,
255 .pwrsts = PWRSTS_OFF | PWRSTS_ON | PWRSTS_RET,
256 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
257 };
258
259 static struct gdsc *gpucc_sdm660_gdscs[] = {
260 [GPU_CX_GDSC] = &gpu_cx_gdsc,
261 [GPU_GX_GDSC] = &gpu_gx_gdsc,
262 };
263
264 static const struct qcom_reset_map gpucc_sdm660_resets[] = {
265 [GPU_CX_BCR] = { 0x1000 },
266 [RBCPR_BCR] = { 0x1050 },
267 [GPU_GX_BCR] = { 0x1090 },
268 [SPDM_BCR] = { 0x10E0 },
269 };
270
271 static struct clk_regmap *gpucc_sdm660_clocks[] = {
272 [GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr,
273 [GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr,
274 [GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr,
275 [GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,
276 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
277 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
278 [GPUCC_RBCPR_CLK] = &gpucc_rbcpr_clk.clkr,
279 [GPUCC_GFX3D_CLK] = &gpucc_gfx3d_clk.clkr,
280 [GPUCC_RBBMTIMER_CLK] = &gpucc_rbbmtimer_clk.clkr,
281 };
282
283 static const struct regmap_config gpucc_660_regmap_config = {
284 .reg_bits = 32,
285 .reg_stride = 4,
286 .val_bits = 32,
287 .max_register = 0x9034,
288 .fast_io = true,
289 };
290
291 static const struct qcom_cc_desc gpucc_sdm660_desc = {
292 .config = &gpucc_660_regmap_config,
293 .clks = gpucc_sdm660_clocks,
294 .num_clks = ARRAY_SIZE(gpucc_sdm660_clocks),
295 .resets = gpucc_sdm660_resets,
296 .num_resets = ARRAY_SIZE(gpucc_sdm660_resets),
297 .gdscs = gpucc_sdm660_gdscs,
298 .num_gdscs = ARRAY_SIZE(gpucc_sdm660_gdscs),
299 };
300
301 static const struct of_device_id gpucc_sdm660_match_table[] = {
302 { .compatible = "qcom,gpucc-sdm660" },
303 { .compatible = "qcom,gpucc-sdm630" },
304 { }
305 };
306 MODULE_DEVICE_TABLE(of, gpucc_sdm660_match_table);
307
gpucc_sdm660_probe(struct platform_device * pdev)308 static int gpucc_sdm660_probe(struct platform_device *pdev)
309 {
310 struct regmap *regmap;
311 struct alpha_pll_config gpu_pll_config = {
312 .config_ctl_val = 0x4001055b,
313 .alpha = 0xaaaaab00,
314 .alpha_en_mask = BIT(24),
315 .vco_val = 0x2 << 20,
316 .vco_mask = 0x3 << 20,
317 .main_output_mask = 0x1,
318 };
319
320 regmap = qcom_cc_map(pdev, &gpucc_sdm660_desc);
321 if (IS_ERR(regmap))
322 return PTR_ERR(regmap);
323
324 /* 800MHz configuration for GPU PLL0 */
325 gpu_pll_config.l = 0x29;
326 gpu_pll_config.alpha_hi = 0xaa;
327 clk_alpha_pll_configure(&gpu_pll0_pll_out_main, regmap, &gpu_pll_config);
328
329 /* 740MHz configuration for GPU PLL1 */
330 gpu_pll_config.l = 0x26;
331 gpu_pll_config.alpha_hi = 0x8a;
332 clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap, &gpu_pll_config);
333
334 return qcom_cc_really_probe(pdev, &gpucc_sdm660_desc, regmap);
335 }
336
337 static struct platform_driver gpucc_sdm660_driver = {
338 .probe = gpucc_sdm660_probe,
339 .driver = {
340 .name = "gpucc-sdm660",
341 .of_match_table = gpucc_sdm660_match_table,
342 },
343 };
344 module_platform_driver(gpucc_sdm660_driver);
345
346 MODULE_DESCRIPTION("Qualcomm SDM630/SDM660 GPUCC Driver");
347 MODULE_LICENSE("GPL v2");
348