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Searched refs:reg_base (Results 1 – 25 of 341) sorted by relevance

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/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_reg.c31 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
33 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
47 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
61 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); in analogix_dp_lane_swap()
69 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); in analogix_dp_init_analog_param()
72 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); in analogix_dp_init_analog_param()
79 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); in analogix_dp_init_analog_param()
[all …]
/drivers/gpio/
Dgpio-bcm-kona.c59 void __iomem *reg_base; member
75 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base, in bcm_kona_gpio_write_lock_regs() argument
78 writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET); in bcm_kona_gpio_write_lock_regs()
79 writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_write_lock_regs()
91 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_lock_gpio()
93 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_lock_gpio()
107 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_unlock_gpio()
109 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_unlock_gpio()
117 void __iomem *reg_base = kona_gpio->reg_base; in bcm_kona_gpio_get_dir() local
120 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK; in bcm_kona_gpio_get_dir()
[all …]
Dgpio-amdpt.c28 void __iomem *reg_base; member
41 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_request()
49 writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_request()
64 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free()
66 writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG); in pt_gpio_free()
88 pt_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0); in pt_gpio_probe()
89 if (IS_ERR(pt_gpio->reg_base)) { in pt_gpio_probe()
91 return PTR_ERR(pt_gpio->reg_base); in pt_gpio_probe()
95 pt_gpio->reg_base + PT_INPUTDATA_REG, in pt_gpio_probe()
96 pt_gpio->reg_base + PT_OUTPUTDATA_REG, NULL, in pt_gpio_probe()
[all …]
Dgpio-menz127.c34 void __iomem *reg_base; member
69 db_en = readl(priv->reg_base + MEN_Z127_DBER); in men_z127_debounce()
79 writel(db_en, priv->reg_base + MEN_Z127_DBER); in men_z127_debounce()
80 writel(db_cnt, priv->reg_base + GPIO_TO_DBCNT_REG(gpio)); in men_z127_debounce()
95 od_en = readl(priv->reg_base + MEN_Z127_ODER); in men_z127_set_single_ended()
103 writel(od_en, priv->reg_base + MEN_Z127_ODER); in men_z127_set_single_ended()
148 men_z127_gpio->reg_base = ioremap(men_z127_gpio->mem->start, in men_z127_probe()
150 if (men_z127_gpio->reg_base == NULL) { in men_z127_probe()
158 men_z127_gpio->reg_base + MEN_Z127_PSR, in men_z127_probe()
159 men_z127_gpio->reg_base + MEN_Z127_CTRL, in men_z127_probe()
[all …]
/drivers/spi/
Dspi-gxp.c44 void __iomem *reg_base; member
54 void __iomem *reg_base = spifi->reg_base; in gxp_spi_set_mode() local
56 value = readb(reg_base + OFFSET_SPIMCTRL); in gxp_spi_set_mode()
59 writeb(0x55, reg_base + OFFSET_SPICMD); in gxp_spi_set_mode()
60 writeb(0xaa, reg_base + OFFSET_SPICMD); in gxp_spi_set_mode()
65 writeb(value, reg_base + OFFSET_SPIMCTRL); in gxp_spi_set_mode()
72 void __iomem *reg_base = spifi->reg_base; in gxp_spi_read_reg() local
75 value = readl(reg_base + OFFSET_SPIMCFG); in gxp_spi_read_reg()
80 writel(value, reg_base + OFFSET_SPIMCFG); in gxp_spi_read_reg()
82 writel(0, reg_base + OFFSET_SPIADDR); in gxp_spi_read_reg()
[all …]
Dspi-fsl-spi.c93 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_change_mode() local
94 __be32 __iomem *mode = &reg_base->mode; in fsl_spi_change_mode()
246 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs() local
251 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE); in fsl_spi_cpu_bufs()
255 mpc8xxx_spi_write_reg(&reg_base->transmit, word); in fsl_spi_cpu_bufs()
264 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_bufs() local
269 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs()
302 mpc8xxx_spi_write_reg(&reg_base->mask, 0); in fsl_spi_bufs()
388 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_setup() local
406 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup()
[all …]
Dspi-cadence-quadspi.c409 void __iomem *reg_base = cqspi->iobase; in cqspi_exec_flash_cmd() local
413 writel(reg, reg_base + CQSPI_REG_CMDCTRL); in cqspi_exec_flash_cmd()
416 writel(reg, reg_base + CQSPI_REG_CMDCTRL); in cqspi_exec_flash_cmd()
419 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, in cqspi_exec_flash_cmd()
436 void __iomem *reg_base = cqspi->iobase; in cqspi_setup_opcode_ext() local
446 reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER); in cqspi_setup_opcode_ext()
449 writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER); in cqspi_setup_opcode_ext()
458 void __iomem *reg_base = cqspi->iobase; in cqspi_enable_dtr() local
462 reg = readl(reg_base + CQSPI_REG_CONFIG); in cqspi_enable_dtr()
481 writel(reg, reg_base + CQSPI_REG_CONFIG); in cqspi_enable_dtr()
[all …]
/drivers/irqchip/
Dirq-csky-apb-intc.c34 static void __iomem *reg_base; variable
60 static void __init ck_set_gc(struct device_node *node, void __iomem *reg_base, in ck_set_gc() argument
66 gc->reg_base = reg_base; in ck_set_gc()
111 reg_base = of_iomap(node, 0); in ck_intc_init_comm()
112 if (!reg_base) { in ck_intc_init_comm()
153 readl(reg_base + GX_INTC_PEN63_32), 32); in gx_irq_handler()
158 readl(reg_base + GX_INTC_PEN31_00), 0); in gx_irq_handler()
175 writel(0x0, reg_base + GX_INTC_NEN31_00); in gx_intc_init()
176 writel(0x0, reg_base + GX_INTC_NEN63_32); in gx_intc_init()
181 writel(0x0, reg_base + GX_INTC_NMASK31_00); in gx_intc_init()
[all …]
Dirq-digicolor.c57 static void __init digicolor_set_gc(void __iomem *reg_base, unsigned irq_base, in digicolor_set_gc() argument
63 gc->reg_base = reg_base; in digicolor_set_gc()
74 void __iomem *reg_base; in digicolor_of_init() local
79 reg_base = of_iomap(node, 0); in digicolor_of_init()
80 if (!reg_base) { in digicolor_of_init()
86 writel(0, reg_base + IC_INT0ENABLE_LO); in digicolor_of_init()
87 writel(0, reg_base + IC_INT0ENABLE_XLO); in digicolor_of_init()
112 digicolor_set_gc(reg_base, 0, IC_INT0ENABLE_LO, IC_FLAG_CLEAR_LO); in digicolor_of_init()
113 digicolor_set_gc(reg_base, 32, IC_INT0ENABLE_XLO, IC_FLAG_CLEAR_XLO); in digicolor_of_init()
/drivers/net/ethernet/cavium/thunder/
Dthunder_xcv.c47 void __iomem *reg_base; member
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
84 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
87 writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
92 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
94 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
95 readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
[all …]
/drivers/ata/
Dahci_qoriq.c63 struct ccsr_ahci *reg_base; member
169 void __iomem *reg_base = hpriv->mmio; in ahci_qoriq_phy_init() local
177 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); in ahci_qoriq_phy_init()
178 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2); in ahci_qoriq_phy_init()
179 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); in ahci_qoriq_phy_init()
180 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4); in ahci_qoriq_phy_init()
181 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5); in ahci_qoriq_phy_init()
182 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); in ahci_qoriq_phy_init()
185 reg_base + LS1021A_AXICC_ADDR); in ahci_qoriq_phy_init()
195 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); in ahci_qoriq_phy_init()
[all …]
Dahci_sunxi.c86 static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) in ahci_sunxi_phy_init() argument
92 writel(0, reg_base + AHCI_RWCR); in ahci_sunxi_phy_init()
95 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init()
96 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, in ahci_sunxi_phy_init()
99 sunxi_clrsetbits(reg_base + AHCI_PHYCS1R, in ahci_sunxi_phy_init()
102 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); in ahci_sunxi_phy_init()
103 sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); in ahci_sunxi_phy_init()
104 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, in ahci_sunxi_phy_init()
106 sunxi_clrsetbits(reg_base + AHCI_PHYCS2R, in ahci_sunxi_phy_init()
110 sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19)); in ahci_sunxi_phy_init()
[all …]
/drivers/misc/mchp_pci1xxxx/
Dmchp_pci1xxxx_gpio.c39 void __iomem *reg_base; member
51 data = readl(priv->reg_base + INP_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
55 data = readl(priv->reg_base + OUT_EN_OFFSET(nr)); in pci1xxxx_gpio_get_direction()
82 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), true); in pci1xxxx_gpio_direction_input()
83 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), false); in pci1xxxx_gpio_direction_input()
93 return (readl(priv->reg_base + INP_OFFSET(nr)) >> (nr % 32)) & 1; in pci1xxxx_gpio_get()
104 pci1xxx_assign_bit(priv->reg_base, INP_EN_OFFSET(nr), (nr % 32), false); in pci1xxxx_gpio_direction_output()
105 pci1xxx_assign_bit(priv->reg_base, OUT_EN_OFFSET(nr), (nr % 32), true); in pci1xxxx_gpio_direction_output()
106 data = readl(priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output()
111 writel(data, priv->reg_base + OUT_OFFSET(nr)); in pci1xxxx_gpio_direction_output()
[all …]
/drivers/remoteproc/
Dqcom_q6v5_wcss.c110 void __iomem *reg_base; member
161 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
163 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
166 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
168 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
171 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_reset()
180 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
182 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
187 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
190 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
[all …]
Dmtk_scp.c155 val = readl(scp->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_assert()
157 writel(val, scp->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_assert()
164 val = readl(scp->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_deassert()
166 writel(val, scp->reg_base + MT8183_SW_RSTN); in mt8183_scp_reset_deassert()
171 writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET); in mt8192_scp_reset_assert()
176 writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR); in mt8192_scp_reset_deassert()
183 scp_to_host = readl(scp->reg_base + MT8183_SCP_TO_HOST); in mt8183_scp_irq_handler()
191 scp->reg_base + MT8183_SCP_TO_HOST); in mt8183_scp_irq_handler()
198 scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET); in mt8192_scp_irq_handler()
208 scp->reg_base + MT8192_SCP2APMCU_IPC_CLR); in mt8192_scp_irq_handler()
[all …]
/drivers/video/fbdev/mmp/hw/
Dmmp_spi.c34 void __iomem *reg_base = (void __iomem *) in lcd_spi_write() local
38 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); in lcd_spi_write()
42 writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
45 writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
48 writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
55 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
58 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
60 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
63 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
71 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
[all …]
/drivers/net/can/
Dkvaser_pciefd.c265 void __iomem *reg_base; member
278 void __iomem *reg_base; member
338 return readl_poll_timeout(pcie->reg_base + KVASER_PCIEFD_SPI_STATUS_REG, in kvaser_pciefd_spi_wait_loop()
347 iowrite32(BIT(0), pcie->reg_base + KVASER_PCIEFD_SPI_SSEL_REG); in kvaser_pciefd_spi_cmd()
348 iowrite32(BIT(10), pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG); in kvaser_pciefd_spi_cmd()
349 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); in kvaser_pciefd_spi_cmd()
356 iowrite32(*tx++, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG); in kvaser_pciefd_spi_cmd()
361 ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); in kvaser_pciefd_spi_cmd()
369 iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG); in kvaser_pciefd_spi_cmd()
374 *rx++ = ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG); in kvaser_pciefd_spi_cmd()
[all …]
/drivers/clk/samsung/
Dclk-s5pv210-audss.c24 static void __iomem *reg_base; variable
43 reg_save[i][1] = readl(reg_base + reg_save[i][0]); in s5pv210_audss_clk_suspend()
53 writel(reg_save[i][1], reg_base + reg_save[i][0]); in s5pv210_audss_clk_resume()
72 reg_base = devm_platform_ioremap_resource(pdev, 0); in s5pv210_audss_clk_probe()
73 if (IS_ERR(reg_base)) in s5pv210_audss_clk_probe()
74 return PTR_ERR(reg_base); in s5pv210_audss_clk_probe()
116 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in s5pv210_audss_clk_probe()
127 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in s5pv210_audss_clk_probe()
131 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); in s5pv210_audss_clk_probe()
134 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); in s5pv210_audss_clk_probe()
[all …]
Dclk-exynos-audss.c22 static void __iomem *reg_base; variable
47 reg_save[i][1] = readl(reg_base + reg_save[i][0]); in exynos_audss_clk_suspend()
57 writel(reg_save[i][1], reg_base + reg_save[i][0]); in exynos_audss_clk_resume()
139 reg_base = devm_platform_ioremap_resource(pdev, 0); in exynos_audss_clk_probe()
140 if (IS_ERR(reg_base)) in exynos_audss_clk_probe()
141 return PTR_ERR(reg_base); in exynos_audss_clk_probe()
187 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); in exynos_audss_clk_probe()
198 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); in exynos_audss_clk_probe()
202 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); in exynos_audss_clk_probe()
206 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); in exynos_audss_clk_probe()
[all …]
/drivers/rtc/
Drtc-zynqmp.c52 void __iomem *reg_base; member
71 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); in xlnx_rtc_set_time()
81 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_set_time()
92 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_read_time()
99 read_time = readl(xrtcdev->reg_base + RTC_CUR_TM); in xlnx_rtc_read_time()
108 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1; in xlnx_rtc_read_time()
119 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time); in xlnx_rtc_read_alarm()
120 alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM; in xlnx_rtc_read_alarm()
135 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_alarm_irq_enable()
143 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_alarm_irq_enable()
[all …]
/drivers/input/serio/
Dsun4i-ps2.c85 void __iomem *reg_base; member
107 intr_status = readl(drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
108 fifo_status = readl(drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
118 writel(rval, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
125 writel(rval, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
130 byte = readl(drvdata->reg_base + PS2_REG_DATA) & 0xff; in sun4i_ps2_interrupt()
134 writel(intr_status, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt()
135 writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt()
154 writel(rval, drvdata->reg_base + PS2_REG_LCTL); in sun4i_ps2_open()
161 writel(rval, drvdata->reg_base + PS2_REG_FCTL); in sun4i_ps2_open()
[all …]
/drivers/crypto/marvell/octeontx2/
Dotx2_cptpf_main.c22 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
24 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
29 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
36 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vfpf_mbox_intr()
48 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr()
50 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr()
53 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr()
60 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_disable_vfpf_mbox_intr()
71 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_VFFLR_INTX(0), in cptpf_enable_vf_flr_me_intrs()
75 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, in cptpf_enable_vf_flr_me_intrs()
[all …]
/drivers/net/ethernet/marvell/octeontx2/af/
Dptp.c102 ptp_clock_hi = readq(ptp->reg_base + PTP_CLOCK_HI); in ptp_reset_thresh()
106 writeq(500000000, ptp->reg_base + PTP_PPS_THRESH_HI); in ptp_reset_thresh()
131 sec = readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL; in read_ptp_tstmp_sec_nsec()
132 nsec = readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_sec_nsec()
133 sec1 = readq(ptp->reg_base + PTP_CLOCK_SEC) & 0xFFFFFFFFUL; in read_ptp_tstmp_sec_nsec()
136 nsec = readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_sec_nsec()
146 return readq(ptp->reg_base + PTP_CLOCK_HI); in read_ptp_tstmp_nsec()
267 writeq(comp, ptp->reg_base + PTP_CLOCK_COMP); in ptp_adjfine()
301 writeq(0x3b9aca00, ptp->reg_base + PTP_SEC_ROLLOVER); in ptp_start()
304 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG); in ptp_start()
[all …]
/drivers/input/keyboard/
Dnspire-keypad.c32 void __iomem *reg_base; member
61 int_sts = readl(keypad->reg_base + KEYPAD_INT) & keypad->int_mask; in nspire_keypad_irq()
65 memcpy_fromio(state, keypad->reg_base + KEYPAD_DATA, sizeof(state)); in nspire_keypad_irq()
91 writel(0x3, keypad->reg_base + KEYPAD_INT); in nspire_keypad_irq()
121 writel(val, keypad->reg_base + KEYPAD_SCAN_MODE); in nspire_keypad_open()
124 writel(val, keypad->reg_base + KEYPAD_CNTL); in nspire_keypad_open()
128 writel(keypad->int_mask, keypad->reg_base + KEYPAD_INTMSK); in nspire_keypad_open()
138 writel(0, keypad->reg_base + KEYPAD_INTMSK); in nspire_keypad_close()
140 writel(~0, keypad->reg_base + KEYPAD_INT); in nspire_keypad_close()
190 keypad->reg_base = devm_ioremap_resource(&pdev->dev, res); in nspire_keypad_probe()
[all …]
/drivers/fpga/
Daltera-pr-ip-core.c29 void __iomem *reg_base; member
39 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_state()
90 val = readl(priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init()
99 writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST); in alt_pr_fpga_write_init()
116 writel(buffer_32[i++], priv->reg_base); in alt_pr_fpga_write()
123 writel(buffer_32[i++] & 0x00ffffff, priv->reg_base); in alt_pr_fpga_write()
126 writel(buffer_32[i++] & 0x0000ffff, priv->reg_base); in alt_pr_fpga_write()
129 writel(buffer_32[i++] & 0x000000ff, priv->reg_base); in alt_pr_fpga_write()
176 int alt_pr_register(struct device *dev, void __iomem *reg_base) in alt_pr_register() argument
186 priv->reg_base = reg_base; in alt_pr_register()
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