| /drivers/bus/ |
| D | omap_l3_smx.h | 29 static const u64 shift = 1; variable
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
32 #define L3_STATUS_0_MPUIA_RSP (shift << 1)
33 #define L3_STATUS_0_MPUIA_INBAND (shift << 2)
34 #define L3_STATUS_0_IVAIA_BRST (shift << 6)
35 #define L3_STATUS_0_IVAIA_RSP (shift << 7)
36 #define L3_STATUS_0_IVAIA_INBAND (shift << 8)
37 #define L3_STATUS_0_SGXIA_BRST (shift << 9)
38 #define L3_STATUS_0_SGXIA_RSP (shift << 10)
39 #define L3_STATUS_0_SGXIA_MERROR (shift << 11)
[all …]
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| D | da8xx-mstpri.c | 55 int shift; member
62 .shift = 0,
67 .shift = 4,
72 .shift = 16,
77 .shift = 20,
82 .shift = 0,
87 .shift = 4,
92 .shift = 8,
97 .shift = 12,
102 .shift = 16,
[all …]
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| /drivers/clk/imx/ |
| D | clk.h | 112 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ argument
113 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
121 #define imx_clk_divider(name, parent, reg, shift, width) \ argument
122 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
124 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \ argument
125 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
127 #define imx_clk_gate(name, parent, reg, shift) \ argument
128 to_clk(imx_clk_hw_gate(name, parent, reg, shift))
130 #define imx_clk_gate_dis(name, parent, reg, shift) \ argument
131 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
[all …]
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| /drivers/memory/tegra/ |
| D | tegra114.c | 21 .shift = 0,
37 .shift = 0,
53 .shift = 0,
69 .shift = 16,
85 .shift = 16,
101 .shift = 0,
117 .shift = 0,
133 .shift = 0,
149 .shift = 0,
165 .shift = 16,
[all …]
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| D | tegra210.c | 26 .shift = 0,
42 .shift = 0,
58 .shift = 16,
74 .shift = 16,
90 .shift = 0,
106 .shift = 0,
122 .shift = 0,
138 .shift = 0,
154 .shift = 0,
170 .shift = 0,
[all …]
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| D | tegra124.c | 22 .shift = 0,
38 .shift = 0,
54 .shift = 0,
70 .shift = 16,
86 .shift = 16,
102 .shift = 0,
118 .shift = 0,
134 .shift = 0,
150 .shift = 0,
166 .shift = 0,
[all …]
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| D | tegra30.c | 43 .shift = 0,
60 .shift = 0,
77 .shift = 0,
94 .shift = 16,
111 .shift = 16,
128 .shift = 0,
145 .shift = 0,
162 .shift = 16,
179 .shift = 16,
196 .shift = 0,
[all …]
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| /drivers/mfd/ |
| D | atmel-smc.c | 94 unsigned int shift, unsigned int ncycles) in atmel_smc_cs_conf_set_timing() argument
99 if (shift != ATMEL_HSMC_TIMINGS_TCLR_SHIFT && in atmel_smc_cs_conf_set_timing()
100 shift != ATMEL_HSMC_TIMINGS_TADL_SHIFT && in atmel_smc_cs_conf_set_timing()
101 shift != ATMEL_HSMC_TIMINGS_TAR_SHIFT && in atmel_smc_cs_conf_set_timing()
102 shift != ATMEL_HSMC_TIMINGS_TRR_SHIFT && in atmel_smc_cs_conf_set_timing()
103 shift != ATMEL_HSMC_TIMINGS_TWB_SHIFT) in atmel_smc_cs_conf_set_timing()
113 conf->timings &= ~GENMASK(shift + 3, shift); in atmel_smc_cs_conf_set_timing()
114 conf->timings |= val << shift; in atmel_smc_cs_conf_set_timing()
136 unsigned int shift, unsigned int ncycles) in atmel_smc_cs_conf_set_setup() argument
141 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT && in atmel_smc_cs_conf_set_setup()
[all …]
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| D | tmio_core.c | 29 int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base) in tmio_core_mmc_enable() argument
32 sd_config_write16(cnf, shift, CNF_CMD, SDCREN); in tmio_core_mmc_enable()
33 sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe); in tmio_core_mmc_enable()
36 sd_config_write8(cnf, shift, CNF_PWR_CTL_3, 0x01); in tmio_core_mmc_enable()
39 sd_config_write8(cnf, shift, CNF_STOP_CLK_CTL, 0x1f); in tmio_core_mmc_enable()
42 sd_config_write8(cnf, shift, CNF_PWR_CTL_2, 0x00); in tmio_core_mmc_enable()
48 int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base) in tmio_core_mmc_resume() argument
52 sd_config_write16(cnf, shift, CNF_CMD, SDCREN); in tmio_core_mmc_resume()
53 sd_config_write32(cnf, shift, CNF_CTL_BASE, base & 0xfffe); in tmio_core_mmc_resume()
59 void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state) in tmio_core_mmc_pwr() argument
[all …]
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| /drivers/clk/meson/ |
| D | parm.h | 14 #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) argument
15 #define CLRPMASK(width, shift) (~SETPMASK(width, shift)) argument
17 #define PARM_GET(width, shift, reg) \ argument
18 (((reg) & SETPMASK(width, shift)) >> (shift))
19 #define PARM_SET(width, shift, reg, val) \ argument
20 (((reg) & CLRPMASK(width, shift)) | ((val) << (shift)))
26 u8 shift; member
35 return PARM_GET(p->width, p->shift, val); in meson_parm_read()
41 regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift), in meson_parm_write()
42 val << p->shift); in meson_parm_write()
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| D | axg.c | 30 .shift = 30,
35 .shift = 0,
40 .shift = 9,
45 .shift = 0,
50 .shift = 31,
55 .shift = 29,
72 .shift = 16,
94 .shift = 30,
99 .shift = 0,
104 .shift = 9,
[all …]
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| /drivers/mtd/maps/ |
| D | physmap-bt1-rom.c | 34 unsigned int shift; in bt1_rom_map_read() local
39 shift = (uintptr_t)src & 0x3; in bt1_rom_map_read()
40 data = readl_relaxed(src - shift); in bt1_rom_map_read()
41 if (!shift) { in bt1_rom_map_read()
45 ret.x[0] = data >> (shift * BITS_PER_BYTE); in bt1_rom_map_read()
48 shift = 4 - shift; in bt1_rom_map_read()
49 if (ofs + shift >= map->size) in bt1_rom_map_read()
52 data = readl_relaxed(src + shift); in bt1_rom_map_read()
53 ret.x[0] |= data << (shift * BITS_PER_BYTE); in bt1_rom_map_read()
63 unsigned int shift, chunk; in bt1_rom_map_copy_from() local
[all …]
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| /drivers/video/fbdev/core/ |
| D | sysimgblt.c | 57 u32 color = 0, val, shift; in color_imageblit() local
67 shift = 0; in color_imageblit()
74 shift = start_index; in color_imageblit()
83 val |= FB_SHIFT_HIGH(p, color, shift); in color_imageblit()
84 if (shift >= null_bits) { in color_imageblit()
87 val = (shift == null_bits) ? 0 : in color_imageblit()
88 FB_SHIFT_LOW(p, color, 32 - shift); in color_imageblit()
90 shift += bpp; in color_imageblit()
91 shift &= (32 - 1); in color_imageblit()
94 if (shift) { in color_imageblit()
[all …]
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| D | cfbimgblt.c | 82 u32 color = 0, val, shift; in color_imageblit() local
93 shift = 0; in color_imageblit()
100 shift = start_index; in color_imageblit()
109 val |= FB_SHIFT_HIGH(p, color, shift ^ bswapmask); in color_imageblit()
110 if (shift >= null_bits) { in color_imageblit()
113 val = (shift == null_bits) ? 0 : in color_imageblit()
114 FB_SHIFT_LOW(p, color, 32 - shift); in color_imageblit()
116 shift += bpp; in color_imageblit()
117 shift &= (32 - 1); in color_imageblit()
120 if (shift) { in color_imageblit()
[all …]
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| /drivers/soc/fsl/qe/ |
| D | ucc.c | 89 unsigned int *reg_num, unsigned int *shift) in get_cmxucr_reg() argument
95 *shift = 16 - 8 * (ucc_num & 2); in get_cmxucr_reg()
102 unsigned int shift; in ucc_mux_set_grant_tsa_bkpt() local
108 get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift); in ucc_mux_set_grant_tsa_bkpt()
111 qe_setbits_be32(cmxucr, mask << shift); in ucc_mux_set_grant_tsa_bkpt()
113 qe_clrbits_be32(cmxucr, mask << shift); in ucc_mux_set_grant_tsa_bkpt()
123 unsigned int shift; in ucc_set_qe_mux_rxtx() local
134 get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift); in ucc_set_qe_mux_rxtx()
207 shift += 4; in ucc_set_qe_mux_rxtx()
209 qe_clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift, in ucc_set_qe_mux_rxtx()
[all …]
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| /drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/ |
| D | phy_qmath.c | 98 s32 qm_shl32(s32 op, int shift) in qm_shl32() argument
103 if (shift > 31) in qm_shl32()
104 shift = 31; in qm_shl32()
105 else if (shift < -31) in qm_shl32()
106 shift = -31; in qm_shl32()
107 if (shift >= 0) { in qm_shl32()
108 for (i = 0; i < shift; i++) in qm_shl32()
111 result = result >> (-shift); in qm_shl32()
123 s16 qm_shl16(s16 op, int shift) in qm_shl16() argument
128 if (shift > 15) in qm_shl16()
[all …]
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| /drivers/md/persistent-data/ |
| D | dm-btree-remove.c | 59 static void node_shift(struct btree_node *n, int shift) in node_shift() argument
64 if (shift < 0) { in node_shift()
65 shift = -shift; in node_shift()
66 BUG_ON(shift > nr_entries); in node_shift()
67 BUG_ON((void *) key_ptr(n, shift) >= value_ptr(n, shift)); in node_shift()
69 key_ptr(n, shift), in node_shift()
70 (nr_entries - shift) * sizeof(__le64)); in node_shift()
72 value_ptr(n, shift), in node_shift()
73 (nr_entries - shift) * value_size); in node_shift()
75 BUG_ON(nr_entries + shift > le32_to_cpu(n->header.max_entries)); in node_shift()
[all …]
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| /drivers/clk/at91/ |
| D | clk-peripheral.c | 138 int shift = 0; in clk_sam9x5_peripheral_autodiv() local
149 for (; shift < PERIPHERAL_MAX_SHIFT; shift++) { in clk_sam9x5_peripheral_autodiv()
150 if (parent_rate >> shift <= periph->range.max) in clk_sam9x5_peripheral_autodiv()
156 periph->div = shift; in clk_sam9x5_peripheral_autodiv()
253 u32 shift, long *best_diff, in clk_sam9x5_peripheral_best_diff() argument
256 unsigned long tmp_rate = parent_rate >> shift; in clk_sam9x5_peripheral_best_diff()
276 u32 shift; in clk_sam9x5_peripheral_determine_rate() local
282 for (shift = 0; shift <= PERIPHERAL_MAX_SHIFT; shift++) { in clk_sam9x5_peripheral_determine_rate()
283 tmp_rate = parent_rate >> shift; in clk_sam9x5_peripheral_determine_rate()
289 shift, &best_diff, &best_rate); in clk_sam9x5_peripheral_determine_rate()
[all …]
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| /drivers/infiniband/core/ |
| D | packer.c | 71 int shift; in ib_pack() local
76 shift = 32 - desc[i].offset_bits - desc[i].size_bits; in ib_pack()
80 structure) << shift; in ib_pack()
84 mask = cpu_to_be32(((1ull << desc[i].size_bits) - 1) << shift); in ib_pack()
88 int shift; in ib_pack() local
93 shift = 64 - desc[i].offset_bits - desc[i].size_bits; in ib_pack()
97 structure) << shift; in ib_pack()
101 mask = cpu_to_be64((~0ull >> (64 - desc[i].size_bits)) << shift); in ib_pack()
160 int shift; in ib_unpack() local
165 shift = 32 - desc[i].offset_bits - desc[i].size_bits; in ib_unpack()
[all …]
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| /drivers/media/platform/ti/davinci/ |
| D | vpss.c | 229 u32 utemp, mask = 0x1, shift = 0; in dm355_enable_clock() local
236 shift = 2; in dm355_enable_clock()
239 shift = 3; in dm355_enable_clock()
242 shift = 4; in dm355_enable_clock()
245 shift = 5; in dm355_enable_clock()
248 shift = 6; in dm355_enable_clock()
259 utemp &= ~(mask << shift); in dm355_enable_clock()
261 utemp |= (mask << shift); in dm355_enable_clock()
271 u32 utemp, mask = 0x1, shift = 0, offset = DM365_ISP5_PCCR; in dm365_enable_clock() local
279 shift = 1; in dm365_enable_clock()
[all …]
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| /drivers/regulator/ |
| D | max8998.c | 41 int *reg, int *shift) in max8998_get_enable_register() argument
48 *shift = 3 - (ldo - MAX8998_LDO2); in max8998_get_enable_register()
52 *shift = 7 - (ldo - MAX8998_LDO6); in max8998_get_enable_register()
56 *shift = 7 - (ldo - MAX8998_LDO14); in max8998_get_enable_register()
60 *shift = 7 - (ldo - MAX8998_BUCK1); in max8998_get_enable_register()
64 *shift = 7 - (ldo - MAX8998_EN32KHZ_AP); in max8998_get_enable_register()
68 *shift = 7 - (ldo - MAX8998_ESAFEOUT1); in max8998_get_enable_register()
72 *shift = 0; in max8998_get_enable_register()
85 int ret, reg, shift = 8; in max8998_ldo_is_enabled() local
88 ret = max8998_get_enable_register(rdev, ®, &shift); in max8998_ldo_is_enabled()
[all …]
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| /drivers/soc/aspeed/ |
| D | aspeed-uart-routing.c | 44 uint8_t shift; member
70 .shift = 8,
90 .shift = 28,
110 .shift = 25,
128 .shift = 22,
146 .shift = 19,
164 .shift = 16,
182 .shift = 12,
200 .shift = 9,
218 .shift = 6,
[all …]
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| /drivers/clk/ |
| D | clk-axm5516.c | 78 u32 shift; member
94 div = 1 + ((ctrl >> divclk->shift) & ((1 << divclk->width)-1)); in axxia_divclk_recalc_rate()
113 u32 shift; member
128 parent = (ctrl >> mux->shift) & ((1 << mux->width) - 1); in axxia_clkmux_get_parent()
216 .shift = 0,
230 .shift = 4,
244 .shift = 8,
258 .shift = 12,
272 .shift = 0,
286 .shift = 4,
[all …]
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| /drivers/media/platform/nvidia/tegra-vde/ |
| D | iommu.c | 25 unsigned long shift; in tegra_vde_iommu_map() local
31 shift = iova_shift(&vde->iova); in tegra_vde_iommu_map()
33 iova = alloc_iova(&vde->iova, size >> shift, end >> shift, true); in tegra_vde_iommu_map()
53 unsigned long shift = iova_shift(&vde->iova); in tegra_vde_iommu_unmap() local
54 unsigned long size = iova_size(iova) << shift; in tegra_vde_iommu_unmap()
66 unsigned long shift; in tegra_vde_iommu_init() local
102 shift = iova_shift(&vde->iova); in tegra_vde_iommu_init()
103 iova = reserve_iova(&vde->iova, 0x60000000 >> shift, in tegra_vde_iommu_init()
104 0x70000000 >> shift); in tegra_vde_iommu_init()
118 iova = reserve_iova(&vde->iova, 0xffffffff >> shift, in tegra_vde_iommu_init()
[all …]
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| /drivers/net/ethernet/mellanox/mlxsw/ |
| D | item.h | 15 unsigned char shift; /* shift in bits */ member
52 tmp >>= item->shift; in __mlxsw_item_get8()
55 tmp <<= item->shift; in __mlxsw_item_get8()
65 u8 mask = GENMASK(item->size.bits - 1, 0) << item->shift; in __mlxsw_item_set8()
69 val <<= item->shift; in __mlxsw_item_set8()
86 tmp >>= item->shift; in __mlxsw_item_get16()
89 tmp <<= item->shift; in __mlxsw_item_get16()
99 u16 mask = GENMASK(item->size.bits - 1, 0) << item->shift; in __mlxsw_item_set16()
103 val <<= item->shift; in __mlxsw_item_set16()
120 tmp >>= item->shift; in __mlxsw_item_get32()
[all …]
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