1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __MACH_IMX_CLK_H
3 #define __MACH_IMX_CLK_H
4
5 #include <linux/bits.h>
6 #include <linux/spinlock.h>
7 #include <linux/clk-provider.h>
8
9 extern spinlock_t imx_ccm_lock;
10 extern bool mcore_booted;
11
12 void imx_check_clocks(struct clk *clks[], unsigned int count);
13 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
14 #ifndef MODULE
15 void imx_register_uart_clocks(unsigned int clk_count);
16 #else
imx_register_uart_clocks(unsigned int clk_count)17 static inline void imx_register_uart_clocks(unsigned int clk_count)
18 {
19 }
20 #endif
21 void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
22 void imx_unregister_clocks(struct clk *clks[], unsigned int count);
23 void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count);
24
25 extern void imx_cscmr1_fixup(u32 *val);
26
27 enum imx_pllv1_type {
28 IMX_PLLV1_IMX1,
29 IMX_PLLV1_IMX21,
30 IMX_PLLV1_IMX25,
31 IMX_PLLV1_IMX27,
32 IMX_PLLV1_IMX31,
33 IMX_PLLV1_IMX35,
34 };
35
36 enum imx_sscg_pll_type {
37 SCCG_PLL1,
38 SCCG_PLL2,
39 };
40
41 enum imx_pll14xx_type {
42 PLL_1416X,
43 PLL_1443X,
44 };
45
46 enum imx_pllv4_type {
47 IMX_PLLV4_IMX7ULP,
48 IMX_PLLV4_IMX8ULP,
49 IMX_PLLV4_IMX8ULP_1GHZ,
50 };
51
52 enum imx_pfdv2_type {
53 IMX_PFDV2_IMX7ULP,
54 IMX_PFDV2_IMX8ULP,
55 };
56
57 /* NOTE: Rate table should be kept sorted in descending order. */
58 struct imx_pll14xx_rate_table {
59 unsigned int rate;
60 unsigned int pdiv;
61 unsigned int mdiv;
62 unsigned int sdiv;
63 unsigned int kdiv;
64 };
65
66 struct imx_pll14xx_clk {
67 enum imx_pll14xx_type type;
68 const struct imx_pll14xx_rate_table *rate_table;
69 int rate_count;
70 int flags;
71 };
72
73 extern struct imx_pll14xx_clk imx_1416x_pll;
74 extern struct imx_pll14xx_clk imx_1443x_pll;
75 extern struct imx_pll14xx_clk imx_1443x_dram_pll;
76
77 /* NOTE: Rate table should be kept sorted in descending order. */
78 struct imx_fracn_gppll_rate_table {
79 unsigned int rate;
80 unsigned int mfi;
81 unsigned int mfn;
82 unsigned int mfd;
83 unsigned int rdiv;
84 unsigned int odiv;
85 };
86
87 struct imx_fracn_gppll_clk {
88 const struct imx_fracn_gppll_rate_table *rate_table;
89 int rate_count;
90 int flags;
91 };
92
93 struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,
94 const struct imx_fracn_gppll_clk *pll_clk);
95
96 extern struct imx_fracn_gppll_clk imx_fracn_gppll;
97
98 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
99 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
100
101 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
102 cgr_val, cgr_mask, clk_gate_flags, lock, share_count) \
103 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
104 cgr_val, cgr_mask, clk_gate_flags, lock, share_count))
105
106 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
107 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
108
109 #define imx_clk_pfd(name, parent_name, reg, idx) \
110 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
111
112 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
113 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
114
115 #define imx_clk_fixed(name, rate) \
116 to_clk(imx_clk_hw_fixed(name, rate))
117
118 #define imx_clk_fixed_factor(name, parent, mult, div) \
119 to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
120
121 #define imx_clk_divider(name, parent, reg, shift, width) \
122 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
123
124 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \
125 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
126
127 #define imx_clk_gate(name, parent, reg, shift) \
128 to_clk(imx_clk_hw_gate(name, parent, reg, shift))
129
130 #define imx_clk_gate_dis(name, parent, reg, shift) \
131 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
132
133 #define imx_clk_gate2(name, parent, reg, shift) \
134 to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
135
136 #define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \
137 to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))
138
139 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
140 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
141
142 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \
143 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
144
145 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
146 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
147
148 #define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \
149 to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags))
150
151 #define imx_clk_pllv1(type, name, parent, base) \
152 to_clk(imx_clk_hw_pllv1(type, name, parent, base))
153
154 #define imx_clk_pllv2(name, parent, base) \
155 to_clk(imx_clk_hw_pllv2(name, parent, base))
156
157 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
158 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
159
160 #define imx_clk_hw_gate(name, parent, reg, shift) \
161 imx_clk_hw_gate_flags(name, parent, reg, shift, 0)
162
163 #define imx_clk_hw_gate2(name, parent, reg, shift) \
164 imx_clk_hw_gate2_flags(name, parent, reg, shift, 0)
165
166 #define imx_clk_hw_gate_dis(name, parent, reg, shift) \
167 imx_clk_hw_gate_dis_flags(name, parent, reg, shift, 0)
168
169 #define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \
170 __imx_clk_hw_gate(name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE)
171
172 #define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \
173 __imx_clk_hw_gate(name, parent, reg, shift, flags, 0)
174
175 #define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \
176 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, flags, NULL)
177
178 #define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \
179 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, 0, shared_count)
180
181 #define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \
182 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count)
183
184 #define imx_clk_hw_gate3(name, parent, reg, shift) \
185 imx_clk_hw_gate3_flags(name, parent, reg, shift, 0)
186
187 #define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \
188 __imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0)
189
190 #define imx_clk_hw_gate4(name, parent, reg, shift) \
191 imx_clk_hw_gate4_flags(name, parent, reg, shift, 0)
192
193 #define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \
194 imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE)
195
196 #define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \
197 imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0)
198
199 #define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \
200 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, 0, 0)
201
202 #define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
203 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags, 0)
204
205 #define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \
206 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY)
207
208 #define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \
209 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0)
210
211 #define imx_clk_hw_divider(name, parent, reg, shift, width) \
212 __imx_clk_hw_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT)
213
214 #define imx_clk_hw_divider2(name, parent, reg, shift, width) \
215 __imx_clk_hw_divider(name, parent, reg, shift, width, \
216 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE)
217
218 #define imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags) \
219 __imx_clk_hw_divider(name, parent, reg, shift, width, flags)
220
221 #define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \
222 imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk)
223
224 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
225 const char *parent_name, void __iomem *base,
226 const struct imx_pll14xx_clk *pll_clk);
227
228 struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
229 const char *parent, void __iomem *base);
230
231 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
232 void __iomem *base);
233
234 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
235 void __iomem *base);
236
237 struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
238 const char * const *parent_names,
239 u8 num_parents,
240 u8 parent, u8 bypass1, u8 bypass2,
241 void __iomem *base,
242 unsigned long flags);
243
244 enum imx_pllv3_type {
245 IMX_PLLV3_GENERIC,
246 IMX_PLLV3_SYS,
247 IMX_PLLV3_USB,
248 IMX_PLLV3_USB_VF610,
249 IMX_PLLV3_AV,
250 IMX_PLLV3_ENET,
251 IMX_PLLV3_ENET_IMX7,
252 IMX_PLLV3_SYS_VF610,
253 IMX_PLLV3_DDR_IMX7,
254 IMX_PLLV3_AV_IMX7,
255 };
256
257 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
258 const char *parent_name, void __iomem *base, u32 div_mask);
259
260 #define PLL_1416X_RATE(_rate, _m, _p, _s) \
261 { \
262 .rate = (_rate), \
263 .mdiv = (_m), \
264 .pdiv = (_p), \
265 .sdiv = (_s), \
266 }
267
268 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
269 { \
270 .rate = (_rate), \
271 .mdiv = (_m), \
272 .pdiv = (_p), \
273 .sdiv = (_s), \
274 .kdiv = (_k), \
275 }
276
277 struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name,
278 const char *parent_name, void __iomem *base);
279
280 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
281 const char *parent_name, unsigned long flags,
282 void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask,
283 u8 clk_gate_flags, spinlock_t *lock,
284 unsigned int *share_count);
285
286 struct clk * imx_obtain_fixed_clock(
287 const char *name, unsigned long rate);
288
289 struct clk_hw *imx_obtain_fixed_clock_hw(
290 const char *name, unsigned long rate);
291
292 struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np,
293 const char *name);
294
295 struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
296 void __iomem *reg, u8 shift, u32 exclusive_mask);
297
298 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
299 void __iomem *reg, u8 idx);
300
301 struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name,
302 const char *parent_name, void __iomem *reg, u8 idx);
303
304 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
305 void __iomem *reg, u8 shift, u8 width,
306 void __iomem *busy_reg, u8 busy_shift);
307
308 struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
309 u8 width, void __iomem *busy_reg, u8 busy_shift,
310 const char * const *parent_names, int num_parents);
311
312 struct clk_hw *imx7ulp_clk_hw_composite(const char *name,
313 const char * const *parent_names,
314 int num_parents, bool mux_present,
315 bool rate_present, bool gate_present,
316 void __iomem *reg);
317
318 struct clk_hw *imx8ulp_clk_hw_composite(const char *name,
319 const char * const *parent_names,
320 int num_parents, bool mux_present,
321 bool rate_present, bool gate_present,
322 void __iomem *reg, bool has_swrst);
323
324 struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
325 void __iomem *reg, u8 shift, u8 width,
326 void (*fixup)(u32 *val));
327
328 struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
329 u8 shift, u8 width, const char * const *parents,
330 int num_parents, void (*fixup)(u32 *val));
331
to_clk(struct clk_hw * hw)332 static inline struct clk *to_clk(struct clk_hw *hw)
333 {
334 if (IS_ERR_OR_NULL(hw))
335 return ERR_CAST(hw);
336 return hw->clk;
337 }
338
imx_clk_hw_fixed(const char * name,int rate)339 static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
340 {
341 return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
342 }
343
imx_clk_hw_fixed_factor(const char * name,const char * parent,unsigned int mult,unsigned int div)344 static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name,
345 const char *parent, unsigned int mult, unsigned int div)
346 {
347 return clk_hw_register_fixed_factor(NULL, name, parent,
348 CLK_SET_RATE_PARENT, mult, div);
349 }
350
__imx_clk_hw_divider(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 width,unsigned long flags)351 static inline struct clk_hw *__imx_clk_hw_divider(const char *name,
352 const char *parent,
353 void __iomem *reg, u8 shift,
354 u8 width, unsigned long flags)
355 {
356 return clk_hw_register_divider(NULL, name, parent, flags,
357 reg, shift, width, 0, &imx_ccm_lock);
358 }
359
__imx_clk_hw_gate(const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned long flags,unsigned long clk_gate_flags)360 static inline struct clk_hw *__imx_clk_hw_gate(const char *name, const char *parent,
361 void __iomem *reg, u8 shift,
362 unsigned long flags,
363 unsigned long clk_gate_flags)
364 {
365 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
366 shift, clk_gate_flags, &imx_ccm_lock);
367 }
368
__imx_clk_hw_gate2(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 cgr_val,unsigned long flags,unsigned int * share_count)369 static inline struct clk_hw *__imx_clk_hw_gate2(const char *name, const char *parent,
370 void __iomem *reg, u8 shift, u8 cgr_val,
371 unsigned long flags,
372 unsigned int *share_count)
373 {
374 return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
375 shift, cgr_val, 0x3, 0, &imx_ccm_lock, share_count);
376 }
377
__imx_clk_hw_mux(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents,unsigned long flags,unsigned long clk_mux_flags)378 static inline struct clk_hw *__imx_clk_hw_mux(const char *name, void __iomem *reg,
379 u8 shift, u8 width, const char * const *parents,
380 int num_parents, unsigned long flags, unsigned long clk_mux_flags)
381 {
382 return clk_hw_register_mux(NULL, name, parents, num_parents,
383 flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
384 width, clk_mux_flags, &imx_ccm_lock);
385 }
386
387 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
388 struct clk *div, struct clk *mux, struct clk *pll,
389 struct clk *step);
390
391 #define IMX_COMPOSITE_CORE BIT(0)
392 #define IMX_COMPOSITE_BUS BIT(1)
393 #define IMX_COMPOSITE_FW_MANAGED BIT(2)
394
395 #define IMX_COMPOSITE_CLK_FLAGS_DEFAULT \
396 (CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
397 #define IMX_COMPOSITE_CLK_FLAGS_CRITICAL \
398 (IMX_COMPOSITE_CLK_FLAGS_DEFAULT | CLK_IS_CRITICAL)
399 #define IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE \
400 (IMX_COMPOSITE_CLK_FLAGS_DEFAULT | CLK_GET_RATE_NOCACHE)
401 #define IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE \
402 (IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE | CLK_IS_CRITICAL)
403
404 struct clk_hw *__imx8m_clk_hw_composite(const char *name,
405 const char * const *parent_names,
406 int num_parents,
407 void __iomem *reg,
408 u32 composite_flags,
409 unsigned long flags);
410
411 #define _imx8m_clk_hw_composite(name, parent_names, reg, composite_flags, flags) \
412 __imx8m_clk_hw_composite(name, parent_names, \
413 ARRAY_SIZE(parent_names), reg, composite_flags, flags)
414
415 #define imx8m_clk_hw_composite(name, parent_names, reg) \
416 _imx8m_clk_hw_composite(name, parent_names, reg, \
417 0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
418
419 #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
420 _imx8m_clk_hw_composite(name, parent_names, reg, \
421 0, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
422
423 #define imx8m_clk_hw_composite_bus(name, parent_names, reg) \
424 _imx8m_clk_hw_composite(name, parent_names, reg, \
425 IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
426
427 #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \
428 _imx8m_clk_hw_composite(name, parent_names, reg, \
429 IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)
430
431 #define imx8m_clk_hw_composite_core(name, parent_names, reg) \
432 _imx8m_clk_hw_composite(name, parent_names, reg, \
433 IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_DEFAULT)
434
435 #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \
436 _imx8m_clk_hw_composite(name, parent_names, reg, \
437 IMX_COMPOSITE_FW_MANAGED, \
438 IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE)
439
440 #define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \
441 _imx8m_clk_hw_composite(name, parent_names, reg, \
442 IMX_COMPOSITE_FW_MANAGED, \
443 IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE)
444
445 struct clk_hw *imx93_clk_composite_flags(const char *name,
446 const char * const *parent_names,
447 int num_parents,
448 void __iomem *reg,
449 u32 domain_id,
450 unsigned long flags);
451 #define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \
452 imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \
453 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
454
455 struct clk_hw *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name,
456 unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val,
457 u32 mask, u32 domain_id, unsigned int *share_count);
458
459 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,
460 unsigned long flags, void __iomem *reg, u8 shift, u8 width,
461 u8 clk_divider_flags, const struct clk_div_table *table,
462 spinlock_t *lock);
463 #endif
464