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Searched refs:APBC_SSP0 (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/mmp/
Dclk-pxa910.c30 #define APBC_SSP0 0x1c macro
238 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); in pxa910_clk_init()
242 apbc_base + APBC_SSP0, 10, 0, &clk_lock); in pxa910_clk_init()
Dclk-of-pxa910.c32 #define APBC_SSP0 0x1c macro
128 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
150 …{PXA910_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_…
Dclk-of-pxa168.c39 #define APBC_SSP0 0x81c macro
171 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
192 …{PXA168_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_…
Dclk-pxa168.c30 #define APBC_SSP0 0x81c macro
233 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); in pxa168_clk_init()
236 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, in pxa168_clk_init()
Dclk-mmp2.c37 #define APBC_SSP0 0x50 macro
289 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); in mmp2_clk_init()
293 apbc_base + APBC_SSP0, 10, 0, &clk_lock); in mmp2_clk_init()
Dclk-of-mmp2.c43 #define APBC_SSP0 0x50 macro
241 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
267 …{MMP2_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x7, 0x3, 0x0, 0, &ssp0_lo…