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Searched refs:APBC_SSP2 (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/mmp/
Dclk-of-pxa168.c41 #define APBC_SSP2 0x84c macro
173 …{0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4,…
194 …{PXA168_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x3, 0x3, 0x0, 0, &ssp2_…
Dclk-pxa168.c32 #define APBC_SSP2 0x84c macro
253 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); in pxa168_clk_init()
256 clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2, in pxa168_clk_init()
Dclk-mmp2.c39 #define APBC_SSP2 0x58 macro
309 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); in mmp2_clk_init()
313 apbc_base + APBC_SSP2, 10, 0, &clk_lock); in mmp2_clk_init()
Dclk-of-mmp2.c45 #define APBC_SSP2 0x58 macro
243 …{0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4,…
269 …{MMP2_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x7, 0x3, 0x0, 0, &ssp2_lo…
Dclk-pxa910.c32 #define APBC_SSP2 0x4c macro
Dclk-of-pxa910.c34 #define APBC_SSP2 0x4c macro