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Searched refs:MODE (Results 1 – 25 of 41) sorted by relevance

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/drivers/gpu/drm/i2c/
Dch7006_mode.c134 #define MODE(f, hd, vd, ht, vt, hsynp, vsynp, \ macro
145 MODE(21000, 512, 384, 840, 500, N, N, 181.797557582, 5_4, 0x6, PAL_LIKE),
146 MODE(26250, 512, 384, 840, 625, N, N, 145.438046066, 1_1, 0x1, PAL_LIKE),
147 MODE(20140, 512, 384, 800, 420, N, N, 213.257083791, 5_4, 0x4, NTSC_LIKE),
148 MODE(24671, 512, 384, 784, 525, N, N, 174.0874153, 1_1, 0x3, NTSC_LIKE),
149 MODE(28125, 720, 400, 1125, 500, N, N, 135.742176298, 5_4, 0x6, PAL_LIKE),
150 MODE(34875, 720, 400, 1116, 625, N, N, 109.469496898, 1_1, 0x1, PAL_LIKE),
151 MODE(23790, 720, 400, 945, 420, N, N, 160.475642016, 5_4, 0x4, NTSC_LIKE),
152 MODE(29455, 720, 400, 936, 525, N, N, 129.614941843, 1_1, 0x3, NTSC_LIKE),
153 MODE(25000, 640, 400, 1000, 500, N, N, 152.709948279, 5_4, 0x6, PAL_LIKE),
[all …]
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_hpo_dp_link_encoder.c100 MODE, DP2_LINK_ACTIVE); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
104 MODE, DP2_LINK_TRAINING_TPS1); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
108 MODE, DP2_LINK_TRAINING_TPS2); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
117 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
126 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
140 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
154 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
168 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
182 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
196 MODE, DP2_TEST_PATTERN); in dcn31_hpo_dp_link_enc_set_link_test_pattern()
[all …]
Ddcn31_hpo_dp_link_encoder.h112 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, MODE, mask_sh),\
140 type MODE;\
/drivers/media/dvb-frontends/
Dbcm3510.c506 cmd.ACQUIRE0.MODE = 0x1; in bcm3510_set_frontend()
511 cmd.ACQUIRE0.MODE = 0x2; in bcm3510_set_frontend()
517 cmd.ACQUIRE0.MODE = 0x3; in bcm3510_set_frontend()
520 cmd.ACQUIRE0.MODE = 0x4; in bcm3510_set_frontend()
523 cmd.ACQUIRE0.MODE = 0x5; in bcm3510_set_frontend()
526 cmd.ACQUIRE0.MODE = 0x6; in bcm3510_set_frontend()
529 cmd.ACQUIRE0.MODE = 0x7; in bcm3510_set_frontend()
533 cmd.ACQUIRE0.MODE = 0x8; in bcm3510_set_frontend()
538 cmd.ACQUIRE0.MODE = 0x9; in bcm3510_set_frontend()
Dbcm3510_priv.h176 u8 MODE :4; member
201 u8 MODE :4; member
/drivers/gpu/drm/nouveau/
Dnouveau_connector.h75 NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, MODE, DYNAMIC_2X2),
77 NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, MODE, STATIC_2X2),
79 NVDEF(NV907D, HEAD_SET_DITHER_CONTROL, MODE, TEMPORAL),
/drivers/soc/bcm/brcmstb/pm/
Dpm-mips.c40 #define MODE 7 macro
103 ctx->cp0_regs[MODE] = read_c0_brcm_mode(); in brcm_pm_save_cp0_context()
126 write_c0_brcm_mode(ctx->cp0_regs[MODE]); in brcm_pm_restore_cp0_context()
/drivers/gpu/drm/nouveau/dispnv50/
Dcore507d.c44 NVDEF(NV507D, SET_NOTIFIER_CONTROL, MODE, WRITE) | in core507d_update()
91 NVDEF(NV507D, SET_NOTIFIER_CONTROL, MODE, WRITE) | in core507d_read_caps()
Dhead507d.c61 NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in head507d_dither()
305 NVVAL(NV507D, HEAD_SET_BASE_LUT_LO, MODE, asyh->olut.mode) | in head507d_olut_set()
358 NVDEF(NV507D, HEAD_SET_PIXEL_CLOCK, MODE, CLK_CUSTOM) | in head507d_mode()
Dhead907d.c90 NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in head907d_dither()
275 NVVAL(NV907D, HEAD_SET_OUTPUT_LUT_LO, MODE, asyh->olut.mode) | in head907d_olut_set()
368 NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, MODE, CLK_CUSTOM) | in head907d_mode()
Dovly907e.c45 NVDEF(NV907E, SET_COMPOSITION_CONTROL, MODE, OPAQUE)); in ovly907e_image_set()
Dovly827e.c48 NVDEF(NV827E, SET_COMPOSITION_CONTROL, MODE, OPAQUE_SUSPEND_BASE)); in ovly827e_image_set()
Dheadc37d.c99 NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in headc37d_dither()
146 NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, MODE, BLEND)); in headc37d_curs_set()
Dhead917d.c43 NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | in head917d_dither()
Dcorec37d.c62 NVDEF(NVC37D, SET_NOTIFIER_CONTROL, MODE, WRITE) | in corec37d_update()
Dovly507e.c71 NVDEF(NV507E, SET_COMPOSITION_CONTROL, MODE, OPAQUE_SUSPEND_BASE)); in ovly507e_image_set()
Dbase907c.c95 NVVAL(NV907C, SET_BASE_LUT_LO, MODE, asyw->xlut.i.mode), in base907c_xlut_set()
Dhead827d.c139 NVVAL(NV827D, HEAD_SET_BASE_LUT_LO, MODE, asyh->olut.mode) | in head827d_olut_set()
Dwndwc57e.c136 NVVAL(NVC57E, SET_ILUT_CONTROL, MODE, asyw->xlut.i.mode) | in wndwc57e_ilut_set()
Dheadc57d.c110 NVVAL(NVC57D, HEAD_SET_OLUT_CONTROL, MODE, asyh->olut.mode) | in headc57d_olut_set()
/drivers/power/supply/
Dmax77976_charger.c85 MODE, /* CHG_CNFG_00 */ enumerator
98 [MODE] = REG_FIELD(MAX77976_REG_CHG_CNFG_00, 0, 3),
430 err = regmap_field_write(chg->rfield[MODE], MAX77976_MODE_CHARGER_BUCK); in max77976_configure()
/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_hpo_dp_link_encoder.h36 SE_SF(DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL, MODE, mask_sh),\
/drivers/char/pcmcia/
Dsynclink_cs.c253 #define MODE 0x22 macro
2919 write_reg(info, CHB + MODE, val); in enable_auxclk()
3004 val = read_reg(info, CHA + MODE) | BIT0; in loopback_enable()
3005 write_reg(info, CHA + MODE, val); in loopback_enable()
3062 write_reg(info, CHA + MODE, val); in hdlc_mode()
3255 clear_reg_bits(info, CHA + MODE, BIT3); in rx_stop()
3272 set_reg_bits(info, CHA + MODE, BIT3); in rx_start()
3334 write_reg(info, CHA + MODE, 0); in reset_device()
3335 write_reg(info, CHB + MODE, 0); in reset_device()
3408 write_reg(info, CHA + MODE, val); in async_mode()
[all …]
/drivers/gpu/drm/mediatek/
Dmtk_dsi.c50 #define MODE (3) macro
1026 if (dsi_mode & MODE) { in mtk_dsi_host_transfer()
1076 if (dsi_mode & MODE) { in mtk_dsi_host_transfer()
/drivers/pinctrl/
Dpinctrl-tb10x.c400 #define DEFPINFUNCGRP(NAME, PORT, MODE, ISGPIO) { \ argument
403 .port = (PORT), .mode = (MODE), \

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