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Searched refs:resets (Results 1 – 25 of 148) sorted by relevance

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/drivers/reset/
Dcore.c199 static int reset_control_array_reset(struct reset_control_array *resets) in reset_control_array_reset() argument
203 for (i = 0; i < resets->num_rstcs; i++) { in reset_control_array_reset()
204 ret = reset_control_reset(resets->rstc[i]); in reset_control_array_reset()
212 static int reset_control_array_rearm(struct reset_control_array *resets) in reset_control_array_rearm() argument
217 for (i = 0; i < resets->num_rstcs; i++) { in reset_control_array_rearm()
218 rstc = resets->rstc[i]; in reset_control_array_rearm()
235 for (i = 0; i < resets->num_rstcs; i++) { in reset_control_array_rearm()
236 rstc = resets->rstc[i]; in reset_control_array_rearm()
245 static int reset_control_array_assert(struct reset_control_array *resets) in reset_control_array_assert() argument
249 for (i = 0; i < resets->num_rstcs; i++) { in reset_control_array_assert()
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Dreset-qcom-pdc.c22 const struct qcom_pdc_reset_map *resets; member
56 .resets = sdm845_pdc_resets,
77 .resets = sc7280_pdc_resets,
92 u32 mask = BIT(data->desc->resets[idx].bit); in qcom_pdc_control_assert()
101 u32 mask = BIT(data->desc->resets[idx].bit); in qcom_pdc_control_deassert()
Dreset-qcom-aoss.c19 const struct qcom_aoss_reset_map *resets; member
40 .resets = sdm845_aoss_resets,
54 const struct qcom_aoss_reset_map *map = &data->desc->resets[idx]; in qcom_aoss_control_assert()
66 const struct qcom_aoss_reset_map *map = &data->desc->resets[idx]; in qcom_aoss_control_deassert()
/drivers/usb/dwc3/
Ddwc3-of-simple.c29 struct reset_control *resets; member
55 simple->resets = of_reset_control_array_get(np, false, true, in dwc3_of_simple_probe()
57 if (IS_ERR(simple->resets)) { in dwc3_of_simple_probe()
58 ret = PTR_ERR(simple->resets); in dwc3_of_simple_probe()
63 ret = reset_control_deassert(simple->resets); in dwc3_of_simple_probe()
91 reset_control_assert(simple->resets); in dwc3_of_simple_probe()
94 reset_control_put(simple->resets); in dwc3_of_simple_probe()
106 reset_control_assert(simple->resets); in __dwc3_of_simple_teardown()
108 reset_control_put(simple->resets); in __dwc3_of_simple_teardown()
152 reset_control_assert(simple->resets); in dwc3_of_simple_suspend()
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Ddwc3-qcom.c74 struct reset_control *resets; member
841 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev); in dwc3_qcom_probe()
842 if (IS_ERR(qcom->resets)) { in dwc3_qcom_probe()
843 ret = PTR_ERR(qcom->resets); in dwc3_qcom_probe()
848 ret = reset_control_assert(qcom->resets); in dwc3_qcom_probe()
856 ret = reset_control_deassert(qcom->resets); in dwc3_qcom_probe()
970 reset_control_assert(qcom->resets); in dwc3_qcom_probe()
1000 reset_control_assert(qcom->resets); in dwc3_qcom_remove()
/drivers/phy/
Dphy-lgm-usb.c41 struct reset_control *resets[ARRAY_SIZE(PHY_RESETS)]; member
78 reset_control_deassert(ta->resets[i]); in phy_init()
115 reset_control_assert(ta->resets[i]); in phy_shutdown()
189 struct reset_control *resets[ARRAY_SIZE(CTL_RESETS)]; in phy_probe() local
221 resets[i] = devm_reset_control_get_exclusive(dev, CTL_RESETS[i]); in phy_probe()
222 if (IS_ERR(resets[i])) { in phy_probe()
224 return PTR_ERR(resets[i]); in phy_probe()
229 ta->resets[i] = devm_reset_control_get_exclusive(dev, PHY_RESETS[i]); in phy_probe()
230 if (IS_ERR(ta->resets[i])) { in phy_probe()
232 return PTR_ERR(ta->resets[i]); in phy_probe()
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/drivers/gpu/drm/tegra/
Dgr2d.c35 struct reset_control_bulk_data resets[RST_GR2D_MAX]; member
223 gr2d->resets[RST_MC].id = "mc"; in gr2d_get_resets()
224 gr2d->resets[RST_GR2D].id = "2d"; in gr2d_get_resets()
228 dev, gr2d->nresets, gr2d->resets); in gr2d_get_resets()
234 if (WARN_ON(!gr2d->resets[RST_GR2D].rstc)) in gr2d_get_resets()
319 reset_control_bulk_release(gr2d->nresets, gr2d->resets); in gr2d_runtime_suspend()
333 err = reset_control_acquire(gr2d->resets[RST_MC].rstc); in gr2d_runtime_suspend()
339 err = reset_control_assert(gr2d->resets[RST_MC].rstc); in gr2d_runtime_suspend()
340 reset_control_release(gr2d->resets[RST_MC].rstc); in gr2d_runtime_suspend()
351 reset_control_bulk_acquire(gr2d->nresets, gr2d->resets); in gr2d_runtime_suspend()
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Dgr3d.c47 struct reset_control_bulk_data resets[RST_GR3D_MAX]; member
473 gr3d->resets[RST_MC].id = "mc"; in gr3d_get_resets()
474 gr3d->resets[RST_MC2].id = "mc2"; in gr3d_get_resets()
475 gr3d->resets[RST_GR3D].id = "3d"; in gr3d_get_resets()
476 gr3d->resets[RST_GR3D2].id = "3d2"; in gr3d_get_resets()
480 dev, gr3d->nresets, gr3d->resets); in gr3d_get_resets()
486 if (WARN_ON(!gr3d->resets[RST_GR3D].rstc) || in gr3d_get_resets()
487 WARN_ON(!gr3d->resets[RST_GR3D2].rstc && gr3d->nresets == 4)) in gr3d_get_resets()
575 err = reset_control_bulk_assert(gr3d->nresets, gr3d->resets); in gr3d_runtime_suspend()
590 reset_control_bulk_release(gr3d->nresets, gr3d->resets); in gr3d_runtime_suspend()
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/drivers/clk/visconti/
Dreset.c26 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_assert()
41 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_deassert()
65 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_status()
88 const struct visconti_reset_data *resets, in visconti_register_reset_controller() argument
100 reset->resets = resets; in visconti_register_reset_controller()
Dreset.h24 const struct visconti_reset_data *resets; member
32 const struct visconti_reset_data *resets,
/drivers/usb/host/
Dohci-platform.c41 struct reset_control *resets; member
157 priv->resets = devm_reset_control_array_get_optional_shared( in ohci_platform_probe()
159 if (IS_ERR(priv->resets)) { in ohci_platform_probe()
160 err = PTR_ERR(priv->resets); in ohci_platform_probe()
164 err = reset_control_deassert(priv->resets); in ohci_platform_probe()
229 reset_control_assert(priv->resets); in ohci_platform_probe()
255 reset_control_assert(priv->resets); in ohci_platform_remove()
/drivers/clk/sunxi-ng/
Dccu-sun8i-de2.c188 .resets = sun8i_a83t_de2_resets,
198 .resets = sun8i_h3_de2_resets,
208 .resets = sun8i_a83t_de2_resets,
218 .resets = sun8i_a83t_de2_resets,
228 .resets = sun50i_a64_de2_resets,
238 .resets = sun50i_h5_de2_resets,
Dccu-sun8i-r.c210 .resets = sun8i_a83t_r_ccu_resets,
220 .resets = sun8i_h3_r_ccu_resets,
230 .resets = sun50i_a64_r_ccu_resets,
Dccu-sun50i-h6-r.c206 .resets = sun50i_h6_r_ccu_resets,
216 .resets = sun50i_h616_r_ccu_resets,
Dccu_common.h49 struct ccu_reset_map *resets; member
/drivers/gpu/host1x/
Ddev.c461 host->resets[0].id = "mc"; in host1x_get_resets()
462 host->resets[1].id = "host1x"; in host1x_get_resets()
463 host->nresets = ARRAY_SIZE(host->resets); in host1x_get_resets()
466 host->dev, host->nresets, host->resets); in host1x_get_resets()
649 err = reset_control_bulk_assert(host->nresets, host->resets); in host1x_runtime_suspend()
658 reset_control_bulk_release(host->nresets, host->resets); in host1x_runtime_suspend()
675 err = reset_control_bulk_acquire(host->nresets, host->resets); in host1x_runtime_resume()
687 err = reset_control_bulk_deassert(host->nresets, host->resets); in host1x_runtime_resume()
702 reset_control_bulk_release(host->nresets, host->resets); in host1x_runtime_resume()
/drivers/phy/qualcomm/
Dphy-qcom-qmp-pcie-msm8996.c272 struct reset_control_bulk_data *resets; member
431 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_msm8996_com_init()
437 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); in qmp_pcie_msm8996_com_init()
455 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_msm8996_com_init()
484 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_msm8996_com_exit()
664 qmp->resets = devm_kcalloc(dev, cfg->num_resets, in qmp_pcie_msm8996_reset_init()
665 sizeof(*qmp->resets), GFP_KERNEL); in qmp_pcie_msm8996_reset_init()
666 if (!qmp->resets) in qmp_pcie_msm8996_reset_init()
670 qmp->resets[i].id = cfg->reset_list[i]; in qmp_pcie_msm8996_reset_init()
672 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); in qmp_pcie_msm8996_reset_init()
/drivers/clk/renesas/
Drzg2l-cpg.c1123 unsigned int reg = info->resets[id].off; in rzg2l_cpg_assert()
1124 u32 mask = BIT(info->resets[id].bit); in rzg2l_cpg_assert()
1125 s8 monbit = info->resets[id].monbit; in rzg2l_cpg_assert()
1152 unsigned int reg = info->resets[id].off; in rzg2l_cpg_deassert()
1153 u32 mask = BIT(info->resets[id].bit); in rzg2l_cpg_deassert()
1154 s8 monbit = info->resets[id].monbit; in rzg2l_cpg_deassert()
1194 s8 monbit = info->resets[id].monbit; in rzg2l_cpg_status()
1199 reg = CLK_MRST_R(info->resets[id].off); in rzg2l_cpg_status()
1200 bitmask = BIT(info->resets[id].bit); in rzg2l_cpg_status()
1225 if (id >= rcdev->nr_resets || !info->resets[id].off) { in rzg2l_cpg_reset_xlate()
/drivers/clk/imx/
Dclk-imx8ulp.c55 const u32 *resets; member
85 u32 offset = pcc_reset->resets[id]; in imx8ulp_pcc_assert()
103 u32 offset = pcc_reset->resets[id]; in imx8ulp_pcc_deassert()
124 const u32 *resets, unsigned int nr_resets) in imx8ulp_pcc_reset_init() argument
136 pcc_reset->resets = resets; in imx8ulp_pcc_reset_init()
/drivers/gpu/drm/i915/gt/
Dselftest_rc6.c210 unsigned int resets = in live_rc6_ctx_wa() local
240 if (resets != in live_rc6_ctx_wa()
/drivers/clk/actions/
Dowl-common.h29 const struct owl_reset_map *resets; member
/drivers/media/platform/verisilicon/
Dhantro_drv.c951 vpu->resets = devm_reset_control_array_get(&pdev->dev, false, true); in hantro_probe()
952 if (IS_ERR(vpu->resets)) in hantro_probe()
953 return PTR_ERR(vpu->resets); in hantro_probe()
1028 ret = reset_control_deassert(vpu->resets); in hantro_probe()
1094 reset_control_assert(vpu->resets); in hantro_probe()
1114 reset_control_assert(vpu->resets); in hantro_remove()
/drivers/media/platform/qcom/venus/
Dpm_helpers.c940 ret = reset_control_assert(core->resets[i]); in core_resets_reset()
945 ret = reset_control_deassert(core->resets[i]); in core_resets_reset()
965 core->resets[i] = in core_resets_get()
966 devm_reset_control_get_exclusive(dev, res->resets[i]); in core_resets_get()
967 if (IS_ERR(core->resets[i])) { in core_resets_get()
968 ret = PTR_ERR(core->resets[i]); in core_resets_get()
/drivers/clk/qcom/
Dgpucc-sdm660.c247 .resets = (unsigned int []){ GPU_GX_BCR },
295 .resets = gpucc_sdm660_resets,
Dgpucc-msm8998.c263 .resets = (unsigned int []){ GPU_GX_BCR },
313 .resets = gpucc_msm8998_resets,

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