| /drivers/clk/mediatek/ |
| D | clk-mt8183-ipu_conn.c | 15 .set_ofs = 0x4,
21 .set_ofs = 0x10,
27 .set_ofs = 0x18,
33 .set_ofs = 0x1c,
39 .set_ofs = 0x20,
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| D | clk-mt8186-vdec.c | 16 .set_ofs = 0x0,
22 .set_ofs = 0x190,
28 .set_ofs = 0x200,
34 .set_ofs = 0x8,
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| D | clk-mt8195-vdo1.c | 14 .set_ofs = 0x104,
20 .set_ofs = 0x124,
26 .set_ofs = 0x134,
32 .set_ofs = 0x144,
38 .set_ofs = 0x400,
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| D | clk-gate.c | 20 int set_ofs; member
55 regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit)); in mtk_cg_set_bit()
157 struct regmap *regmap, int set_ofs, in mtk_clk_register_gate() argument
177 cg->set_ofs = set_ofs; in mtk_clk_register_gate()
234 gate->regs->set_ofs, in mtk_clk_register_gates_with_dev()
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| D | clk-mt2701-aud.c | 31 .set_ofs = 0x0,
37 .set_ofs = 0x10,
43 .set_ofs = 0x14,
49 .set_ofs = 0x634,
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| D | clk-mt7622-aud.c | 32 .set_ofs = 0x0,
38 .set_ofs = 0x10,
44 .set_ofs = 0x14,
50 .set_ofs = 0x634,
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| D | clk-mt8192-vdec.c | 16 .set_ofs = 0x0,
22 .set_ofs = 0x200,
28 .set_ofs = 0x8,
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| D | clk-mt8195-infra_ao.c | 15 .set_ofs = 0x80,
21 .set_ofs = 0x88,
27 .set_ofs = 0xa4,
33 .set_ofs = 0xc0,
39 .set_ofs = 0xe0,
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| D | clk-mt8195-vdec.c | 14 .set_ofs = 0x0,
20 .set_ofs = 0x200,
26 .set_ofs = 0x8,
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| D | clk-mt8195-vpp0.c | 14 .set_ofs = 0x24,
20 .set_ofs = 0x30,
26 .set_ofs = 0x3c,
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| D | clk-mt8192-mm.c | 15 .set_ofs = 0x104,
21 .set_ofs = 0x114,
27 .set_ofs = 0x1a4,
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| D | clk-mt8192-aud.c | 16 .set_ofs = 0x0,
22 .set_ofs = 0x4,
28 .set_ofs = 0x8,
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| D | clk-mt7986-eth.c | 20 .set_ofs = 0xe4,
36 .set_ofs = 0xe4,
52 .set_ofs = 0x30,
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| D | clk-mt8195-wpe.c | 14 .set_ofs = 0x0,
20 .set_ofs = 0x58,
26 .set_ofs = 0x5c,
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| D | clk-mt6765.c | 469 .set_ofs = 0x0,
475 .set_ofs = 0x104,
481 .set_ofs = 0x320,
521 .set_ofs = 0x80,
527 .set_ofs = 0x88,
533 .set_ofs = 0xa4,
539 .set_ofs = 0xc0,
630 .set_ofs = 0x14,
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| D | clk-mt8186-infra_ao.c | 15 .set_ofs = 0x80,
21 .set_ofs = 0x88,
27 .set_ofs = 0xa4,
33 .set_ofs = 0xc0,
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| D | clk-mt2712-mm.c | 16 .set_ofs = 0x104,
22 .set_ofs = 0x114,
28 .set_ofs = 0x224,
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| D | clk-mt8195-vdo0.c | 14 .set_ofs = 0x104,
20 .set_ofs = 0x114,
26 .set_ofs = 0x124,
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| D | clk-mt6795-vdecsys.c | 18 .set_ofs = 0x0000,
24 .set_ofs = 0x0008,
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| D | clk-mt8192.c | 721 .set_ofs = 0x14,
734 .set_ofs = 0x80,
740 .set_ofs = 0x88,
746 .set_ofs = 0xa4,
752 .set_ofs = 0xc0,
758 .set_ofs = 0xd0,
764 .set_ofs = 0xe0,
936 .set_ofs = 0x20c,
949 .set_ofs = 0x150,
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| D | clk-mt7622.c | 265 .set_ofs = 0x8,
271 .set_ofs = 0x40,
277 .set_ofs = 0x120,
283 .set_ofs = 0x128,
289 .set_ofs = 0x8,
295 .set_ofs = 0xC,
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| D | clk-mt6779-vdec.c | 17 .set_ofs = 0x0000,
23 .set_ofs = 0x0008,
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| D | clk-mt8183-vdec.c | 15 .set_ofs = 0x0,
21 .set_ofs = 0x8,
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| D | clk-mt2701-vdec.c | 16 .set_ofs = 0x0000,
22 .set_ofs = 0x0008,
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| D | clk-mt8365-vdec.c | 14 .set_ofs = 0x0,
20 .set_ofs = 0x8,
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