1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2017 MediaTek Inc.
4 * Author: Chen Zhong <chen.zhong@mediatek.com>
5 * Sean Wang <sean.wang@mediatek.com>
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13
14 #include "clk-cpumux.h"
15 #include "clk-gate.h"
16 #include "clk-mtk.h"
17 #include "clk-pll.h"
18
19 #include <dt-bindings/clock/mt7622-clk.h>
20 #include <linux/clk.h> /* for consumer */
21
22 #define MT7622_PLL_FMAX (2500UL * MHZ)
23 #define CON0_MT7622_RST_BAR BIT(27)
24
25 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
26 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
27 _pcw_shift, _div_table, _parent_name) { \
28 .id = _id, \
29 .name = _name, \
30 .reg = _reg, \
31 .pwr_reg = _pwr_reg, \
32 .en_mask = _en_mask, \
33 .flags = _flags, \
34 .rst_bar_mask = CON0_MT7622_RST_BAR, \
35 .fmax = MT7622_PLL_FMAX, \
36 .pcwbits = _pcwbits, \
37 .pd_reg = _pd_reg, \
38 .pd_shift = _pd_shift, \
39 .tuner_reg = _tuner_reg, \
40 .pcw_reg = _pcw_reg, \
41 .pcw_shift = _pcw_shift, \
42 .div_table = _div_table, \
43 .parent_name = _parent_name, \
44 }
45
46 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
47 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
48 _pcw_shift) \
49 PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
50 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
51 NULL, "clkxtal")
52
53 #define GATE_APMIXED_AO(_id, _name, _parent, _shift) \
54 GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, _shift, \
55 &mtk_clk_gate_ops_no_setclr_inv, CLK_IS_CRITICAL)
56
57 #define GATE_INFRA(_id, _name, _parent, _shift) \
58 GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
59
60 #define GATE_TOP0(_id, _name, _parent, _shift) \
61 GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
62
63 #define GATE_TOP1(_id, _name, _parent, _shift) \
64 GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
65
66 #define GATE_PERI0(_id, _name, _parent, _shift) \
67 GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
68
69 #define GATE_PERI0_AO(_id, _name, _parent, _shift) \
70 GATE_MTK_FLAGS(_id, _name, _parent, &peri0_cg_regs, _shift, \
71 &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL)
72
73 #define GATE_PERI1(_id, _name, _parent, _shift) \
74 GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
75
76 static DEFINE_SPINLOCK(mt7622_clk_lock);
77
78 static const char * const infra_mux1_parents[] = {
79 "clkxtal",
80 "armpll",
81 "main_core_en",
82 "armpll"
83 };
84
85 static const char * const axi_parents[] = {
86 "clkxtal",
87 "syspll1_d2",
88 "syspll_d5",
89 "syspll1_d4",
90 "univpll_d5",
91 "univpll2_d2",
92 "univpll_d7"
93 };
94
95 static const char * const mem_parents[] = {
96 "clkxtal",
97 "dmpll_ck"
98 };
99
100 static const char * const ddrphycfg_parents[] = {
101 "clkxtal",
102 "syspll1_d8"
103 };
104
105 static const char * const eth_parents[] = {
106 "clkxtal",
107 "syspll1_d2",
108 "univpll1_d2",
109 "syspll1_d4",
110 "univpll_d5",
111 "clk_null",
112 "univpll_d7"
113 };
114
115 static const char * const pwm_parents[] = {
116 "clkxtal",
117 "univpll2_d4"
118 };
119
120 static const char * const f10m_ref_parents[] = {
121 "clkxtal",
122 "syspll4_d16"
123 };
124
125 static const char * const nfi_infra_parents[] = {
126 "clkxtal",
127 "clkxtal",
128 "clkxtal",
129 "clkxtal",
130 "clkxtal",
131 "clkxtal",
132 "clkxtal",
133 "clkxtal",
134 "univpll2_d8",
135 "syspll1_d8",
136 "univpll1_d8",
137 "syspll4_d2",
138 "univpll2_d4",
139 "univpll3_d2",
140 "syspll1_d4"
141 };
142
143 static const char * const flash_parents[] = {
144 "clkxtal",
145 "univpll_d80_d4",
146 "syspll2_d8",
147 "syspll3_d4",
148 "univpll3_d4",
149 "univpll1_d8",
150 "syspll2_d4",
151 "univpll2_d4"
152 };
153
154 static const char * const uart_parents[] = {
155 "clkxtal",
156 "univpll2_d8"
157 };
158
159 static const char * const spi0_parents[] = {
160 "clkxtal",
161 "syspll3_d2",
162 "clkxtal",
163 "syspll2_d4",
164 "syspll4_d2",
165 "univpll2_d4",
166 "univpll1_d8",
167 "clkxtal"
168 };
169
170 static const char * const spi1_parents[] = {
171 "clkxtal",
172 "syspll3_d2",
173 "clkxtal",
174 "syspll4_d4",
175 "syspll4_d2",
176 "univpll2_d4",
177 "univpll1_d8",
178 "clkxtal"
179 };
180
181 static const char * const msdc30_0_parents[] = {
182 "clkxtal",
183 "univpll2_d16",
184 "univ48m"
185 };
186
187 static const char * const a1sys_hp_parents[] = {
188 "clkxtal",
189 "aud1pll_ck",
190 "aud2pll_ck",
191 "clkxtal"
192 };
193
194 static const char * const intdir_parents[] = {
195 "clkxtal",
196 "syspll_d2",
197 "univpll_d2",
198 "sgmiipll_ck"
199 };
200
201 static const char * const aud_intbus_parents[] = {
202 "clkxtal",
203 "syspll1_d4",
204 "syspll4_d2",
205 "syspll3_d2"
206 };
207
208 static const char * const pmicspi_parents[] = {
209 "clkxtal",
210 "clk_null",
211 "clk_null",
212 "clk_null",
213 "clk_null",
214 "univpll2_d16"
215 };
216
217 static const char * const atb_parents[] = {
218 "clkxtal",
219 "syspll1_d2",
220 "syspll_d5"
221 };
222
223 static const char * const audio_parents[] = {
224 "clkxtal",
225 "syspll3_d4",
226 "syspll4_d4",
227 "univpll1_d16"
228 };
229
230 static const char * const usb20_parents[] = {
231 "clkxtal",
232 "univpll3_d4",
233 "syspll1_d8",
234 "clkxtal"
235 };
236
237 static const char * const aud1_parents[] = {
238 "clkxtal",
239 "aud1pll_ck"
240 };
241
242 static const char * const aud2_parents[] = {
243 "clkxtal",
244 "aud2pll_ck"
245 };
246
247 static const char * const asm_l_parents[] = {
248 "clkxtal",
249 "syspll_d5",
250 "univpll2_d2",
251 "univpll2_d4"
252 };
253
254 static const char * const apll1_ck_parents[] = {
255 "aud1_sel",
256 "aud2_sel"
257 };
258
259 static const char * const peribus_ck_parents[] = {
260 "syspll1_d8",
261 "syspll1_d4"
262 };
263
264 static const struct mtk_gate_regs apmixed_cg_regs = {
265 .set_ofs = 0x8,
266 .clr_ofs = 0x8,
267 .sta_ofs = 0x8,
268 };
269
270 static const struct mtk_gate_regs infra_cg_regs = {
271 .set_ofs = 0x40,
272 .clr_ofs = 0x44,
273 .sta_ofs = 0x48,
274 };
275
276 static const struct mtk_gate_regs top0_cg_regs = {
277 .set_ofs = 0x120,
278 .clr_ofs = 0x120,
279 .sta_ofs = 0x120,
280 };
281
282 static const struct mtk_gate_regs top1_cg_regs = {
283 .set_ofs = 0x128,
284 .clr_ofs = 0x128,
285 .sta_ofs = 0x128,
286 };
287
288 static const struct mtk_gate_regs peri0_cg_regs = {
289 .set_ofs = 0x8,
290 .clr_ofs = 0x10,
291 .sta_ofs = 0x18,
292 };
293
294 static const struct mtk_gate_regs peri1_cg_regs = {
295 .set_ofs = 0xC,
296 .clr_ofs = 0x14,
297 .sta_ofs = 0x1C,
298 };
299
300 static const struct mtk_pll_data plls[] = {
301 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
302 PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
303 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
304 HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
305 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
306 HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
307 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
308 0, 21, 0x0300, 1, 0, 0x0304, 0),
309 PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0,
310 0, 21, 0x0314, 1, 0, 0x0318, 0),
311 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0,
312 0, 31, 0x0324, 1, 0, 0x0328, 0),
313 PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0,
314 0, 31, 0x0334, 1, 0, 0x0338, 0),
315 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0,
316 0, 21, 0x0344, 1, 0, 0x0348, 0),
317 PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
318 0, 21, 0x0358, 1, 0, 0x035C, 0),
319 };
320
321 static const struct mtk_gate apmixed_clks[] = {
322 GATE_APMIXED_AO(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
323 };
324
325 static const struct mtk_gate infra_clks[] = {
326 GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
327 GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
328 GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
329 GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
330 GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
331 GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
332 };
333
334 static const struct mtk_fixed_clk top_fixed_clks[] = {
335 FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
336 31250000),
337 FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
338 31250000),
339 FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
340 125000000),
341 FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
342 125000000),
343 FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
344 250000000),
345 FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
346 250000000),
347 FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
348 33333333),
349 FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
350 50000000),
351 FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
352 50000000),
353 FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
354 50000000),
355 };
356
357 static const struct mtk_fixed_factor top_divs[] = {
358 FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
359 FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
360 FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
361 FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
362 FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
363 FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
364 FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
365 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
366 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
367 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
368 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
369 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
370 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
371 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
372 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
373 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
374 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
375 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
376 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
377 FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
378 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
379 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
380 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
381 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
382 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
383 FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32),
384 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
385 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
386 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
387 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
388 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
389 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
390 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
391 FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
392 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
393 FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
394 FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
395 FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1),
396 FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
397 FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1),
398 FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1),
399 FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2),
400 FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4),
401 FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
402 FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
403 FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
404 };
405
406 static const struct mtk_gate top_clks[] = {
407 /* TOP0 */
408 GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
409 GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
410 GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
411 2),
412 GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
413 3),
414 GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
415 4),
416 GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
417 5),
418
419 /* TOP1 */
420 GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
421 GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16),
422 };
423
424 static const struct mtk_clk_divider top_adj_divs[] = {
425 DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel",
426 0x120, 24, 3),
427 DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel",
428 0x120, 28, 3),
429 DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel",
430 0x124, 0, 7),
431 DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel",
432 0x124, 8, 7),
433 DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck",
434 0x124, 16, 7),
435 DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel",
436 0x124, 24, 7),
437 DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel",
438 0x128, 8, 7),
439 DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel",
440 0x128, 24, 7),
441 };
442
443 static const struct mtk_gate peri_clks[] = {
444 /* PERI0 */
445 GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
446 GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
447 GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
448 GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
449 GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
450 GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
451 GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
452 GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
453 GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
454 GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
455 GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
456 GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
457 GATE_PERI0_AO(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
458 GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
459 GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
460 GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
461 GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21),
462 GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22),
463 GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23),
464 GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24),
465 GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25),
466 GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26),
467 GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27),
468 GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28),
469 GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29),
470 GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30),
471 GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31),
472
473 /* PERI1 */
474 GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1),
475 GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
476 };
477
478 static struct mtk_composite infra_muxes[] = {
479 MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents,
480 0x000, 2, 2),
481 };
482
483 static struct mtk_composite top_muxes[] = {
484 /* CLK_CFG_0 */
485 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
486 0x040, 0, 3, 7, CLK_IS_CRITICAL),
487 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
488 0x040, 8, 1, 15, CLK_IS_CRITICAL),
489 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
490 0x040, 16, 1, 23, CLK_IS_CRITICAL),
491 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
492 0x040, 24, 3, 31),
493
494 /* CLK_CFG_1 */
495 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
496 0x050, 0, 2, 7),
497 MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
498 0x050, 8, 1, 15),
499 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
500 0x050, 16, 4, 23),
501 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
502 0x050, 24, 3, 31),
503
504 /* CLK_CFG_2 */
505 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
506 0x060, 0, 1, 7),
507 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
508 0x060, 8, 3, 15),
509 MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
510 0x060, 16, 3, 23),
511 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
512 0x060, 24, 3, 31),
513
514 /* CLK_CFG_3 */
515 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
516 0x070, 0, 3, 7),
517 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
518 0x070, 8, 3, 15),
519 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
520 0x070, 16, 2, 23),
521 MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents,
522 0x070, 24, 2, 31),
523
524 /* CLK_CFG_4 */
525 MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
526 0x080, 0, 2, 7),
527 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
528 0x080, 8, 2, 15),
529 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
530 0x080, 16, 3, 23),
531 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
532 0x080, 24, 2, 31),
533
534 /* CLK_CFG_5 */
535 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
536 0x090, 0, 2, 7),
537 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
538 0x090, 8, 3, 15),
539 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
540 0x090, 16, 2, 23),
541 MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
542 0x090, 24, 2, 31),
543
544 /* CLK_CFG_6 */
545 MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
546 0x0A0, 0, 1, 7),
547 MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
548 0x0A0, 8, 1, 15),
549 MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents,
550 0x0A0, 16, 1, 23),
551 MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
552 0x0A0, 24, 1, 31),
553
554 /* CLK_CFG_7 */
555 MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents,
556 0x0B0, 0, 2, 7),
557 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents,
558 0x0B0, 8, 2, 15),
559 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents,
560 0x0B0, 16, 2, 23),
561
562 /* CLK_AUDDIV_0 */
563 MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents,
564 0x120, 6, 1),
565 MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents,
566 0x120, 7, 1),
567 MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents,
568 0x120, 8, 1),
569 MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents,
570 0x120, 9, 1),
571 MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents,
572 0x120, 10, 1),
573 MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents,
574 0x120, 11, 1),
575 };
576
577 static struct mtk_composite peri_muxes[] = {
578 /* PERI_GLOBALCON_CKSEL */
579 MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
580 };
581
582 static u16 infrasys_rst_ofs[] = { 0x30, };
583 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
584
585 static const struct mtk_clk_rst_desc clk_rst_desc[] = {
586 /* infrasys */
587 {
588 .version = MTK_RST_SIMPLE,
589 .rst_bank_ofs = infrasys_rst_ofs,
590 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
591 },
592 /* pericfg */
593 {
594 .version = MTK_RST_SIMPLE,
595 .rst_bank_ofs = pericfg_rst_ofs,
596 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
597 },
598 };
599
mtk_topckgen_init(struct platform_device * pdev)600 static int mtk_topckgen_init(struct platform_device *pdev)
601 {
602 struct clk_hw_onecell_data *clk_data;
603 void __iomem *base;
604 struct device_node *node = pdev->dev.of_node;
605
606 base = devm_platform_ioremap_resource(pdev, 0);
607 if (IS_ERR(base))
608 return PTR_ERR(base);
609
610 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
611
612 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
613 clk_data);
614
615 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
616 clk_data);
617
618 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
619 base, &mt7622_clk_lock, clk_data);
620
621 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
622 base, &mt7622_clk_lock, clk_data);
623
624 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
625 clk_data);
626
627 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
628 }
629
mtk_infrasys_init(struct platform_device * pdev)630 static int mtk_infrasys_init(struct platform_device *pdev)
631 {
632 struct device_node *node = pdev->dev.of_node;
633 struct clk_hw_onecell_data *clk_data;
634 int r;
635
636 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
637
638 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
639 clk_data);
640
641 mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
642 clk_data);
643
644 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
645 clk_data);
646 if (r)
647 return r;
648
649 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
650
651 return 0;
652 }
653
mtk_apmixedsys_init(struct platform_device * pdev)654 static int mtk_apmixedsys_init(struct platform_device *pdev)
655 {
656 struct clk_hw_onecell_data *clk_data;
657 struct device_node *node = pdev->dev.of_node;
658
659 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
660 if (!clk_data)
661 return -ENOMEM;
662
663 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
664 clk_data);
665
666 mtk_clk_register_gates(node, apmixed_clks,
667 ARRAY_SIZE(apmixed_clks), clk_data);
668
669 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
670 }
671
mtk_pericfg_init(struct platform_device * pdev)672 static int mtk_pericfg_init(struct platform_device *pdev)
673 {
674 struct clk_hw_onecell_data *clk_data;
675 void __iomem *base;
676 int r;
677 struct device_node *node = pdev->dev.of_node;
678
679 base = devm_platform_ioremap_resource(pdev, 0);
680 if (IS_ERR(base))
681 return PTR_ERR(base);
682
683 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
684
685 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
686 clk_data);
687
688 mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
689 &mt7622_clk_lock, clk_data);
690
691 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
692 if (r)
693 return r;
694
695 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
696
697 return 0;
698 }
699
700 static const struct of_device_id of_match_clk_mt7622[] = {
701 {
702 .compatible = "mediatek,mt7622-apmixedsys",
703 .data = mtk_apmixedsys_init,
704 }, {
705 .compatible = "mediatek,mt7622-infracfg",
706 .data = mtk_infrasys_init,
707 }, {
708 .compatible = "mediatek,mt7622-topckgen",
709 .data = mtk_topckgen_init,
710 }, {
711 .compatible = "mediatek,mt7622-pericfg",
712 .data = mtk_pericfg_init,
713 }, {
714 /* sentinel */
715 }
716 };
717
clk_mt7622_probe(struct platform_device * pdev)718 static int clk_mt7622_probe(struct platform_device *pdev)
719 {
720 int (*clk_init)(struct platform_device *);
721 int r;
722
723 clk_init = of_device_get_match_data(&pdev->dev);
724 if (!clk_init)
725 return -EINVAL;
726
727 r = clk_init(pdev);
728 if (r)
729 dev_err(&pdev->dev,
730 "could not register clock provider: %s: %d\n",
731 pdev->name, r);
732
733 return r;
734 }
735
736 static struct platform_driver clk_mt7622_drv = {
737 .probe = clk_mt7622_probe,
738 .driver = {
739 .name = "clk-mt7622",
740 .of_match_table = of_match_clk_mt7622,
741 },
742 };
743
clk_mt7622_init(void)744 static int clk_mt7622_init(void)
745 {
746 return platform_driver_register(&clk_mt7622_drv);
747 }
748
749 arch_initcall(clk_mt7622_init);
750