1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de>
4 */
5
6 #include <linux/module.h>
7 #include <linux/clk.h>
8 #include <linux/clkdev.h>
9 #include <linux/io.h>
10 #include <linux/err.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <soc/imx/revision.h>
14 #include <soc/imx/timer.h>
15 #include <asm/irq.h>
16
17 #include "clk.h"
18
19 #define MX31_CCM_BASE_ADDR 0x53f80000
20 #define MX31_GPT1_BASE_ADDR 0x53f90000
21 #define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
22
23 #define MXC_CCM_CCMR 0x00
24 #define MXC_CCM_PDR0 0x04
25 #define MXC_CCM_PDR1 0x08
26 #define MXC_CCM_MPCTL 0x10
27 #define MXC_CCM_UPCTL 0x14
28 #define MXC_CCM_SRPCTL 0x18
29 #define MXC_CCM_CGR0 0x20
30 #define MXC_CCM_CGR1 0x24
31 #define MXC_CCM_CGR2 0x28
32 #define MXC_CCM_PMCR0 0x5c
33
34 static const char *mcu_main_sel[] = { "spll", "mpll", };
35 static const char *per_sel[] = { "per_div", "ipg", };
36 static const char *csi_sel[] = { "upll", "spll", };
37 static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
38
39 enum mx31_clks {
40 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg,
41 per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
42 fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
43 iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
44 uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
45 mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate,
46 sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate,
47 uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate,
48 gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max
49 };
50
51 static struct clk *clk[clk_max];
52 static struct clk_onecell_data clk_data;
53
_mx31_clocks_init(void __iomem * base,unsigned long fref)54 static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref)
55 {
56 clk[dummy] = imx_clk_fixed("dummy", 0);
57 clk[ckih] = imx_clk_fixed("ckih", fref);
58 clk[ckil] = imx_clk_fixed("ckil", 32768);
59 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL);
60 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL);
61 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL);
62 clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
63 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3);
64 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3);
65 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3);
66 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2);
67 clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5);
68 clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));
69 clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel));
70 clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel));
71 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9);
72 clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2);
73 clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3);
74 clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3);
75 clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6);
76 clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0);
77 clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2);
78 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4);
79 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6);
80 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8);
81 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10);
82 clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12);
83 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14);
84 clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16);
85 clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18);
86 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20);
87 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22);
88 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24);
89 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26);
90 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28);
91 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30);
92 clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0);
93 clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2);
94 clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4);
95 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6);
96 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8);
97 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10);
98 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12);
99 clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14);
100 clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16);
101 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18);
102 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20);
103 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22);
104 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24);
105 clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26);
106 clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28);
107 clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30);
108 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0);
109 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2);
110 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4);
111 clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6);
112 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8);
113 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
114 clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
115
116 imx_check_clocks(clk, ARRAY_SIZE(clk));
117
118 clk_set_parent(clk[csi], clk[upll]);
119 clk_prepare_enable(clk[emi_gate]);
120 clk_prepare_enable(clk[iim_gate]);
121 mx31_revision();
122 clk_disable_unprepare(clk[iim_gate]);
123 }
124
mx31_clocks_init_dt(struct device_node * np)125 static void __init mx31_clocks_init_dt(struct device_node *np)
126 {
127 struct device_node *osc_np;
128 u32 fref = 26000000; /* default */
129 void __iomem *ccm;
130
131 for_each_compatible_node(osc_np, NULL, "fixed-clock") {
132 if (!of_device_is_compatible(osc_np, "fsl,imx-osc26m"))
133 continue;
134
135 if (!of_property_read_u32(osc_np, "clock-frequency", &fref)) {
136 of_node_put(osc_np);
137 break;
138 }
139 }
140
141 ccm = of_iomap(np, 0);
142 if (!ccm)
143 panic("%s: failed to map registers\n", __func__);
144
145 _mx31_clocks_init(ccm, fref);
146
147 clk_data.clks = clk;
148 clk_data.clk_num = ARRAY_SIZE(clk);
149 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
150 }
151
152 CLK_OF_DECLARE(imx31_ccm, "fsl,imx31-ccm", mx31_clocks_init_dt);
153