1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: James Liao <jamesjj.liao@mediatek.com>
5 * Copyright (c) 2023 Collabora, Ltd.
6 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/slab.h>
13 #include <linux/mfd/syscon.h>
14 #include <dt-bindings/clock/mt8135-clk.h>
15
16 #include "clk-gate.h"
17 #include "clk-mtk.h"
18 #include "clk-pll.h"
19
20 static DEFINE_SPINLOCK(mt8135_clk_lock);
21
22 static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
23 FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
24 FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
25 FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
26 FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
27 };
28
29 static const struct mtk_fixed_factor top_divs[] __initconst = {
30 FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2),
31 FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3),
32 FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5),
33 FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7),
34
35 FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
36 FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
37 FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5),
38 FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7),
39 FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26),
40
41 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
42 FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3),
43 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
44 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
45 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2),
46 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2),
47
48 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1),
49 FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2),
50 FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3),
51 FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4),
52 FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5),
53 FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6),
54 FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8),
55 FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12),
56
57 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1),
58
59 FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1),
60 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1),
61
62 FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1),
63
64 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
65 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
66 FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6),
67 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
68 FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
69
70 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
71 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
72 FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6),
73 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
74
75 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1),
76 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
77 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1),
78 FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2),
79 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
80
81 FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1),
82 FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4),
83 FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8),
84 FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16),
85 FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24),
86
87 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
88 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
89 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
90
91 FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1),
92 FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1),
93
94 FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1),
95
96 FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2),
97 FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3),
98
99 FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2),
100 FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4),
101
102 FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
103 };
104
105 static const char * const axi_parents[] __initconst = {
106 "clk26m",
107 "syspll_d3",
108 "syspll_d4",
109 "syspll_d6",
110 "univpll_d5",
111 "univpll2_d2",
112 "syspll_d3p5"
113 };
114
115 static const char * const smi_parents[] __initconst = {
116 "clk26m",
117 "clkph_mck",
118 "syspll_d2p5",
119 "syspll_d3",
120 "syspll_d8",
121 "univpll_d5",
122 "univpll1_d2",
123 "univpll1_d6",
124 "mmpll_d3",
125 "mmpll_d4",
126 "mmpll_d5",
127 "mmpll_d6",
128 "mmpll_d7",
129 "vdecpll",
130 "lvdspll"
131 };
132
133 static const char * const mfg_parents[] __initconst = {
134 "clk26m",
135 "univpll1_d4",
136 "syspll_d2",
137 "syspll_d2p5",
138 "syspll_d3",
139 "univpll_d5",
140 "univpll1_d2",
141 "mmpll_d2",
142 "mmpll_d3",
143 "mmpll_d4",
144 "mmpll_d5",
145 "mmpll_d6",
146 "mmpll_d7"
147 };
148
149 static const char * const irda_parents[] __initconst = {
150 "clk26m",
151 "univpll2_d8",
152 "univpll1_d6"
153 };
154
155 static const char * const cam_parents[] __initconst = {
156 "clk26m",
157 "syspll_d3",
158 "syspll_d3p5",
159 "syspll_d4",
160 "univpll_d5",
161 "univpll2_d2",
162 "univpll_d7",
163 "univpll1_d4"
164 };
165
166 static const char * const aud_intbus_parents[] __initconst = {
167 "clk26m",
168 "syspll_d6",
169 "univpll_d10"
170 };
171
172 static const char * const jpg_parents[] __initconst = {
173 "clk26m",
174 "syspll_d5",
175 "syspll_d4",
176 "syspll_d3",
177 "univpll_d7",
178 "univpll2_d2",
179 "univpll_d5"
180 };
181
182 static const char * const disp_parents[] __initconst = {
183 "clk26m",
184 "syspll_d3p5",
185 "syspll_d3",
186 "univpll2_d2",
187 "univpll_d5",
188 "univpll1_d2",
189 "lvdspll",
190 "vdecpll"
191 };
192
193 static const char * const msdc30_parents[] __initconst = {
194 "clk26m",
195 "syspll_d6",
196 "syspll_d5",
197 "univpll1_d4",
198 "univpll2_d4",
199 "msdcpll"
200 };
201
202 static const char * const usb20_parents[] __initconst = {
203 "clk26m",
204 "univpll2_d6",
205 "univpll1_d10"
206 };
207
208 static const char * const venc_parents[] __initconst = {
209 "clk26m",
210 "syspll_d3",
211 "syspll_d8",
212 "univpll_d5",
213 "univpll1_d6",
214 "mmpll_d4",
215 "mmpll_d5",
216 "mmpll_d6"
217 };
218
219 static const char * const spi_parents[] __initconst = {
220 "clk26m",
221 "syspll_d6",
222 "syspll_d8",
223 "syspll_d10",
224 "univpll1_d6",
225 "univpll1_d8"
226 };
227
228 static const char * const uart_parents[] __initconst = {
229 "clk26m",
230 "univpll2_d8"
231 };
232
233 static const char * const mem_parents[] __initconst = {
234 "clk26m",
235 "clkph_mck"
236 };
237
238 static const char * const camtg_parents[] __initconst = {
239 "clk26m",
240 "univpll_d26",
241 "univpll1_d6",
242 "syspll_d16",
243 "syspll_d8"
244 };
245
246 static const char * const audio_parents[] __initconst = {
247 "clk26m",
248 "syspll_d24"
249 };
250
251 static const char * const fix_parents[] __initconst = {
252 "rtc32k",
253 "clk26m",
254 "univpll_d5",
255 "univpll_d7",
256 "univpll1_d2",
257 "univpll1_d4",
258 "univpll1_d6",
259 "univpll1_d8"
260 };
261
262 static const char * const vdec_parents[] __initconst = {
263 "clk26m",
264 "vdecpll",
265 "clkph_mck",
266 "syspll_d2p5",
267 "syspll_d3",
268 "syspll_d3p5",
269 "syspll_d4",
270 "syspll_d5",
271 "syspll_d6",
272 "syspll_d8",
273 "univpll1_d2",
274 "univpll2_d2",
275 "univpll_d7",
276 "univpll_d10",
277 "univpll2_d4",
278 "lvdspll"
279 };
280
281 static const char * const ddrphycfg_parents[] __initconst = {
282 "clk26m",
283 "axi_sel",
284 "syspll_d12"
285 };
286
287 static const char * const dpilvds_parents[] __initconst = {
288 "clk26m",
289 "lvdspll",
290 "lvdspll_d2",
291 "lvdspll_d4",
292 "lvdspll_d8"
293 };
294
295 static const char * const pmicspi_parents[] __initconst = {
296 "clk26m",
297 "univpll2_d6",
298 "syspll_d8",
299 "syspll_d10",
300 "univpll1_d10",
301 "mempll_mck_d4",
302 "univpll_d26",
303 "syspll_d24"
304 };
305
306 static const char * const smi_mfg_as_parents[] __initconst = {
307 "clk26m",
308 "smi_sel",
309 "mfg_sel",
310 "mem_sel"
311 };
312
313 static const char * const gcpu_parents[] __initconst = {
314 "clk26m",
315 "syspll_d4",
316 "univpll_d7",
317 "syspll_d5",
318 "syspll_d6"
319 };
320
321 static const char * const dpi1_parents[] __initconst = {
322 "clk26m",
323 "tvhdmi_h_ck",
324 "tvhdmi_d2",
325 "tvhdmi_d4"
326 };
327
328 static const char * const cci_parents[] __initconst = {
329 "clk26m",
330 "mainpll_537p3m",
331 "univpll_d3",
332 "syspll_d2p5",
333 "syspll_d3",
334 "syspll_d5"
335 };
336
337 static const char * const apll_parents[] __initconst = {
338 "clk26m",
339 "apll_ck",
340 "apll_d4",
341 "apll_d8",
342 "apll_d16",
343 "apll_d24"
344 };
345
346 static const char * const hdmipll_parents[] __initconst = {
347 "clk26m",
348 "hdmitx_clkdig_cts",
349 "hdmitx_clkdig_d2",
350 "hdmitx_clkdig_d3"
351 };
352
353 static const struct mtk_composite top_muxes[] __initconst = {
354 /* CLK_CFG_0 */
355 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
356 0x0140, 0, 3, INVALID_MUX_GATE_BIT),
357 MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),
358 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
359 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31),
360 /* CLK_CFG_1 */
361 MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),
362 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
363 0x0144, 8, 2, 15),
364 MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),
365 MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31),
366 /* CLK_CFG_2 */
367 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
368 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),
369 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23),
370 MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31),
371 /* CLK_CFG_3 */
372 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7),
373 /* CLK_CFG_4 */
374 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
375 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
376 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
377 /* CLK_CFG_6 */
378 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
379 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15),
380 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31),
381 /* CLK_CFG_7 */
382 MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7),
383 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
384 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
385 0x015c, 16, 2, 23),
386 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31),
387 /* CLK_CFG_8 */
388 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7),
389 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
390 MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents,
391 0x0164, 16, 2, 23),
392 MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31),
393 /* CLK_CFG_9 */
394 MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7),
395 MUX_GATE_FLAGS(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15, CLK_IS_CRITICAL),
396 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
397 MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31),
398 };
399
400 static const struct mtk_gate_regs infra_cg_regs = {
401 .set_ofs = 0x0040,
402 .clr_ofs = 0x0044,
403 .sta_ofs = 0x0048,
404 };
405
406 #define GATE_ICG(_id, _name, _parent, _shift) \
407 GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
408
409 #define GATE_ICG_AO(_id, _name, _parent, _shift) \
410 GATE_MTK_FLAGS(_id, _name, _parent, &infra_cg_regs, _shift, \
411 &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL)
412
413 static const struct mtk_gate infra_clks[] __initconst = {
414 GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
415 GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
416 GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21),
417 GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20),
418 GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
419 GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15),
420 GATE_ICG_AO(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
421 GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7),
422 GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6),
423 GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5),
424 GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2),
425 GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1),
426 GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0),
427 };
428
429 static const struct mtk_gate_regs peri0_cg_regs = {
430 .set_ofs = 0x0008,
431 .clr_ofs = 0x0010,
432 .sta_ofs = 0x0018,
433 };
434
435 static const struct mtk_gate_regs peri1_cg_regs = {
436 .set_ofs = 0x000c,
437 .clr_ofs = 0x0014,
438 .sta_ofs = 0x001c,
439 };
440
441 #define GATE_PERI0(_id, _name, _parent, _shift) \
442 GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
443
444 #define GATE_PERI1(_id, _name, _parent, _shift) \
445 GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
446
447 static const struct mtk_gate peri_gates[] __initconst = {
448 /* PERI0 */
449 GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31),
450 GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30),
451 GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29),
452 GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28),
453 GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27),
454 GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26),
455 GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25),
456 GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
457 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
458 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
459 GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21),
460 GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20),
461 GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19),
462 GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18),
463 GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17),
464 GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16),
465 GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15),
466 GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14),
467 GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13),
468 GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
469 GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
470 GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
471 GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
472 GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
473 GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
474 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
475 GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
476 GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
477 GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
478 GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
479 GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
480 GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),
481 /* PERI1 */
482 GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8),
483 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7),
484 GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6),
485 GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5),
486 GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4),
487 GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3),
488 GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2),
489 GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1),
490 GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0),
491 };
492
493 static const char * const uart_ck_sel_parents[] __initconst = {
494 "clk26m",
495 "uart_sel",
496 };
497
498 static const struct mtk_composite peri_clks[] __initconst = {
499 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
500 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
501 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
502 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
503 };
504
505 static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
506 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
507
508 static const struct mtk_clk_rst_desc clk_rst_desc[] = {
509 /* infrasys */
510 {
511 .version = MTK_RST_SIMPLE,
512 .rst_bank_ofs = infrasys_rst_ofs,
513 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
514 },
515 /* pericfg */
516 {
517 .version = MTK_RST_SIMPLE,
518 .rst_bank_ofs = pericfg_rst_ofs,
519 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
520 }
521 };
522
mtk_topckgen_init(struct device_node * node)523 static void __init mtk_topckgen_init(struct device_node *node)
524 {
525 struct clk_hw_onecell_data *clk_data;
526 void __iomem *base;
527 int r;
528
529 base = of_iomap(node, 0);
530 if (!base) {
531 pr_err("%s(): ioremap failed\n", __func__);
532 return;
533 }
534
535 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
536
537 mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
538 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
539 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
540 &mt8135_clk_lock, clk_data);
541
542 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
543 if (r)
544 pr_err("%s(): could not register clock provider: %d\n",
545 __func__, r);
546 }
547 CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init);
548
mtk_infrasys_init(struct device_node * node)549 static void __init mtk_infrasys_init(struct device_node *node)
550 {
551 struct clk_hw_onecell_data *clk_data;
552 int r;
553
554 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
555
556 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
557 clk_data);
558
559 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
560 if (r)
561 pr_err("%s(): could not register clock provider: %d\n",
562 __func__, r);
563
564 mtk_register_reset_controller(node, &clk_rst_desc[0]);
565 }
566 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
567
mtk_pericfg_init(struct device_node * node)568 static void __init mtk_pericfg_init(struct device_node *node)
569 {
570 struct clk_hw_onecell_data *clk_data;
571 int r;
572 void __iomem *base;
573
574 base = of_iomap(node, 0);
575 if (!base) {
576 pr_err("%s(): ioremap failed\n", __func__);
577 return;
578 }
579
580 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
581
582 mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
583 clk_data);
584 mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
585 &mt8135_clk_lock, clk_data);
586
587 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
588 if (r)
589 pr_err("%s(): could not register clock provider: %d\n",
590 __func__, r);
591
592 mtk_register_reset_controller(node, &clk_rst_desc[1]);
593 }
594 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
595
596 #define MT8135_PLL_FMAX (2000 * MHZ)
597 #define CON0_MT8135_RST_BAR BIT(27)
598
599 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
600 .id = _id, \
601 .name = _name, \
602 .reg = _reg, \
603 .pwr_reg = _pwr_reg, \
604 .en_mask = _en_mask, \
605 .flags = _flags, \
606 .rst_bar_mask = CON0_MT8135_RST_BAR, \
607 .fmax = MT8135_PLL_FMAX, \
608 .pcwbits = _pcwbits, \
609 .pd_reg = _pd_reg, \
610 .pd_shift = _pd_shift, \
611 .tuner_reg = _tuner_reg, \
612 .pcw_reg = _pcw_reg, \
613 .pcw_shift = _pcw_shift, \
614 }
615
616 static const struct mtk_pll_data plls[] = {
617 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0),
618 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
619 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),
620 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),
621 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),
622 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
623 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0),
624 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
625 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
626 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
627 };
628
mtk_apmixedsys_init(struct device_node * node)629 static void __init mtk_apmixedsys_init(struct device_node *node)
630 {
631 struct clk_hw_onecell_data *clk_data;
632
633 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
634 if (!clk_data)
635 return;
636
637 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
638 }
639 CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys",
640 mtk_apmixedsys_init);
641