1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2018, Craig Tatlor.
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/bitops.h>
9 #include <linux/err.h>
10 #include <linux/platform_device.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/clk-provider.h>
15 #include <linux/regmap.h>
16 #include <linux/reset-controller.h>
17
18 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
19
20 #include "common.h"
21 #include "clk-regmap.h"
22 #include "clk-alpha-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
25 #include "reset.h"
26 #include "gdsc.h"
27
28 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
29
30 enum {
31 P_XO,
32 P_SLEEP_CLK,
33 P_GPLL0,
34 P_GPLL1,
35 P_GPLL4,
36 P_GPLL0_EARLY_DIV,
37 P_GPLL1_EARLY_DIV,
38 };
39
40 static struct clk_fixed_factor xo = {
41 .mult = 1,
42 .div = 1,
43 .hw.init = &(struct clk_init_data){
44 .name = "xo",
45 .parent_data = &(const struct clk_parent_data) {
46 .fw_name = "xo"
47 },
48 .num_parents = 1,
49 .ops = &clk_fixed_factor_ops,
50 },
51 };
52
53 static struct clk_alpha_pll gpll0_early = {
54 .offset = 0x0,
55 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
56 .clkr = {
57 .enable_reg = 0x52000,
58 .enable_mask = BIT(0),
59 .hw.init = &(struct clk_init_data){
60 .name = "gpll0_early",
61 .parent_data = &(const struct clk_parent_data){
62 .fw_name = "xo",
63 },
64 .num_parents = 1,
65 .ops = &clk_alpha_pll_ops,
66 },
67 },
68 };
69
70 static struct clk_fixed_factor gpll0_early_div = {
71 .mult = 1,
72 .div = 2,
73 .hw.init = &(struct clk_init_data){
74 .name = "gpll0_early_div",
75 .parent_hws = (const struct clk_hw*[]){
76 &gpll0_early.clkr.hw,
77 },
78 .num_parents = 1,
79 .ops = &clk_fixed_factor_ops,
80 },
81 };
82
83 static struct clk_alpha_pll_postdiv gpll0 = {
84 .offset = 0x00000,
85 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
86 .clkr.hw.init = &(struct clk_init_data){
87 .name = "gpll0",
88 .parent_hws = (const struct clk_hw*[]){
89 &gpll0_early.clkr.hw,
90 },
91 .num_parents = 1,
92 .ops = &clk_alpha_pll_postdiv_ops,
93 },
94 };
95
96 static struct clk_alpha_pll gpll1_early = {
97 .offset = 0x1000,
98 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
99 .clkr = {
100 .enable_reg = 0x52000,
101 .enable_mask = BIT(1),
102 .hw.init = &(struct clk_init_data){
103 .name = "gpll1_early",
104 .parent_data = &(const struct clk_parent_data){
105 .fw_name = "xo",
106 },
107 .num_parents = 1,
108 .ops = &clk_alpha_pll_ops,
109 },
110 },
111 };
112
113 static struct clk_fixed_factor gpll1_early_div = {
114 .mult = 1,
115 .div = 2,
116 .hw.init = &(struct clk_init_data){
117 .name = "gpll1_early_div",
118 .parent_hws = (const struct clk_hw*[]){
119 &gpll1_early.clkr.hw,
120 },
121 .num_parents = 1,
122 .ops = &clk_fixed_factor_ops,
123 },
124 };
125
126 static struct clk_alpha_pll_postdiv gpll1 = {
127 .offset = 0x1000,
128 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
129 .clkr.hw.init = &(struct clk_init_data){
130 .name = "gpll1",
131 .parent_hws = (const struct clk_hw*[]){
132 &gpll1_early.clkr.hw,
133 },
134 .num_parents = 1,
135 .ops = &clk_alpha_pll_postdiv_ops,
136 },
137 };
138
139 static struct clk_alpha_pll gpll4_early = {
140 .offset = 0x77000,
141 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
142 .clkr = {
143 .enable_reg = 0x52000,
144 .enable_mask = BIT(4),
145 .hw.init = &(struct clk_init_data){
146 .name = "gpll4_early",
147 .parent_data = &(const struct clk_parent_data){
148 .fw_name = "xo",
149 },
150 .num_parents = 1,
151 .ops = &clk_alpha_pll_ops,
152 },
153 },
154 };
155
156 static struct clk_alpha_pll_postdiv gpll4 = {
157 .offset = 0x77000,
158 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
159 .clkr.hw.init = &(struct clk_init_data)
160 {
161 .name = "gpll4",
162 .parent_hws = (const struct clk_hw*[]){
163 &gpll4_early.clkr.hw,
164 },
165 .num_parents = 1,
166 .ops = &clk_alpha_pll_postdiv_ops,
167 },
168 };
169
170 static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = {
171 { P_XO, 0 },
172 { P_GPLL0, 1 },
173 { P_GPLL0_EARLY_DIV, 6 },
174 };
175
176 static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div[] = {
177 { .fw_name = "xo" },
178 { .hw = &gpll0.clkr.hw },
179 { .hw = &gpll0_early_div.hw },
180 };
181
182 static const struct parent_map gcc_parent_map_xo_gpll0[] = {
183 { P_XO, 0 },
184 { P_GPLL0, 1 },
185 };
186
187 static const struct clk_parent_data gcc_parent_data_xo_gpll0[] = {
188 { .fw_name = "xo" },
189 { .hw = &gpll0.clkr.hw },
190 };
191
192 static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = {
193 { P_XO, 0 },
194 { P_GPLL0, 1 },
195 { P_SLEEP_CLK, 5 },
196 { P_GPLL0_EARLY_DIV, 6 },
197 };
198
199 static const struct clk_parent_data gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div[] = {
200 { .fw_name = "xo" },
201 { .hw = &gpll0.clkr.hw },
202 { .fw_name = "sleep_clk" },
203 { .hw = &gpll0_early_div.hw },
204 };
205
206 static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {
207 { P_XO, 0 },
208 { P_SLEEP_CLK, 5 },
209 };
210
211 static const struct clk_parent_data gcc_parent_data_xo_sleep_clk[] = {
212 { .fw_name = "xo" },
213 { .fw_name = "sleep_clk" },
214 };
215
216 static const struct parent_map gcc_parent_map_xo_gpll4[] = {
217 { P_XO, 0 },
218 { P_GPLL4, 5 },
219 };
220
221 static const struct clk_parent_data gcc_parent_data_xo_gpll4[] = {
222 { .fw_name = "xo" },
223 { .hw = &gpll4.clkr.hw },
224 };
225
226 static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
227 { P_XO, 0 },
228 { P_GPLL0, 1 },
229 { P_GPLL0_EARLY_DIV, 3 },
230 { P_GPLL1, 4 },
231 { P_GPLL4, 5 },
232 { P_GPLL1_EARLY_DIV, 6 },
233 };
234
235 static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
236 { .fw_name = "xo" },
237 { .hw = &gpll0.clkr.hw },
238 { .hw = &gpll0_early_div.hw },
239 { .hw = &gpll1.clkr.hw },
240 { .hw = &gpll4.clkr.hw },
241 { .hw = &gpll1_early_div.hw },
242 };
243
244 static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = {
245 { P_XO, 0 },
246 { P_GPLL0, 1 },
247 { P_GPLL4, 5 },
248 { P_GPLL0_EARLY_DIV, 6 },
249 };
250
251 static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div[] = {
252 { .fw_name = "xo" },
253 { .hw = &gpll0.clkr.hw },
254 { .hw = &gpll4.clkr.hw },
255 { .hw = &gpll0_early_div.hw },
256 };
257
258 static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = {
259 { P_XO, 0 },
260 { P_GPLL0, 1 },
261 { P_GPLL0_EARLY_DIV, 2 },
262 { P_GPLL4, 5 },
263 };
264
265 static const struct clk_parent_data gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4[] = {
266 { .fw_name = "xo" },
267 { .hw = &gpll0.clkr.hw },
268 { .hw = &gpll0_early_div.hw },
269 { .hw = &gpll4.clkr.hw },
270 };
271
272 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
273 F(19200000, P_XO, 1, 0, 0),
274 F(50000000, P_GPLL0, 12, 0, 0),
275 { }
276 };
277
278 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
279 .cmd_rcgr = 0x19020,
280 .mnd_width = 0,
281 .hid_width = 5,
282 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
283 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
284 .clkr.hw.init = &(struct clk_init_data){
285 .name = "blsp1_qup1_i2c_apps_clk_src",
286 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
287 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
288 .ops = &clk_rcg2_ops,
289 },
290 };
291
292 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
293 F(960000, P_XO, 10, 1, 2),
294 F(4800000, P_XO, 4, 0, 0),
295 F(9600000, P_XO, 2, 0, 0),
296 F(15000000, P_GPLL0, 10, 1, 4),
297 F(19200000, P_XO, 1, 0, 0),
298 F(25000000, P_GPLL0, 12, 1, 2),
299 F(50000000, P_GPLL0, 12, 0, 0),
300 { }
301 };
302
303 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
304 .cmd_rcgr = 0x1900c,
305 .mnd_width = 8,
306 .hid_width = 5,
307 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
308 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
309 .clkr.hw.init = &(struct clk_init_data){
310 .name = "blsp1_qup1_spi_apps_clk_src",
311 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
312 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
313 .ops = &clk_rcg2_ops,
314 },
315 };
316
317 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
318 .cmd_rcgr = 0x1b020,
319 .mnd_width = 0,
320 .hid_width = 5,
321 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
322 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
323 .clkr.hw.init = &(struct clk_init_data){
324 .name = "blsp1_qup2_i2c_apps_clk_src",
325 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
326 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
327 .ops = &clk_rcg2_ops,
328 },
329 };
330
331 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
332 .cmd_rcgr = 0x1b00c,
333 .mnd_width = 8,
334 .hid_width = 5,
335 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
336 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
337 .clkr.hw.init = &(struct clk_init_data){
338 .name = "blsp1_qup2_spi_apps_clk_src",
339 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
340 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
341 .ops = &clk_rcg2_ops,
342 },
343 };
344
345 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
346 .cmd_rcgr = 0x1d020,
347 .mnd_width = 0,
348 .hid_width = 5,
349 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
350 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
351 .clkr.hw.init = &(struct clk_init_data){
352 .name = "blsp1_qup3_i2c_apps_clk_src",
353 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
354 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
355 .ops = &clk_rcg2_ops,
356 },
357 };
358
359 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
360 .cmd_rcgr = 0x1d00c,
361 .mnd_width = 8,
362 .hid_width = 5,
363 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
364 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
365 .clkr.hw.init = &(struct clk_init_data){
366 .name = "blsp1_qup3_spi_apps_clk_src",
367 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
368 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
369 .ops = &clk_rcg2_ops,
370 },
371 };
372
373 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
374 .cmd_rcgr = 0x1f020,
375 .mnd_width = 0,
376 .hid_width = 5,
377 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
378 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
379 .clkr.hw.init = &(struct clk_init_data){
380 .name = "blsp1_qup4_i2c_apps_clk_src",
381 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
382 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
383 .ops = &clk_rcg2_ops,
384 },
385 };
386
387 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
388 .cmd_rcgr = 0x1f00c,
389 .mnd_width = 8,
390 .hid_width = 5,
391 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
392 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
393 .clkr.hw.init = &(struct clk_init_data){
394 .name = "blsp1_qup4_spi_apps_clk_src",
395 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
396 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
397 .ops = &clk_rcg2_ops,
398 },
399 };
400
401 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
402 F(3686400, P_GPLL0, 1, 96, 15625),
403 F(7372800, P_GPLL0, 1, 192, 15625),
404 F(14745600, P_GPLL0, 1, 384, 15625),
405 F(16000000, P_GPLL0, 5, 2, 15),
406 F(19200000, P_XO, 1, 0, 0),
407 F(24000000, P_GPLL0, 5, 1, 5),
408 F(32000000, P_GPLL0, 1, 4, 75),
409 F(40000000, P_GPLL0, 15, 0, 0),
410 F(46400000, P_GPLL0, 1, 29, 375),
411 F(48000000, P_GPLL0, 12.5, 0, 0),
412 F(51200000, P_GPLL0, 1, 32, 375),
413 F(56000000, P_GPLL0, 1, 7, 75),
414 F(58982400, P_GPLL0, 1, 1536, 15625),
415 F(60000000, P_GPLL0, 10, 0, 0),
416 F(63157895, P_GPLL0, 9.5, 0, 0),
417 { }
418 };
419
420 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
421 .cmd_rcgr = 0x1a00c,
422 .mnd_width = 16,
423 .hid_width = 5,
424 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
425 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
426 .clkr.hw.init = &(struct clk_init_data){
427 .name = "blsp1_uart1_apps_clk_src",
428 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
429 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
430 .ops = &clk_rcg2_ops,
431 },
432 };
433
434 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
435 .cmd_rcgr = 0x1c00c,
436 .mnd_width = 16,
437 .hid_width = 5,
438 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
439 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
440 .clkr.hw.init = &(struct clk_init_data){
441 .name = "blsp1_uart2_apps_clk_src",
442 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
443 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
444 .ops = &clk_rcg2_ops,
445 },
446 };
447
448 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
449 .cmd_rcgr = 0x26020,
450 .mnd_width = 0,
451 .hid_width = 5,
452 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
453 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
454 .clkr.hw.init = &(struct clk_init_data){
455 .name = "blsp2_qup1_i2c_apps_clk_src",
456 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
457 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
458 .ops = &clk_rcg2_ops,
459 },
460 };
461
462 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
463 .cmd_rcgr = 0x2600c,
464 .mnd_width = 8,
465 .hid_width = 5,
466 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
467 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
468 .clkr.hw.init = &(struct clk_init_data){
469 .name = "blsp2_qup1_spi_apps_clk_src",
470 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
471 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
472 .ops = &clk_rcg2_ops,
473 },
474 };
475
476 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
477 .cmd_rcgr = 0x28020,
478 .mnd_width = 0,
479 .hid_width = 5,
480 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
481 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
482 .clkr.hw.init = &(struct clk_init_data){
483 .name = "blsp2_qup2_i2c_apps_clk_src",
484 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
485 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
486 .ops = &clk_rcg2_ops,
487 },
488 };
489
490 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
491 .cmd_rcgr = 0x2800c,
492 .mnd_width = 8,
493 .hid_width = 5,
494 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
495 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
496 .clkr.hw.init = &(struct clk_init_data){
497 .name = "blsp2_qup2_spi_apps_clk_src",
498 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
499 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
500 .ops = &clk_rcg2_ops,
501 },
502 };
503
504 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
505 .cmd_rcgr = 0x2a020,
506 .mnd_width = 0,
507 .hid_width = 5,
508 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
509 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
510 .clkr.hw.init = &(struct clk_init_data){
511 .name = "blsp2_qup3_i2c_apps_clk_src",
512 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
513 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
514 .ops = &clk_rcg2_ops,
515 },
516 };
517
518 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
519 .cmd_rcgr = 0x2a00c,
520 .mnd_width = 8,
521 .hid_width = 5,
522 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
523 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
524 .clkr.hw.init = &(struct clk_init_data){
525 .name = "blsp2_qup3_spi_apps_clk_src",
526 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
527 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
528 .ops = &clk_rcg2_ops,
529 },
530 };
531
532 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
533 .cmd_rcgr = 0x2c020,
534 .mnd_width = 0,
535 .hid_width = 5,
536 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
537 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
538 .clkr.hw.init = &(struct clk_init_data){
539 .name = "blsp2_qup4_i2c_apps_clk_src",
540 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
541 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
542 .ops = &clk_rcg2_ops,
543 },
544 };
545
546 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
547 .cmd_rcgr = 0x2c00c,
548 .mnd_width = 8,
549 .hid_width = 5,
550 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
551 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
552 .clkr.hw.init = &(struct clk_init_data){
553 .name = "blsp2_qup4_spi_apps_clk_src",
554 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
555 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
556 .ops = &clk_rcg2_ops,
557 },
558 };
559
560 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
561 .cmd_rcgr = 0x2700c,
562 .mnd_width = 16,
563 .hid_width = 5,
564 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
565 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
566 .clkr.hw.init = &(struct clk_init_data){
567 .name = "blsp2_uart1_apps_clk_src",
568 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
569 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
570 .ops = &clk_rcg2_ops,
571 },
572 };
573
574 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
575 .cmd_rcgr = 0x2900c,
576 .mnd_width = 16,
577 .hid_width = 5,
578 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
579 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
580 .clkr.hw.init = &(struct clk_init_data){
581 .name = "blsp2_uart2_apps_clk_src",
582 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
583 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
584 .ops = &clk_rcg2_ops,
585 },
586 };
587
588 static const struct freq_tbl ftbl_gp1_clk_src[] = {
589 F(19200000, P_XO, 1, 0, 0),
590 F(100000000, P_GPLL0, 6, 0, 0),
591 F(200000000, P_GPLL0, 3, 0, 0),
592 { }
593 };
594
595 static struct clk_rcg2 gp1_clk_src = {
596 .cmd_rcgr = 0x64004,
597 .mnd_width = 8,
598 .hid_width = 5,
599 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
600 .freq_tbl = ftbl_gp1_clk_src,
601 .clkr.hw.init = &(struct clk_init_data){
602 .name = "gp1_clk_src",
603 .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,
604 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div),
605 .ops = &clk_rcg2_ops,
606 },
607 };
608
609 static struct clk_rcg2 gp2_clk_src = {
610 .cmd_rcgr = 0x65004,
611 .mnd_width = 8,
612 .hid_width = 5,
613 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
614 .freq_tbl = ftbl_gp1_clk_src,
615 .clkr.hw.init = &(struct clk_init_data){
616 .name = "gp2_clk_src",
617 .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,
618 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div),
619 .ops = &clk_rcg2_ops,
620 },
621 };
622
623 static struct clk_rcg2 gp3_clk_src = {
624 .cmd_rcgr = 0x66004,
625 .mnd_width = 8,
626 .hid_width = 5,
627 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
628 .freq_tbl = ftbl_gp1_clk_src,
629 .clkr.hw.init = &(struct clk_init_data){
630 .name = "gp3_clk_src",
631 .parent_data = gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div,
632 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_sleep_clk_gpll0_early_div),
633 .ops = &clk_rcg2_ops,
634 },
635 };
636
637 static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
638 F(300000000, P_GPLL0, 2, 0, 0),
639 F(600000000, P_GPLL0, 1, 0, 0),
640 { }
641 };
642
643 static struct clk_rcg2 hmss_gpll0_clk_src = {
644 .cmd_rcgr = 0x4805c,
645 .mnd_width = 0,
646 .hid_width = 5,
647 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
648 .freq_tbl = ftbl_hmss_gpll0_clk_src,
649 .clkr.hw.init = &(struct clk_init_data){
650 .name = "hmss_gpll0_clk_src",
651 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
652 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
653 .ops = &clk_rcg2_ops,
654 },
655 };
656
657 static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = {
658 F(384000000, P_GPLL4, 4, 0, 0),
659 F(768000000, P_GPLL4, 2, 0, 0),
660 F(1536000000, P_GPLL4, 1, 0, 0),
661 { }
662 };
663
664 static struct clk_rcg2 hmss_gpll4_clk_src = {
665 .cmd_rcgr = 0x48074,
666 .mnd_width = 0,
667 .hid_width = 5,
668 .parent_map = gcc_parent_map_xo_gpll4,
669 .freq_tbl = ftbl_hmss_gpll4_clk_src,
670 .clkr.hw.init = &(struct clk_init_data){
671 .name = "hmss_gpll4_clk_src",
672 .parent_data = gcc_parent_data_xo_gpll4,
673 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll4),
674 .ops = &clk_rcg2_ops,
675 },
676 };
677
678 static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
679 F(19200000, P_XO, 1, 0, 0),
680 { }
681 };
682
683 static struct clk_rcg2 hmss_rbcpr_clk_src = {
684 .cmd_rcgr = 0x48044,
685 .mnd_width = 0,
686 .hid_width = 5,
687 .parent_map = gcc_parent_map_xo_gpll0,
688 .freq_tbl = ftbl_hmss_rbcpr_clk_src,
689 .clkr.hw.init = &(struct clk_init_data){
690 .name = "hmss_rbcpr_clk_src",
691 .parent_data = gcc_parent_data_xo_gpll0,
692 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0),
693 .ops = &clk_rcg2_ops,
694 },
695 };
696
697 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
698 F(60000000, P_GPLL0, 10, 0, 0),
699 { }
700 };
701
702 static struct clk_rcg2 pdm2_clk_src = {
703 .cmd_rcgr = 0x33010,
704 .mnd_width = 0,
705 .hid_width = 5,
706 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
707 .freq_tbl = ftbl_pdm2_clk_src,
708 .clkr.hw.init = &(struct clk_init_data){
709 .name = "pdm2_clk_src",
710 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
711 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
712 .ops = &clk_rcg2_ops,
713 },
714 };
715
716 static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
717 F(19200000, P_XO, 1, 0, 0),
718 F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
719 F(160400000, P_GPLL1, 5, 0, 0),
720 F(267333333, P_GPLL1, 3, 0, 0),
721 { }
722 };
723
724 static struct clk_rcg2 qspi_ser_clk_src = {
725 .cmd_rcgr = 0x4d00c,
726 .mnd_width = 0,
727 .hid_width = 5,
728 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
729 .freq_tbl = ftbl_qspi_ser_clk_src,
730 .clkr.hw.init = &(struct clk_init_data){
731 .name = "qspi_ser_clk_src",
732 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
733 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div),
734 .ops = &clk_rcg2_ops,
735 },
736 };
737
738 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
739 F(144000, P_XO, 16, 3, 25),
740 F(400000, P_XO, 12, 1, 4),
741 F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
742 F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
743 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
744 F(100000000, P_GPLL0, 6, 0, 0),
745 F(192000000, P_GPLL4, 8, 0, 0),
746 F(384000000, P_GPLL4, 4, 0, 0),
747 { }
748 };
749
750 static struct clk_rcg2 sdcc1_apps_clk_src = {
751 .cmd_rcgr = 0x1602c,
752 .mnd_width = 8,
753 .hid_width = 5,
754 .parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,
755 .freq_tbl = ftbl_sdcc1_apps_clk_src,
756 .clkr.hw.init = &(struct clk_init_data){
757 .name = "sdcc1_apps_clk_src",
758 .parent_data = gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div,
759 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll4_gpll0_early_div),
760 .ops = &clk_rcg2_floor_ops,
761 },
762 };
763
764 static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
765 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
766 F(150000000, P_GPLL0, 4, 0, 0),
767 F(200000000, P_GPLL0, 3, 0, 0),
768 F(300000000, P_GPLL0, 2, 0, 0),
769 { }
770 };
771
772 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
773 .cmd_rcgr = 0x16010,
774 .mnd_width = 0,
775 .hid_width = 5,
776 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
777 .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
778 .clkr.hw.init = &(struct clk_init_data){
779 .name = "sdcc1_ice_core_clk_src",
780 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
781 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
782 .ops = &clk_rcg2_ops,
783 },
784 };
785
786 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
787 F(144000, P_XO, 16, 3, 25),
788 F(400000, P_XO, 12, 1, 4),
789 F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
790 F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
791 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
792 F(100000000, P_GPLL0, 6, 0, 0),
793 F(192000000, P_GPLL4, 8, 0, 0),
794 F(200000000, P_GPLL0, 3, 0, 0),
795 { }
796 };
797
798 static struct clk_rcg2 sdcc2_apps_clk_src = {
799 .cmd_rcgr = 0x14010,
800 .mnd_width = 8,
801 .hid_width = 5,
802 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,
803 .freq_tbl = ftbl_sdcc2_apps_clk_src,
804 .clkr.hw.init = &(struct clk_init_data){
805 .name = "sdcc2_apps_clk_src",
806 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4,
807 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div_gpll4),
808 .ops = &clk_rcg2_floor_ops,
809 },
810 };
811
812 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
813 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
814 F(100000000, P_GPLL0, 6, 0, 0),
815 F(150000000, P_GPLL0, 4, 0, 0),
816 F(200000000, P_GPLL0, 3, 0, 0),
817 F(240000000, P_GPLL0, 2.5, 0, 0),
818 { }
819 };
820
821 static struct clk_rcg2 ufs_axi_clk_src = {
822 .cmd_rcgr = 0x75018,
823 .mnd_width = 8,
824 .hid_width = 5,
825 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
826 .freq_tbl = ftbl_ufs_axi_clk_src,
827 .clkr.hw.init = &(struct clk_init_data){
828 .name = "ufs_axi_clk_src",
829 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
830 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
831 .ops = &clk_rcg2_ops,
832 },
833 };
834
835 static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
836 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
837 F(150000000, P_GPLL0, 4, 0, 0),
838 F(300000000, P_GPLL0, 2, 0, 0),
839 { }
840 };
841
842 static struct clk_rcg2 ufs_ice_core_clk_src = {
843 .cmd_rcgr = 0x76010,
844 .mnd_width = 0,
845 .hid_width = 5,
846 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
847 .freq_tbl = ftbl_ufs_ice_core_clk_src,
848 .clkr.hw.init = &(struct clk_init_data){
849 .name = "ufs_ice_core_clk_src",
850 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
851 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
852 .ops = &clk_rcg2_ops,
853 },
854 };
855
856 static struct clk_rcg2 ufs_phy_aux_clk_src = {
857 .cmd_rcgr = 0x76044,
858 .mnd_width = 0,
859 .hid_width = 5,
860 .parent_map = gcc_parent_map_xo_sleep_clk,
861 .freq_tbl = ftbl_hmss_rbcpr_clk_src,
862 .clkr.hw.init = &(struct clk_init_data){
863 .name = "ufs_phy_aux_clk_src",
864 .parent_data = gcc_parent_data_xo_sleep_clk,
865 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk),
866 .ops = &clk_rcg2_ops,
867 },
868 };
869
870 static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
871 F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
872 F(75000000, P_GPLL0, 8, 0, 0),
873 F(150000000, P_GPLL0, 4, 0, 0),
874 { }
875 };
876
877 static struct clk_rcg2 ufs_unipro_core_clk_src = {
878 .cmd_rcgr = 0x76028,
879 .mnd_width = 0,
880 .hid_width = 5,
881 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
882 .freq_tbl = ftbl_ufs_unipro_core_clk_src,
883 .clkr.hw.init = &(struct clk_init_data){
884 .name = "ufs_unipro_core_clk_src",
885 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
886 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
887 .ops = &clk_rcg2_ops,
888 },
889 };
890
891 static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
892 F(19200000, P_XO, 1, 0, 0),
893 F(60000000, P_GPLL0, 10, 0, 0),
894 F(120000000, P_GPLL0, 5, 0, 0),
895 { }
896 };
897
898 static struct clk_rcg2 usb20_master_clk_src = {
899 .cmd_rcgr = 0x2f010,
900 .mnd_width = 8,
901 .hid_width = 5,
902 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
903 .freq_tbl = ftbl_usb20_master_clk_src,
904 .clkr.hw.init = &(struct clk_init_data){
905 .name = "usb20_master_clk_src",
906 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
907 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
908 .ops = &clk_rcg2_ops,
909 },
910 };
911
912 static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = {
913 F(19200000, P_XO, 1, 0, 0),
914 F(60000000, P_GPLL0, 10, 0, 0),
915 { }
916 };
917
918 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
919 .cmd_rcgr = 0x2f024,
920 .mnd_width = 0,
921 .hid_width = 5,
922 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
923 .freq_tbl = ftbl_usb20_mock_utmi_clk_src,
924 .clkr.hw.init = &(struct clk_init_data){
925 .name = "usb20_mock_utmi_clk_src",
926 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
927 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
928 .ops = &clk_rcg2_ops,
929 },
930 };
931
932 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
933 F(19200000, P_XO, 1, 0, 0),
934 F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
935 F(120000000, P_GPLL0, 5, 0, 0),
936 F(133333333, P_GPLL0, 4.5, 0, 0),
937 F(150000000, P_GPLL0, 4, 0, 0),
938 F(200000000, P_GPLL0, 3, 0, 0),
939 F(240000000, P_GPLL0, 2.5, 0, 0),
940 { }
941 };
942
943 static struct clk_rcg2 usb30_master_clk_src = {
944 .cmd_rcgr = 0xf014,
945 .mnd_width = 8,
946 .hid_width = 5,
947 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
948 .freq_tbl = ftbl_usb30_master_clk_src,
949 .clkr.hw.init = &(struct clk_init_data){
950 .name = "usb30_master_clk_src",
951 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
952 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
953 .ops = &clk_rcg2_ops,
954 },
955 };
956
957 static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
958 F(19200000, P_XO, 1, 0, 0),
959 F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
960 F(60000000, P_GPLL0, 10, 0, 0),
961 { }
962 };
963
964 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
965 .cmd_rcgr = 0xf028,
966 .mnd_width = 0,
967 .hid_width = 5,
968 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
969 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
970 .clkr.hw.init = &(struct clk_init_data){
971 .name = "usb30_mock_utmi_clk_src",
972 .parent_data = gcc_parent_data_xo_gpll0_gpll0_early_div,
973 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_gpll0_gpll0_early_div),
974 .ops = &clk_rcg2_ops,
975 },
976 };
977
978 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
979 F(1200000, P_XO, 16, 0, 0),
980 F(19200000, P_XO, 1, 0, 0),
981 { }
982 };
983
984 static struct clk_rcg2 usb3_phy_aux_clk_src = {
985 .cmd_rcgr = 0x5000c,
986 .mnd_width = 0,
987 .hid_width = 5,
988 .parent_map = gcc_parent_map_xo_sleep_clk,
989 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
990 .clkr.hw.init = &(struct clk_init_data){
991 .name = "usb3_phy_aux_clk_src",
992 .parent_data = gcc_parent_data_xo_sleep_clk,
993 .num_parents = ARRAY_SIZE(gcc_parent_data_xo_sleep_clk),
994 .ops = &clk_rcg2_ops,
995 },
996 };
997
998 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
999 .halt_reg = 0x75034,
1000 .halt_check = BRANCH_HALT,
1001 .clkr = {
1002 .enable_reg = 0x75034,
1003 .enable_mask = BIT(0),
1004 .hw.init = &(struct clk_init_data){
1005 .name = "gcc_aggre2_ufs_axi_clk",
1006 .parent_hws = (const struct clk_hw*[]) {
1007 &ufs_axi_clk_src.clkr.hw,
1008 },
1009 .num_parents = 1,
1010 .ops = &clk_branch2_ops,
1011 },
1012 },
1013 };
1014
1015 static struct clk_branch gcc_aggre2_usb3_axi_clk = {
1016 .halt_reg = 0xf03c,
1017 .halt_check = BRANCH_HALT,
1018 .clkr = {
1019 .enable_reg = 0xf03c,
1020 .enable_mask = BIT(0),
1021 .hw.init = &(struct clk_init_data){
1022 .name = "gcc_aggre2_usb3_axi_clk",
1023 .parent_hws = (const struct clk_hw*[]) {
1024 &usb30_master_clk_src.clkr.hw,
1025 },
1026 .num_parents = 1,
1027 .ops = &clk_branch2_ops,
1028 },
1029 },
1030 };
1031
1032 static struct clk_branch gcc_bimc_gfx_clk = {
1033 .halt_reg = 0x7106c,
1034 .halt_check = BRANCH_VOTED,
1035 .clkr = {
1036 .enable_reg = 0x7106c,
1037 .enable_mask = BIT(0),
1038 .hw.init = &(struct clk_init_data){
1039 .name = "gcc_bimc_gfx_clk",
1040 .ops = &clk_branch2_ops,
1041 },
1042 },
1043 };
1044
1045 static struct clk_branch gcc_bimc_hmss_axi_clk = {
1046 .halt_reg = 0x48004,
1047 .halt_check = BRANCH_HALT_VOTED,
1048 .clkr = {
1049 .enable_reg = 0x52004,
1050 .enable_mask = BIT(22),
1051 .hw.init = &(struct clk_init_data){
1052 .name = "gcc_bimc_hmss_axi_clk",
1053 .ops = &clk_branch2_ops,
1054 },
1055 },
1056 };
1057
1058 static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
1059 .halt_reg = 0x4401c,
1060 .halt_check = BRANCH_HALT,
1061 .clkr = {
1062 .enable_reg = 0x4401c,
1063 .enable_mask = BIT(0),
1064 .hw.init = &(struct clk_init_data){
1065 .name = "gcc_bimc_mss_q6_axi_clk",
1066 .ops = &clk_branch2_ops,
1067 },
1068 },
1069 };
1070
1071 static struct clk_branch gcc_blsp1_ahb_clk = {
1072 .halt_reg = 0x17004,
1073 .halt_check = BRANCH_HALT_VOTED,
1074 .clkr = {
1075 .enable_reg = 0x52004,
1076 .enable_mask = BIT(17),
1077 .hw.init = &(struct clk_init_data){
1078 .name = "gcc_blsp1_ahb_clk",
1079 .ops = &clk_branch2_ops,
1080 },
1081 },
1082 };
1083
1084 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1085 .halt_reg = 0x19008,
1086 .halt_check = BRANCH_HALT,
1087 .clkr = {
1088 .enable_reg = 0x19008,
1089 .enable_mask = BIT(0),
1090 .hw.init = &(struct clk_init_data){
1091 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1092 .parent_hws = (const struct clk_hw*[]) {
1093 &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1094 },
1095 .num_parents = 1,
1096 .flags = CLK_SET_RATE_PARENT,
1097 .ops = &clk_branch2_ops,
1098 },
1099 },
1100 };
1101
1102 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1103 .halt_reg = 0x19004,
1104 .halt_check = BRANCH_HALT,
1105 .clkr = {
1106 .enable_reg = 0x19004,
1107 .enable_mask = BIT(0),
1108 .hw.init = &(struct clk_init_data){
1109 .name = "gcc_blsp1_qup1_spi_apps_clk",
1110 .parent_hws = (const struct clk_hw*[]) {
1111 &blsp1_qup1_spi_apps_clk_src.clkr.hw,
1112 },
1113 .num_parents = 1,
1114 .flags = CLK_SET_RATE_PARENT,
1115 .ops = &clk_branch2_ops,
1116 },
1117 },
1118 };
1119
1120 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1121 .halt_reg = 0x1b008,
1122 .halt_check = BRANCH_HALT,
1123 .clkr = {
1124 .enable_reg = 0x1b008,
1125 .enable_mask = BIT(0),
1126 .hw.init = &(struct clk_init_data){
1127 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1128 .parent_hws = (const struct clk_hw*[]) {
1129 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1130 },
1131 .num_parents = 1,
1132 .flags = CLK_SET_RATE_PARENT,
1133 .ops = &clk_branch2_ops,
1134 },
1135 },
1136 };
1137
1138 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1139 .halt_reg = 0x1b004,
1140 .halt_check = BRANCH_HALT,
1141 .clkr = {
1142 .enable_reg = 0x1b004,
1143 .enable_mask = BIT(0),
1144 .hw.init = &(struct clk_init_data){
1145 .name = "gcc_blsp1_qup2_spi_apps_clk",
1146 .parent_hws = (const struct clk_hw*[]) {
1147 &blsp1_qup2_spi_apps_clk_src.clkr.hw,
1148 },
1149 .num_parents = 1,
1150 .flags = CLK_SET_RATE_PARENT,
1151 .ops = &clk_branch2_ops,
1152 },
1153 },
1154 };
1155
1156 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1157 .halt_reg = 0x1d008,
1158 .halt_check = BRANCH_HALT,
1159 .clkr = {
1160 .enable_reg = 0x1d008,
1161 .enable_mask = BIT(0),
1162 .hw.init = &(struct clk_init_data){
1163 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1164 .parent_hws = (const struct clk_hw*[]) {
1165 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1166 },
1167 .num_parents = 1,
1168 .flags = CLK_SET_RATE_PARENT,
1169 .ops = &clk_branch2_ops,
1170 },
1171 },
1172 };
1173
1174 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1175 .halt_reg = 0x1d004,
1176 .halt_check = BRANCH_HALT,
1177 .clkr = {
1178 .enable_reg = 0x1d004,
1179 .enable_mask = BIT(0),
1180 .hw.init = &(struct clk_init_data){
1181 .name = "gcc_blsp1_qup3_spi_apps_clk",
1182 .parent_hws = (const struct clk_hw*[]) {
1183 &blsp1_qup3_spi_apps_clk_src.clkr.hw,
1184 },
1185 .num_parents = 1,
1186 .flags = CLK_SET_RATE_PARENT,
1187 .ops = &clk_branch2_ops,
1188 },
1189 },
1190 };
1191
1192 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1193 .halt_reg = 0x1f008,
1194 .halt_check = BRANCH_HALT,
1195 .clkr = {
1196 .enable_reg = 0x1f008,
1197 .enable_mask = BIT(0),
1198 .hw.init = &(struct clk_init_data){
1199 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1200 .parent_hws = (const struct clk_hw*[]) {
1201 &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
1202 },
1203 .num_parents = 1,
1204 .flags = CLK_SET_RATE_PARENT,
1205 .ops = &clk_branch2_ops,
1206 },
1207 },
1208 };
1209
1210 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1211 .halt_reg = 0x1f004,
1212 .halt_check = BRANCH_HALT,
1213 .clkr = {
1214 .enable_reg = 0x1f004,
1215 .enable_mask = BIT(0),
1216 .hw.init = &(struct clk_init_data){
1217 .name = "gcc_blsp1_qup4_spi_apps_clk",
1218 .parent_hws = (const struct clk_hw*[]) {
1219 &blsp1_qup4_spi_apps_clk_src.clkr.hw,
1220 },
1221 .num_parents = 1,
1222 .flags = CLK_SET_RATE_PARENT,
1223 .ops = &clk_branch2_ops,
1224 },
1225 },
1226 };
1227
1228 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1229 .halt_reg = 0x1a004,
1230 .halt_check = BRANCH_HALT,
1231 .clkr = {
1232 .enable_reg = 0x1a004,
1233 .enable_mask = BIT(0),
1234 .hw.init = &(struct clk_init_data){
1235 .name = "gcc_blsp1_uart1_apps_clk",
1236 .parent_hws = (const struct clk_hw*[]) {
1237 &blsp1_uart1_apps_clk_src.clkr.hw,
1238 },
1239 .num_parents = 1,
1240 .flags = CLK_SET_RATE_PARENT,
1241 .ops = &clk_branch2_ops,
1242 },
1243 },
1244 };
1245
1246 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1247 .halt_reg = 0x1c004,
1248 .halt_check = BRANCH_HALT,
1249 .clkr = {
1250 .enable_reg = 0x1c004,
1251 .enable_mask = BIT(0),
1252 .hw.init = &(struct clk_init_data){
1253 .name = "gcc_blsp1_uart2_apps_clk",
1254 .parent_hws = (const struct clk_hw*[]) {
1255 &blsp1_uart2_apps_clk_src.clkr.hw,
1256 },
1257 .num_parents = 1,
1258 .flags = CLK_SET_RATE_PARENT,
1259 .ops = &clk_branch2_ops,
1260 },
1261 },
1262 };
1263
1264 static struct clk_branch gcc_blsp2_ahb_clk = {
1265 .halt_reg = 0x25004,
1266 .halt_check = BRANCH_HALT_VOTED,
1267 .clkr = {
1268 .enable_reg = 0x52004,
1269 .enable_mask = BIT(15),
1270 .hw.init = &(struct clk_init_data){
1271 .name = "gcc_blsp2_ahb_clk",
1272 .ops = &clk_branch2_ops,
1273 },
1274 },
1275 };
1276
1277 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1278 .halt_reg = 0x26008,
1279 .halt_check = BRANCH_HALT,
1280 .clkr = {
1281 .enable_reg = 0x26008,
1282 .enable_mask = BIT(0),
1283 .hw.init = &(struct clk_init_data){
1284 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1285 .parent_hws = (const struct clk_hw*[]) {
1286 &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
1287 },
1288 .num_parents = 1,
1289 .flags = CLK_SET_RATE_PARENT,
1290 .ops = &clk_branch2_ops,
1291 },
1292 },
1293 };
1294
1295 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1296 .halt_reg = 0x26004,
1297 .halt_check = BRANCH_HALT,
1298 .clkr = {
1299 .enable_reg = 0x26004,
1300 .enable_mask = BIT(0),
1301 .hw.init = &(struct clk_init_data){
1302 .name = "gcc_blsp2_qup1_spi_apps_clk",
1303 .parent_hws = (const struct clk_hw*[]) {
1304 &blsp2_qup1_spi_apps_clk_src.clkr.hw,
1305 },
1306 .num_parents = 1,
1307 .flags = CLK_SET_RATE_PARENT,
1308 .ops = &clk_branch2_ops,
1309 },
1310 },
1311 };
1312
1313 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1314 .halt_reg = 0x28008,
1315 .halt_check = BRANCH_HALT,
1316 .clkr = {
1317 .enable_reg = 0x28008,
1318 .enable_mask = BIT(0),
1319 .hw.init = &(struct clk_init_data){
1320 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1321 .parent_hws = (const struct clk_hw*[]) {
1322 &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
1323 },
1324 .num_parents = 1,
1325 .flags = CLK_SET_RATE_PARENT,
1326 .ops = &clk_branch2_ops,
1327 },
1328 },
1329 };
1330
1331 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1332 .halt_reg = 0x28004,
1333 .halt_check = BRANCH_HALT,
1334 .clkr = {
1335 .enable_reg = 0x28004,
1336 .enable_mask = BIT(0),
1337 .hw.init = &(struct clk_init_data){
1338 .name = "gcc_blsp2_qup2_spi_apps_clk",
1339 .parent_hws = (const struct clk_hw*[]) {
1340 &blsp2_qup2_spi_apps_clk_src.clkr.hw,
1341 },
1342 .num_parents = 1,
1343 .flags = CLK_SET_RATE_PARENT,
1344 .ops = &clk_branch2_ops,
1345 },
1346 },
1347 };
1348
1349 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1350 .halt_reg = 0x2a008,
1351 .halt_check = BRANCH_HALT,
1352 .clkr = {
1353 .enable_reg = 0x2a008,
1354 .enable_mask = BIT(0),
1355 .hw.init = &(struct clk_init_data){
1356 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1357 .parent_hws = (const struct clk_hw*[]) {
1358 &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
1359 },
1360 .num_parents = 1,
1361 .flags = CLK_SET_RATE_PARENT,
1362 .ops = &clk_branch2_ops,
1363 },
1364 },
1365 };
1366
1367 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1368 .halt_reg = 0x2a004,
1369 .halt_check = BRANCH_HALT,
1370 .clkr = {
1371 .enable_reg = 0x2a004,
1372 .enable_mask = BIT(0),
1373 .hw.init = &(struct clk_init_data){
1374 .name = "gcc_blsp2_qup3_spi_apps_clk",
1375 .parent_hws = (const struct clk_hw*[]) {
1376 &blsp2_qup3_spi_apps_clk_src.clkr.hw,
1377 },
1378 .num_parents = 1,
1379 .flags = CLK_SET_RATE_PARENT,
1380 .ops = &clk_branch2_ops,
1381 },
1382 },
1383 };
1384
1385 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1386 .halt_reg = 0x2c008,
1387 .halt_check = BRANCH_HALT,
1388 .clkr = {
1389 .enable_reg = 0x2c008,
1390 .enable_mask = BIT(0),
1391 .hw.init = &(struct clk_init_data){
1392 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1393 .parent_hws = (const struct clk_hw*[]) {
1394 &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
1395 },
1396 .num_parents = 1,
1397 .flags = CLK_SET_RATE_PARENT,
1398 .ops = &clk_branch2_ops,
1399 },
1400 },
1401 };
1402
1403 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1404 .halt_reg = 0x2c004,
1405 .halt_check = BRANCH_HALT,
1406 .clkr = {
1407 .enable_reg = 0x2c004,
1408 .enable_mask = BIT(0),
1409 .hw.init = &(struct clk_init_data){
1410 .name = "gcc_blsp2_qup4_spi_apps_clk",
1411 .parent_hws = (const struct clk_hw*[]) {
1412 &blsp2_qup4_spi_apps_clk_src.clkr.hw,
1413 },
1414 .num_parents = 1,
1415 .flags = CLK_SET_RATE_PARENT,
1416 .ops = &clk_branch2_ops,
1417 },
1418 },
1419 };
1420
1421 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1422 .halt_reg = 0x27004,
1423 .halt_check = BRANCH_HALT,
1424 .clkr = {
1425 .enable_reg = 0x27004,
1426 .enable_mask = BIT(0),
1427 .hw.init = &(struct clk_init_data){
1428 .name = "gcc_blsp2_uart1_apps_clk",
1429 .parent_hws = (const struct clk_hw*[]) {
1430 &blsp2_uart1_apps_clk_src.clkr.hw,
1431 },
1432 .num_parents = 1,
1433 .flags = CLK_SET_RATE_PARENT,
1434 .ops = &clk_branch2_ops,
1435 },
1436 },
1437 };
1438
1439 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1440 .halt_reg = 0x29004,
1441 .halt_check = BRANCH_HALT,
1442 .clkr = {
1443 .enable_reg = 0x29004,
1444 .enable_mask = BIT(0),
1445 .hw.init = &(struct clk_init_data){
1446 .name = "gcc_blsp2_uart2_apps_clk",
1447 .parent_hws = (const struct clk_hw*[]) {
1448 &blsp2_uart2_apps_clk_src.clkr.hw,
1449 },
1450 .num_parents = 1,
1451 .flags = CLK_SET_RATE_PARENT,
1452 .ops = &clk_branch2_ops,
1453 },
1454 },
1455 };
1456
1457 static struct clk_branch gcc_boot_rom_ahb_clk = {
1458 .halt_reg = 0x38004,
1459 .halt_check = BRANCH_HALT_VOTED,
1460 .clkr = {
1461 .enable_reg = 0x52004,
1462 .enable_mask = BIT(10),
1463 .hw.init = &(struct clk_init_data){
1464 .name = "gcc_boot_rom_ahb_clk",
1465 .ops = &clk_branch2_ops,
1466 },
1467 },
1468 };
1469
1470 static struct clk_branch gcc_cfg_noc_usb2_axi_clk = {
1471 .halt_reg = 0x5058,
1472 .halt_check = BRANCH_HALT,
1473 .clkr = {
1474 .enable_reg = 0x5058,
1475 .enable_mask = BIT(0),
1476 .hw.init = &(struct clk_init_data){
1477 .name = "gcc_cfg_noc_usb2_axi_clk",
1478 .parent_hws = (const struct clk_hw*[]) {
1479 &usb20_master_clk_src.clkr.hw,
1480 },
1481 .num_parents = 1,
1482 .ops = &clk_branch2_ops,
1483 },
1484 },
1485 };
1486
1487 static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
1488 .halt_reg = 0x5018,
1489 .halt_check = BRANCH_HALT,
1490 .clkr = {
1491 .enable_reg = 0x5018,
1492 .enable_mask = BIT(0),
1493 .hw.init = &(struct clk_init_data){
1494 .name = "gcc_cfg_noc_usb3_axi_clk",
1495 .parent_hws = (const struct clk_hw*[]) {
1496 &usb30_master_clk_src.clkr.hw,
1497 },
1498 .num_parents = 1,
1499 .ops = &clk_branch2_ops,
1500 },
1501 },
1502 };
1503
1504 static struct clk_branch gcc_dcc_ahb_clk = {
1505 .halt_reg = 0x84004,
1506 .clkr = {
1507 .enable_reg = 0x84004,
1508 .enable_mask = BIT(0),
1509 .hw.init = &(struct clk_init_data){
1510 .name = "gcc_dcc_ahb_clk",
1511 .ops = &clk_branch2_ops,
1512 },
1513 },
1514 };
1515
1516 static struct clk_branch gcc_gp1_clk = {
1517 .halt_reg = 0x64000,
1518 .halt_check = BRANCH_HALT,
1519 .clkr = {
1520 .enable_reg = 0x64000,
1521 .enable_mask = BIT(0),
1522 .hw.init = &(struct clk_init_data){
1523 .name = "gcc_gp1_clk",
1524 .parent_hws = (const struct clk_hw*[]) {
1525 &gp1_clk_src.clkr.hw,
1526 },
1527 .num_parents = 1,
1528 .flags = CLK_SET_RATE_PARENT,
1529 .ops = &clk_branch2_ops,
1530 },
1531 },
1532 };
1533
1534 static struct clk_branch gcc_gp2_clk = {
1535 .halt_reg = 0x65000,
1536 .halt_check = BRANCH_HALT,
1537 .clkr = {
1538 .enable_reg = 0x65000,
1539 .enable_mask = BIT(0),
1540 .hw.init = &(struct clk_init_data){
1541 .name = "gcc_gp2_clk",
1542 .parent_hws = (const struct clk_hw*[]) {
1543 &gp2_clk_src.clkr.hw,
1544 },
1545 .num_parents = 1,
1546 .flags = CLK_SET_RATE_PARENT,
1547 .ops = &clk_branch2_ops,
1548 },
1549 },
1550 };
1551
1552 static struct clk_branch gcc_gp3_clk = {
1553 .halt_reg = 0x66000,
1554 .halt_check = BRANCH_HALT,
1555 .clkr = {
1556 .enable_reg = 0x66000,
1557 .enable_mask = BIT(0),
1558 .hw.init = &(struct clk_init_data){
1559 .name = "gcc_gp3_clk",
1560 .parent_hws = (const struct clk_hw*[]) {
1561 &gp3_clk_src.clkr.hw,
1562 },
1563 .num_parents = 1,
1564 .flags = CLK_SET_RATE_PARENT,
1565 .ops = &clk_branch2_ops,
1566 },
1567 },
1568 };
1569
1570 static struct clk_branch gcc_gpu_bimc_gfx_clk = {
1571 .halt_reg = 0x71010,
1572 .halt_check = BRANCH_VOTED,
1573 .clkr = {
1574 .enable_reg = 0x71010,
1575 .enable_mask = BIT(0),
1576 .hw.init = &(struct clk_init_data){
1577 .name = "gcc_gpu_bimc_gfx_clk",
1578 .ops = &clk_branch2_ops,
1579 },
1580 },
1581 };
1582
1583 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1584 .halt_reg = 0x71004,
1585 .halt_check = BRANCH_VOTED,
1586 .clkr = {
1587 .enable_reg = 0x71004,
1588 .enable_mask = BIT(0),
1589 .hw.init = &(struct clk_init_data){
1590 .name = "gcc_gpu_cfg_ahb_clk",
1591 .ops = &clk_branch2_ops,
1592 .flags = CLK_IS_CRITICAL,
1593 },
1594 },
1595 };
1596
1597 static struct clk_branch gcc_gpu_gpll0_clk = {
1598 .halt_reg = 0x5200c,
1599 .halt_check = BRANCH_HALT_DELAY,
1600 .clkr = {
1601 .enable_reg = 0x5200c,
1602 .enable_mask = BIT(4),
1603 .hw.init = &(struct clk_init_data){
1604 .name = "gcc_gpu_gpll0_clk",
1605 .parent_hws = (const struct clk_hw*[]) {
1606 &gpll0.clkr.hw,
1607 },
1608 .num_parents = 1,
1609 .ops = &clk_branch2_ops,
1610 },
1611 },
1612 };
1613
1614 static struct clk_branch gcc_gpu_gpll0_div_clk = {
1615 .halt_reg = 0x5200c,
1616 .halt_check = BRANCH_HALT_DELAY,
1617 .clkr = {
1618 .enable_reg = 0x5200c,
1619 .enable_mask = BIT(3),
1620 .hw.init = &(struct clk_init_data){
1621 .name = "gcc_gpu_gpll0_div_clk",
1622 .parent_hws = (const struct clk_hw*[]) {
1623 &gpll0_early_div.hw,
1624 },
1625 .num_parents = 1,
1626 .ops = &clk_branch2_ops,
1627 },
1628 },
1629 };
1630
1631 static struct clk_branch gcc_hmss_dvm_bus_clk = {
1632 .halt_reg = 0x4808c,
1633 .halt_check = BRANCH_HALT,
1634 .clkr = {
1635 .enable_reg = 0x4808c,
1636 .enable_mask = BIT(0),
1637 .hw.init = &(struct clk_init_data){
1638 .name = "gcc_hmss_dvm_bus_clk",
1639 .ops = &clk_branch2_ops,
1640 .flags = CLK_IGNORE_UNUSED,
1641 },
1642 },
1643 };
1644
1645 static struct clk_branch gcc_hmss_rbcpr_clk = {
1646 .halt_reg = 0x48008,
1647 .halt_check = BRANCH_HALT,
1648 .clkr = {
1649 .enable_reg = 0x48008,
1650 .enable_mask = BIT(0),
1651 .hw.init = &(struct clk_init_data){
1652 .name = "gcc_hmss_rbcpr_clk",
1653 .parent_hws = (const struct clk_hw*[]) {
1654 &hmss_rbcpr_clk_src.clkr.hw,
1655 },
1656 .num_parents = 1,
1657 .flags = CLK_SET_RATE_PARENT,
1658 .ops = &clk_branch2_ops,
1659 },
1660 },
1661 };
1662
1663 static struct clk_branch gcc_mmss_gpll0_clk = {
1664 .halt_reg = 0x5200c,
1665 .halt_check = BRANCH_HALT_DELAY,
1666 .clkr = {
1667 .enable_reg = 0x5200c,
1668 .enable_mask = BIT(1),
1669 .hw.init = &(struct clk_init_data){
1670 .name = "gcc_mmss_gpll0_clk",
1671 .parent_hws = (const struct clk_hw*[]) {
1672 &gpll0.clkr.hw,
1673 },
1674 .num_parents = 1,
1675 .ops = &clk_branch2_ops,
1676 },
1677 },
1678 };
1679
1680 static struct clk_branch gcc_mmss_gpll0_div_clk = {
1681 .halt_reg = 0x5200c,
1682 .halt_check = BRANCH_HALT_DELAY,
1683 .clkr = {
1684 .enable_reg = 0x5200c,
1685 .enable_mask = BIT(0),
1686 .hw.init = &(struct clk_init_data){
1687 .name = "gcc_mmss_gpll0_div_clk",
1688 .parent_hws = (const struct clk_hw*[]) {
1689 &gpll0_early_div.hw,
1690 },
1691 .num_parents = 1,
1692 .ops = &clk_branch2_ops,
1693 },
1694 },
1695 };
1696
1697 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1698 .halt_reg = 0x9004,
1699 .halt_check = BRANCH_HALT,
1700 .clkr = {
1701 .enable_reg = 0x9004,
1702 .enable_mask = BIT(0),
1703 .hw.init = &(struct clk_init_data){
1704 .name = "gcc_mmss_noc_cfg_ahb_clk",
1705 .ops = &clk_branch2_ops,
1706 /*
1707 * Any access to mmss depends on this clock.
1708 * Gating this clock has been shown to crash the system
1709 * when mmssnoc_axi_rpm_clk is inited in rpmcc.
1710 */
1711 .flags = CLK_IS_CRITICAL,
1712 },
1713 },
1714 };
1715
1716 static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
1717 .halt_reg = 0x9000,
1718 .halt_check = BRANCH_HALT,
1719 .clkr = {
1720 .enable_reg = 0x9000,
1721 .enable_mask = BIT(0),
1722 .hw.init = &(struct clk_init_data){
1723 .name = "gcc_mmss_sys_noc_axi_clk",
1724 .ops = &clk_branch2_ops,
1725 },
1726 },
1727 };
1728
1729 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1730 .halt_reg = 0x8a000,
1731 .clkr = {
1732 .enable_reg = 0x8a000,
1733 .enable_mask = BIT(0),
1734 .hw.init = &(struct clk_init_data){
1735 .name = "gcc_mss_cfg_ahb_clk",
1736 .ops = &clk_branch2_ops,
1737 },
1738 },
1739 };
1740
1741 static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
1742 .halt_reg = 0x8a004,
1743 .halt_check = BRANCH_HALT,
1744 .hwcg_reg = 0x8a004,
1745 .hwcg_bit = 1,
1746 .clkr = {
1747 .enable_reg = 0x8a004,
1748 .enable_mask = BIT(0),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "gcc_mss_mnoc_bimc_axi_clk",
1751 .ops = &clk_branch2_ops,
1752 },
1753 },
1754 };
1755
1756 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1757 .halt_reg = 0x8a040,
1758 .clkr = {
1759 .enable_reg = 0x8a040,
1760 .enable_mask = BIT(0),
1761 .hw.init = &(struct clk_init_data){
1762 .name = "gcc_mss_q6_bimc_axi_clk",
1763 .ops = &clk_branch2_ops,
1764 },
1765 },
1766 };
1767
1768 static struct clk_branch gcc_mss_snoc_axi_clk = {
1769 .halt_reg = 0x8a03c,
1770 .clkr = {
1771 .enable_reg = 0x8a03c,
1772 .enable_mask = BIT(0),
1773 .hw.init = &(struct clk_init_data){
1774 .name = "gcc_mss_snoc_axi_clk",
1775 .ops = &clk_branch2_ops,
1776 },
1777 },
1778 };
1779
1780 static struct clk_branch gcc_pdm2_clk = {
1781 .halt_reg = 0x3300c,
1782 .halt_check = BRANCH_HALT,
1783 .clkr = {
1784 .enable_reg = 0x3300c,
1785 .enable_mask = BIT(0),
1786 .hw.init = &(struct clk_init_data){
1787 .name = "gcc_pdm2_clk",
1788 .parent_hws = (const struct clk_hw*[]) {
1789 &pdm2_clk_src.clkr.hw,
1790 },
1791 .num_parents = 1,
1792 .flags = CLK_SET_RATE_PARENT,
1793 .ops = &clk_branch2_ops,
1794 },
1795 },
1796 };
1797
1798 static struct clk_branch gcc_pdm_ahb_clk = {
1799 .halt_reg = 0x33004,
1800 .halt_check = BRANCH_HALT,
1801 .clkr = {
1802 .enable_reg = 0x33004,
1803 .enable_mask = BIT(0),
1804 .hw.init = &(struct clk_init_data){
1805 .name = "gcc_pdm_ahb_clk",
1806 .ops = &clk_branch2_ops,
1807 },
1808 },
1809 };
1810
1811 static struct clk_branch gcc_prng_ahb_clk = {
1812 .halt_reg = 0x34004,
1813 .halt_check = BRANCH_HALT_VOTED,
1814 .clkr = {
1815 .enable_reg = 0x52004,
1816 .enable_mask = BIT(13),
1817 .hw.init = &(struct clk_init_data){
1818 .name = "gcc_prng_ahb_clk",
1819 .ops = &clk_branch2_ops,
1820 },
1821 },
1822 };
1823
1824 static struct clk_branch gcc_qspi_ahb_clk = {
1825 .halt_reg = 0x4d004,
1826 .halt_check = BRANCH_HALT,
1827 .clkr = {
1828 .enable_reg = 0x4d004,
1829 .enable_mask = BIT(0),
1830 .hw.init = &(struct clk_init_data){
1831 .name = "gcc_qspi_ahb_clk",
1832 .ops = &clk_branch2_ops,
1833 },
1834 },
1835 };
1836
1837 static struct clk_branch gcc_qspi_ser_clk = {
1838 .halt_reg = 0x4d008,
1839 .halt_check = BRANCH_HALT,
1840 .clkr = {
1841 .enable_reg = 0x4d008,
1842 .enable_mask = BIT(0),
1843 .hw.init = &(struct clk_init_data){
1844 .name = "gcc_qspi_ser_clk",
1845 .parent_hws = (const struct clk_hw*[]) {
1846 &qspi_ser_clk_src.clkr.hw,
1847 },
1848 .num_parents = 1,
1849 .flags = CLK_SET_RATE_PARENT,
1850 .ops = &clk_branch2_ops,
1851 },
1852 },
1853 };
1854
1855 static struct clk_branch gcc_rx0_usb2_clkref_clk = {
1856 .halt_reg = 0x88018,
1857 .halt_check = BRANCH_HALT_VOTED,
1858 .clkr = {
1859 .enable_reg = 0x88018,
1860 .enable_mask = BIT(0),
1861 .hw.init = &(struct clk_init_data){
1862 .name = "gcc_rx0_usb2_clkref_clk",
1863 .ops = &clk_branch2_ops,
1864 },
1865 },
1866 };
1867
1868 static struct clk_branch gcc_rx1_usb2_clkref_clk = {
1869 .halt_reg = 0x88014,
1870 .halt_check = BRANCH_HALT_VOTED,
1871 .clkr = {
1872 .enable_reg = 0x88014,
1873 .enable_mask = BIT(0),
1874 .hw.init = &(struct clk_init_data){
1875 .name = "gcc_rx1_usb2_clkref_clk",
1876 .ops = &clk_branch2_ops,
1877 },
1878 },
1879 };
1880
1881 static struct clk_branch gcc_sdcc1_ahb_clk = {
1882 .halt_reg = 0x16008,
1883 .halt_check = BRANCH_HALT,
1884 .clkr = {
1885 .enable_reg = 0x16008,
1886 .enable_mask = BIT(0),
1887 .hw.init = &(struct clk_init_data){
1888 .name = "gcc_sdcc1_ahb_clk",
1889 .ops = &clk_branch2_ops,
1890 },
1891 },
1892 };
1893
1894 static struct clk_branch gcc_sdcc1_apps_clk = {
1895 .halt_reg = 0x16004,
1896 .halt_check = BRANCH_HALT,
1897 .clkr = {
1898 .enable_reg = 0x16004,
1899 .enable_mask = BIT(0),
1900 .hw.init = &(struct clk_init_data){
1901 .name = "gcc_sdcc1_apps_clk",
1902 .parent_hws = (const struct clk_hw*[]) {
1903 &sdcc1_apps_clk_src.clkr.hw,
1904 },
1905 .num_parents = 1,
1906 .flags = CLK_SET_RATE_PARENT,
1907 .ops = &clk_branch2_ops,
1908 },
1909 },
1910 };
1911
1912 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1913 .halt_reg = 0x1600c,
1914 .halt_check = BRANCH_HALT,
1915 .clkr = {
1916 .enable_reg = 0x1600c,
1917 .enable_mask = BIT(0),
1918 .hw.init = &(struct clk_init_data){
1919 .name = "gcc_sdcc1_ice_core_clk",
1920 .parent_hws = (const struct clk_hw*[]) {
1921 &sdcc1_ice_core_clk_src.clkr.hw,
1922 },
1923 .num_parents = 1,
1924 .flags = CLK_SET_RATE_PARENT,
1925 .ops = &clk_branch2_ops,
1926 },
1927 },
1928 };
1929
1930 static struct clk_branch gcc_sdcc2_ahb_clk = {
1931 .halt_reg = 0x14008,
1932 .halt_check = BRANCH_HALT,
1933 .clkr = {
1934 .enable_reg = 0x14008,
1935 .enable_mask = BIT(0),
1936 .hw.init = &(struct clk_init_data){
1937 .name = "gcc_sdcc2_ahb_clk",
1938 .ops = &clk_branch2_ops,
1939 },
1940 },
1941 };
1942
1943 static struct clk_branch gcc_sdcc2_apps_clk = {
1944 .halt_reg = 0x14004,
1945 .halt_check = BRANCH_HALT,
1946 .clkr = {
1947 .enable_reg = 0x14004,
1948 .enable_mask = BIT(0),
1949 .hw.init = &(struct clk_init_data){
1950 .name = "gcc_sdcc2_apps_clk",
1951 .parent_hws = (const struct clk_hw*[]) {
1952 &sdcc2_apps_clk_src.clkr.hw,
1953 },
1954 .num_parents = 1,
1955 .flags = CLK_SET_RATE_PARENT,
1956 .ops = &clk_branch2_ops,
1957 },
1958 },
1959 };
1960
1961 static struct clk_branch gcc_ufs_ahb_clk = {
1962 .halt_reg = 0x7500c,
1963 .halt_check = BRANCH_HALT,
1964 .clkr = {
1965 .enable_reg = 0x7500c,
1966 .enable_mask = BIT(0),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "gcc_ufs_ahb_clk",
1969 .ops = &clk_branch2_ops,
1970 },
1971 },
1972 };
1973
1974 static struct clk_branch gcc_ufs_axi_clk = {
1975 .halt_reg = 0x75008,
1976 .halt_check = BRANCH_HALT,
1977 .clkr = {
1978 .enable_reg = 0x75008,
1979 .enable_mask = BIT(0),
1980 .hw.init = &(struct clk_init_data){
1981 .name = "gcc_ufs_axi_clk",
1982 .parent_hws = (const struct clk_hw*[]) {
1983 &ufs_axi_clk_src.clkr.hw,
1984 },
1985 .num_parents = 1,
1986 .flags = CLK_SET_RATE_PARENT,
1987 .ops = &clk_branch2_ops,
1988 },
1989 },
1990 };
1991
1992 static struct clk_branch gcc_ufs_clkref_clk = {
1993 .halt_reg = 0x88008,
1994 .halt_check = BRANCH_HALT,
1995 .clkr = {
1996 .enable_reg = 0x88008,
1997 .enable_mask = BIT(0),
1998 .hw.init = &(struct clk_init_data){
1999 .name = "gcc_ufs_clkref_clk",
2000 .ops = &clk_branch2_ops,
2001 },
2002 },
2003 };
2004
2005 static struct clk_branch gcc_ufs_ice_core_clk = {
2006 .halt_reg = 0x7600c,
2007 .halt_check = BRANCH_HALT,
2008 .clkr = {
2009 .enable_reg = 0x7600c,
2010 .enable_mask = BIT(0),
2011 .hw.init = &(struct clk_init_data){
2012 .name = "gcc_ufs_ice_core_clk",
2013 .parent_hws = (const struct clk_hw*[]) {
2014 &ufs_ice_core_clk_src.clkr.hw,
2015 },
2016 .num_parents = 1,
2017 .flags = CLK_SET_RATE_PARENT,
2018 .ops = &clk_branch2_ops,
2019 },
2020 },
2021 };
2022
2023 static struct clk_branch gcc_ufs_phy_aux_clk = {
2024 .halt_reg = 0x76040,
2025 .halt_check = BRANCH_HALT,
2026 .clkr = {
2027 .enable_reg = 0x76040,
2028 .enable_mask = BIT(0),
2029 .hw.init = &(struct clk_init_data){
2030 .name = "gcc_ufs_phy_aux_clk",
2031 .parent_hws = (const struct clk_hw*[]) {
2032 &ufs_phy_aux_clk_src.clkr.hw,
2033 },
2034 .num_parents = 1,
2035 .flags = CLK_SET_RATE_PARENT,
2036 .ops = &clk_branch2_ops,
2037 },
2038 },
2039 };
2040
2041 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2042 .halt_reg = 0x75014,
2043 .halt_check = BRANCH_HALT_SKIP,
2044 .clkr = {
2045 .enable_reg = 0x75014,
2046 .enable_mask = BIT(0),
2047 .hw.init = &(struct clk_init_data){
2048 .name = "gcc_ufs_rx_symbol_0_clk",
2049 .ops = &clk_branch2_ops,
2050 },
2051 },
2052 };
2053
2054 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2055 .halt_reg = 0x7605c,
2056 .halt_check = BRANCH_HALT_SKIP,
2057 .clkr = {
2058 .enable_reg = 0x7605c,
2059 .enable_mask = BIT(0),
2060 .hw.init = &(struct clk_init_data){
2061 .name = "gcc_ufs_rx_symbol_1_clk",
2062 .ops = &clk_branch2_ops,
2063 },
2064 },
2065 };
2066
2067 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2068 .halt_reg = 0x75010,
2069 .halt_check = BRANCH_HALT_SKIP,
2070 .clkr = {
2071 .enable_reg = 0x75010,
2072 .enable_mask = BIT(0),
2073 .hw.init = &(struct clk_init_data){
2074 .name = "gcc_ufs_tx_symbol_0_clk",
2075 .ops = &clk_branch2_ops,
2076 },
2077 },
2078 };
2079
2080 static struct clk_branch gcc_ufs_unipro_core_clk = {
2081 .halt_reg = 0x76008,
2082 .halt_check = BRANCH_HALT,
2083 .clkr = {
2084 .enable_reg = 0x76008,
2085 .enable_mask = BIT(0),
2086 .hw.init = &(struct clk_init_data){
2087 .name = "gcc_ufs_unipro_core_clk",
2088 .parent_hws = (const struct clk_hw*[]) {
2089 &ufs_unipro_core_clk_src.clkr.hw,
2090 },
2091 .flags = CLK_SET_RATE_PARENT,
2092 .num_parents = 1,
2093 .ops = &clk_branch2_ops,
2094 },
2095 },
2096 };
2097
2098 static struct clk_branch gcc_usb20_master_clk = {
2099 .halt_reg = 0x2f004,
2100 .halt_check = BRANCH_HALT,
2101 .clkr = {
2102 .enable_reg = 0x2f004,
2103 .enable_mask = BIT(0),
2104 .hw.init = &(struct clk_init_data){
2105 .name = "gcc_usb20_master_clk",
2106 .parent_hws = (const struct clk_hw*[]) {
2107 &usb20_master_clk_src.clkr.hw,
2108 },
2109 .flags = CLK_SET_RATE_PARENT,
2110 .num_parents = 1,
2111 .ops = &clk_branch2_ops,
2112 },
2113 },
2114 };
2115
2116 static struct clk_branch gcc_usb20_mock_utmi_clk = {
2117 .halt_reg = 0x2f00c,
2118 .halt_check = BRANCH_HALT,
2119 .clkr = {
2120 .enable_reg = 0x2f00c,
2121 .enable_mask = BIT(0),
2122 .hw.init = &(struct clk_init_data){
2123 .name = "gcc_usb20_mock_utmi_clk",
2124 .parent_hws = (const struct clk_hw*[]) {
2125 &usb20_mock_utmi_clk_src.clkr.hw,
2126 },
2127 .num_parents = 1,
2128 .flags = CLK_SET_RATE_PARENT,
2129 .ops = &clk_branch2_ops,
2130 },
2131 },
2132 };
2133
2134 static struct clk_branch gcc_usb20_sleep_clk = {
2135 .halt_reg = 0x2f008,
2136 .halt_check = BRANCH_HALT,
2137 .clkr = {
2138 .enable_reg = 0x2f008,
2139 .enable_mask = BIT(0),
2140 .hw.init = &(struct clk_init_data){
2141 .name = "gcc_usb20_sleep_clk",
2142 .ops = &clk_branch2_ops,
2143 },
2144 },
2145 };
2146
2147 static struct clk_branch gcc_usb30_master_clk = {
2148 .halt_reg = 0xf008,
2149 .halt_check = BRANCH_HALT,
2150 .clkr = {
2151 .enable_reg = 0xf008,
2152 .enable_mask = BIT(0),
2153 .hw.init = &(struct clk_init_data){
2154 .name = "gcc_usb30_master_clk",
2155 .parent_hws = (const struct clk_hw*[]) {
2156 &usb30_master_clk_src.clkr.hw,
2157 },
2158 .num_parents = 1,
2159 .flags = CLK_SET_RATE_PARENT,
2160 .ops = &clk_branch2_ops,
2161 },
2162 },
2163 };
2164
2165 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2166 .halt_reg = 0xf010,
2167 .halt_check = BRANCH_HALT,
2168 .clkr = {
2169 .enable_reg = 0xf010,
2170 .enable_mask = BIT(0),
2171 .hw.init = &(struct clk_init_data){
2172 .name = "gcc_usb30_mock_utmi_clk",
2173 .parent_hws = (const struct clk_hw*[]) {
2174 &usb30_mock_utmi_clk_src.clkr.hw,
2175 },
2176 .num_parents = 1,
2177 .flags = CLK_SET_RATE_PARENT,
2178 .ops = &clk_branch2_ops,
2179 },
2180 },
2181 };
2182
2183 static struct clk_branch gcc_usb30_sleep_clk = {
2184 .halt_reg = 0xf00c,
2185 .halt_check = BRANCH_HALT,
2186 .clkr = {
2187 .enable_reg = 0xf00c,
2188 .enable_mask = BIT(0),
2189 .hw.init = &(struct clk_init_data){
2190 .name = "gcc_usb30_sleep_clk",
2191 .ops = &clk_branch2_ops,
2192 },
2193 },
2194 };
2195
2196 static struct clk_branch gcc_usb3_clkref_clk = {
2197 .halt_reg = 0x8800c,
2198 .halt_check = BRANCH_HALT,
2199 .clkr = {
2200 .enable_reg = 0x8800c,
2201 .enable_mask = BIT(0),
2202 .hw.init = &(struct clk_init_data){
2203 .name = "gcc_usb3_clkref_clk",
2204 .ops = &clk_branch2_ops,
2205 },
2206 },
2207 };
2208
2209 static struct clk_branch gcc_usb3_phy_aux_clk = {
2210 .halt_reg = 0x50000,
2211 .halt_check = BRANCH_HALT,
2212 .clkr = {
2213 .enable_reg = 0x50000,
2214 .enable_mask = BIT(0),
2215 .hw.init = &(struct clk_init_data){
2216 .name = "gcc_usb3_phy_aux_clk",
2217 .parent_hws = (const struct clk_hw*[]) {
2218 &usb3_phy_aux_clk_src.clkr.hw,
2219 },
2220 .num_parents = 1,
2221 .flags = CLK_SET_RATE_PARENT,
2222 .ops = &clk_branch2_ops,
2223 },
2224 },
2225 };
2226
2227 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2228 .halt_reg = 0x50004,
2229 .halt_check = BRANCH_HALT_DELAY,
2230 .clkr = {
2231 .enable_reg = 0x50004,
2232 .enable_mask = BIT(0),
2233 .hw.init = &(struct clk_init_data){
2234 .name = "gcc_usb3_phy_pipe_clk",
2235 .ops = &clk_branch2_ops,
2236 },
2237 },
2238 };
2239
2240 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2241 .halt_reg = 0x6a004,
2242 .halt_check = BRANCH_HALT,
2243 .clkr = {
2244 .enable_reg = 0x6a004,
2245 .enable_mask = BIT(0),
2246 .hw.init = &(struct clk_init_data){
2247 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2248 .ops = &clk_branch2_ops,
2249 },
2250 },
2251 };
2252
2253 static struct gdsc ufs_gdsc = {
2254 .gdscr = 0x75004,
2255 .gds_hw_ctrl = 0x0,
2256 .pd = {
2257 .name = "ufs_gdsc",
2258 },
2259 .pwrsts = PWRSTS_OFF_ON,
2260 .flags = VOTABLE,
2261 };
2262
2263 static struct gdsc usb_30_gdsc = {
2264 .gdscr = 0xf004,
2265 .gds_hw_ctrl = 0x0,
2266 .pd = {
2267 .name = "usb_30_gdsc",
2268 },
2269 .pwrsts = PWRSTS_OFF_ON,
2270 .flags = VOTABLE,
2271 };
2272
2273 static struct gdsc pcie_0_gdsc = {
2274 .gdscr = 0x6b004,
2275 .gds_hw_ctrl = 0x0,
2276 .pd = {
2277 .name = "pcie_0_gdsc",
2278 },
2279 .pwrsts = PWRSTS_OFF_ON,
2280 .flags = VOTABLE,
2281 };
2282
2283 static struct clk_hw *gcc_sdm660_hws[] = {
2284 &xo.hw,
2285 &gpll0_early_div.hw,
2286 &gpll1_early_div.hw,
2287 };
2288
2289 static struct clk_regmap *gcc_sdm660_clocks[] = {
2290 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2291 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2292 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2293 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2294 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2295 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2296 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2297 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2298 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2299 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2300 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2301 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2302 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2303 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2304 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2305 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2306 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2307 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2308 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2309 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2310 [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
2311 [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
2312 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
2313 [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
2314 [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
2315 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2316 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2317 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2318 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2319 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2320 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2321 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2322 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2323 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2324 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2325 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2326 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2327 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2328 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2329 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2330 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2331 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2332 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2333 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2334 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2335 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2336 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2337 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2338 [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr,
2339 [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
2340 [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
2341 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2342 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2343 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2344 [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
2345 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2346 [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
2347 [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
2348 [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
2349 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
2350 [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
2351 [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
2352 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2353 [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
2354 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2355 [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
2356 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2357 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
2358 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2359 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2360 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2361 [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
2362 [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
2363 [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr,
2364 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
2365 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2366 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2367 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2368 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2369 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2370 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2371 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2372 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
2373 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
2374 [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
2375 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2376 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2377 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2378 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
2379 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
2380 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
2381 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
2382 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2383 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2384 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2385 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
2386 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2387 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2388 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2389 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2390 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2391 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2392 [GPLL0] = &gpll0.clkr,
2393 [GPLL0_EARLY] = &gpll0_early.clkr,
2394 [GPLL1] = &gpll1.clkr,
2395 [GPLL1_EARLY] = &gpll1_early.clkr,
2396 [GPLL4] = &gpll4.clkr,
2397 [GPLL4_EARLY] = &gpll4_early.clkr,
2398 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
2399 [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr,
2400 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
2401 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2402 [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
2403 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2404 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
2405 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2406 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2407 [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
2408 [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr,
2409 [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
2410 [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
2411 [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
2412 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2413 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2414 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2415 };
2416
2417 static struct gdsc *gcc_sdm660_gdscs[] = {
2418 [UFS_GDSC] = &ufs_gdsc,
2419 [USB_30_GDSC] = &usb_30_gdsc,
2420 [PCIE_0_GDSC] = &pcie_0_gdsc,
2421 };
2422
2423 static const struct qcom_reset_map gcc_sdm660_resets[] = {
2424 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
2425 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
2426 [GCC_UFS_BCR] = { 0x75000 },
2427 [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
2428 [GCC_USB3_PHY_BCR] = { 0x50020 },
2429 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
2430 [GCC_USB_20_BCR] = { 0x2f000 },
2431 [GCC_USB_30_BCR] = { 0xf000 },
2432 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2433 [GCC_MSS_RESTART] = { 0x79000 },
2434 };
2435
2436 static const struct regmap_config gcc_sdm660_regmap_config = {
2437 .reg_bits = 32,
2438 .reg_stride = 4,
2439 .val_bits = 32,
2440 .max_register = 0x94000,
2441 .fast_io = true,
2442 };
2443
2444 static const struct qcom_cc_desc gcc_sdm660_desc = {
2445 .config = &gcc_sdm660_regmap_config,
2446 .clks = gcc_sdm660_clocks,
2447 .num_clks = ARRAY_SIZE(gcc_sdm660_clocks),
2448 .resets = gcc_sdm660_resets,
2449 .num_resets = ARRAY_SIZE(gcc_sdm660_resets),
2450 .gdscs = gcc_sdm660_gdscs,
2451 .num_gdscs = ARRAY_SIZE(gcc_sdm660_gdscs),
2452 .clk_hws = gcc_sdm660_hws,
2453 .num_clk_hws = ARRAY_SIZE(gcc_sdm660_hws),
2454 };
2455
2456 static const struct of_device_id gcc_sdm660_match_table[] = {
2457 { .compatible = "qcom,gcc-sdm630" },
2458 { .compatible = "qcom,gcc-sdm660" },
2459 { }
2460 };
2461 MODULE_DEVICE_TABLE(of, gcc_sdm660_match_table);
2462
gcc_sdm660_probe(struct platform_device * pdev)2463 static int gcc_sdm660_probe(struct platform_device *pdev)
2464 {
2465 int ret;
2466 struct regmap *regmap;
2467
2468 regmap = qcom_cc_map(pdev, &gcc_sdm660_desc);
2469 if (IS_ERR(regmap))
2470 return PTR_ERR(regmap);
2471
2472 /*
2473 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
2474 * turned off by hardware during certain apps low power modes.
2475 */
2476 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
2477 if (ret)
2478 return ret;
2479
2480 return qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap);
2481 }
2482
2483 static struct platform_driver gcc_sdm660_driver = {
2484 .probe = gcc_sdm660_probe,
2485 .driver = {
2486 .name = "gcc-sdm660",
2487 .of_match_table = gcc_sdm660_match_table,
2488 },
2489 };
2490
gcc_sdm660_init(void)2491 static int __init gcc_sdm660_init(void)
2492 {
2493 return platform_driver_register(&gcc_sdm660_driver);
2494 }
2495 core_initcall_sync(gcc_sdm660_init);
2496
gcc_sdm660_exit(void)2497 static void __exit gcc_sdm660_exit(void)
2498 {
2499 platform_driver_unregister(&gcc_sdm660_driver);
2500 }
2501 module_exit(gcc_sdm660_exit);
2502
2503 MODULE_LICENSE("GPL v2");
2504 MODULE_DESCRIPTION("QCOM GCC sdm660 Driver");
2505