1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2021 Aspeed Technology Inc.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/module.h>
8 #include <linux/of_address.h>
9 #include <linux/of_device.h>
10 #include <linux/of_irq.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13
14 #include "aspeed-hace.h"
15
16 #ifdef CONFIG_CRYPTO_DEV_ASPEED_DEBUG
17 #define HACE_DBG(d, fmt, ...) \
18 dev_info((d)->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
19 #else
20 #define HACE_DBG(d, fmt, ...) \
21 dev_dbg((d)->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
22 #endif
23
24 /* HACE interrupt service routine */
aspeed_hace_irq(int irq,void * dev)25 static irqreturn_t aspeed_hace_irq(int irq, void *dev)
26 {
27 struct aspeed_hace_dev *hace_dev = (struct aspeed_hace_dev *)dev;
28 struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
29 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine;
30 u32 sts;
31
32 sts = ast_hace_read(hace_dev, ASPEED_HACE_STS);
33 ast_hace_write(hace_dev, sts, ASPEED_HACE_STS);
34
35 HACE_DBG(hace_dev, "irq status: 0x%x\n", sts);
36
37 if (sts & HACE_HASH_ISR) {
38 if (hash_engine->flags & CRYPTO_FLAGS_BUSY)
39 tasklet_schedule(&hash_engine->done_task);
40 else
41 dev_warn(hace_dev->dev, "HASH no active requests.\n");
42 }
43
44 if (sts & HACE_CRYPTO_ISR) {
45 if (crypto_engine->flags & CRYPTO_FLAGS_BUSY)
46 tasklet_schedule(&crypto_engine->done_task);
47 else
48 dev_warn(hace_dev->dev, "CRYPTO no active requests.\n");
49 }
50
51 return IRQ_HANDLED;
52 }
53
aspeed_hace_crypto_done_task(unsigned long data)54 static void aspeed_hace_crypto_done_task(unsigned long data)
55 {
56 struct aspeed_hace_dev *hace_dev = (struct aspeed_hace_dev *)data;
57 struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
58
59 crypto_engine->resume(hace_dev);
60 }
61
aspeed_hace_hash_done_task(unsigned long data)62 static void aspeed_hace_hash_done_task(unsigned long data)
63 {
64 struct aspeed_hace_dev *hace_dev = (struct aspeed_hace_dev *)data;
65 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine;
66
67 hash_engine->resume(hace_dev);
68 }
69
aspeed_hace_register(struct aspeed_hace_dev * hace_dev)70 static void aspeed_hace_register(struct aspeed_hace_dev *hace_dev)
71 {
72 #ifdef CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH
73 aspeed_register_hace_hash_algs(hace_dev);
74 #endif
75 #ifdef CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO
76 aspeed_register_hace_crypto_algs(hace_dev);
77 #endif
78 }
79
aspeed_hace_unregister(struct aspeed_hace_dev * hace_dev)80 static void aspeed_hace_unregister(struct aspeed_hace_dev *hace_dev)
81 {
82 #ifdef CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH
83 aspeed_unregister_hace_hash_algs(hace_dev);
84 #endif
85 #ifdef CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO
86 aspeed_unregister_hace_crypto_algs(hace_dev);
87 #endif
88 }
89
90 static const struct of_device_id aspeed_hace_of_matches[] = {
91 { .compatible = "aspeed,ast2500-hace", .data = (void *)5, },
92 { .compatible = "aspeed,ast2600-hace", .data = (void *)6, },
93 {},
94 };
95
aspeed_hace_probe(struct platform_device * pdev)96 static int aspeed_hace_probe(struct platform_device *pdev)
97 {
98 struct aspeed_engine_crypto *crypto_engine;
99 const struct of_device_id *hace_dev_id;
100 struct aspeed_engine_hash *hash_engine;
101 struct aspeed_hace_dev *hace_dev;
102 struct resource *res;
103 int rc;
104
105 hace_dev = devm_kzalloc(&pdev->dev, sizeof(struct aspeed_hace_dev),
106 GFP_KERNEL);
107 if (!hace_dev)
108 return -ENOMEM;
109
110 hace_dev_id = of_match_device(aspeed_hace_of_matches, &pdev->dev);
111 if (!hace_dev_id) {
112 dev_err(&pdev->dev, "Failed to match hace dev id\n");
113 return -EINVAL;
114 }
115
116 hace_dev->dev = &pdev->dev;
117 hace_dev->version = (unsigned long)hace_dev_id->data;
118 hash_engine = &hace_dev->hash_engine;
119 crypto_engine = &hace_dev->crypto_engine;
120
121 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
122
123 platform_set_drvdata(pdev, hace_dev);
124
125 hace_dev->regs = devm_ioremap_resource(&pdev->dev, res);
126 if (IS_ERR(hace_dev->regs))
127 return PTR_ERR(hace_dev->regs);
128
129 /* Get irq number and register it */
130 hace_dev->irq = platform_get_irq(pdev, 0);
131 if (hace_dev->irq < 0)
132 return -ENXIO;
133
134 rc = devm_request_irq(&pdev->dev, hace_dev->irq, aspeed_hace_irq, 0,
135 dev_name(&pdev->dev), hace_dev);
136 if (rc) {
137 dev_err(&pdev->dev, "Failed to request interrupt\n");
138 return rc;
139 }
140
141 /* Get clk and enable it */
142 hace_dev->clk = devm_clk_get(&pdev->dev, NULL);
143 if (IS_ERR(hace_dev->clk)) {
144 dev_err(&pdev->dev, "Failed to get clk\n");
145 return -ENODEV;
146 }
147
148 rc = clk_prepare_enable(hace_dev->clk);
149 if (rc) {
150 dev_err(&pdev->dev, "Failed to enable clock 0x%x\n", rc);
151 return rc;
152 }
153
154 /* Initialize crypto hardware engine structure for hash */
155 hace_dev->crypt_engine_hash = crypto_engine_alloc_init(hace_dev->dev,
156 true);
157 if (!hace_dev->crypt_engine_hash) {
158 rc = -ENOMEM;
159 goto clk_exit;
160 }
161
162 rc = crypto_engine_start(hace_dev->crypt_engine_hash);
163 if (rc)
164 goto err_engine_hash_start;
165
166 tasklet_init(&hash_engine->done_task, aspeed_hace_hash_done_task,
167 (unsigned long)hace_dev);
168
169 /* Initialize crypto hardware engine structure for crypto */
170 hace_dev->crypt_engine_crypto = crypto_engine_alloc_init(hace_dev->dev,
171 true);
172 if (!hace_dev->crypt_engine_crypto) {
173 rc = -ENOMEM;
174 goto err_engine_hash_start;
175 }
176
177 rc = crypto_engine_start(hace_dev->crypt_engine_crypto);
178 if (rc)
179 goto err_engine_crypto_start;
180
181 tasklet_init(&crypto_engine->done_task, aspeed_hace_crypto_done_task,
182 (unsigned long)hace_dev);
183
184 /* Allocate DMA buffer for hash engine input used */
185 hash_engine->ahash_src_addr =
186 dmam_alloc_coherent(&pdev->dev,
187 ASPEED_HASH_SRC_DMA_BUF_LEN,
188 &hash_engine->ahash_src_dma_addr,
189 GFP_KERNEL);
190 if (!hash_engine->ahash_src_addr) {
191 dev_err(&pdev->dev, "Failed to allocate dma buffer\n");
192 rc = -ENOMEM;
193 goto err_engine_crypto_start;
194 }
195
196 /* Allocate DMA buffer for crypto engine context used */
197 crypto_engine->cipher_ctx =
198 dmam_alloc_coherent(&pdev->dev,
199 PAGE_SIZE,
200 &crypto_engine->cipher_ctx_dma,
201 GFP_KERNEL);
202 if (!crypto_engine->cipher_ctx) {
203 dev_err(&pdev->dev, "Failed to allocate cipher ctx dma\n");
204 rc = -ENOMEM;
205 goto err_engine_crypto_start;
206 }
207
208 /* Allocate DMA buffer for crypto engine input used */
209 crypto_engine->cipher_addr =
210 dmam_alloc_coherent(&pdev->dev,
211 ASPEED_CRYPTO_SRC_DMA_BUF_LEN,
212 &crypto_engine->cipher_dma_addr,
213 GFP_KERNEL);
214 if (!crypto_engine->cipher_addr) {
215 dev_err(&pdev->dev, "Failed to allocate cipher addr dma\n");
216 rc = -ENOMEM;
217 goto err_engine_crypto_start;
218 }
219
220 /* Allocate DMA buffer for crypto engine output used */
221 if (hace_dev->version == AST2600_VERSION) {
222 crypto_engine->dst_sg_addr =
223 dmam_alloc_coherent(&pdev->dev,
224 ASPEED_CRYPTO_DST_DMA_BUF_LEN,
225 &crypto_engine->dst_sg_dma_addr,
226 GFP_KERNEL);
227 if (!crypto_engine->dst_sg_addr) {
228 dev_err(&pdev->dev, "Failed to allocate dst_sg dma\n");
229 rc = -ENOMEM;
230 goto err_engine_crypto_start;
231 }
232 }
233
234 aspeed_hace_register(hace_dev);
235
236 dev_info(&pdev->dev, "Aspeed Crypto Accelerator successfully registered\n");
237
238 return 0;
239
240 err_engine_crypto_start:
241 crypto_engine_exit(hace_dev->crypt_engine_crypto);
242 err_engine_hash_start:
243 crypto_engine_exit(hace_dev->crypt_engine_hash);
244 clk_exit:
245 clk_disable_unprepare(hace_dev->clk);
246
247 return rc;
248 }
249
aspeed_hace_remove(struct platform_device * pdev)250 static int aspeed_hace_remove(struct platform_device *pdev)
251 {
252 struct aspeed_hace_dev *hace_dev = platform_get_drvdata(pdev);
253 struct aspeed_engine_crypto *crypto_engine = &hace_dev->crypto_engine;
254 struct aspeed_engine_hash *hash_engine = &hace_dev->hash_engine;
255
256 aspeed_hace_unregister(hace_dev);
257
258 crypto_engine_exit(hace_dev->crypt_engine_hash);
259 crypto_engine_exit(hace_dev->crypt_engine_crypto);
260
261 tasklet_kill(&hash_engine->done_task);
262 tasklet_kill(&crypto_engine->done_task);
263
264 clk_disable_unprepare(hace_dev->clk);
265
266 return 0;
267 }
268
269 MODULE_DEVICE_TABLE(of, aspeed_hace_of_matches);
270
271 static struct platform_driver aspeed_hace_driver = {
272 .probe = aspeed_hace_probe,
273 .remove = aspeed_hace_remove,
274 .driver = {
275 .name = KBUILD_MODNAME,
276 .of_match_table = aspeed_hace_of_matches,
277 },
278 };
279
280 module_platform_driver(aspeed_hace_driver);
281
282 MODULE_AUTHOR("Neal Liu <neal_liu@aspeedtech.com>");
283 MODULE_DESCRIPTION("Aspeed HACE driver Crypto Accelerator");
284 MODULE_LICENSE("GPL");
285