1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
4 *
5 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
6 * Copyright (C) 2016 Freescale Semiconductor Inc.
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/spinlock.h>
13 #include <linux/io.h>
14 #include <linux/of.h>
15 #include <linux/of_gpio.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_platform.h>
19 #include <linux/property.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/slab.h>
22 #include <linux/irq.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/bitops.h>
25 #include <linux/interrupt.h>
26
27 #define MPC8XXX_GPIO_PINS 32
28
29 #define GPIO_DIR 0x00
30 #define GPIO_ODR 0x04
31 #define GPIO_DAT 0x08
32 #define GPIO_IER 0x0c
33 #define GPIO_IMR 0x10
34 #define GPIO_ICR 0x14
35 #define GPIO_ICR2 0x18
36 #define GPIO_IBE 0x18
37
38 struct mpc8xxx_gpio_chip {
39 struct gpio_chip gc;
40 void __iomem *regs;
41 raw_spinlock_t lock;
42
43 int (*direction_output)(struct gpio_chip *chip,
44 unsigned offset, int value);
45
46 struct irq_domain *irq;
47 int irqn;
48 };
49
50 /*
51 * This hardware has a big endian bit assignment such that GPIO line 0 is
52 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
53 * This inline helper give the right bitmask for a certain line.
54 */
mpc_pin2mask(unsigned int offset)55 static inline u32 mpc_pin2mask(unsigned int offset)
56 {
57 return BIT(31 - offset);
58 }
59
60 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
61 * defined as output cannot be determined by reading GPDAT register,
62 * so we use shadow data register instead. The status of input pins
63 * is determined by reading GPDAT register.
64 */
mpc8572_gpio_get(struct gpio_chip * gc,unsigned int gpio)65 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
66 {
67 u32 val;
68 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
69 u32 out_mask, out_shadow;
70
71 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
72 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
73 out_shadow = gc->bgpio_data & out_mask;
74
75 return !!((val | out_shadow) & mpc_pin2mask(gpio));
76 }
77
mpc5121_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)78 static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
79 unsigned int gpio, int val)
80 {
81 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
82 /* GPIO 28..31 are input only on MPC5121 */
83 if (gpio >= 28)
84 return -EINVAL;
85
86 return mpc8xxx_gc->direction_output(gc, gpio, val);
87 }
88
mpc5125_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)89 static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
90 unsigned int gpio, int val)
91 {
92 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
93 /* GPIO 0..3 are input only on MPC5125 */
94 if (gpio <= 3)
95 return -EINVAL;
96
97 return mpc8xxx_gc->direction_output(gc, gpio, val);
98 }
99
mpc8xxx_gpio_to_irq(struct gpio_chip * gc,unsigned offset)100 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
101 {
102 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
103
104 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
105 return irq_create_mapping(mpc8xxx_gc->irq, offset);
106 else
107 return -ENXIO;
108 }
109
mpc8xxx_gpio_irq_cascade(int irq,void * data)110 static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
111 {
112 struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
113 struct gpio_chip *gc = &mpc8xxx_gc->gc;
114 unsigned long mask;
115 int i;
116
117 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
118 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
119 for_each_set_bit(i, &mask, 32)
120 generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
121
122 return IRQ_HANDLED;
123 }
124
mpc8xxx_irq_unmask(struct irq_data * d)125 static void mpc8xxx_irq_unmask(struct irq_data *d)
126 {
127 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
128 struct gpio_chip *gc = &mpc8xxx_gc->gc;
129 unsigned long flags;
130
131 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
132
133 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
134 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
135 | mpc_pin2mask(irqd_to_hwirq(d)));
136
137 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
138 }
139
mpc8xxx_irq_mask(struct irq_data * d)140 static void mpc8xxx_irq_mask(struct irq_data *d)
141 {
142 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
143 struct gpio_chip *gc = &mpc8xxx_gc->gc;
144 unsigned long flags;
145
146 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
147
148 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
149 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
150 & ~mpc_pin2mask(irqd_to_hwirq(d)));
151
152 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
153 }
154
mpc8xxx_irq_ack(struct irq_data * d)155 static void mpc8xxx_irq_ack(struct irq_data *d)
156 {
157 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
158 struct gpio_chip *gc = &mpc8xxx_gc->gc;
159
160 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
161 mpc_pin2mask(irqd_to_hwirq(d)));
162 }
163
mpc8xxx_irq_set_type(struct irq_data * d,unsigned int flow_type)164 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
165 {
166 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
167 struct gpio_chip *gc = &mpc8xxx_gc->gc;
168 unsigned long flags;
169
170 switch (flow_type) {
171 case IRQ_TYPE_EDGE_FALLING:
172 case IRQ_TYPE_LEVEL_LOW:
173 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
174 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
175 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
176 | mpc_pin2mask(irqd_to_hwirq(d)));
177 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
178 break;
179
180 case IRQ_TYPE_EDGE_BOTH:
181 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
182 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
183 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
184 & ~mpc_pin2mask(irqd_to_hwirq(d)));
185 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
186 break;
187
188 default:
189 return -EINVAL;
190 }
191
192 return 0;
193 }
194
mpc512x_irq_set_type(struct irq_data * d,unsigned int flow_type)195 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
196 {
197 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
198 struct gpio_chip *gc = &mpc8xxx_gc->gc;
199 unsigned long gpio = irqd_to_hwirq(d);
200 void __iomem *reg;
201 unsigned int shift;
202 unsigned long flags;
203
204 if (gpio < 16) {
205 reg = mpc8xxx_gc->regs + GPIO_ICR;
206 shift = (15 - gpio) * 2;
207 } else {
208 reg = mpc8xxx_gc->regs + GPIO_ICR2;
209 shift = (15 - (gpio % 16)) * 2;
210 }
211
212 switch (flow_type) {
213 case IRQ_TYPE_EDGE_FALLING:
214 case IRQ_TYPE_LEVEL_LOW:
215 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
216 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
217 | (2 << shift));
218 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
219 break;
220
221 case IRQ_TYPE_EDGE_RISING:
222 case IRQ_TYPE_LEVEL_HIGH:
223 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
224 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
225 | (1 << shift));
226 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
227 break;
228
229 case IRQ_TYPE_EDGE_BOTH:
230 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
231 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
232 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
233 break;
234
235 default:
236 return -EINVAL;
237 }
238
239 return 0;
240 }
241
242 static struct irq_chip mpc8xxx_irq_chip = {
243 .name = "mpc8xxx-gpio",
244 .irq_unmask = mpc8xxx_irq_unmask,
245 .irq_mask = mpc8xxx_irq_mask,
246 .irq_ack = mpc8xxx_irq_ack,
247 /* this might get overwritten in mpc8xxx_probe() */
248 .irq_set_type = mpc8xxx_irq_set_type,
249 };
250
mpc8xxx_gpio_irq_map(struct irq_domain * h,unsigned int irq,irq_hw_number_t hwirq)251 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
252 irq_hw_number_t hwirq)
253 {
254 irq_set_chip_data(irq, h->host_data);
255 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
256
257 return 0;
258 }
259
260 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
261 .map = mpc8xxx_gpio_irq_map,
262 .xlate = irq_domain_xlate_twocell,
263 };
264
265 struct mpc8xxx_gpio_devtype {
266 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
267 int (*gpio_get)(struct gpio_chip *, unsigned int);
268 int (*irq_set_type)(struct irq_data *, unsigned int);
269 };
270
271 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
272 .gpio_dir_out = mpc5121_gpio_dir_out,
273 .irq_set_type = mpc512x_irq_set_type,
274 };
275
276 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
277 .gpio_dir_out = mpc5125_gpio_dir_out,
278 .irq_set_type = mpc512x_irq_set_type,
279 };
280
281 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
282 .gpio_get = mpc8572_gpio_get,
283 };
284
285 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
286 .irq_set_type = mpc8xxx_irq_set_type,
287 };
288
289 static const struct of_device_id mpc8xxx_gpio_ids[] = {
290 { .compatible = "fsl,mpc8349-gpio", },
291 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
292 { .compatible = "fsl,mpc8610-gpio", },
293 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
294 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
295 { .compatible = "fsl,pq3-gpio", },
296 { .compatible = "fsl,ls1028a-gpio", },
297 { .compatible = "fsl,ls1088a-gpio", },
298 { .compatible = "fsl,qoriq-gpio", },
299 {}
300 };
301
mpc8xxx_probe(struct platform_device * pdev)302 static int mpc8xxx_probe(struct platform_device *pdev)
303 {
304 struct device_node *np = pdev->dev.of_node;
305 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
306 struct gpio_chip *gc;
307 const struct mpc8xxx_gpio_devtype *devtype = NULL;
308 struct fwnode_handle *fwnode;
309 int ret;
310
311 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
312 if (!mpc8xxx_gc)
313 return -ENOMEM;
314
315 platform_set_drvdata(pdev, mpc8xxx_gc);
316
317 raw_spin_lock_init(&mpc8xxx_gc->lock);
318
319 mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
320 if (IS_ERR(mpc8xxx_gc->regs))
321 return PTR_ERR(mpc8xxx_gc->regs);
322
323 gc = &mpc8xxx_gc->gc;
324 gc->parent = &pdev->dev;
325
326 if (device_property_read_bool(&pdev->dev, "little-endian")) {
327 ret = bgpio_init(gc, &pdev->dev, 4,
328 mpc8xxx_gc->regs + GPIO_DAT,
329 NULL, NULL,
330 mpc8xxx_gc->regs + GPIO_DIR, NULL,
331 BGPIOF_BIG_ENDIAN);
332 if (ret)
333 return ret;
334 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
335 } else {
336 ret = bgpio_init(gc, &pdev->dev, 4,
337 mpc8xxx_gc->regs + GPIO_DAT,
338 NULL, NULL,
339 mpc8xxx_gc->regs + GPIO_DIR, NULL,
340 BGPIOF_BIG_ENDIAN
341 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
342 if (ret)
343 return ret;
344 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
345 }
346
347 mpc8xxx_gc->direction_output = gc->direction_output;
348
349 devtype = device_get_match_data(&pdev->dev);
350 if (!devtype)
351 devtype = &mpc8xxx_gpio_devtype_default;
352
353 /*
354 * It's assumed that only a single type of gpio controller is available
355 * on the current machine, so overwriting global data is fine.
356 */
357 if (devtype->irq_set_type)
358 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
359
360 if (devtype->gpio_dir_out)
361 gc->direction_output = devtype->gpio_dir_out;
362 if (devtype->gpio_get)
363 gc->get = devtype->gpio_get;
364
365 gc->to_irq = mpc8xxx_gpio_to_irq;
366
367 /*
368 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
369 * the input enable of each individual GPIO port. When an individual
370 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
371 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
372 * the port value to the GPIO Data Register.
373 */
374 fwnode = dev_fwnode(&pdev->dev);
375 if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
376 of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
377 of_device_is_compatible(np, "fsl,ls1088a-gpio") ||
378 is_acpi_node(fwnode))
379 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
380
381 ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc);
382 if (ret) {
383 dev_err(&pdev->dev,
384 "GPIO chip registration failed with status %d\n", ret);
385 return ret;
386 }
387
388 mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
389 if (mpc8xxx_gc->irqn < 0)
390 return mpc8xxx_gc->irqn;
391
392 mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
393 MPC8XXX_GPIO_PINS,
394 &mpc8xxx_gpio_irq_ops,
395 mpc8xxx_gc);
396
397 if (!mpc8xxx_gc->irq)
398 return 0;
399
400 /* ack and mask all irqs */
401 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
402 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
403
404 ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
405 mpc8xxx_gpio_irq_cascade,
406 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
407 mpc8xxx_gc);
408 if (ret) {
409 dev_err(&pdev->dev,
410 "failed to devm_request_irq(%d), ret = %d\n",
411 mpc8xxx_gc->irqn, ret);
412 goto err;
413 }
414
415 return 0;
416 err:
417 irq_domain_remove(mpc8xxx_gc->irq);
418 return ret;
419 }
420
mpc8xxx_remove(struct platform_device * pdev)421 static int mpc8xxx_remove(struct platform_device *pdev)
422 {
423 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
424
425 if (mpc8xxx_gc->irq) {
426 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
427 irq_domain_remove(mpc8xxx_gc->irq);
428 }
429
430 return 0;
431 }
432
433 #ifdef CONFIG_ACPI
434 static const struct acpi_device_id gpio_acpi_ids[] = {
435 {"NXP0031",},
436 { }
437 };
438 MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
439 #endif
440
441 static struct platform_driver mpc8xxx_plat_driver = {
442 .probe = mpc8xxx_probe,
443 .remove = mpc8xxx_remove,
444 .driver = {
445 .name = "gpio-mpc8xxx",
446 .of_match_table = mpc8xxx_gpio_ids,
447 .acpi_match_table = ACPI_PTR(gpio_acpi_ids),
448 },
449 };
450
mpc8xxx_init(void)451 static int __init mpc8xxx_init(void)
452 {
453 return platform_driver_register(&mpc8xxx_plat_driver);
454 }
455
456 arch_initcall(mpc8xxx_init);
457